2 * Driver for Motorola/Freescale IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
39 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
47 /* Register definitions */
48 #define URXD0 0x0 /* Receiver Register */
49 #define URTX0 0x40 /* Transmitter Register */
50 #define UCR1 0x80 /* Control Register 1 */
51 #define UCR2 0x84 /* Control Register 2 */
52 #define UCR3 0x88 /* Control Register 3 */
53 #define UCR4 0x8c /* Control Register 4 */
54 #define UFCR 0x90 /* FIFO Control Register */
55 #define USR1 0x94 /* Status Register 1 */
56 #define USR2 0x98 /* Status Register 2 */
57 #define UESC 0x9c /* Escape Character Register */
58 #define UTIM 0xa0 /* Escape Timer Register */
59 #define UBIR 0xa4 /* BRM Incremental Register */
60 #define UBMR 0xa8 /* BRM Modulator Register */
61 #define UBRC 0xac /* Baud Rate Count Register */
62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
66 /* UART Control Register Bit Fields.*/
67 #define URXD_DUMMY_READ (1<<16)
68 #define URXD_CHARRDY (1<<15)
69 #define URXD_ERR (1<<14)
70 #define URXD_OVRRUN (1<<13)
71 #define URXD_FRMERR (1<<12)
72 #define URXD_BRK (1<<11)
73 #define URXD_PRERR (1<<10)
74 #define URXD_RX_DATA (0xFF<<0)
75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82 #define UCR1_IREN (1<<7) /* Infrared interface enable */
83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85 #define UCR1_SNDBRK (1<<4) /* Send break */
86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
89 #define UCR1_DOZE (1<<1) /* Doze */
90 #define UCR1_UARTEN (1<<0) /* UART enabled */
91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93 #define UCR2_CTSC (1<<13) /* CTS pin control */
94 #define UCR2_CTS (1<<12) /* Clear to send */
95 #define UCR2_ESCEN (1<<11) /* Escape enable */
96 #define UCR2_PREN (1<<8) /* Parity enable */
97 #define UCR2_PROE (1<<7) /* Parity odd/even */
98 #define UCR2_STPB (1<<6) /* Stop */
99 #define UCR2_WS (1<<5) /* Word size */
100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
103 #define UCR2_RXEN (1<<1) /* Receiver enabled */
104 #define UCR2_SRST (1<<0) /* SW reset */
105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106 #define UCR3_PARERREN (1<<12) /* Parity enable */
107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108 #define UCR3_DSR (1<<10) /* Data set ready */
109 #define UCR3_DCD (1<<9) /* Data carrier detect */
110 #define UCR3_RI (1<<8) /* Ring indicator */
111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117 #define UCR3_BPEN (1<<0) /* Preset registers enable */
118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
125 #define UCR4_IRSC (1<<5) /* IR special case */
126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 207
167 #define MINOR_START 16
168 #define DEV_NAME "ttymxc"
171 * This determines how often we check the modem status signals
172 * for any change. They generally aren't connected to an IRQ
173 * so we have to poll them. We also check immediately before
174 * filling the TX fifo incase CTS has been dropped.
176 #define MCTRL_TIMEOUT (250*HZ/1000)
178 #define DRIVER_NAME "IMX-uart"
182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
189 /* device type dependent stuff */
190 struct imx_uart_data
{
192 enum imx_uart_type devtype
;
196 struct uart_port port
;
197 struct timer_list timer
;
198 unsigned int old_status
;
199 unsigned int have_rtscts
:1;
200 unsigned int dte_mode
:1;
201 unsigned int irda_inv_rx
:1;
202 unsigned int irda_inv_tx
:1;
203 unsigned short trcv_delay
; /* transceiver delay */
206 const struct imx_uart_data
*devdata
;
209 unsigned int dma_is_inited
:1;
210 unsigned int dma_is_enabled
:1;
211 unsigned int dma_is_rxing
:1;
212 unsigned int dma_is_txing
:1;
213 struct dma_chan
*dma_chan_rx
, *dma_chan_tx
;
214 struct scatterlist rx_sgl
, tx_sgl
[2];
216 unsigned int tx_bytes
;
217 unsigned int dma_tx_nents
;
218 wait_queue_head_t dma_wait
;
219 unsigned int saved_reg
[10];
223 struct imx_port_ucrs
{
229 static struct imx_uart_data imx_uart_devdata
[] = {
232 .devtype
= IMX1_UART
,
235 .uts_reg
= IMX21_UTS
,
236 .devtype
= IMX21_UART
,
239 .uts_reg
= IMX21_UTS
,
240 .devtype
= IMX6Q_UART
,
244 static const struct platform_device_id imx_uart_devtype
[] = {
247 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX1_UART
],
249 .name
= "imx21-uart",
250 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX21_UART
],
252 .name
= "imx6q-uart",
253 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX6Q_UART
],
258 MODULE_DEVICE_TABLE(platform
, imx_uart_devtype
);
260 static const struct of_device_id imx_uart_dt_ids
[] = {
261 { .compatible
= "fsl,imx6q-uart", .data
= &imx_uart_devdata
[IMX6Q_UART
], },
262 { .compatible
= "fsl,imx1-uart", .data
= &imx_uart_devdata
[IMX1_UART
], },
263 { .compatible
= "fsl,imx21-uart", .data
= &imx_uart_devdata
[IMX21_UART
], },
266 MODULE_DEVICE_TABLE(of
, imx_uart_dt_ids
);
268 static inline unsigned uts_reg(struct imx_port
*sport
)
270 return sport
->devdata
->uts_reg
;
273 static inline int is_imx1_uart(struct imx_port
*sport
)
275 return sport
->devdata
->devtype
== IMX1_UART
;
278 static inline int is_imx21_uart(struct imx_port
*sport
)
280 return sport
->devdata
->devtype
== IMX21_UART
;
283 static inline int is_imx6q_uart(struct imx_port
*sport
)
285 return sport
->devdata
->devtype
== IMX6Q_UART
;
288 * Save and restore functions for UCR1, UCR2 and UCR3 registers
290 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
291 static void imx_port_ucrs_save(struct uart_port
*port
,
292 struct imx_port_ucrs
*ucr
)
294 /* save control registers */
295 ucr
->ucr1
= readl(port
->membase
+ UCR1
);
296 ucr
->ucr2
= readl(port
->membase
+ UCR2
);
297 ucr
->ucr3
= readl(port
->membase
+ UCR3
);
300 static void imx_port_ucrs_restore(struct uart_port
*port
,
301 struct imx_port_ucrs
*ucr
)
303 /* restore control registers */
304 writel(ucr
->ucr1
, port
->membase
+ UCR1
);
305 writel(ucr
->ucr2
, port
->membase
+ UCR2
);
306 writel(ucr
->ucr3
, port
->membase
+ UCR3
);
311 * Handle any change of modem status signal since we were last called.
313 static void imx_mctrl_check(struct imx_port
*sport
)
315 unsigned int status
, changed
;
317 status
= sport
->port
.ops
->get_mctrl(&sport
->port
);
318 changed
= status
^ sport
->old_status
;
323 sport
->old_status
= status
;
325 if (changed
& TIOCM_RI
)
326 sport
->port
.icount
.rng
++;
327 if (changed
& TIOCM_DSR
)
328 sport
->port
.icount
.dsr
++;
329 if (changed
& TIOCM_CAR
)
330 uart_handle_dcd_change(&sport
->port
, status
& TIOCM_CAR
);
331 if (changed
& TIOCM_CTS
)
332 uart_handle_cts_change(&sport
->port
, status
& TIOCM_CTS
);
334 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
338 * This is our per-port timeout handler, for checking the
339 * modem status signals.
341 static void imx_timeout(unsigned long data
)
343 struct imx_port
*sport
= (struct imx_port
*)data
;
346 if (sport
->port
.state
) {
347 spin_lock_irqsave(&sport
->port
.lock
, flags
);
348 imx_mctrl_check(sport
);
349 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
351 mod_timer(&sport
->timer
, jiffies
+ MCTRL_TIMEOUT
);
356 * interrupts disabled on entry
358 static void imx_stop_tx(struct uart_port
*port
)
360 struct imx_port
*sport
= (struct imx_port
*)port
;
364 * We are maybe in the SMP context, so if the DMA TX thread is running
365 * on other cpu, we have to wait for it to finish.
367 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
370 temp
= readl(port
->membase
+ UCR1
);
371 writel(temp
& ~UCR1_TXMPTYEN
, port
->membase
+ UCR1
);
373 /* in rs485 mode disable transmitter if shifter is empty */
374 if (port
->rs485
.flags
& SER_RS485_ENABLED
&&
375 readl(port
->membase
+ USR2
) & USR2_TXDC
) {
376 temp
= readl(port
->membase
+ UCR2
);
377 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
381 writel(temp
, port
->membase
+ UCR2
);
383 temp
= readl(port
->membase
+ UCR4
);
385 writel(temp
, port
->membase
+ UCR4
);
390 * interrupts disabled on entry
392 static void imx_stop_rx(struct uart_port
*port
)
394 struct imx_port
*sport
= (struct imx_port
*)port
;
397 if (sport
->dma_is_enabled
&& sport
->dma_is_rxing
) {
398 if (sport
->port
.suspended
) {
399 dmaengine_terminate_all(sport
->dma_chan_rx
);
400 sport
->dma_is_rxing
= 0;
406 temp
= readl(sport
->port
.membase
+ UCR2
);
407 writel(temp
& ~UCR2_RXEN
, sport
->port
.membase
+ UCR2
);
409 /* disable the `Receiver Ready Interrrupt` */
410 temp
= readl(sport
->port
.membase
+ UCR1
);
411 writel(temp
& ~UCR1_RRDYEN
, sport
->port
.membase
+ UCR1
);
415 * Set the modem control timer to fire immediately.
417 static void imx_enable_ms(struct uart_port
*port
)
419 struct imx_port
*sport
= (struct imx_port
*)port
;
421 mod_timer(&sport
->timer
, jiffies
);
424 static void imx_dma_tx(struct imx_port
*sport
);
425 static inline void imx_transmit_buffer(struct imx_port
*sport
)
427 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
430 if (sport
->port
.x_char
) {
432 writel(sport
->port
.x_char
, sport
->port
.membase
+ URTX0
);
433 sport
->port
.icount
.tx
++;
434 sport
->port
.x_char
= 0;
438 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
439 imx_stop_tx(&sport
->port
);
443 if (sport
->dma_is_enabled
) {
445 * We've just sent a X-char Ensure the TX DMA is enabled
446 * and the TX IRQ is disabled.
448 temp
= readl(sport
->port
.membase
+ UCR1
);
449 temp
&= ~UCR1_TXMPTYEN
;
450 if (sport
->dma_is_txing
) {
452 writel(temp
, sport
->port
.membase
+ UCR1
);
454 writel(temp
, sport
->port
.membase
+ UCR1
);
459 while (!uart_circ_empty(xmit
) &&
460 !(readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)) {
461 /* send xmit->buf[xmit->tail]
462 * out the port here */
463 writel(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ URTX0
);
464 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
465 sport
->port
.icount
.tx
++;
468 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
469 uart_write_wakeup(&sport
->port
);
471 if (uart_circ_empty(xmit
))
472 imx_stop_tx(&sport
->port
);
475 static void dma_tx_callback(void *data
)
477 struct imx_port
*sport
= data
;
478 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
479 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
483 spin_lock_irqsave(&sport
->port
.lock
, flags
);
485 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
487 temp
= readl(sport
->port
.membase
+ UCR1
);
488 temp
&= ~UCR1_TDMAEN
;
489 writel(temp
, sport
->port
.membase
+ UCR1
);
491 /* update the stat */
492 xmit
->tail
= (xmit
->tail
+ sport
->tx_bytes
) & (UART_XMIT_SIZE
- 1);
493 sport
->port
.icount
.tx
+= sport
->tx_bytes
;
495 dev_dbg(sport
->port
.dev
, "we finish the TX DMA.\n");
497 sport
->dma_is_txing
= 0;
499 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
501 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
502 uart_write_wakeup(&sport
->port
);
504 if (waitqueue_active(&sport
->dma_wait
)) {
505 wake_up(&sport
->dma_wait
);
506 dev_dbg(sport
->port
.dev
, "exit in %s.\n", __func__
);
510 spin_lock_irqsave(&sport
->port
.lock
, flags
);
511 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
513 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
516 static void imx_dma_tx(struct imx_port
*sport
)
518 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
519 struct scatterlist
*sgl
= sport
->tx_sgl
;
520 struct dma_async_tx_descriptor
*desc
;
521 struct dma_chan
*chan
= sport
->dma_chan_tx
;
522 struct device
*dev
= sport
->port
.dev
;
526 if (sport
->dma_is_txing
)
529 sport
->tx_bytes
= uart_circ_chars_pending(xmit
);
531 if (xmit
->tail
< xmit
->head
) {
532 sport
->dma_tx_nents
= 1;
533 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->tx_bytes
);
535 sport
->dma_tx_nents
= 2;
536 sg_init_table(sgl
, 2);
537 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
538 UART_XMIT_SIZE
- xmit
->tail
);
539 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
542 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
544 dev_err(dev
, "DMA mapping error for TX.\n");
547 desc
= dmaengine_prep_slave_sg(chan
, sgl
, sport
->dma_tx_nents
,
548 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
550 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
,
552 dev_err(dev
, "We cannot prepare for the TX slave dma!\n");
555 desc
->callback
= dma_tx_callback
;
556 desc
->callback_param
= sport
;
558 dev_dbg(dev
, "TX: prepare to send %lu bytes by DMA.\n",
559 uart_circ_chars_pending(xmit
));
561 temp
= readl(sport
->port
.membase
+ UCR1
);
563 writel(temp
, sport
->port
.membase
+ UCR1
);
566 sport
->dma_is_txing
= 1;
567 dmaengine_submit(desc
);
568 dma_async_issue_pending(chan
);
573 * interrupts disabled on entry
575 static void imx_start_tx(struct uart_port
*port
)
577 struct imx_port
*sport
= (struct imx_port
*)port
;
580 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
581 /* enable transmitter and shifter empty irq */
582 temp
= readl(port
->membase
+ UCR2
);
583 if (port
->rs485
.flags
& SER_RS485_RTS_ON_SEND
)
587 writel(temp
, port
->membase
+ UCR2
);
589 temp
= readl(port
->membase
+ UCR4
);
591 writel(temp
, port
->membase
+ UCR4
);
594 if (!sport
->dma_is_enabled
) {
595 temp
= readl(sport
->port
.membase
+ UCR1
);
596 writel(temp
| UCR1_TXMPTYEN
, sport
->port
.membase
+ UCR1
);
599 if (sport
->dma_is_enabled
) {
600 if (sport
->port
.x_char
) {
601 /* We have X-char to send, so enable TX IRQ and
602 * disable TX DMA to let TX interrupt to send X-char */
603 temp
= readl(sport
->port
.membase
+ UCR1
);
604 temp
&= ~UCR1_TDMAEN
;
605 temp
|= UCR1_TXMPTYEN
;
606 writel(temp
, sport
->port
.membase
+ UCR1
);
610 if (!uart_circ_empty(&port
->state
->xmit
) &&
611 !uart_tx_stopped(port
))
617 static irqreturn_t
imx_rtsint(int irq
, void *dev_id
)
619 struct imx_port
*sport
= dev_id
;
623 spin_lock_irqsave(&sport
->port
.lock
, flags
);
625 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
626 val
= readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
;
627 uart_handle_cts_change(&sport
->port
, !!val
);
628 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
630 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
634 static irqreturn_t
imx_txint(int irq
, void *dev_id
)
636 struct imx_port
*sport
= dev_id
;
639 spin_lock_irqsave(&sport
->port
.lock
, flags
);
640 imx_transmit_buffer(sport
);
641 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
645 static irqreturn_t
imx_rxint(int irq
, void *dev_id
)
647 struct imx_port
*sport
= dev_id
;
648 unsigned int rx
, flg
, ignored
= 0;
649 struct tty_port
*port
= &sport
->port
.state
->port
;
650 unsigned long flags
, temp
;
652 spin_lock_irqsave(&sport
->port
.lock
, flags
);
654 while (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
) {
656 sport
->port
.icount
.rx
++;
658 rx
= readl(sport
->port
.membase
+ URXD0
);
660 temp
= readl(sport
->port
.membase
+ USR2
);
661 if (temp
& USR2_BRCD
) {
662 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
663 if (uart_handle_break(&sport
->port
))
667 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
670 if (unlikely(rx
& URXD_ERR
)) {
672 sport
->port
.icount
.brk
++;
673 else if (rx
& URXD_PRERR
)
674 sport
->port
.icount
.parity
++;
675 else if (rx
& URXD_FRMERR
)
676 sport
->port
.icount
.frame
++;
677 if (rx
& URXD_OVRRUN
)
678 sport
->port
.icount
.overrun
++;
680 if (rx
& sport
->port
.ignore_status_mask
) {
686 rx
&= (sport
->port
.read_status_mask
| 0xFF);
690 else if (rx
& URXD_PRERR
)
692 else if (rx
& URXD_FRMERR
)
694 if (rx
& URXD_OVRRUN
)
698 sport
->port
.sysrq
= 0;
702 if (sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)
705 if (tty_insert_flip_char(port
, rx
, flg
) == 0)
706 sport
->port
.icount
.buf_overrun
++;
710 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
711 tty_flip_buffer_push(port
);
715 static int start_rx_dma(struct imx_port
*sport
);
717 * If the RXFIFO is filled with some data, and then we
718 * arise a DMA operation to receive them.
720 static void imx_dma_rxint(struct imx_port
*sport
)
725 spin_lock_irqsave(&sport
->port
.lock
, flags
);
727 temp
= readl(sport
->port
.membase
+ USR2
);
728 if ((temp
& USR2_RDR
) && !sport
->dma_is_rxing
) {
729 sport
->dma_is_rxing
= 1;
731 /* disable the `Recerver Ready Interrrupt` */
732 temp
= readl(sport
->port
.membase
+ UCR1
);
733 temp
&= ~(UCR1_RRDYEN
);
734 writel(temp
, sport
->port
.membase
+ UCR1
);
736 /* tell the DMA to receive the data. */
740 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
743 static irqreturn_t
imx_int(int irq
, void *dev_id
)
745 struct imx_port
*sport
= dev_id
;
749 sts
= readl(sport
->port
.membase
+ USR1
);
750 sts2
= readl(sport
->port
.membase
+ USR2
);
752 if (sts
& USR1_RRDY
) {
753 if (sport
->dma_is_enabled
)
754 imx_dma_rxint(sport
);
756 imx_rxint(irq
, dev_id
);
759 if ((sts
& USR1_TRDY
&&
760 readl(sport
->port
.membase
+ UCR1
) & UCR1_TXMPTYEN
) ||
762 readl(sport
->port
.membase
+ UCR4
) & UCR4_TCEN
))
763 imx_txint(irq
, dev_id
);
766 imx_rtsint(irq
, dev_id
);
768 if (sts
& USR1_AWAKE
)
769 writel(USR1_AWAKE
, sport
->port
.membase
+ USR1
);
771 if (sts2
& USR2_ORE
) {
772 sport
->port
.icount
.overrun
++;
773 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
780 * Return TIOCSER_TEMT when transmitter is not busy.
782 static unsigned int imx_tx_empty(struct uart_port
*port
)
784 struct imx_port
*sport
= (struct imx_port
*)port
;
787 ret
= (readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
) ? TIOCSER_TEMT
: 0;
789 /* If the TX DMA is working, return 0. */
790 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
797 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
799 static unsigned int imx_get_mctrl(struct uart_port
*port
)
801 struct imx_port
*sport
= (struct imx_port
*)port
;
802 unsigned int tmp
= TIOCM_DSR
| TIOCM_CAR
;
804 if (readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
)
807 if (readl(sport
->port
.membase
+ UCR2
) & UCR2_CTS
)
810 if (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_LOOP
)
816 static void imx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
818 struct imx_port
*sport
= (struct imx_port
*)port
;
821 if (!(port
->rs485
.flags
& SER_RS485_ENABLED
)) {
822 temp
= readl(sport
->port
.membase
+ UCR2
);
823 temp
&= ~(UCR2_CTS
| UCR2_CTSC
);
824 if (mctrl
& TIOCM_RTS
)
825 temp
|= UCR2_CTS
| UCR2_CTSC
;
826 writel(temp
, sport
->port
.membase
+ UCR2
);
829 temp
= readl(sport
->port
.membase
+ uts_reg(sport
)) & ~UTS_LOOP
;
830 if (mctrl
& TIOCM_LOOP
)
832 writel(temp
, sport
->port
.membase
+ uts_reg(sport
));
836 * Interrupts always disabled.
838 static void imx_break_ctl(struct uart_port
*port
, int break_state
)
840 struct imx_port
*sport
= (struct imx_port
*)port
;
841 unsigned long flags
, temp
;
843 spin_lock_irqsave(&sport
->port
.lock
, flags
);
845 temp
= readl(sport
->port
.membase
+ UCR1
) & ~UCR1_SNDBRK
;
847 if (break_state
!= 0)
850 writel(temp
, sport
->port
.membase
+ UCR1
);
852 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
855 #define TXTL 2 /* reset default */
856 #define RXTL 1 /* reset default */
858 static void imx_setup_ufcr(struct imx_port
*sport
, unsigned int mode
)
862 /* set receiver / transmitter trigger level */
863 val
= readl(sport
->port
.membase
+ UFCR
) & (UFCR_RFDIV
| UFCR_DCEDTE
);
864 val
|= TXTL
<< UFCR_TXTL_SHF
| RXTL
;
865 writel(val
, sport
->port
.membase
+ UFCR
);
868 #define RX_BUF_SIZE (PAGE_SIZE)
869 static void imx_rx_dma_done(struct imx_port
*sport
)
874 spin_lock_irqsave(&sport
->port
.lock
, flags
);
876 /* Enable this interrupt when the RXFIFO is empty. */
877 temp
= readl(sport
->port
.membase
+ UCR1
);
879 writel(temp
, sport
->port
.membase
+ UCR1
);
881 sport
->dma_is_rxing
= 0;
883 /* Is the shutdown waiting for us? */
884 if (waitqueue_active(&sport
->dma_wait
))
885 wake_up(&sport
->dma_wait
);
887 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
891 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
892 * [1] the RX DMA buffer is full.
893 * [2] the Aging timer expires(wait for 8 bytes long)
894 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
896 * The [2] is trigger when a character was been sitting in the FIFO
897 * meanwhile [3] can wait for 32 bytes long when the RX line is
898 * on IDLE state and RxFIFO is empty.
900 static void dma_rx_callback(void *data
)
902 struct imx_port
*sport
= data
;
903 struct dma_chan
*chan
= sport
->dma_chan_rx
;
904 struct scatterlist
*sgl
= &sport
->rx_sgl
;
905 struct tty_port
*port
= &sport
->port
.state
->port
;
906 struct dma_tx_state state
;
907 enum dma_status status
;
911 dma_unmap_sg(sport
->port
.dev
, sgl
, 1, DMA_FROM_DEVICE
);
913 status
= dmaengine_tx_status(chan
, (dma_cookie_t
)0, &state
);
914 count
= RX_BUF_SIZE
- state
.residue
;
916 if (readl(sport
->port
.membase
+ USR2
) & USR2_IDLE
) {
917 /* In condition [3] the SDMA counted up too early */
920 writel(USR2_IDLE
, sport
->port
.membase
+ USR2
);
923 dev_dbg(sport
->port
.dev
, "We get %d bytes.\n", count
);
926 if (!(sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)) {
927 int bytes
= tty_insert_flip_string(port
, sport
->rx_buf
,
931 sport
->port
.icount
.buf_overrun
++;
933 tty_flip_buffer_push(port
);
936 } else if (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
) {
938 * start rx_dma directly once data in RXFIFO, more efficient
940 * 1. call imx_rx_dma_done to stop dma if no data received
941 * 2. wait next RDR interrupt to start dma transfer.
946 * stop dma to prevent too many IDLE event trigged if no data
949 imx_rx_dma_done(sport
);
953 static int start_rx_dma(struct imx_port
*sport
)
955 struct scatterlist
*sgl
= &sport
->rx_sgl
;
956 struct dma_chan
*chan
= sport
->dma_chan_rx
;
957 struct device
*dev
= sport
->port
.dev
;
958 struct dma_async_tx_descriptor
*desc
;
961 sg_init_one(sgl
, sport
->rx_buf
, RX_BUF_SIZE
);
962 ret
= dma_map_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
964 dev_err(dev
, "DMA mapping error for RX.\n");
967 desc
= dmaengine_prep_slave_sg(chan
, sgl
, 1, DMA_DEV_TO_MEM
,
970 dma_unmap_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
971 dev_err(dev
, "We cannot prepare for the RX slave dma!\n");
974 desc
->callback
= dma_rx_callback
;
975 desc
->callback_param
= sport
;
977 dev_dbg(dev
, "RX: prepare for the DMA.\n");
978 dmaengine_submit(desc
);
979 dma_async_issue_pending(chan
);
983 static void imx_uart_dma_exit(struct imx_port
*sport
)
985 if (sport
->dma_chan_rx
) {
986 dma_release_channel(sport
->dma_chan_rx
);
987 sport
->dma_chan_rx
= NULL
;
989 kfree(sport
->rx_buf
);
990 sport
->rx_buf
= NULL
;
993 if (sport
->dma_chan_tx
) {
994 dma_release_channel(sport
->dma_chan_tx
);
995 sport
->dma_chan_tx
= NULL
;
998 sport
->dma_is_inited
= 0;
1001 static int imx_uart_dma_init(struct imx_port
*sport
)
1003 struct dma_slave_config slave_config
= {};
1004 struct device
*dev
= sport
->port
.dev
;
1007 /* Prepare for RX : */
1008 sport
->dma_chan_rx
= dma_request_slave_channel(dev
, "rx");
1009 if (!sport
->dma_chan_rx
) {
1010 dev_dbg(dev
, "cannot get the DMA channel.\n");
1015 slave_config
.direction
= DMA_DEV_TO_MEM
;
1016 slave_config
.src_addr
= sport
->port
.mapbase
+ URXD0
;
1017 slave_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1018 slave_config
.src_maxburst
= RXTL
;
1019 ret
= dmaengine_slave_config(sport
->dma_chan_rx
, &slave_config
);
1021 dev_err(dev
, "error in RX dma configuration.\n");
1025 sport
->rx_buf
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1026 if (!sport
->rx_buf
) {
1031 /* Prepare for TX : */
1032 sport
->dma_chan_tx
= dma_request_slave_channel(dev
, "tx");
1033 if (!sport
->dma_chan_tx
) {
1034 dev_err(dev
, "cannot get the TX DMA channel!\n");
1039 slave_config
.direction
= DMA_MEM_TO_DEV
;
1040 slave_config
.dst_addr
= sport
->port
.mapbase
+ URTX0
;
1041 slave_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1042 slave_config
.dst_maxburst
= TXTL
;
1043 ret
= dmaengine_slave_config(sport
->dma_chan_tx
, &slave_config
);
1045 dev_err(dev
, "error in TX dma configuration.");
1049 sport
->dma_is_inited
= 1;
1053 imx_uart_dma_exit(sport
);
1057 static void imx_enable_dma(struct imx_port
*sport
)
1061 init_waitqueue_head(&sport
->dma_wait
);
1064 temp
= readl(sport
->port
.membase
+ UCR1
);
1065 temp
|= UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
|
1066 /* wait for 32 idle frames for IDDMA interrupt */
1068 writel(temp
, sport
->port
.membase
+ UCR1
);
1071 temp
= readl(sport
->port
.membase
+ UCR4
);
1072 temp
|= UCR4_IDDMAEN
;
1073 writel(temp
, sport
->port
.membase
+ UCR4
);
1075 sport
->dma_is_enabled
= 1;
1078 static void imx_disable_dma(struct imx_port
*sport
)
1083 temp
= readl(sport
->port
.membase
+ UCR1
);
1084 temp
&= ~(UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
);
1085 writel(temp
, sport
->port
.membase
+ UCR1
);
1088 temp
= readl(sport
->port
.membase
+ UCR2
);
1089 temp
&= ~(UCR2_CTSC
| UCR2_CTS
);
1090 writel(temp
, sport
->port
.membase
+ UCR2
);
1093 temp
= readl(sport
->port
.membase
+ UCR4
);
1094 temp
&= ~UCR4_IDDMAEN
;
1095 writel(temp
, sport
->port
.membase
+ UCR4
);
1097 sport
->dma_is_enabled
= 0;
1100 /* half the RX buffer size */
1103 static int imx_startup(struct uart_port
*port
)
1105 struct imx_port
*sport
= (struct imx_port
*)port
;
1107 unsigned long flags
, temp
;
1109 retval
= clk_prepare_enable(sport
->clk_per
);
1112 retval
= clk_prepare_enable(sport
->clk_ipg
);
1114 clk_disable_unprepare(sport
->clk_per
);
1118 imx_setup_ufcr(sport
, 0);
1120 /* disable the DREN bit (Data Ready interrupt enable) before
1123 temp
= readl(sport
->port
.membase
+ UCR4
);
1125 /* set the trigger level for CTS */
1126 temp
&= ~(UCR4_CTSTL_MASK
<< UCR4_CTSTL_SHF
);
1127 temp
|= CTSTL
<< UCR4_CTSTL_SHF
;
1129 writel(temp
& ~UCR4_DREN
, sport
->port
.membase
+ UCR4
);
1131 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1132 /* Reset fifo's and state machines */
1135 temp
= readl(sport
->port
.membase
+ UCR2
);
1137 writel(temp
, sport
->port
.membase
+ UCR2
);
1139 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1143 * Finally, clear and enable interrupts
1145 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
1146 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1148 temp
= readl(sport
->port
.membase
+ UCR1
);
1149 temp
|= UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
;
1151 writel(temp
, sport
->port
.membase
+ UCR1
);
1153 temp
= readl(sport
->port
.membase
+ UCR4
);
1155 writel(temp
, sport
->port
.membase
+ UCR4
);
1157 temp
= readl(sport
->port
.membase
+ UCR2
);
1158 temp
|= (UCR2_RXEN
| UCR2_TXEN
);
1159 if (!sport
->have_rtscts
)
1161 writel(temp
, sport
->port
.membase
+ UCR2
);
1163 if (!is_imx1_uart(sport
)) {
1164 temp
= readl(sport
->port
.membase
+ UCR3
);
1165 temp
|= IMX21_UCR3_RXDMUXSEL
| UCR3_ADNIMP
;
1166 writel(temp
, sport
->port
.membase
+ UCR3
);
1170 * Enable modem status interrupts
1172 imx_enable_ms(&sport
->port
);
1173 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1178 static void imx_shutdown(struct uart_port
*port
)
1180 struct imx_port
*sport
= (struct imx_port
*)port
;
1182 unsigned long flags
;
1184 if (sport
->dma_is_enabled
) {
1187 /* We have to wait for the DMA to finish. */
1188 ret
= wait_event_interruptible(sport
->dma_wait
,
1189 !sport
->dma_is_rxing
&& !sport
->dma_is_txing
);
1191 sport
->dma_is_rxing
= 0;
1192 sport
->dma_is_txing
= 0;
1193 dmaengine_terminate_all(sport
->dma_chan_tx
);
1194 dmaengine_terminate_all(sport
->dma_chan_rx
);
1196 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1199 imx_disable_dma(sport
);
1200 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1201 imx_uart_dma_exit(sport
);
1204 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1205 temp
= readl(sport
->port
.membase
+ UCR2
);
1206 temp
&= ~(UCR2_TXEN
);
1207 writel(temp
, sport
->port
.membase
+ UCR2
);
1208 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1213 del_timer_sync(&sport
->timer
);
1216 * Disable all interrupts, port and break condition.
1219 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1220 temp
= readl(sport
->port
.membase
+ UCR1
);
1221 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
);
1223 writel(temp
, sport
->port
.membase
+ UCR1
);
1224 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1226 clk_disable_unprepare(sport
->clk_per
);
1227 clk_disable_unprepare(sport
->clk_ipg
);
1230 static void imx_flush_buffer(struct uart_port
*port
)
1232 struct imx_port
*sport
= (struct imx_port
*)port
;
1233 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
1235 int i
= 100, ubir
, ubmr
, uts
;
1237 if (!sport
->dma_chan_tx
)
1240 sport
->tx_bytes
= 0;
1241 dmaengine_terminate_all(sport
->dma_chan_tx
);
1242 if (sport
->dma_is_txing
) {
1243 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
,
1245 temp
= readl(sport
->port
.membase
+ UCR1
);
1246 temp
&= ~UCR1_TDMAEN
;
1247 writel(temp
, sport
->port
.membase
+ UCR1
);
1248 sport
->dma_is_txing
= false;
1252 * According to the Reference Manual description of the UART SRST bit:
1253 * "Reset the transmit and receive state machines,
1254 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1255 * and UTS[6-3]". As we don't need to restore the old values from
1256 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1258 ubir
= readl(sport
->port
.membase
+ UBIR
);
1259 ubmr
= readl(sport
->port
.membase
+ UBMR
);
1260 uts
= readl(sport
->port
.membase
+ IMX21_UTS
);
1262 temp
= readl(sport
->port
.membase
+ UCR2
);
1264 writel(temp
, sport
->port
.membase
+ UCR2
);
1266 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1269 /* Restore the registers */
1270 writel(ubir
, sport
->port
.membase
+ UBIR
);
1271 writel(ubmr
, sport
->port
.membase
+ UBMR
);
1272 writel(uts
, sport
->port
.membase
+ IMX21_UTS
);
1276 imx_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1277 struct ktermios
*old
)
1279 struct imx_port
*sport
= (struct imx_port
*)port
;
1280 unsigned long flags
;
1281 unsigned int ucr2
, old_ucr1
, old_txrxen
, baud
, quot
;
1282 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1283 unsigned int div
, ufcr
;
1284 unsigned long num
, denom
;
1288 * We only support CS7 and CS8.
1290 while ((termios
->c_cflag
& CSIZE
) != CS7
&&
1291 (termios
->c_cflag
& CSIZE
) != CS8
) {
1292 termios
->c_cflag
&= ~CSIZE
;
1293 termios
->c_cflag
|= old_csize
;
1297 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1298 ucr2
= UCR2_WS
| UCR2_SRST
| UCR2_IRTS
;
1300 ucr2
= UCR2_SRST
| UCR2_IRTS
;
1302 if (termios
->c_cflag
& CRTSCTS
) {
1303 if (sport
->have_rtscts
) {
1306 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1308 * RTS is mandatory for rs485 operation, so keep
1309 * it under manual control and keep transmitter
1312 if (!(port
->rs485
.flags
&
1313 SER_RS485_RTS_AFTER_SEND
))
1319 /* Can we enable the DMA support? */
1320 if (is_imx6q_uart(sport
) && !uart_console(port
)
1321 && !sport
->dma_is_inited
)
1322 imx_uart_dma_init(sport
);
1324 termios
->c_cflag
&= ~CRTSCTS
;
1326 } else if (port
->rs485
.flags
& SER_RS485_ENABLED
)
1327 /* disable transmitter */
1328 if (!(port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
))
1331 if (termios
->c_cflag
& CSTOPB
)
1333 if (termios
->c_cflag
& PARENB
) {
1335 if (termios
->c_cflag
& PARODD
)
1339 del_timer_sync(&sport
->timer
);
1342 * Ask the core to calculate the divisor for us.
1344 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1345 quot
= uart_get_divisor(port
, baud
);
1347 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1349 sport
->port
.read_status_mask
= 0;
1350 if (termios
->c_iflag
& INPCK
)
1351 sport
->port
.read_status_mask
|= (URXD_FRMERR
| URXD_PRERR
);
1352 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
1353 sport
->port
.read_status_mask
|= URXD_BRK
;
1356 * Characters to ignore
1358 sport
->port
.ignore_status_mask
= 0;
1359 if (termios
->c_iflag
& IGNPAR
)
1360 sport
->port
.ignore_status_mask
|= URXD_PRERR
| URXD_FRMERR
;
1361 if (termios
->c_iflag
& IGNBRK
) {
1362 sport
->port
.ignore_status_mask
|= URXD_BRK
;
1364 * If we're ignoring parity and break indicators,
1365 * ignore overruns too (for real raw support).
1367 if (termios
->c_iflag
& IGNPAR
)
1368 sport
->port
.ignore_status_mask
|= URXD_OVRRUN
;
1371 if ((termios
->c_cflag
& CREAD
) == 0)
1372 sport
->port
.ignore_status_mask
|= URXD_DUMMY_READ
;
1375 * Update the per-port timeout.
1377 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1380 * disable interrupts and drain transmitter
1382 old_ucr1
= readl(sport
->port
.membase
+ UCR1
);
1383 writel(old_ucr1
& ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
),
1384 sport
->port
.membase
+ UCR1
);
1386 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
))
1389 /* then, disable everything */
1390 old_txrxen
= readl(sport
->port
.membase
+ UCR2
);
1391 writel(old_txrxen
& ~(UCR2_TXEN
| UCR2_RXEN
),
1392 sport
->port
.membase
+ UCR2
);
1393 old_txrxen
&= (UCR2_TXEN
| UCR2_RXEN
);
1395 /* custom-baudrate handling */
1396 div
= sport
->port
.uartclk
/ (baud
* 16);
1397 if (baud
== 38400 && quot
!= div
)
1398 baud
= sport
->port
.uartclk
/ (quot
* 16);
1400 div
= sport
->port
.uartclk
/ (baud
* 16);
1406 rational_best_approximation(16 * div
* baud
, sport
->port
.uartclk
,
1407 1 << 16, 1 << 16, &num
, &denom
);
1409 tdiv64
= sport
->port
.uartclk
;
1411 do_div(tdiv64
, denom
* 16 * div
);
1412 tty_termios_encode_baud_rate(termios
,
1413 (speed_t
)tdiv64
, (speed_t
)tdiv64
);
1418 ufcr
= readl(sport
->port
.membase
+ UFCR
);
1419 ufcr
= (ufcr
& (~UFCR_RFDIV
)) | UFCR_RFDIV_REG(div
);
1420 if (sport
->dte_mode
)
1421 ufcr
|= UFCR_DCEDTE
;
1422 writel(ufcr
, sport
->port
.membase
+ UFCR
);
1424 writel(num
, sport
->port
.membase
+ UBIR
);
1425 writel(denom
, sport
->port
.membase
+ UBMR
);
1427 if (!is_imx1_uart(sport
))
1428 writel(sport
->port
.uartclk
/ div
/ 1000,
1429 sport
->port
.membase
+ IMX21_ONEMS
);
1431 writel(old_ucr1
, sport
->port
.membase
+ UCR1
);
1433 /* set the parity, stop bits and data size */
1434 writel(ucr2
| old_txrxen
, sport
->port
.membase
+ UCR2
);
1436 if (UART_ENABLE_MS(&sport
->port
, termios
->c_cflag
))
1437 imx_enable_ms(&sport
->port
);
1439 if (sport
->dma_is_inited
&& !sport
->dma_is_enabled
)
1440 imx_enable_dma(sport
);
1441 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1444 static const char *imx_type(struct uart_port
*port
)
1446 struct imx_port
*sport
= (struct imx_port
*)port
;
1448 return sport
->port
.type
== PORT_IMX
? "IMX" : NULL
;
1452 * Configure/autoconfigure the port.
1454 static void imx_config_port(struct uart_port
*port
, int flags
)
1456 struct imx_port
*sport
= (struct imx_port
*)port
;
1458 if (flags
& UART_CONFIG_TYPE
)
1459 sport
->port
.type
= PORT_IMX
;
1463 * Verify the new serial_struct (for TIOCSSERIAL).
1464 * The only change we allow are to the flags and type, and
1465 * even then only between PORT_IMX and PORT_UNKNOWN
1468 imx_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1470 struct imx_port
*sport
= (struct imx_port
*)port
;
1473 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_IMX
)
1475 if (sport
->port
.irq
!= ser
->irq
)
1477 if (ser
->io_type
!= UPIO_MEM
)
1479 if (sport
->port
.uartclk
/ 16 != ser
->baud_base
)
1481 if (sport
->port
.mapbase
!= (unsigned long)ser
->iomem_base
)
1483 if (sport
->port
.iobase
!= ser
->port
)
1490 #if defined(CONFIG_CONSOLE_POLL)
1492 static int imx_poll_init(struct uart_port
*port
)
1494 struct imx_port
*sport
= (struct imx_port
*)port
;
1495 unsigned long flags
;
1499 retval
= clk_prepare_enable(sport
->clk_ipg
);
1502 retval
= clk_prepare_enable(sport
->clk_per
);
1504 clk_disable_unprepare(sport
->clk_ipg
);
1506 imx_setup_ufcr(sport
, 0);
1508 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1510 temp
= readl(sport
->port
.membase
+ UCR1
);
1511 if (is_imx1_uart(sport
))
1512 temp
|= IMX1_UCR1_UARTCLKEN
;
1513 temp
|= UCR1_UARTEN
| UCR1_RRDYEN
;
1514 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1515 writel(temp
, sport
->port
.membase
+ UCR1
);
1517 temp
= readl(sport
->port
.membase
+ UCR2
);
1519 writel(temp
, sport
->port
.membase
+ UCR2
);
1521 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1526 static int imx_poll_get_char(struct uart_port
*port
)
1528 if (!(readl_relaxed(port
->membase
+ USR2
) & USR2_RDR
))
1529 return NO_POLL_CHAR
;
1531 return readl_relaxed(port
->membase
+ URXD0
) & URXD_RX_DATA
;
1534 static void imx_poll_put_char(struct uart_port
*port
, unsigned char c
)
1536 unsigned int status
;
1540 status
= readl_relaxed(port
->membase
+ USR1
);
1541 } while (~status
& USR1_TRDY
);
1544 writel_relaxed(c
, port
->membase
+ URTX0
);
1548 status
= readl_relaxed(port
->membase
+ USR2
);
1549 } while (~status
& USR2_TXDC
);
1553 static int imx_rs485_config(struct uart_port
*port
,
1554 struct serial_rs485
*rs485conf
)
1556 struct imx_port
*sport
= (struct imx_port
*)port
;
1559 rs485conf
->delay_rts_before_send
= 0;
1560 rs485conf
->delay_rts_after_send
= 0;
1561 rs485conf
->flags
|= SER_RS485_RX_DURING_TX
;
1563 /* RTS is required to control the transmitter */
1564 if (!sport
->have_rtscts
)
1565 rs485conf
->flags
&= ~SER_RS485_ENABLED
;
1567 if (rs485conf
->flags
& SER_RS485_ENABLED
) {
1570 /* disable transmitter */
1571 temp
= readl(sport
->port
.membase
+ UCR2
);
1573 if (rs485conf
->flags
& SER_RS485_RTS_AFTER_SEND
)
1577 writel(temp
, sport
->port
.membase
+ UCR2
);
1580 port
->rs485
= *rs485conf
;
1585 static struct uart_ops imx_pops
= {
1586 .tx_empty
= imx_tx_empty
,
1587 .set_mctrl
= imx_set_mctrl
,
1588 .get_mctrl
= imx_get_mctrl
,
1589 .stop_tx
= imx_stop_tx
,
1590 .start_tx
= imx_start_tx
,
1591 .stop_rx
= imx_stop_rx
,
1592 .enable_ms
= imx_enable_ms
,
1593 .break_ctl
= imx_break_ctl
,
1594 .startup
= imx_startup
,
1595 .shutdown
= imx_shutdown
,
1596 .flush_buffer
= imx_flush_buffer
,
1597 .set_termios
= imx_set_termios
,
1599 .config_port
= imx_config_port
,
1600 .verify_port
= imx_verify_port
,
1601 #if defined(CONFIG_CONSOLE_POLL)
1602 .poll_init
= imx_poll_init
,
1603 .poll_get_char
= imx_poll_get_char
,
1604 .poll_put_char
= imx_poll_put_char
,
1608 static struct imx_port
*imx_ports
[UART_NR
];
1610 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1611 static void imx_console_putchar(struct uart_port
*port
, int ch
)
1613 struct imx_port
*sport
= (struct imx_port
*)port
;
1615 while (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)
1618 writel(ch
, sport
->port
.membase
+ URTX0
);
1622 * Interrupts are disabled on entering
1625 imx_console_write(struct console
*co
, const char *s
, unsigned int count
)
1627 struct imx_port
*sport
= imx_ports
[co
->index
];
1628 struct imx_port_ucrs old_ucr
;
1630 unsigned long flags
= 0;
1634 retval
= clk_prepare_enable(sport
->clk_per
);
1637 retval
= clk_prepare_enable(sport
->clk_ipg
);
1639 clk_disable_unprepare(sport
->clk_per
);
1643 if (sport
->port
.sysrq
)
1645 else if (oops_in_progress
)
1646 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1648 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1651 * First, save UCR1/2/3 and then disable interrupts
1653 imx_port_ucrs_save(&sport
->port
, &old_ucr
);
1654 ucr1
= old_ucr
.ucr1
;
1656 if (is_imx1_uart(sport
))
1657 ucr1
|= IMX1_UCR1_UARTCLKEN
;
1658 ucr1
|= UCR1_UARTEN
;
1659 ucr1
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
);
1661 writel(ucr1
, sport
->port
.membase
+ UCR1
);
1663 writel(old_ucr
.ucr2
| UCR2_TXEN
, sport
->port
.membase
+ UCR2
);
1665 uart_console_write(&sport
->port
, s
, count
, imx_console_putchar
);
1668 * Finally, wait for transmitter to become empty
1669 * and restore UCR1/2/3
1671 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
));
1673 imx_port_ucrs_restore(&sport
->port
, &old_ucr
);
1676 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1678 clk_disable_unprepare(sport
->clk_ipg
);
1679 clk_disable_unprepare(sport
->clk_per
);
1683 * If the port was already initialised (eg, by a boot loader),
1684 * try to determine the current setup.
1687 imx_console_get_options(struct imx_port
*sport
, int *baud
,
1688 int *parity
, int *bits
)
1691 if (readl(sport
->port
.membase
+ UCR1
) & UCR1_UARTEN
) {
1692 /* ok, the port was enabled */
1693 unsigned int ucr2
, ubir
, ubmr
, uartclk
;
1694 unsigned int baud_raw
;
1695 unsigned int ucfr_rfdiv
;
1697 ucr2
= readl(sport
->port
.membase
+ UCR2
);
1700 if (ucr2
& UCR2_PREN
) {
1701 if (ucr2
& UCR2_PROE
)
1712 ubir
= readl(sport
->port
.membase
+ UBIR
) & 0xffff;
1713 ubmr
= readl(sport
->port
.membase
+ UBMR
) & 0xffff;
1715 ucfr_rfdiv
= (readl(sport
->port
.membase
+ UFCR
) & UFCR_RFDIV
) >> 7;
1716 if (ucfr_rfdiv
== 6)
1719 ucfr_rfdiv
= 6 - ucfr_rfdiv
;
1721 uartclk
= clk_get_rate(sport
->clk_per
);
1722 uartclk
/= ucfr_rfdiv
;
1725 * The next code provides exact computation of
1726 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1727 * without need of float support or long long division,
1728 * which would be required to prevent 32bit arithmetic overflow
1730 unsigned int mul
= ubir
+ 1;
1731 unsigned int div
= 16 * (ubmr
+ 1);
1732 unsigned int rem
= uartclk
% div
;
1734 baud_raw
= (uartclk
/ div
) * mul
;
1735 baud_raw
+= (rem
* mul
+ div
/ 2) / div
;
1736 *baud
= (baud_raw
+ 50) / 100 * 100;
1739 if (*baud
!= baud_raw
)
1740 pr_info("Console IMX rounded baud rate from %d to %d\n",
1746 imx_console_setup(struct console
*co
, char *options
)
1748 struct imx_port
*sport
;
1756 * Check whether an invalid uart number has been specified, and
1757 * if so, search for the first available port that does have
1760 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(imx_ports
))
1762 sport
= imx_ports
[co
->index
];
1766 /* For setting the registers, we only need to enable the ipg clock. */
1767 retval
= clk_prepare_enable(sport
->clk_ipg
);
1772 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1774 imx_console_get_options(sport
, &baud
, &parity
, &bits
);
1776 imx_setup_ufcr(sport
, 0);
1778 retval
= uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1780 clk_disable_unprepare(sport
->clk_ipg
);
1786 static struct uart_driver imx_reg
;
1787 static struct console imx_console
= {
1789 .write
= imx_console_write
,
1790 .device
= uart_console_device
,
1791 .setup
= imx_console_setup
,
1792 .flags
= CON_PRINTBUFFER
,
1797 #define IMX_CONSOLE &imx_console
1799 #define IMX_CONSOLE NULL
1802 static struct uart_driver imx_reg
= {
1803 .owner
= THIS_MODULE
,
1804 .driver_name
= DRIVER_NAME
,
1805 .dev_name
= DEV_NAME
,
1806 .major
= SERIAL_IMX_MAJOR
,
1807 .minor
= MINOR_START
,
1808 .nr
= ARRAY_SIZE(imx_ports
),
1809 .cons
= IMX_CONSOLE
,
1814 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1815 * could successfully get all information from dt or a negative errno.
1817 static int serial_imx_probe_dt(struct imx_port
*sport
,
1818 struct platform_device
*pdev
)
1820 struct device_node
*np
= pdev
->dev
.of_node
;
1821 const struct of_device_id
*of_id
=
1822 of_match_device(imx_uart_dt_ids
, &pdev
->dev
);
1826 /* no device tree device */
1829 ret
= of_alias_get_id(np
, "serial");
1831 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
1834 sport
->port
.line
= ret
;
1836 if (of_get_property(np
, "fsl,uart-has-rtscts", NULL
))
1837 sport
->have_rtscts
= 1;
1839 if (of_get_property(np
, "fsl,dte-mode", NULL
))
1840 sport
->dte_mode
= 1;
1842 sport
->devdata
= of_id
->data
;
1847 static inline int serial_imx_probe_dt(struct imx_port
*sport
,
1848 struct platform_device
*pdev
)
1854 static void serial_imx_probe_pdata(struct imx_port
*sport
,
1855 struct platform_device
*pdev
)
1857 struct imxuart_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
1859 sport
->port
.line
= pdev
->id
;
1860 sport
->devdata
= (struct imx_uart_data
*) pdev
->id_entry
->driver_data
;
1865 if (pdata
->flags
& IMXUART_HAVE_RTSCTS
)
1866 sport
->have_rtscts
= 1;
1869 static int serial_imx_probe(struct platform_device
*pdev
)
1871 struct imx_port
*sport
;
1874 struct resource
*res
;
1875 int txirq
, rxirq
, rtsirq
;
1877 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
1881 ret
= serial_imx_probe_dt(sport
, pdev
);
1883 serial_imx_probe_pdata(sport
, pdev
);
1887 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1888 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1890 return PTR_ERR(base
);
1892 rxirq
= platform_get_irq(pdev
, 0);
1893 txirq
= platform_get_irq(pdev
, 1);
1894 rtsirq
= platform_get_irq(pdev
, 2);
1896 sport
->port
.dev
= &pdev
->dev
;
1897 sport
->port
.mapbase
= res
->start
;
1898 sport
->port
.membase
= base
;
1899 sport
->port
.type
= PORT_IMX
,
1900 sport
->port
.iotype
= UPIO_MEM
;
1901 sport
->port
.irq
= rxirq
;
1902 sport
->port
.fifosize
= 32;
1903 sport
->port
.ops
= &imx_pops
;
1904 sport
->port
.rs485_config
= imx_rs485_config
;
1905 sport
->port
.rs485
.flags
=
1906 SER_RS485_RTS_ON_SEND
| SER_RS485_RX_DURING_TX
;
1907 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
1908 init_timer(&sport
->timer
);
1909 sport
->timer
.function
= imx_timeout
;
1910 sport
->timer
.data
= (unsigned long)sport
;
1912 sport
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
1913 if (IS_ERR(sport
->clk_ipg
)) {
1914 ret
= PTR_ERR(sport
->clk_ipg
);
1915 dev_err(&pdev
->dev
, "failed to get ipg clk: %d\n", ret
);
1919 sport
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
1920 if (IS_ERR(sport
->clk_per
)) {
1921 ret
= PTR_ERR(sport
->clk_per
);
1922 dev_err(&pdev
->dev
, "failed to get per clk: %d\n", ret
);
1926 sport
->port
.uartclk
= clk_get_rate(sport
->clk_per
);
1928 /* For register access, we only need to enable the ipg clock. */
1929 ret
= clk_prepare_enable(sport
->clk_ipg
);
1933 /* Disable interrupts before requesting them */
1934 reg
= readl_relaxed(sport
->port
.membase
+ UCR1
);
1935 reg
&= ~(UCR1_ADEN
| UCR1_TRDYEN
| UCR1_IDEN
| UCR1_RRDYEN
|
1936 UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1937 writel_relaxed(reg
, sport
->port
.membase
+ UCR1
);
1939 clk_disable_unprepare(sport
->clk_ipg
);
1942 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1943 * chips only have one interrupt.
1946 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_rxint
, 0,
1947 dev_name(&pdev
->dev
), sport
);
1951 ret
= devm_request_irq(&pdev
->dev
, txirq
, imx_txint
, 0,
1952 dev_name(&pdev
->dev
), sport
);
1956 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_int
, 0,
1957 dev_name(&pdev
->dev
), sport
);
1962 imx_ports
[sport
->port
.line
] = sport
;
1964 platform_set_drvdata(pdev
, sport
);
1966 return uart_add_one_port(&imx_reg
, &sport
->port
);
1969 static int serial_imx_remove(struct platform_device
*pdev
)
1971 struct imx_port
*sport
= platform_get_drvdata(pdev
);
1973 return uart_remove_one_port(&imx_reg
, &sport
->port
);
1976 static void serial_imx_restore_context(struct imx_port
*sport
)
1978 if (!sport
->context_saved
)
1981 writel(sport
->saved_reg
[4], sport
->port
.membase
+ UFCR
);
1982 writel(sport
->saved_reg
[5], sport
->port
.membase
+ UESC
);
1983 writel(sport
->saved_reg
[6], sport
->port
.membase
+ UTIM
);
1984 writel(sport
->saved_reg
[7], sport
->port
.membase
+ UBIR
);
1985 writel(sport
->saved_reg
[8], sport
->port
.membase
+ UBMR
);
1986 writel(sport
->saved_reg
[9], sport
->port
.membase
+ IMX21_UTS
);
1987 writel(sport
->saved_reg
[0], sport
->port
.membase
+ UCR1
);
1988 writel(sport
->saved_reg
[1] | UCR2_SRST
, sport
->port
.membase
+ UCR2
);
1989 writel(sport
->saved_reg
[2], sport
->port
.membase
+ UCR3
);
1990 writel(sport
->saved_reg
[3], sport
->port
.membase
+ UCR4
);
1991 sport
->context_saved
= false;
1994 static void serial_imx_save_context(struct imx_port
*sport
)
1996 /* Save necessary regs */
1997 sport
->saved_reg
[0] = readl(sport
->port
.membase
+ UCR1
);
1998 sport
->saved_reg
[1] = readl(sport
->port
.membase
+ UCR2
);
1999 sport
->saved_reg
[2] = readl(sport
->port
.membase
+ UCR3
);
2000 sport
->saved_reg
[3] = readl(sport
->port
.membase
+ UCR4
);
2001 sport
->saved_reg
[4] = readl(sport
->port
.membase
+ UFCR
);
2002 sport
->saved_reg
[5] = readl(sport
->port
.membase
+ UESC
);
2003 sport
->saved_reg
[6] = readl(sport
->port
.membase
+ UTIM
);
2004 sport
->saved_reg
[7] = readl(sport
->port
.membase
+ UBIR
);
2005 sport
->saved_reg
[8] = readl(sport
->port
.membase
+ UBMR
);
2006 sport
->saved_reg
[9] = readl(sport
->port
.membase
+ IMX21_UTS
);
2007 sport
->context_saved
= true;
2010 static void serial_imx_enable_wakeup(struct imx_port
*sport
, bool on
)
2014 val
= readl(sport
->port
.membase
+ UCR3
);
2018 val
&= ~UCR3_AWAKEN
;
2019 writel(val
, sport
->port
.membase
+ UCR3
);
2021 val
= readl(sport
->port
.membase
+ UCR1
);
2025 val
&= ~UCR1_RTSDEN
;
2026 writel(val
, sport
->port
.membase
+ UCR1
);
2029 static int imx_serial_port_suspend_noirq(struct device
*dev
)
2031 struct platform_device
*pdev
= to_platform_device(dev
);
2032 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2035 ret
= clk_enable(sport
->clk_ipg
);
2039 serial_imx_save_context(sport
);
2041 clk_disable(sport
->clk_ipg
);
2046 static int imx_serial_port_resume_noirq(struct device
*dev
)
2048 struct platform_device
*pdev
= to_platform_device(dev
);
2049 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2052 ret
= clk_enable(sport
->clk_ipg
);
2056 serial_imx_restore_context(sport
);
2058 clk_disable(sport
->clk_ipg
);
2063 static int imx_serial_port_suspend(struct device
*dev
)
2065 struct platform_device
*pdev
= to_platform_device(dev
);
2066 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2068 /* enable wakeup from i.MX UART */
2069 serial_imx_enable_wakeup(sport
, true);
2071 uart_suspend_port(&imx_reg
, &sport
->port
);
2076 static int imx_serial_port_resume(struct device
*dev
)
2078 struct platform_device
*pdev
= to_platform_device(dev
);
2079 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2081 /* disable wakeup from i.MX UART */
2082 serial_imx_enable_wakeup(sport
, false);
2084 uart_resume_port(&imx_reg
, &sport
->port
);
2089 static const struct dev_pm_ops imx_serial_port_pm_ops
= {
2090 .suspend_noirq
= imx_serial_port_suspend_noirq
,
2091 .resume_noirq
= imx_serial_port_resume_noirq
,
2092 .suspend
= imx_serial_port_suspend
,
2093 .resume
= imx_serial_port_resume
,
2096 static struct platform_driver serial_imx_driver
= {
2097 .probe
= serial_imx_probe
,
2098 .remove
= serial_imx_remove
,
2100 .id_table
= imx_uart_devtype
,
2103 .of_match_table
= imx_uart_dt_ids
,
2104 .pm
= &imx_serial_port_pm_ops
,
2108 static int __init
imx_serial_init(void)
2110 int ret
= uart_register_driver(&imx_reg
);
2115 ret
= platform_driver_register(&serial_imx_driver
);
2117 uart_unregister_driver(&imx_reg
);
2122 static void __exit
imx_serial_exit(void)
2124 platform_driver_unregister(&serial_imx_driver
);
2125 uart_unregister_driver(&imx_reg
);
2128 module_init(imx_serial_init
);
2129 module_exit(imx_serial_exit
);
2131 MODULE_AUTHOR("Sascha Hauer");
2132 MODULE_DESCRIPTION("IMX generic serial port driver");
2133 MODULE_LICENSE("GPL");
2134 MODULE_ALIAS("platform:imx-uart");