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Merge tag 'for-linus-4.3-merge-window-part-1' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola/Freescale IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
46
47 /* Register definitions */
48 #define URXD0 0x0 /* Receiver Register */
49 #define URTX0 0x40 /* Transmitter Register */
50 #define UCR1 0x80 /* Control Register 1 */
51 #define UCR2 0x84 /* Control Register 2 */
52 #define UCR3 0x88 /* Control Register 3 */
53 #define UCR4 0x8c /* Control Register 4 */
54 #define UFCR 0x90 /* FIFO Control Register */
55 #define USR1 0x94 /* Status Register 1 */
56 #define USR2 0x98 /* Status Register 2 */
57 #define UESC 0x9c /* Escape Character Register */
58 #define UTIM 0xa0 /* Escape Timer Register */
59 #define UBIR 0xa4 /* BRM Incremental Register */
60 #define UBMR 0xa8 /* BRM Modulator Register */
61 #define UBRC 0xac /* Baud Rate Count Register */
62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
65
66 /* UART Control Register Bit Fields.*/
67 #define URXD_DUMMY_READ (1<<16)
68 #define URXD_CHARRDY (1<<15)
69 #define URXD_ERR (1<<14)
70 #define URXD_OVRRUN (1<<13)
71 #define URXD_FRMERR (1<<12)
72 #define URXD_BRK (1<<11)
73 #define URXD_PRERR (1<<10)
74 #define URXD_RX_DATA (0xFF<<0)
75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82 #define UCR1_IREN (1<<7) /* Infrared interface enable */
83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85 #define UCR1_SNDBRK (1<<4) /* Send break */
86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
89 #define UCR1_DOZE (1<<1) /* Doze */
90 #define UCR1_UARTEN (1<<0) /* UART enabled */
91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93 #define UCR2_CTSC (1<<13) /* CTS pin control */
94 #define UCR2_CTS (1<<12) /* Clear to send */
95 #define UCR2_ESCEN (1<<11) /* Escape enable */
96 #define UCR2_PREN (1<<8) /* Parity enable */
97 #define UCR2_PROE (1<<7) /* Parity odd/even */
98 #define UCR2_STPB (1<<6) /* Stop */
99 #define UCR2_WS (1<<5) /* Word size */
100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
103 #define UCR2_RXEN (1<<1) /* Receiver enabled */
104 #define UCR2_SRST (1<<0) /* SW reset */
105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106 #define UCR3_PARERREN (1<<12) /* Parity enable */
107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108 #define UCR3_DSR (1<<10) /* Data set ready */
109 #define UCR3_DCD (1<<9) /* Data carrier detect */
110 #define UCR3_RI (1<<8) /* Ring indicator */
111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117 #define UCR3_BPEN (1<<0) /* Preset registers enable */
118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
125 #define UCR4_IRSC (1<<5) /* IR special case */
126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
164
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 207
167 #define MINOR_START 16
168 #define DEV_NAME "ttymxc"
169
170 /*
171 * This determines how often we check the modem status signals
172 * for any change. They generally aren't connected to an IRQ
173 * so we have to poll them. We also check immediately before
174 * filling the TX fifo incase CTS has been dropped.
175 */
176 #define MCTRL_TIMEOUT (250*HZ/1000)
177
178 #define DRIVER_NAME "IMX-uart"
179
180 #define UART_NR 8
181
182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
183 enum imx_uart_type {
184 IMX1_UART,
185 IMX21_UART,
186 IMX6Q_UART,
187 };
188
189 /* device type dependent stuff */
190 struct imx_uart_data {
191 unsigned uts_reg;
192 enum imx_uart_type devtype;
193 };
194
195 struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int dte_mode:1;
201 unsigned int irda_inv_rx:1;
202 unsigned int irda_inv_tx:1;
203 unsigned short trcv_delay; /* transceiver delay */
204 struct clk *clk_ipg;
205 struct clk *clk_per;
206 const struct imx_uart_data *devdata;
207
208 /* DMA fields */
209 unsigned int dma_is_inited:1;
210 unsigned int dma_is_enabled:1;
211 unsigned int dma_is_rxing:1;
212 unsigned int dma_is_txing:1;
213 struct dma_chan *dma_chan_rx, *dma_chan_tx;
214 struct scatterlist rx_sgl, tx_sgl[2];
215 void *rx_buf;
216 unsigned int tx_bytes;
217 unsigned int dma_tx_nents;
218 wait_queue_head_t dma_wait;
219 unsigned int saved_reg[10];
220 bool context_saved;
221 };
222
223 struct imx_port_ucrs {
224 unsigned int ucr1;
225 unsigned int ucr2;
226 unsigned int ucr3;
227 };
228
229 static struct imx_uart_data imx_uart_devdata[] = {
230 [IMX1_UART] = {
231 .uts_reg = IMX1_UTS,
232 .devtype = IMX1_UART,
233 },
234 [IMX21_UART] = {
235 .uts_reg = IMX21_UTS,
236 .devtype = IMX21_UART,
237 },
238 [IMX6Q_UART] = {
239 .uts_reg = IMX21_UTS,
240 .devtype = IMX6Q_UART,
241 },
242 };
243
244 static const struct platform_device_id imx_uart_devtype[] = {
245 {
246 .name = "imx1-uart",
247 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
248 }, {
249 .name = "imx21-uart",
250 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
251 }, {
252 .name = "imx6q-uart",
253 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
254 }, {
255 /* sentinel */
256 }
257 };
258 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
259
260 static const struct of_device_id imx_uart_dt_ids[] = {
261 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
262 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
263 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
264 { /* sentinel */ }
265 };
266 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
267
268 static inline unsigned uts_reg(struct imx_port *sport)
269 {
270 return sport->devdata->uts_reg;
271 }
272
273 static inline int is_imx1_uart(struct imx_port *sport)
274 {
275 return sport->devdata->devtype == IMX1_UART;
276 }
277
278 static inline int is_imx21_uart(struct imx_port *sport)
279 {
280 return sport->devdata->devtype == IMX21_UART;
281 }
282
283 static inline int is_imx6q_uart(struct imx_port *sport)
284 {
285 return sport->devdata->devtype == IMX6Q_UART;
286 }
287 /*
288 * Save and restore functions for UCR1, UCR2 and UCR3 registers
289 */
290 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
291 static void imx_port_ucrs_save(struct uart_port *port,
292 struct imx_port_ucrs *ucr)
293 {
294 /* save control registers */
295 ucr->ucr1 = readl(port->membase + UCR1);
296 ucr->ucr2 = readl(port->membase + UCR2);
297 ucr->ucr3 = readl(port->membase + UCR3);
298 }
299
300 static void imx_port_ucrs_restore(struct uart_port *port,
301 struct imx_port_ucrs *ucr)
302 {
303 /* restore control registers */
304 writel(ucr->ucr1, port->membase + UCR1);
305 writel(ucr->ucr2, port->membase + UCR2);
306 writel(ucr->ucr3, port->membase + UCR3);
307 }
308 #endif
309
310 /*
311 * Handle any change of modem status signal since we were last called.
312 */
313 static void imx_mctrl_check(struct imx_port *sport)
314 {
315 unsigned int status, changed;
316
317 status = sport->port.ops->get_mctrl(&sport->port);
318 changed = status ^ sport->old_status;
319
320 if (changed == 0)
321 return;
322
323 sport->old_status = status;
324
325 if (changed & TIOCM_RI)
326 sport->port.icount.rng++;
327 if (changed & TIOCM_DSR)
328 sport->port.icount.dsr++;
329 if (changed & TIOCM_CAR)
330 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
331 if (changed & TIOCM_CTS)
332 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
333
334 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
335 }
336
337 /*
338 * This is our per-port timeout handler, for checking the
339 * modem status signals.
340 */
341 static void imx_timeout(unsigned long data)
342 {
343 struct imx_port *sport = (struct imx_port *)data;
344 unsigned long flags;
345
346 if (sport->port.state) {
347 spin_lock_irqsave(&sport->port.lock, flags);
348 imx_mctrl_check(sport);
349 spin_unlock_irqrestore(&sport->port.lock, flags);
350
351 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
352 }
353 }
354
355 /*
356 * interrupts disabled on entry
357 */
358 static void imx_stop_tx(struct uart_port *port)
359 {
360 struct imx_port *sport = (struct imx_port *)port;
361 unsigned long temp;
362
363 /*
364 * We are maybe in the SMP context, so if the DMA TX thread is running
365 * on other cpu, we have to wait for it to finish.
366 */
367 if (sport->dma_is_enabled && sport->dma_is_txing)
368 return;
369
370 temp = readl(port->membase + UCR1);
371 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
372
373 /* in rs485 mode disable transmitter if shifter is empty */
374 if (port->rs485.flags & SER_RS485_ENABLED &&
375 readl(port->membase + USR2) & USR2_TXDC) {
376 temp = readl(port->membase + UCR2);
377 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
378 temp &= ~UCR2_CTS;
379 else
380 temp |= UCR2_CTS;
381 writel(temp, port->membase + UCR2);
382
383 temp = readl(port->membase + UCR4);
384 temp &= ~UCR4_TCEN;
385 writel(temp, port->membase + UCR4);
386 }
387 }
388
389 /*
390 * interrupts disabled on entry
391 */
392 static void imx_stop_rx(struct uart_port *port)
393 {
394 struct imx_port *sport = (struct imx_port *)port;
395 unsigned long temp;
396
397 if (sport->dma_is_enabled && sport->dma_is_rxing) {
398 if (sport->port.suspended) {
399 dmaengine_terminate_all(sport->dma_chan_rx);
400 sport->dma_is_rxing = 0;
401 } else {
402 return;
403 }
404 }
405
406 temp = readl(sport->port.membase + UCR2);
407 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
408
409 /* disable the `Receiver Ready Interrrupt` */
410 temp = readl(sport->port.membase + UCR1);
411 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
412 }
413
414 /*
415 * Set the modem control timer to fire immediately.
416 */
417 static void imx_enable_ms(struct uart_port *port)
418 {
419 struct imx_port *sport = (struct imx_port *)port;
420
421 mod_timer(&sport->timer, jiffies);
422 }
423
424 static void imx_dma_tx(struct imx_port *sport);
425 static inline void imx_transmit_buffer(struct imx_port *sport)
426 {
427 struct circ_buf *xmit = &sport->port.state->xmit;
428 unsigned long temp;
429
430 if (sport->port.x_char) {
431 /* Send next char */
432 writel(sport->port.x_char, sport->port.membase + URTX0);
433 sport->port.icount.tx++;
434 sport->port.x_char = 0;
435 return;
436 }
437
438 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
439 imx_stop_tx(&sport->port);
440 return;
441 }
442
443 if (sport->dma_is_enabled) {
444 /*
445 * We've just sent a X-char Ensure the TX DMA is enabled
446 * and the TX IRQ is disabled.
447 **/
448 temp = readl(sport->port.membase + UCR1);
449 temp &= ~UCR1_TXMPTYEN;
450 if (sport->dma_is_txing) {
451 temp |= UCR1_TDMAEN;
452 writel(temp, sport->port.membase + UCR1);
453 } else {
454 writel(temp, sport->port.membase + UCR1);
455 imx_dma_tx(sport);
456 }
457 }
458
459 while (!uart_circ_empty(xmit) &&
460 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
461 /* send xmit->buf[xmit->tail]
462 * out the port here */
463 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
464 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
465 sport->port.icount.tx++;
466 }
467
468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
469 uart_write_wakeup(&sport->port);
470
471 if (uart_circ_empty(xmit))
472 imx_stop_tx(&sport->port);
473 }
474
475 static void dma_tx_callback(void *data)
476 {
477 struct imx_port *sport = data;
478 struct scatterlist *sgl = &sport->tx_sgl[0];
479 struct circ_buf *xmit = &sport->port.state->xmit;
480 unsigned long flags;
481 unsigned long temp;
482
483 spin_lock_irqsave(&sport->port.lock, flags);
484
485 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
486
487 temp = readl(sport->port.membase + UCR1);
488 temp &= ~UCR1_TDMAEN;
489 writel(temp, sport->port.membase + UCR1);
490
491 /* update the stat */
492 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
493 sport->port.icount.tx += sport->tx_bytes;
494
495 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
496
497 sport->dma_is_txing = 0;
498
499 spin_unlock_irqrestore(&sport->port.lock, flags);
500
501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
502 uart_write_wakeup(&sport->port);
503
504 if (waitqueue_active(&sport->dma_wait)) {
505 wake_up(&sport->dma_wait);
506 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
507 return;
508 }
509
510 spin_lock_irqsave(&sport->port.lock, flags);
511 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
512 imx_dma_tx(sport);
513 spin_unlock_irqrestore(&sport->port.lock, flags);
514 }
515
516 static void imx_dma_tx(struct imx_port *sport)
517 {
518 struct circ_buf *xmit = &sport->port.state->xmit;
519 struct scatterlist *sgl = sport->tx_sgl;
520 struct dma_async_tx_descriptor *desc;
521 struct dma_chan *chan = sport->dma_chan_tx;
522 struct device *dev = sport->port.dev;
523 unsigned long temp;
524 int ret;
525
526 if (sport->dma_is_txing)
527 return;
528
529 sport->tx_bytes = uart_circ_chars_pending(xmit);
530
531 if (xmit->tail < xmit->head) {
532 sport->dma_tx_nents = 1;
533 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
534 } else {
535 sport->dma_tx_nents = 2;
536 sg_init_table(sgl, 2);
537 sg_set_buf(sgl, xmit->buf + xmit->tail,
538 UART_XMIT_SIZE - xmit->tail);
539 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
540 }
541
542 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
543 if (ret == 0) {
544 dev_err(dev, "DMA mapping error for TX.\n");
545 return;
546 }
547 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
548 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
549 if (!desc) {
550 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
551 DMA_TO_DEVICE);
552 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
553 return;
554 }
555 desc->callback = dma_tx_callback;
556 desc->callback_param = sport;
557
558 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
559 uart_circ_chars_pending(xmit));
560
561 temp = readl(sport->port.membase + UCR1);
562 temp |= UCR1_TDMAEN;
563 writel(temp, sport->port.membase + UCR1);
564
565 /* fire it */
566 sport->dma_is_txing = 1;
567 dmaengine_submit(desc);
568 dma_async_issue_pending(chan);
569 return;
570 }
571
572 /*
573 * interrupts disabled on entry
574 */
575 static void imx_start_tx(struct uart_port *port)
576 {
577 struct imx_port *sport = (struct imx_port *)port;
578 unsigned long temp;
579
580 if (port->rs485.flags & SER_RS485_ENABLED) {
581 /* enable transmitter and shifter empty irq */
582 temp = readl(port->membase + UCR2);
583 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
584 temp &= ~UCR2_CTS;
585 else
586 temp |= UCR2_CTS;
587 writel(temp, port->membase + UCR2);
588
589 temp = readl(port->membase + UCR4);
590 temp |= UCR4_TCEN;
591 writel(temp, port->membase + UCR4);
592 }
593
594 if (!sport->dma_is_enabled) {
595 temp = readl(sport->port.membase + UCR1);
596 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
597 }
598
599 if (sport->dma_is_enabled) {
600 if (sport->port.x_char) {
601 /* We have X-char to send, so enable TX IRQ and
602 * disable TX DMA to let TX interrupt to send X-char */
603 temp = readl(sport->port.membase + UCR1);
604 temp &= ~UCR1_TDMAEN;
605 temp |= UCR1_TXMPTYEN;
606 writel(temp, sport->port.membase + UCR1);
607 return;
608 }
609
610 if (!uart_circ_empty(&port->state->xmit) &&
611 !uart_tx_stopped(port))
612 imx_dma_tx(sport);
613 return;
614 }
615 }
616
617 static irqreturn_t imx_rtsint(int irq, void *dev_id)
618 {
619 struct imx_port *sport = dev_id;
620 unsigned int val;
621 unsigned long flags;
622
623 spin_lock_irqsave(&sport->port.lock, flags);
624
625 writel(USR1_RTSD, sport->port.membase + USR1);
626 val = readl(sport->port.membase + USR1) & USR1_RTSS;
627 uart_handle_cts_change(&sport->port, !!val);
628 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
629
630 spin_unlock_irqrestore(&sport->port.lock, flags);
631 return IRQ_HANDLED;
632 }
633
634 static irqreturn_t imx_txint(int irq, void *dev_id)
635 {
636 struct imx_port *sport = dev_id;
637 unsigned long flags;
638
639 spin_lock_irqsave(&sport->port.lock, flags);
640 imx_transmit_buffer(sport);
641 spin_unlock_irqrestore(&sport->port.lock, flags);
642 return IRQ_HANDLED;
643 }
644
645 static irqreturn_t imx_rxint(int irq, void *dev_id)
646 {
647 struct imx_port *sport = dev_id;
648 unsigned int rx, flg, ignored = 0;
649 struct tty_port *port = &sport->port.state->port;
650 unsigned long flags, temp;
651
652 spin_lock_irqsave(&sport->port.lock, flags);
653
654 while (readl(sport->port.membase + USR2) & USR2_RDR) {
655 flg = TTY_NORMAL;
656 sport->port.icount.rx++;
657
658 rx = readl(sport->port.membase + URXD0);
659
660 temp = readl(sport->port.membase + USR2);
661 if (temp & USR2_BRCD) {
662 writel(USR2_BRCD, sport->port.membase + USR2);
663 if (uart_handle_break(&sport->port))
664 continue;
665 }
666
667 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
668 continue;
669
670 if (unlikely(rx & URXD_ERR)) {
671 if (rx & URXD_BRK)
672 sport->port.icount.brk++;
673 else if (rx & URXD_PRERR)
674 sport->port.icount.parity++;
675 else if (rx & URXD_FRMERR)
676 sport->port.icount.frame++;
677 if (rx & URXD_OVRRUN)
678 sport->port.icount.overrun++;
679
680 if (rx & sport->port.ignore_status_mask) {
681 if (++ignored > 100)
682 goto out;
683 continue;
684 }
685
686 rx &= (sport->port.read_status_mask | 0xFF);
687
688 if (rx & URXD_BRK)
689 flg = TTY_BREAK;
690 else if (rx & URXD_PRERR)
691 flg = TTY_PARITY;
692 else if (rx & URXD_FRMERR)
693 flg = TTY_FRAME;
694 if (rx & URXD_OVRRUN)
695 flg = TTY_OVERRUN;
696
697 #ifdef SUPPORT_SYSRQ
698 sport->port.sysrq = 0;
699 #endif
700 }
701
702 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
703 goto out;
704
705 if (tty_insert_flip_char(port, rx, flg) == 0)
706 sport->port.icount.buf_overrun++;
707 }
708
709 out:
710 spin_unlock_irqrestore(&sport->port.lock, flags);
711 tty_flip_buffer_push(port);
712 return IRQ_HANDLED;
713 }
714
715 static int start_rx_dma(struct imx_port *sport);
716 /*
717 * If the RXFIFO is filled with some data, and then we
718 * arise a DMA operation to receive them.
719 */
720 static void imx_dma_rxint(struct imx_port *sport)
721 {
722 unsigned long temp;
723 unsigned long flags;
724
725 spin_lock_irqsave(&sport->port.lock, flags);
726
727 temp = readl(sport->port.membase + USR2);
728 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
729 sport->dma_is_rxing = 1;
730
731 /* disable the `Recerver Ready Interrrupt` */
732 temp = readl(sport->port.membase + UCR1);
733 temp &= ~(UCR1_RRDYEN);
734 writel(temp, sport->port.membase + UCR1);
735
736 /* tell the DMA to receive the data. */
737 start_rx_dma(sport);
738 }
739
740 spin_unlock_irqrestore(&sport->port.lock, flags);
741 }
742
743 static irqreturn_t imx_int(int irq, void *dev_id)
744 {
745 struct imx_port *sport = dev_id;
746 unsigned int sts;
747 unsigned int sts2;
748
749 sts = readl(sport->port.membase + USR1);
750 sts2 = readl(sport->port.membase + USR2);
751
752 if (sts & USR1_RRDY) {
753 if (sport->dma_is_enabled)
754 imx_dma_rxint(sport);
755 else
756 imx_rxint(irq, dev_id);
757 }
758
759 if ((sts & USR1_TRDY &&
760 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
761 (sts2 & USR2_TXDC &&
762 readl(sport->port.membase + UCR4) & UCR4_TCEN))
763 imx_txint(irq, dev_id);
764
765 if (sts & USR1_RTSD)
766 imx_rtsint(irq, dev_id);
767
768 if (sts & USR1_AWAKE)
769 writel(USR1_AWAKE, sport->port.membase + USR1);
770
771 if (sts2 & USR2_ORE) {
772 sport->port.icount.overrun++;
773 writel(USR2_ORE, sport->port.membase + USR2);
774 }
775
776 return IRQ_HANDLED;
777 }
778
779 /*
780 * Return TIOCSER_TEMT when transmitter is not busy.
781 */
782 static unsigned int imx_tx_empty(struct uart_port *port)
783 {
784 struct imx_port *sport = (struct imx_port *)port;
785 unsigned int ret;
786
787 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
788
789 /* If the TX DMA is working, return 0. */
790 if (sport->dma_is_enabled && sport->dma_is_txing)
791 ret = 0;
792
793 return ret;
794 }
795
796 /*
797 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
798 */
799 static unsigned int imx_get_mctrl(struct uart_port *port)
800 {
801 struct imx_port *sport = (struct imx_port *)port;
802 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
803
804 if (readl(sport->port.membase + USR1) & USR1_RTSS)
805 tmp |= TIOCM_CTS;
806
807 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
808 tmp |= TIOCM_RTS;
809
810 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
811 tmp |= TIOCM_LOOP;
812
813 return tmp;
814 }
815
816 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
817 {
818 struct imx_port *sport = (struct imx_port *)port;
819 unsigned long temp;
820
821 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
822 temp = readl(sport->port.membase + UCR2);
823 temp &= ~(UCR2_CTS | UCR2_CTSC);
824 if (mctrl & TIOCM_RTS)
825 temp |= UCR2_CTS | UCR2_CTSC;
826 writel(temp, sport->port.membase + UCR2);
827 }
828
829 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
830 if (mctrl & TIOCM_LOOP)
831 temp |= UTS_LOOP;
832 writel(temp, sport->port.membase + uts_reg(sport));
833 }
834
835 /*
836 * Interrupts always disabled.
837 */
838 static void imx_break_ctl(struct uart_port *port, int break_state)
839 {
840 struct imx_port *sport = (struct imx_port *)port;
841 unsigned long flags, temp;
842
843 spin_lock_irqsave(&sport->port.lock, flags);
844
845 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
846
847 if (break_state != 0)
848 temp |= UCR1_SNDBRK;
849
850 writel(temp, sport->port.membase + UCR1);
851
852 spin_unlock_irqrestore(&sport->port.lock, flags);
853 }
854
855 #define TXTL 2 /* reset default */
856 #define RXTL 1 /* reset default */
857
858 static void imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
859 {
860 unsigned int val;
861
862 /* set receiver / transmitter trigger level */
863 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
864 val |= TXTL << UFCR_TXTL_SHF | RXTL;
865 writel(val, sport->port.membase + UFCR);
866 }
867
868 #define RX_BUF_SIZE (PAGE_SIZE)
869 static void imx_rx_dma_done(struct imx_port *sport)
870 {
871 unsigned long temp;
872 unsigned long flags;
873
874 spin_lock_irqsave(&sport->port.lock, flags);
875
876 /* Enable this interrupt when the RXFIFO is empty. */
877 temp = readl(sport->port.membase + UCR1);
878 temp |= UCR1_RRDYEN;
879 writel(temp, sport->port.membase + UCR1);
880
881 sport->dma_is_rxing = 0;
882
883 /* Is the shutdown waiting for us? */
884 if (waitqueue_active(&sport->dma_wait))
885 wake_up(&sport->dma_wait);
886
887 spin_unlock_irqrestore(&sport->port.lock, flags);
888 }
889
890 /*
891 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
892 * [1] the RX DMA buffer is full.
893 * [2] the Aging timer expires(wait for 8 bytes long)
894 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
895 *
896 * The [2] is trigger when a character was been sitting in the FIFO
897 * meanwhile [3] can wait for 32 bytes long when the RX line is
898 * on IDLE state and RxFIFO is empty.
899 */
900 static void dma_rx_callback(void *data)
901 {
902 struct imx_port *sport = data;
903 struct dma_chan *chan = sport->dma_chan_rx;
904 struct scatterlist *sgl = &sport->rx_sgl;
905 struct tty_port *port = &sport->port.state->port;
906 struct dma_tx_state state;
907 enum dma_status status;
908 unsigned int count;
909
910 /* unmap it first */
911 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
912
913 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
914 count = RX_BUF_SIZE - state.residue;
915
916 if (readl(sport->port.membase + USR2) & USR2_IDLE) {
917 /* In condition [3] the SDMA counted up too early */
918 count--;
919
920 writel(USR2_IDLE, sport->port.membase + USR2);
921 }
922
923 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
924
925 if (count) {
926 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
927 int bytes = tty_insert_flip_string(port, sport->rx_buf,
928 count);
929
930 if (bytes != count)
931 sport->port.icount.buf_overrun++;
932 }
933 tty_flip_buffer_push(port);
934
935 start_rx_dma(sport);
936 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
937 /*
938 * start rx_dma directly once data in RXFIFO, more efficient
939 * than before:
940 * 1. call imx_rx_dma_done to stop dma if no data received
941 * 2. wait next RDR interrupt to start dma transfer.
942 */
943 start_rx_dma(sport);
944 } else {
945 /*
946 * stop dma to prevent too many IDLE event trigged if no data
947 * in RXFIFO
948 */
949 imx_rx_dma_done(sport);
950 }
951 }
952
953 static int start_rx_dma(struct imx_port *sport)
954 {
955 struct scatterlist *sgl = &sport->rx_sgl;
956 struct dma_chan *chan = sport->dma_chan_rx;
957 struct device *dev = sport->port.dev;
958 struct dma_async_tx_descriptor *desc;
959 int ret;
960
961 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
962 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
963 if (ret == 0) {
964 dev_err(dev, "DMA mapping error for RX.\n");
965 return -EINVAL;
966 }
967 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
968 DMA_PREP_INTERRUPT);
969 if (!desc) {
970 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
971 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
972 return -EINVAL;
973 }
974 desc->callback = dma_rx_callback;
975 desc->callback_param = sport;
976
977 dev_dbg(dev, "RX: prepare for the DMA.\n");
978 dmaengine_submit(desc);
979 dma_async_issue_pending(chan);
980 return 0;
981 }
982
983 static void imx_uart_dma_exit(struct imx_port *sport)
984 {
985 if (sport->dma_chan_rx) {
986 dma_release_channel(sport->dma_chan_rx);
987 sport->dma_chan_rx = NULL;
988
989 kfree(sport->rx_buf);
990 sport->rx_buf = NULL;
991 }
992
993 if (sport->dma_chan_tx) {
994 dma_release_channel(sport->dma_chan_tx);
995 sport->dma_chan_tx = NULL;
996 }
997
998 sport->dma_is_inited = 0;
999 }
1000
1001 static int imx_uart_dma_init(struct imx_port *sport)
1002 {
1003 struct dma_slave_config slave_config = {};
1004 struct device *dev = sport->port.dev;
1005 int ret;
1006
1007 /* Prepare for RX : */
1008 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1009 if (!sport->dma_chan_rx) {
1010 dev_dbg(dev, "cannot get the DMA channel.\n");
1011 ret = -EINVAL;
1012 goto err;
1013 }
1014
1015 slave_config.direction = DMA_DEV_TO_MEM;
1016 slave_config.src_addr = sport->port.mapbase + URXD0;
1017 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1018 slave_config.src_maxburst = RXTL;
1019 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1020 if (ret) {
1021 dev_err(dev, "error in RX dma configuration.\n");
1022 goto err;
1023 }
1024
1025 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1026 if (!sport->rx_buf) {
1027 ret = -ENOMEM;
1028 goto err;
1029 }
1030
1031 /* Prepare for TX : */
1032 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1033 if (!sport->dma_chan_tx) {
1034 dev_err(dev, "cannot get the TX DMA channel!\n");
1035 ret = -EINVAL;
1036 goto err;
1037 }
1038
1039 slave_config.direction = DMA_MEM_TO_DEV;
1040 slave_config.dst_addr = sport->port.mapbase + URTX0;
1041 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1042 slave_config.dst_maxburst = TXTL;
1043 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1044 if (ret) {
1045 dev_err(dev, "error in TX dma configuration.");
1046 goto err;
1047 }
1048
1049 sport->dma_is_inited = 1;
1050
1051 return 0;
1052 err:
1053 imx_uart_dma_exit(sport);
1054 return ret;
1055 }
1056
1057 static void imx_enable_dma(struct imx_port *sport)
1058 {
1059 unsigned long temp;
1060
1061 init_waitqueue_head(&sport->dma_wait);
1062
1063 /* set UCR1 */
1064 temp = readl(sport->port.membase + UCR1);
1065 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1066 /* wait for 32 idle frames for IDDMA interrupt */
1067 UCR1_ICD_REG(3);
1068 writel(temp, sport->port.membase + UCR1);
1069
1070 /* set UCR4 */
1071 temp = readl(sport->port.membase + UCR4);
1072 temp |= UCR4_IDDMAEN;
1073 writel(temp, sport->port.membase + UCR4);
1074
1075 sport->dma_is_enabled = 1;
1076 }
1077
1078 static void imx_disable_dma(struct imx_port *sport)
1079 {
1080 unsigned long temp;
1081
1082 /* clear UCR1 */
1083 temp = readl(sport->port.membase + UCR1);
1084 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1085 writel(temp, sport->port.membase + UCR1);
1086
1087 /* clear UCR2 */
1088 temp = readl(sport->port.membase + UCR2);
1089 temp &= ~(UCR2_CTSC | UCR2_CTS);
1090 writel(temp, sport->port.membase + UCR2);
1091
1092 /* clear UCR4 */
1093 temp = readl(sport->port.membase + UCR4);
1094 temp &= ~UCR4_IDDMAEN;
1095 writel(temp, sport->port.membase + UCR4);
1096
1097 sport->dma_is_enabled = 0;
1098 }
1099
1100 /* half the RX buffer size */
1101 #define CTSTL 16
1102
1103 static int imx_startup(struct uart_port *port)
1104 {
1105 struct imx_port *sport = (struct imx_port *)port;
1106 int retval, i;
1107 unsigned long flags, temp;
1108
1109 retval = clk_prepare_enable(sport->clk_per);
1110 if (retval)
1111 return retval;
1112 retval = clk_prepare_enable(sport->clk_ipg);
1113 if (retval) {
1114 clk_disable_unprepare(sport->clk_per);
1115 return retval;
1116 }
1117
1118 imx_setup_ufcr(sport, 0);
1119
1120 /* disable the DREN bit (Data Ready interrupt enable) before
1121 * requesting IRQs
1122 */
1123 temp = readl(sport->port.membase + UCR4);
1124
1125 /* set the trigger level for CTS */
1126 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1127 temp |= CTSTL << UCR4_CTSTL_SHF;
1128
1129 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1130
1131 spin_lock_irqsave(&sport->port.lock, flags);
1132 /* Reset fifo's and state machines */
1133 i = 100;
1134
1135 temp = readl(sport->port.membase + UCR2);
1136 temp &= ~UCR2_SRST;
1137 writel(temp, sport->port.membase + UCR2);
1138
1139 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1140 udelay(1);
1141
1142 /*
1143 * Finally, clear and enable interrupts
1144 */
1145 writel(USR1_RTSD, sport->port.membase + USR1);
1146 writel(USR2_ORE, sport->port.membase + USR2);
1147
1148 temp = readl(sport->port.membase + UCR1);
1149 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1150
1151 writel(temp, sport->port.membase + UCR1);
1152
1153 temp = readl(sport->port.membase + UCR4);
1154 temp |= UCR4_OREN;
1155 writel(temp, sport->port.membase + UCR4);
1156
1157 temp = readl(sport->port.membase + UCR2);
1158 temp |= (UCR2_RXEN | UCR2_TXEN);
1159 if (!sport->have_rtscts)
1160 temp |= UCR2_IRTS;
1161 writel(temp, sport->port.membase + UCR2);
1162
1163 if (!is_imx1_uart(sport)) {
1164 temp = readl(sport->port.membase + UCR3);
1165 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1166 writel(temp, sport->port.membase + UCR3);
1167 }
1168
1169 /*
1170 * Enable modem status interrupts
1171 */
1172 imx_enable_ms(&sport->port);
1173 spin_unlock_irqrestore(&sport->port.lock, flags);
1174
1175 return 0;
1176 }
1177
1178 static void imx_shutdown(struct uart_port *port)
1179 {
1180 struct imx_port *sport = (struct imx_port *)port;
1181 unsigned long temp;
1182 unsigned long flags;
1183
1184 if (sport->dma_is_enabled) {
1185 int ret;
1186
1187 /* We have to wait for the DMA to finish. */
1188 ret = wait_event_interruptible(sport->dma_wait,
1189 !sport->dma_is_rxing && !sport->dma_is_txing);
1190 if (ret != 0) {
1191 sport->dma_is_rxing = 0;
1192 sport->dma_is_txing = 0;
1193 dmaengine_terminate_all(sport->dma_chan_tx);
1194 dmaengine_terminate_all(sport->dma_chan_rx);
1195 }
1196 spin_lock_irqsave(&sport->port.lock, flags);
1197 imx_stop_tx(port);
1198 imx_stop_rx(port);
1199 imx_disable_dma(sport);
1200 spin_unlock_irqrestore(&sport->port.lock, flags);
1201 imx_uart_dma_exit(sport);
1202 }
1203
1204 spin_lock_irqsave(&sport->port.lock, flags);
1205 temp = readl(sport->port.membase + UCR2);
1206 temp &= ~(UCR2_TXEN);
1207 writel(temp, sport->port.membase + UCR2);
1208 spin_unlock_irqrestore(&sport->port.lock, flags);
1209
1210 /*
1211 * Stop our timer.
1212 */
1213 del_timer_sync(&sport->timer);
1214
1215 /*
1216 * Disable all interrupts, port and break condition.
1217 */
1218
1219 spin_lock_irqsave(&sport->port.lock, flags);
1220 temp = readl(sport->port.membase + UCR1);
1221 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1222
1223 writel(temp, sport->port.membase + UCR1);
1224 spin_unlock_irqrestore(&sport->port.lock, flags);
1225
1226 clk_disable_unprepare(sport->clk_per);
1227 clk_disable_unprepare(sport->clk_ipg);
1228 }
1229
1230 static void imx_flush_buffer(struct uart_port *port)
1231 {
1232 struct imx_port *sport = (struct imx_port *)port;
1233 struct scatterlist *sgl = &sport->tx_sgl[0];
1234 unsigned long temp;
1235 int i = 100, ubir, ubmr, uts;
1236
1237 if (!sport->dma_chan_tx)
1238 return;
1239
1240 sport->tx_bytes = 0;
1241 dmaengine_terminate_all(sport->dma_chan_tx);
1242 if (sport->dma_is_txing) {
1243 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1244 DMA_TO_DEVICE);
1245 temp = readl(sport->port.membase + UCR1);
1246 temp &= ~UCR1_TDMAEN;
1247 writel(temp, sport->port.membase + UCR1);
1248 sport->dma_is_txing = false;
1249 }
1250
1251 /*
1252 * According to the Reference Manual description of the UART SRST bit:
1253 * "Reset the transmit and receive state machines,
1254 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1255 * and UTS[6-3]". As we don't need to restore the old values from
1256 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1257 */
1258 ubir = readl(sport->port.membase + UBIR);
1259 ubmr = readl(sport->port.membase + UBMR);
1260 uts = readl(sport->port.membase + IMX21_UTS);
1261
1262 temp = readl(sport->port.membase + UCR2);
1263 temp &= ~UCR2_SRST;
1264 writel(temp, sport->port.membase + UCR2);
1265
1266 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1267 udelay(1);
1268
1269 /* Restore the registers */
1270 writel(ubir, sport->port.membase + UBIR);
1271 writel(ubmr, sport->port.membase + UBMR);
1272 writel(uts, sport->port.membase + IMX21_UTS);
1273 }
1274
1275 static void
1276 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1277 struct ktermios *old)
1278 {
1279 struct imx_port *sport = (struct imx_port *)port;
1280 unsigned long flags;
1281 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1282 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1283 unsigned int div, ufcr;
1284 unsigned long num, denom;
1285 uint64_t tdiv64;
1286
1287 /*
1288 * We only support CS7 and CS8.
1289 */
1290 while ((termios->c_cflag & CSIZE) != CS7 &&
1291 (termios->c_cflag & CSIZE) != CS8) {
1292 termios->c_cflag &= ~CSIZE;
1293 termios->c_cflag |= old_csize;
1294 old_csize = CS8;
1295 }
1296
1297 if ((termios->c_cflag & CSIZE) == CS8)
1298 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1299 else
1300 ucr2 = UCR2_SRST | UCR2_IRTS;
1301
1302 if (termios->c_cflag & CRTSCTS) {
1303 if (sport->have_rtscts) {
1304 ucr2 &= ~UCR2_IRTS;
1305
1306 if (port->rs485.flags & SER_RS485_ENABLED) {
1307 /*
1308 * RTS is mandatory for rs485 operation, so keep
1309 * it under manual control and keep transmitter
1310 * disabled.
1311 */
1312 if (!(port->rs485.flags &
1313 SER_RS485_RTS_AFTER_SEND))
1314 ucr2 |= UCR2_CTS;
1315 } else {
1316 ucr2 |= UCR2_CTSC;
1317 }
1318
1319 /* Can we enable the DMA support? */
1320 if (is_imx6q_uart(sport) && !uart_console(port)
1321 && !sport->dma_is_inited)
1322 imx_uart_dma_init(sport);
1323 } else {
1324 termios->c_cflag &= ~CRTSCTS;
1325 }
1326 } else if (port->rs485.flags & SER_RS485_ENABLED)
1327 /* disable transmitter */
1328 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1329 ucr2 |= UCR2_CTS;
1330
1331 if (termios->c_cflag & CSTOPB)
1332 ucr2 |= UCR2_STPB;
1333 if (termios->c_cflag & PARENB) {
1334 ucr2 |= UCR2_PREN;
1335 if (termios->c_cflag & PARODD)
1336 ucr2 |= UCR2_PROE;
1337 }
1338
1339 del_timer_sync(&sport->timer);
1340
1341 /*
1342 * Ask the core to calculate the divisor for us.
1343 */
1344 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1345 quot = uart_get_divisor(port, baud);
1346
1347 spin_lock_irqsave(&sport->port.lock, flags);
1348
1349 sport->port.read_status_mask = 0;
1350 if (termios->c_iflag & INPCK)
1351 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1352 if (termios->c_iflag & (BRKINT | PARMRK))
1353 sport->port.read_status_mask |= URXD_BRK;
1354
1355 /*
1356 * Characters to ignore
1357 */
1358 sport->port.ignore_status_mask = 0;
1359 if (termios->c_iflag & IGNPAR)
1360 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1361 if (termios->c_iflag & IGNBRK) {
1362 sport->port.ignore_status_mask |= URXD_BRK;
1363 /*
1364 * If we're ignoring parity and break indicators,
1365 * ignore overruns too (for real raw support).
1366 */
1367 if (termios->c_iflag & IGNPAR)
1368 sport->port.ignore_status_mask |= URXD_OVRRUN;
1369 }
1370
1371 if ((termios->c_cflag & CREAD) == 0)
1372 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1373
1374 /*
1375 * Update the per-port timeout.
1376 */
1377 uart_update_timeout(port, termios->c_cflag, baud);
1378
1379 /*
1380 * disable interrupts and drain transmitter
1381 */
1382 old_ucr1 = readl(sport->port.membase + UCR1);
1383 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1384 sport->port.membase + UCR1);
1385
1386 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1387 barrier();
1388
1389 /* then, disable everything */
1390 old_txrxen = readl(sport->port.membase + UCR2);
1391 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1392 sport->port.membase + UCR2);
1393 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1394
1395 /* custom-baudrate handling */
1396 div = sport->port.uartclk / (baud * 16);
1397 if (baud == 38400 && quot != div)
1398 baud = sport->port.uartclk / (quot * 16);
1399
1400 div = sport->port.uartclk / (baud * 16);
1401 if (div > 7)
1402 div = 7;
1403 if (!div)
1404 div = 1;
1405
1406 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1407 1 << 16, 1 << 16, &num, &denom);
1408
1409 tdiv64 = sport->port.uartclk;
1410 tdiv64 *= num;
1411 do_div(tdiv64, denom * 16 * div);
1412 tty_termios_encode_baud_rate(termios,
1413 (speed_t)tdiv64, (speed_t)tdiv64);
1414
1415 num -= 1;
1416 denom -= 1;
1417
1418 ufcr = readl(sport->port.membase + UFCR);
1419 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1420 if (sport->dte_mode)
1421 ufcr |= UFCR_DCEDTE;
1422 writel(ufcr, sport->port.membase + UFCR);
1423
1424 writel(num, sport->port.membase + UBIR);
1425 writel(denom, sport->port.membase + UBMR);
1426
1427 if (!is_imx1_uart(sport))
1428 writel(sport->port.uartclk / div / 1000,
1429 sport->port.membase + IMX21_ONEMS);
1430
1431 writel(old_ucr1, sport->port.membase + UCR1);
1432
1433 /* set the parity, stop bits and data size */
1434 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1435
1436 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1437 imx_enable_ms(&sport->port);
1438
1439 if (sport->dma_is_inited && !sport->dma_is_enabled)
1440 imx_enable_dma(sport);
1441 spin_unlock_irqrestore(&sport->port.lock, flags);
1442 }
1443
1444 static const char *imx_type(struct uart_port *port)
1445 {
1446 struct imx_port *sport = (struct imx_port *)port;
1447
1448 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1449 }
1450
1451 /*
1452 * Configure/autoconfigure the port.
1453 */
1454 static void imx_config_port(struct uart_port *port, int flags)
1455 {
1456 struct imx_port *sport = (struct imx_port *)port;
1457
1458 if (flags & UART_CONFIG_TYPE)
1459 sport->port.type = PORT_IMX;
1460 }
1461
1462 /*
1463 * Verify the new serial_struct (for TIOCSSERIAL).
1464 * The only change we allow are to the flags and type, and
1465 * even then only between PORT_IMX and PORT_UNKNOWN
1466 */
1467 static int
1468 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1469 {
1470 struct imx_port *sport = (struct imx_port *)port;
1471 int ret = 0;
1472
1473 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1474 ret = -EINVAL;
1475 if (sport->port.irq != ser->irq)
1476 ret = -EINVAL;
1477 if (ser->io_type != UPIO_MEM)
1478 ret = -EINVAL;
1479 if (sport->port.uartclk / 16 != ser->baud_base)
1480 ret = -EINVAL;
1481 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1482 ret = -EINVAL;
1483 if (sport->port.iobase != ser->port)
1484 ret = -EINVAL;
1485 if (ser->hub6 != 0)
1486 ret = -EINVAL;
1487 return ret;
1488 }
1489
1490 #if defined(CONFIG_CONSOLE_POLL)
1491
1492 static int imx_poll_init(struct uart_port *port)
1493 {
1494 struct imx_port *sport = (struct imx_port *)port;
1495 unsigned long flags;
1496 unsigned long temp;
1497 int retval;
1498
1499 retval = clk_prepare_enable(sport->clk_ipg);
1500 if (retval)
1501 return retval;
1502 retval = clk_prepare_enable(sport->clk_per);
1503 if (retval)
1504 clk_disable_unprepare(sport->clk_ipg);
1505
1506 imx_setup_ufcr(sport, 0);
1507
1508 spin_lock_irqsave(&sport->port.lock, flags);
1509
1510 temp = readl(sport->port.membase + UCR1);
1511 if (is_imx1_uart(sport))
1512 temp |= IMX1_UCR1_UARTCLKEN;
1513 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1514 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1515 writel(temp, sport->port.membase + UCR1);
1516
1517 temp = readl(sport->port.membase + UCR2);
1518 temp |= UCR2_RXEN;
1519 writel(temp, sport->port.membase + UCR2);
1520
1521 spin_unlock_irqrestore(&sport->port.lock, flags);
1522
1523 return 0;
1524 }
1525
1526 static int imx_poll_get_char(struct uart_port *port)
1527 {
1528 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1529 return NO_POLL_CHAR;
1530
1531 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1532 }
1533
1534 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1535 {
1536 unsigned int status;
1537
1538 /* drain */
1539 do {
1540 status = readl_relaxed(port->membase + USR1);
1541 } while (~status & USR1_TRDY);
1542
1543 /* write */
1544 writel_relaxed(c, port->membase + URTX0);
1545
1546 /* flush */
1547 do {
1548 status = readl_relaxed(port->membase + USR2);
1549 } while (~status & USR2_TXDC);
1550 }
1551 #endif
1552
1553 static int imx_rs485_config(struct uart_port *port,
1554 struct serial_rs485 *rs485conf)
1555 {
1556 struct imx_port *sport = (struct imx_port *)port;
1557
1558 /* unimplemented */
1559 rs485conf->delay_rts_before_send = 0;
1560 rs485conf->delay_rts_after_send = 0;
1561 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1562
1563 /* RTS is required to control the transmitter */
1564 if (!sport->have_rtscts)
1565 rs485conf->flags &= ~SER_RS485_ENABLED;
1566
1567 if (rs485conf->flags & SER_RS485_ENABLED) {
1568 unsigned long temp;
1569
1570 /* disable transmitter */
1571 temp = readl(sport->port.membase + UCR2);
1572 temp &= ~UCR2_CTSC;
1573 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1574 temp &= ~UCR2_CTS;
1575 else
1576 temp |= UCR2_CTS;
1577 writel(temp, sport->port.membase + UCR2);
1578 }
1579
1580 port->rs485 = *rs485conf;
1581
1582 return 0;
1583 }
1584
1585 static struct uart_ops imx_pops = {
1586 .tx_empty = imx_tx_empty,
1587 .set_mctrl = imx_set_mctrl,
1588 .get_mctrl = imx_get_mctrl,
1589 .stop_tx = imx_stop_tx,
1590 .start_tx = imx_start_tx,
1591 .stop_rx = imx_stop_rx,
1592 .enable_ms = imx_enable_ms,
1593 .break_ctl = imx_break_ctl,
1594 .startup = imx_startup,
1595 .shutdown = imx_shutdown,
1596 .flush_buffer = imx_flush_buffer,
1597 .set_termios = imx_set_termios,
1598 .type = imx_type,
1599 .config_port = imx_config_port,
1600 .verify_port = imx_verify_port,
1601 #if defined(CONFIG_CONSOLE_POLL)
1602 .poll_init = imx_poll_init,
1603 .poll_get_char = imx_poll_get_char,
1604 .poll_put_char = imx_poll_put_char,
1605 #endif
1606 };
1607
1608 static struct imx_port *imx_ports[UART_NR];
1609
1610 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1611 static void imx_console_putchar(struct uart_port *port, int ch)
1612 {
1613 struct imx_port *sport = (struct imx_port *)port;
1614
1615 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1616 barrier();
1617
1618 writel(ch, sport->port.membase + URTX0);
1619 }
1620
1621 /*
1622 * Interrupts are disabled on entering
1623 */
1624 static void
1625 imx_console_write(struct console *co, const char *s, unsigned int count)
1626 {
1627 struct imx_port *sport = imx_ports[co->index];
1628 struct imx_port_ucrs old_ucr;
1629 unsigned int ucr1;
1630 unsigned long flags = 0;
1631 int locked = 1;
1632 int retval;
1633
1634 retval = clk_prepare_enable(sport->clk_per);
1635 if (retval)
1636 return;
1637 retval = clk_prepare_enable(sport->clk_ipg);
1638 if (retval) {
1639 clk_disable_unprepare(sport->clk_per);
1640 return;
1641 }
1642
1643 if (sport->port.sysrq)
1644 locked = 0;
1645 else if (oops_in_progress)
1646 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1647 else
1648 spin_lock_irqsave(&sport->port.lock, flags);
1649
1650 /*
1651 * First, save UCR1/2/3 and then disable interrupts
1652 */
1653 imx_port_ucrs_save(&sport->port, &old_ucr);
1654 ucr1 = old_ucr.ucr1;
1655
1656 if (is_imx1_uart(sport))
1657 ucr1 |= IMX1_UCR1_UARTCLKEN;
1658 ucr1 |= UCR1_UARTEN;
1659 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1660
1661 writel(ucr1, sport->port.membase + UCR1);
1662
1663 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1664
1665 uart_console_write(&sport->port, s, count, imx_console_putchar);
1666
1667 /*
1668 * Finally, wait for transmitter to become empty
1669 * and restore UCR1/2/3
1670 */
1671 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1672
1673 imx_port_ucrs_restore(&sport->port, &old_ucr);
1674
1675 if (locked)
1676 spin_unlock_irqrestore(&sport->port.lock, flags);
1677
1678 clk_disable_unprepare(sport->clk_ipg);
1679 clk_disable_unprepare(sport->clk_per);
1680 }
1681
1682 /*
1683 * If the port was already initialised (eg, by a boot loader),
1684 * try to determine the current setup.
1685 */
1686 static void __init
1687 imx_console_get_options(struct imx_port *sport, int *baud,
1688 int *parity, int *bits)
1689 {
1690
1691 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1692 /* ok, the port was enabled */
1693 unsigned int ucr2, ubir, ubmr, uartclk;
1694 unsigned int baud_raw;
1695 unsigned int ucfr_rfdiv;
1696
1697 ucr2 = readl(sport->port.membase + UCR2);
1698
1699 *parity = 'n';
1700 if (ucr2 & UCR2_PREN) {
1701 if (ucr2 & UCR2_PROE)
1702 *parity = 'o';
1703 else
1704 *parity = 'e';
1705 }
1706
1707 if (ucr2 & UCR2_WS)
1708 *bits = 8;
1709 else
1710 *bits = 7;
1711
1712 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1713 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1714
1715 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1716 if (ucfr_rfdiv == 6)
1717 ucfr_rfdiv = 7;
1718 else
1719 ucfr_rfdiv = 6 - ucfr_rfdiv;
1720
1721 uartclk = clk_get_rate(sport->clk_per);
1722 uartclk /= ucfr_rfdiv;
1723
1724 { /*
1725 * The next code provides exact computation of
1726 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1727 * without need of float support or long long division,
1728 * which would be required to prevent 32bit arithmetic overflow
1729 */
1730 unsigned int mul = ubir + 1;
1731 unsigned int div = 16 * (ubmr + 1);
1732 unsigned int rem = uartclk % div;
1733
1734 baud_raw = (uartclk / div) * mul;
1735 baud_raw += (rem * mul + div / 2) / div;
1736 *baud = (baud_raw + 50) / 100 * 100;
1737 }
1738
1739 if (*baud != baud_raw)
1740 pr_info("Console IMX rounded baud rate from %d to %d\n",
1741 baud_raw, *baud);
1742 }
1743 }
1744
1745 static int __init
1746 imx_console_setup(struct console *co, char *options)
1747 {
1748 struct imx_port *sport;
1749 int baud = 9600;
1750 int bits = 8;
1751 int parity = 'n';
1752 int flow = 'n';
1753 int retval;
1754
1755 /*
1756 * Check whether an invalid uart number has been specified, and
1757 * if so, search for the first available port that does have
1758 * console support.
1759 */
1760 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1761 co->index = 0;
1762 sport = imx_ports[co->index];
1763 if (sport == NULL)
1764 return -ENODEV;
1765
1766 /* For setting the registers, we only need to enable the ipg clock. */
1767 retval = clk_prepare_enable(sport->clk_ipg);
1768 if (retval)
1769 goto error_console;
1770
1771 if (options)
1772 uart_parse_options(options, &baud, &parity, &bits, &flow);
1773 else
1774 imx_console_get_options(sport, &baud, &parity, &bits);
1775
1776 imx_setup_ufcr(sport, 0);
1777
1778 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1779
1780 clk_disable_unprepare(sport->clk_ipg);
1781
1782 error_console:
1783 return retval;
1784 }
1785
1786 static struct uart_driver imx_reg;
1787 static struct console imx_console = {
1788 .name = DEV_NAME,
1789 .write = imx_console_write,
1790 .device = uart_console_device,
1791 .setup = imx_console_setup,
1792 .flags = CON_PRINTBUFFER,
1793 .index = -1,
1794 .data = &imx_reg,
1795 };
1796
1797 #define IMX_CONSOLE &imx_console
1798 #else
1799 #define IMX_CONSOLE NULL
1800 #endif
1801
1802 static struct uart_driver imx_reg = {
1803 .owner = THIS_MODULE,
1804 .driver_name = DRIVER_NAME,
1805 .dev_name = DEV_NAME,
1806 .major = SERIAL_IMX_MAJOR,
1807 .minor = MINOR_START,
1808 .nr = ARRAY_SIZE(imx_ports),
1809 .cons = IMX_CONSOLE,
1810 };
1811
1812 #ifdef CONFIG_OF
1813 /*
1814 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1815 * could successfully get all information from dt or a negative errno.
1816 */
1817 static int serial_imx_probe_dt(struct imx_port *sport,
1818 struct platform_device *pdev)
1819 {
1820 struct device_node *np = pdev->dev.of_node;
1821 const struct of_device_id *of_id =
1822 of_match_device(imx_uart_dt_ids, &pdev->dev);
1823 int ret;
1824
1825 if (!np)
1826 /* no device tree device */
1827 return 1;
1828
1829 ret = of_alias_get_id(np, "serial");
1830 if (ret < 0) {
1831 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1832 return ret;
1833 }
1834 sport->port.line = ret;
1835
1836 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1837 sport->have_rtscts = 1;
1838
1839 if (of_get_property(np, "fsl,dte-mode", NULL))
1840 sport->dte_mode = 1;
1841
1842 sport->devdata = of_id->data;
1843
1844 return 0;
1845 }
1846 #else
1847 static inline int serial_imx_probe_dt(struct imx_port *sport,
1848 struct platform_device *pdev)
1849 {
1850 return 1;
1851 }
1852 #endif
1853
1854 static void serial_imx_probe_pdata(struct imx_port *sport,
1855 struct platform_device *pdev)
1856 {
1857 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1858
1859 sport->port.line = pdev->id;
1860 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1861
1862 if (!pdata)
1863 return;
1864
1865 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1866 sport->have_rtscts = 1;
1867 }
1868
1869 static int serial_imx_probe(struct platform_device *pdev)
1870 {
1871 struct imx_port *sport;
1872 void __iomem *base;
1873 int ret = 0, reg;
1874 struct resource *res;
1875 int txirq, rxirq, rtsirq;
1876
1877 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1878 if (!sport)
1879 return -ENOMEM;
1880
1881 ret = serial_imx_probe_dt(sport, pdev);
1882 if (ret > 0)
1883 serial_imx_probe_pdata(sport, pdev);
1884 else if (ret < 0)
1885 return ret;
1886
1887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1888 base = devm_ioremap_resource(&pdev->dev, res);
1889 if (IS_ERR(base))
1890 return PTR_ERR(base);
1891
1892 rxirq = platform_get_irq(pdev, 0);
1893 txirq = platform_get_irq(pdev, 1);
1894 rtsirq = platform_get_irq(pdev, 2);
1895
1896 sport->port.dev = &pdev->dev;
1897 sport->port.mapbase = res->start;
1898 sport->port.membase = base;
1899 sport->port.type = PORT_IMX,
1900 sport->port.iotype = UPIO_MEM;
1901 sport->port.irq = rxirq;
1902 sport->port.fifosize = 32;
1903 sport->port.ops = &imx_pops;
1904 sport->port.rs485_config = imx_rs485_config;
1905 sport->port.rs485.flags =
1906 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1907 sport->port.flags = UPF_BOOT_AUTOCONF;
1908 init_timer(&sport->timer);
1909 sport->timer.function = imx_timeout;
1910 sport->timer.data = (unsigned long)sport;
1911
1912 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1913 if (IS_ERR(sport->clk_ipg)) {
1914 ret = PTR_ERR(sport->clk_ipg);
1915 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1916 return ret;
1917 }
1918
1919 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1920 if (IS_ERR(sport->clk_per)) {
1921 ret = PTR_ERR(sport->clk_per);
1922 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1923 return ret;
1924 }
1925
1926 sport->port.uartclk = clk_get_rate(sport->clk_per);
1927
1928 /* For register access, we only need to enable the ipg clock. */
1929 ret = clk_prepare_enable(sport->clk_ipg);
1930 if (ret)
1931 return ret;
1932
1933 /* Disable interrupts before requesting them */
1934 reg = readl_relaxed(sport->port.membase + UCR1);
1935 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
1936 UCR1_TXMPTYEN | UCR1_RTSDEN);
1937 writel_relaxed(reg, sport->port.membase + UCR1);
1938
1939 clk_disable_unprepare(sport->clk_ipg);
1940
1941 /*
1942 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1943 * chips only have one interrupt.
1944 */
1945 if (txirq > 0) {
1946 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1947 dev_name(&pdev->dev), sport);
1948 if (ret)
1949 return ret;
1950
1951 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1952 dev_name(&pdev->dev), sport);
1953 if (ret)
1954 return ret;
1955 } else {
1956 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1957 dev_name(&pdev->dev), sport);
1958 if (ret)
1959 return ret;
1960 }
1961
1962 imx_ports[sport->port.line] = sport;
1963
1964 platform_set_drvdata(pdev, sport);
1965
1966 return uart_add_one_port(&imx_reg, &sport->port);
1967 }
1968
1969 static int serial_imx_remove(struct platform_device *pdev)
1970 {
1971 struct imx_port *sport = platform_get_drvdata(pdev);
1972
1973 return uart_remove_one_port(&imx_reg, &sport->port);
1974 }
1975
1976 static void serial_imx_restore_context(struct imx_port *sport)
1977 {
1978 if (!sport->context_saved)
1979 return;
1980
1981 writel(sport->saved_reg[4], sport->port.membase + UFCR);
1982 writel(sport->saved_reg[5], sport->port.membase + UESC);
1983 writel(sport->saved_reg[6], sport->port.membase + UTIM);
1984 writel(sport->saved_reg[7], sport->port.membase + UBIR);
1985 writel(sport->saved_reg[8], sport->port.membase + UBMR);
1986 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
1987 writel(sport->saved_reg[0], sport->port.membase + UCR1);
1988 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
1989 writel(sport->saved_reg[2], sport->port.membase + UCR3);
1990 writel(sport->saved_reg[3], sport->port.membase + UCR4);
1991 sport->context_saved = false;
1992 }
1993
1994 static void serial_imx_save_context(struct imx_port *sport)
1995 {
1996 /* Save necessary regs */
1997 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
1998 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
1999 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2000 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2001 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2002 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2003 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2004 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2005 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2006 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2007 sport->context_saved = true;
2008 }
2009
2010 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2011 {
2012 unsigned int val;
2013
2014 val = readl(sport->port.membase + UCR3);
2015 if (on)
2016 val |= UCR3_AWAKEN;
2017 else
2018 val &= ~UCR3_AWAKEN;
2019 writel(val, sport->port.membase + UCR3);
2020
2021 val = readl(sport->port.membase + UCR1);
2022 if (on)
2023 val |= UCR1_RTSDEN;
2024 else
2025 val &= ~UCR1_RTSDEN;
2026 writel(val, sport->port.membase + UCR1);
2027 }
2028
2029 static int imx_serial_port_suspend_noirq(struct device *dev)
2030 {
2031 struct platform_device *pdev = to_platform_device(dev);
2032 struct imx_port *sport = platform_get_drvdata(pdev);
2033 int ret;
2034
2035 ret = clk_enable(sport->clk_ipg);
2036 if (ret)
2037 return ret;
2038
2039 serial_imx_save_context(sport);
2040
2041 clk_disable(sport->clk_ipg);
2042
2043 return 0;
2044 }
2045
2046 static int imx_serial_port_resume_noirq(struct device *dev)
2047 {
2048 struct platform_device *pdev = to_platform_device(dev);
2049 struct imx_port *sport = platform_get_drvdata(pdev);
2050 int ret;
2051
2052 ret = clk_enable(sport->clk_ipg);
2053 if (ret)
2054 return ret;
2055
2056 serial_imx_restore_context(sport);
2057
2058 clk_disable(sport->clk_ipg);
2059
2060 return 0;
2061 }
2062
2063 static int imx_serial_port_suspend(struct device *dev)
2064 {
2065 struct platform_device *pdev = to_platform_device(dev);
2066 struct imx_port *sport = platform_get_drvdata(pdev);
2067
2068 /* enable wakeup from i.MX UART */
2069 serial_imx_enable_wakeup(sport, true);
2070
2071 uart_suspend_port(&imx_reg, &sport->port);
2072
2073 return 0;
2074 }
2075
2076 static int imx_serial_port_resume(struct device *dev)
2077 {
2078 struct platform_device *pdev = to_platform_device(dev);
2079 struct imx_port *sport = platform_get_drvdata(pdev);
2080
2081 /* disable wakeup from i.MX UART */
2082 serial_imx_enable_wakeup(sport, false);
2083
2084 uart_resume_port(&imx_reg, &sport->port);
2085
2086 return 0;
2087 }
2088
2089 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2090 .suspend_noirq = imx_serial_port_suspend_noirq,
2091 .resume_noirq = imx_serial_port_resume_noirq,
2092 .suspend = imx_serial_port_suspend,
2093 .resume = imx_serial_port_resume,
2094 };
2095
2096 static struct platform_driver serial_imx_driver = {
2097 .probe = serial_imx_probe,
2098 .remove = serial_imx_remove,
2099
2100 .id_table = imx_uart_devtype,
2101 .driver = {
2102 .name = "imx-uart",
2103 .of_match_table = imx_uart_dt_ids,
2104 .pm = &imx_serial_port_pm_ops,
2105 },
2106 };
2107
2108 static int __init imx_serial_init(void)
2109 {
2110 int ret = uart_register_driver(&imx_reg);
2111
2112 if (ret)
2113 return ret;
2114
2115 ret = platform_driver_register(&serial_imx_driver);
2116 if (ret != 0)
2117 uart_unregister_driver(&imx_reg);
2118
2119 return ret;
2120 }
2121
2122 static void __exit imx_serial_exit(void)
2123 {
2124 platform_driver_unregister(&serial_imx_driver);
2125 uart_unregister_driver(&imx_reg);
2126 }
2127
2128 module_init(imx_serial_init);
2129 module_exit(imx_serial_exit);
2130
2131 MODULE_AUTHOR("Sascha Hauer");
2132 MODULE_DESCRIPTION("IMX generic serial port driver");
2133 MODULE_LICENSE("GPL");
2134 MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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