2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/regmap.h>
25 #include <linux/serial_core.h>
26 #include <linux/serial.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/spi/spi.h>
30 #include <linux/uaccess.h>
32 #define MAX310X_NAME "max310x"
33 #define MAX310X_MAJOR 204
34 #define MAX310X_MINOR 209
36 /* MAX310X register definitions */
37 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
38 #define MAX310X_THR_REG (0x00) /* TX FIFO */
39 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
40 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
41 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
42 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
43 #define MAX310X_REG_05 (0x05)
44 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
45 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
46 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
47 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
48 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
49 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
50 #define MAX310X_LCR_REG (0x0b) /* LCR */
51 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
52 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
53 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
54 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
55 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
56 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
57 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
58 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
59 #define MAX310X_XON1_REG (0x14) /* XON1 character */
60 #define MAX310X_XON2_REG (0x15) /* XON2 character */
61 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
62 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
63 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
64 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
65 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
66 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
67 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
68 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
69 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
70 #define MAX310X_REG_1F (0x1f)
72 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
74 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
75 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
77 /* Extended registers */
78 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
80 /* IRQ register bits */
81 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
82 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
83 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
84 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
85 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
86 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
87 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
88 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
90 /* LSR register bits */
91 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
92 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
93 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
94 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
95 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
96 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
97 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
99 /* Special character register bits */
100 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
101 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
102 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
103 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
104 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
105 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
107 /* Status register bits */
108 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
109 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
110 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
111 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
112 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
113 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
115 /* MODE1 register bits */
116 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
117 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
118 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
119 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
120 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
121 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
122 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
123 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
125 /* MODE2 register bits */
126 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
127 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
128 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
129 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
130 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
131 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
132 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
133 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
135 /* LCR register bits */
136 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
137 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
139 * Word length bits table:
145 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
147 * STOP length bit table:
149 * 1 -> 1-1.5 stop bits if
151 * 2 stop bits otherwise
153 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
154 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
155 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
156 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
157 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
158 #define MAX310X_LCR_WORD_LEN_5 (0x00)
159 #define MAX310X_LCR_WORD_LEN_6 (0x01)
160 #define MAX310X_LCR_WORD_LEN_7 (0x02)
161 #define MAX310X_LCR_WORD_LEN_8 (0x03)
163 /* IRDA register bits */
164 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
165 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
167 /* Flow control trigger level register masks */
168 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
169 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
170 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
171 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
173 /* FIFO interrupt trigger level register masks */
174 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
175 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
176 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
177 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
179 /* Flow control register bits */
180 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
181 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
182 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
183 * are used in conjunction with
184 * XOFF2 for definition of
185 * special character */
186 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
187 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
188 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
190 * SWFLOW bits 1 & 0 table:
191 * 00 -> no transmitter flow
193 * 01 -> receiver compares
197 * 10 -> receiver compares
201 * 11 -> receiver compares
202 * XON1, XON2, XOFF1 and
206 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
207 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
209 * SWFLOW bits 3 & 2 table:
210 * 00 -> no received flow
212 * 01 -> transmitter generates
214 * 10 -> transmitter generates
216 * 11 -> transmitter generates
217 * XON1, XON2, XOFF1 and
221 /* PLL configuration register masks */
222 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
223 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
225 /* Baud rate generator configuration register bits */
226 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
227 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
229 /* Clock source register bits */
230 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
231 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
232 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
233 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
234 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
236 /* Global commands */
237 #define MAX310X_EXTREG_ENBL (0xce)
238 #define MAX310X_EXTREG_DSBL (0xcd)
240 /* Misc definitions */
241 #define MAX310X_FIFO_SIZE (128)
242 #define MAX310x_REV_MASK (0xfc)
244 /* MAX3107 specific */
245 #define MAX3107_REV_ID (0xa0)
247 /* MAX3109 specific */
248 #define MAX3109_REV_ID (0xc0)
250 /* MAX14830 specific */
251 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
252 #define MAX14830_REV_ID (0xb0)
254 struct max310x_devtype
{
257 int (*detect
)(struct device
*);
258 void (*power
)(struct uart_port
*, int);
262 struct uart_port port
;
263 struct work_struct tx_work
;
264 struct work_struct md_work
;
267 struct max310x_port
{
268 struct uart_driver uart
;
269 struct max310x_devtype
*devtype
;
270 struct regmap
*regmap
;
273 #ifdef CONFIG_GPIOLIB
274 struct gpio_chip gpio
;
276 struct max310x_one p
[0];
279 static u8
max310x_port_read(struct uart_port
*port
, u8 reg
)
281 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
282 unsigned int val
= 0;
284 regmap_read(s
->regmap
, port
->iobase
+ reg
, &val
);
289 static void max310x_port_write(struct uart_port
*port
, u8 reg
, u8 val
)
291 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
293 regmap_write(s
->regmap
, port
->iobase
+ reg
, val
);
296 static void max310x_port_update(struct uart_port
*port
, u8 reg
, u8 mask
, u8 val
)
298 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
300 regmap_update_bits(s
->regmap
, port
->iobase
+ reg
, mask
, val
);
303 static int max3107_detect(struct device
*dev
)
305 struct max310x_port
*s
= dev_get_drvdata(dev
);
306 unsigned int val
= 0;
309 ret
= regmap_read(s
->regmap
, MAX310X_REVID_REG
, &val
);
313 if (((val
& MAX310x_REV_MASK
) != MAX3107_REV_ID
)) {
315 "%s ID 0x%02x does not match\n", s
->devtype
->name
, val
);
322 static int max3108_detect(struct device
*dev
)
324 struct max310x_port
*s
= dev_get_drvdata(dev
);
325 unsigned int val
= 0;
328 /* MAX3108 have not REV ID register, we just check default value
329 * from clocksource register to make sure everything works.
331 ret
= regmap_read(s
->regmap
, MAX310X_CLKSRC_REG
, &val
);
335 if (val
!= (MAX310X_CLKSRC_EXTCLK_BIT
| MAX310X_CLKSRC_PLLBYP_BIT
)) {
336 dev_err(dev
, "%s not present\n", s
->devtype
->name
);
343 static int max3109_detect(struct device
*dev
)
345 struct max310x_port
*s
= dev_get_drvdata(dev
);
346 unsigned int val
= 0;
349 ret
= regmap_read(s
->regmap
, MAX310X_REVID_REG
, &val
);
353 if (((val
& MAX310x_REV_MASK
) != MAX3109_REV_ID
)) {
355 "%s ID 0x%02x does not match\n", s
->devtype
->name
, val
);
362 static void max310x_power(struct uart_port
*port
, int on
)
364 max310x_port_update(port
, MAX310X_MODE1_REG
,
365 MAX310X_MODE1_FORCESLEEP_BIT
,
366 on
? 0 : MAX310X_MODE1_FORCESLEEP_BIT
);
371 static int max14830_detect(struct device
*dev
)
373 struct max310x_port
*s
= dev_get_drvdata(dev
);
374 unsigned int val
= 0;
377 ret
= regmap_write(s
->regmap
, MAX310X_GLOBALCMD_REG
,
378 MAX310X_EXTREG_ENBL
);
382 regmap_read(s
->regmap
, MAX310X_REVID_EXTREG
, &val
);
383 regmap_write(s
->regmap
, MAX310X_GLOBALCMD_REG
, MAX310X_EXTREG_DSBL
);
384 if (((val
& MAX310x_REV_MASK
) != MAX14830_REV_ID
)) {
386 "%s ID 0x%02x does not match\n", s
->devtype
->name
, val
);
393 static void max14830_power(struct uart_port
*port
, int on
)
395 max310x_port_update(port
, MAX310X_BRGCFG_REG
,
396 MAX14830_BRGCFG_CLKDIS_BIT
,
397 on
? 0 : MAX14830_BRGCFG_CLKDIS_BIT
);
402 static const struct max310x_devtype max3107_devtype
= {
405 .detect
= max3107_detect
,
406 .power
= max310x_power
,
409 static const struct max310x_devtype max3108_devtype
= {
412 .detect
= max3108_detect
,
413 .power
= max310x_power
,
416 static const struct max310x_devtype max3109_devtype
= {
419 .detect
= max3109_detect
,
420 .power
= max310x_power
,
423 static const struct max310x_devtype max14830_devtype
= {
426 .detect
= max14830_detect
,
427 .power
= max14830_power
,
430 static bool max310x_reg_writeable(struct device
*dev
, unsigned int reg
)
432 switch (reg
& 0x1f) {
433 case MAX310X_IRQSTS_REG
:
434 case MAX310X_LSR_IRQSTS_REG
:
435 case MAX310X_SPCHR_IRQSTS_REG
:
436 case MAX310X_STS_IRQSTS_REG
:
437 case MAX310X_TXFIFOLVL_REG
:
438 case MAX310X_RXFIFOLVL_REG
:
447 static bool max310x_reg_volatile(struct device
*dev
, unsigned int reg
)
449 switch (reg
& 0x1f) {
450 case MAX310X_RHR_REG
:
451 case MAX310X_IRQSTS_REG
:
452 case MAX310X_LSR_IRQSTS_REG
:
453 case MAX310X_SPCHR_IRQSTS_REG
:
454 case MAX310X_STS_IRQSTS_REG
:
455 case MAX310X_TXFIFOLVL_REG
:
456 case MAX310X_RXFIFOLVL_REG
:
457 case MAX310X_GPIODATA_REG
:
458 case MAX310X_BRGDIVLSB_REG
:
469 static bool max310x_reg_precious(struct device
*dev
, unsigned int reg
)
471 switch (reg
& 0x1f) {
472 case MAX310X_RHR_REG
:
473 case MAX310X_IRQSTS_REG
:
474 case MAX310X_SPCHR_IRQSTS_REG
:
475 case MAX310X_STS_IRQSTS_REG
:
484 static int max310x_set_baud(struct uart_port
*port
, int baud
)
486 unsigned int mode
= 0, clk
= port
->uartclk
, div
= clk
/ baud
;
488 /* Check for minimal value for divider */
492 if (clk
% baud
&& (div
/ 16) < 0x8000) {
494 mode
= MAX310X_BRGCFG_2XMODE_BIT
;
495 clk
= port
->uartclk
* 2;
498 if (clk
% baud
&& (div
/ 16) < 0x8000) {
500 mode
= MAX310X_BRGCFG_4XMODE_BIT
;
501 clk
= port
->uartclk
* 4;
506 max310x_port_write(port
, MAX310X_BRGDIVMSB_REG
, (div
/ 16) >> 8);
507 max310x_port_write(port
, MAX310X_BRGDIVLSB_REG
, div
/ 16);
508 max310x_port_write(port
, MAX310X_BRGCFG_REG
, (div
% 16) | mode
);
510 return DIV_ROUND_CLOSEST(clk
, div
);
513 static int max310x_update_best_err(unsigned long f
, long *besterr
)
515 /* Use baudrate 115200 for calculate error */
516 long err
= f
% (115200 * 16);
518 if ((*besterr
< 0) || (*besterr
> err
)) {
526 static int max310x_set_ref_clk(struct max310x_port
*s
, unsigned long freq
,
529 unsigned int div
, clksrc
, pllcfg
= 0;
531 unsigned long fdiv
, fmul
, bestfreq
= freq
;
533 /* First, update error without PLL */
534 max310x_update_best_err(freq
, &besterr
);
536 /* Try all possible PLL dividers */
537 for (div
= 1; (div
<= 63) && besterr
; div
++) {
538 fdiv
= DIV_ROUND_CLOSEST(freq
, div
);
540 /* Try multiplier 6 */
542 if ((fdiv
>= 500000) && (fdiv
<= 800000))
543 if (!max310x_update_best_err(fmul
, &besterr
)) {
544 pllcfg
= (0 << 6) | div
;
547 /* Try multiplier 48 */
549 if ((fdiv
>= 850000) && (fdiv
<= 1200000))
550 if (!max310x_update_best_err(fmul
, &besterr
)) {
551 pllcfg
= (1 << 6) | div
;
554 /* Try multiplier 96 */
556 if ((fdiv
>= 425000) && (fdiv
<= 1000000))
557 if (!max310x_update_best_err(fmul
, &besterr
)) {
558 pllcfg
= (2 << 6) | div
;
561 /* Try multiplier 144 */
563 if ((fdiv
>= 390000) && (fdiv
<= 667000))
564 if (!max310x_update_best_err(fmul
, &besterr
)) {
565 pllcfg
= (3 << 6) | div
;
570 /* Configure clock source */
571 clksrc
= xtal
? MAX310X_CLKSRC_CRYST_BIT
: MAX310X_CLKSRC_EXTCLK_BIT
;
575 clksrc
|= MAX310X_CLKSRC_PLL_BIT
;
576 regmap_write(s
->regmap
, MAX310X_PLLCFG_REG
, pllcfg
);
578 clksrc
|= MAX310X_CLKSRC_PLLBYP_BIT
;
580 regmap_write(s
->regmap
, MAX310X_CLKSRC_REG
, clksrc
);
582 /* Wait for crystal */
586 return (int)bestfreq
;
589 static void max310x_handle_rx(struct uart_port
*port
, unsigned int rxlen
)
591 unsigned int sts
, ch
, flag
;
593 if (unlikely(rxlen
>= port
->fifosize
)) {
594 dev_warn_ratelimited(port
->dev
,
595 "Port %i: Possible RX FIFO overrun\n",
597 port
->icount
.buf_overrun
++;
598 /* Ensure sanity of RX level */
599 rxlen
= port
->fifosize
;
603 ch
= max310x_port_read(port
, MAX310X_RHR_REG
);
604 sts
= max310x_port_read(port
, MAX310X_LSR_IRQSTS_REG
);
606 sts
&= MAX310X_LSR_RXPAR_BIT
| MAX310X_LSR_FRERR_BIT
|
607 MAX310X_LSR_RXOVR_BIT
| MAX310X_LSR_RXBRK_BIT
;
613 if (sts
& MAX310X_LSR_RXBRK_BIT
) {
615 if (uart_handle_break(port
))
617 } else if (sts
& MAX310X_LSR_RXPAR_BIT
)
618 port
->icount
.parity
++;
619 else if (sts
& MAX310X_LSR_FRERR_BIT
)
620 port
->icount
.frame
++;
621 else if (sts
& MAX310X_LSR_RXOVR_BIT
)
622 port
->icount
.overrun
++;
624 sts
&= port
->read_status_mask
;
625 if (sts
& MAX310X_LSR_RXBRK_BIT
)
627 else if (sts
& MAX310X_LSR_RXPAR_BIT
)
629 else if (sts
& MAX310X_LSR_FRERR_BIT
)
631 else if (sts
& MAX310X_LSR_RXOVR_BIT
)
635 if (uart_handle_sysrq_char(port
, ch
))
638 if (sts
& port
->ignore_status_mask
)
641 uart_insert_char(port
, sts
, MAX310X_LSR_RXOVR_BIT
, ch
, flag
);
644 tty_flip_buffer_push(&port
->state
->port
);
647 static void max310x_handle_tx(struct uart_port
*port
)
649 struct circ_buf
*xmit
= &port
->state
->xmit
;
650 unsigned int txlen
, to_send
;
652 if (unlikely(port
->x_char
)) {
653 max310x_port_write(port
, MAX310X_THR_REG
, port
->x_char
);
659 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
))
662 /* Get length of data pending in circular buffer */
663 to_send
= uart_circ_chars_pending(xmit
);
664 if (likely(to_send
)) {
665 /* Limit to size of TX FIFO */
666 txlen
= max310x_port_read(port
, MAX310X_TXFIFOLVL_REG
);
667 txlen
= port
->fifosize
- txlen
;
668 to_send
= (to_send
> txlen
) ? txlen
: to_send
;
670 /* Add data to send */
671 port
->icount
.tx
+= to_send
;
673 max310x_port_write(port
, MAX310X_THR_REG
,
674 xmit
->buf
[xmit
->tail
]);
675 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
679 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
680 uart_write_wakeup(port
);
683 static void max310x_port_irq(struct max310x_port
*s
, int portno
)
685 struct uart_port
*port
= &s
->p
[portno
].port
;
688 unsigned int ists
, lsr
, rxlen
;
690 /* Read IRQ status & RX FIFO level */
691 ists
= max310x_port_read(port
, MAX310X_IRQSTS_REG
);
692 rxlen
= max310x_port_read(port
, MAX310X_RXFIFOLVL_REG
);
696 if (ists
& MAX310X_IRQ_CTS_BIT
) {
697 lsr
= max310x_port_read(port
, MAX310X_LSR_IRQSTS_REG
);
698 uart_handle_cts_change(port
,
699 !!(lsr
& MAX310X_LSR_CTS_BIT
));
702 max310x_handle_rx(port
, rxlen
);
703 if (ists
& MAX310X_IRQ_TXEMPTY_BIT
) {
704 mutex_lock(&s
->mutex
);
705 max310x_handle_tx(port
);
706 mutex_unlock(&s
->mutex
);
711 static irqreturn_t
max310x_ist(int irq
, void *dev_id
)
713 struct max310x_port
*s
= (struct max310x_port
*)dev_id
;
715 if (s
->uart
.nr
> 1) {
717 unsigned int val
= ~0;
719 WARN_ON_ONCE(regmap_read(s
->regmap
,
720 MAX310X_GLOBALIRQ_REG
, &val
));
721 val
= ((1 << s
->uart
.nr
) - 1) & ~val
;
724 max310x_port_irq(s
, fls(val
) - 1);
727 max310x_port_irq(s
, 0);
732 static void max310x_wq_proc(struct work_struct
*ws
)
734 struct max310x_one
*one
= container_of(ws
, struct max310x_one
, tx_work
);
735 struct max310x_port
*s
= dev_get_drvdata(one
->port
.dev
);
737 mutex_lock(&s
->mutex
);
738 max310x_handle_tx(&one
->port
);
739 mutex_unlock(&s
->mutex
);
742 static void max310x_start_tx(struct uart_port
*port
)
744 struct max310x_one
*one
= container_of(port
, struct max310x_one
, port
);
746 if (!work_pending(&one
->tx_work
))
747 schedule_work(&one
->tx_work
);
750 static unsigned int max310x_tx_empty(struct uart_port
*port
)
752 unsigned int lvl
, sts
;
754 lvl
= max310x_port_read(port
, MAX310X_TXFIFOLVL_REG
);
755 sts
= max310x_port_read(port
, MAX310X_IRQSTS_REG
);
757 return ((sts
& MAX310X_IRQ_TXEMPTY_BIT
) && !lvl
) ? TIOCSER_TEMT
: 0;
760 static unsigned int max310x_get_mctrl(struct uart_port
*port
)
762 /* DCD and DSR are not wired and CTS/RTS is handled automatically
763 * so just indicate DSR and CAR asserted
765 return TIOCM_DSR
| TIOCM_CAR
;
768 static void max310x_md_proc(struct work_struct
*ws
)
770 struct max310x_one
*one
= container_of(ws
, struct max310x_one
, md_work
);
772 max310x_port_update(&one
->port
, MAX310X_MODE2_REG
,
773 MAX310X_MODE2_LOOPBACK_BIT
,
774 (one
->port
.mctrl
& TIOCM_LOOP
) ?
775 MAX310X_MODE2_LOOPBACK_BIT
: 0);
778 static void max310x_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
780 struct max310x_one
*one
= container_of(port
, struct max310x_one
, port
);
782 schedule_work(&one
->md_work
);
785 static void max310x_break_ctl(struct uart_port
*port
, int break_state
)
787 max310x_port_update(port
, MAX310X_LCR_REG
,
788 MAX310X_LCR_TXBREAK_BIT
,
789 break_state
? MAX310X_LCR_TXBREAK_BIT
: 0);
792 static void max310x_set_termios(struct uart_port
*port
,
793 struct ktermios
*termios
,
794 struct ktermios
*old
)
796 unsigned int lcr
, flow
= 0;
799 /* Mask termios capabilities we don't support */
800 termios
->c_cflag
&= ~CMSPAR
;
803 switch (termios
->c_cflag
& CSIZE
) {
805 lcr
= MAX310X_LCR_WORD_LEN_5
;
808 lcr
= MAX310X_LCR_WORD_LEN_6
;
811 lcr
= MAX310X_LCR_WORD_LEN_7
;
815 lcr
= MAX310X_LCR_WORD_LEN_8
;
820 if (termios
->c_cflag
& PARENB
) {
821 lcr
|= MAX310X_LCR_PARITY_BIT
;
822 if (!(termios
->c_cflag
& PARODD
))
823 lcr
|= MAX310X_LCR_EVENPARITY_BIT
;
827 if (termios
->c_cflag
& CSTOPB
)
828 lcr
|= MAX310X_LCR_STOPLEN_BIT
; /* 2 stops */
830 /* Update LCR register */
831 max310x_port_write(port
, MAX310X_LCR_REG
, lcr
);
833 /* Set read status mask */
834 port
->read_status_mask
= MAX310X_LSR_RXOVR_BIT
;
835 if (termios
->c_iflag
& INPCK
)
836 port
->read_status_mask
|= MAX310X_LSR_RXPAR_BIT
|
837 MAX310X_LSR_FRERR_BIT
;
838 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
839 port
->read_status_mask
|= MAX310X_LSR_RXBRK_BIT
;
841 /* Set status ignore mask */
842 port
->ignore_status_mask
= 0;
843 if (termios
->c_iflag
& IGNBRK
)
844 port
->ignore_status_mask
|= MAX310X_LSR_RXBRK_BIT
;
845 if (!(termios
->c_cflag
& CREAD
))
846 port
->ignore_status_mask
|= MAX310X_LSR_RXPAR_BIT
|
847 MAX310X_LSR_RXOVR_BIT
|
848 MAX310X_LSR_FRERR_BIT
|
849 MAX310X_LSR_RXBRK_BIT
;
851 /* Configure flow control */
852 max310x_port_write(port
, MAX310X_XON1_REG
, termios
->c_cc
[VSTART
]);
853 max310x_port_write(port
, MAX310X_XOFF1_REG
, termios
->c_cc
[VSTOP
]);
854 if (termios
->c_cflag
& CRTSCTS
)
855 flow
|= MAX310X_FLOWCTRL_AUTOCTS_BIT
|
856 MAX310X_FLOWCTRL_AUTORTS_BIT
;
857 if (termios
->c_iflag
& IXON
)
858 flow
|= MAX310X_FLOWCTRL_SWFLOW3_BIT
|
859 MAX310X_FLOWCTRL_SWFLOWEN_BIT
;
860 if (termios
->c_iflag
& IXOFF
)
861 flow
|= MAX310X_FLOWCTRL_SWFLOW1_BIT
|
862 MAX310X_FLOWCTRL_SWFLOWEN_BIT
;
863 max310x_port_write(port
, MAX310X_FLOWCTRL_REG
, flow
);
865 /* Get baud rate generator configuration */
866 baud
= uart_get_baud_rate(port
, termios
, old
,
867 port
->uartclk
/ 16 / 0xffff,
870 /* Setup baudrate generator */
871 baud
= max310x_set_baud(port
, baud
);
873 /* Update timeout according to new baud rate */
874 uart_update_timeout(port
, termios
->c_cflag
, baud
);
877 static int max310x_ioctl(struct uart_port
*port
, unsigned int cmd
,
880 #if defined(TIOCSRS485) && defined(TIOCGRS485)
881 struct serial_rs485 rs485
;
886 if (copy_from_user(&rs485
, (void __user
*)arg
, sizeof(rs485
)))
888 if (rs485
.delay_rts_before_send
> 0x0f ||
889 rs485
.delay_rts_after_send
> 0x0f)
891 val
= (rs485
.delay_rts_before_send
<< 4) |
892 rs485
.delay_rts_after_send
;
893 max310x_port_write(port
, MAX310X_HDPIXDELAY_REG
, val
);
894 if (rs485
.flags
& SER_RS485_ENABLED
) {
895 max310x_port_update(port
, MAX310X_MODE1_REG
,
896 MAX310X_MODE1_TRNSCVCTRL_BIT
,
897 MAX310X_MODE1_TRNSCVCTRL_BIT
);
898 max310x_port_update(port
, MAX310X_MODE2_REG
,
899 MAX310X_MODE2_ECHOSUPR_BIT
,
900 MAX310X_MODE2_ECHOSUPR_BIT
);
902 max310x_port_update(port
, MAX310X_MODE1_REG
,
903 MAX310X_MODE1_TRNSCVCTRL_BIT
, 0);
904 max310x_port_update(port
, MAX310X_MODE2_REG
,
905 MAX310X_MODE2_ECHOSUPR_BIT
, 0);
909 memset(&rs485
, 0, sizeof(rs485
));
910 val
= max310x_port_read(port
, MAX310X_MODE1_REG
);
911 rs485
.flags
= (val
& MAX310X_MODE1_TRNSCVCTRL_BIT
) ?
912 SER_RS485_ENABLED
: 0;
913 rs485
.flags
|= SER_RS485_RTS_ON_SEND
;
914 val
= max310x_port_read(port
, MAX310X_HDPIXDELAY_REG
);
915 rs485
.delay_rts_before_send
= val
>> 4;
916 rs485
.delay_rts_after_send
= val
& 0x0f;
917 if (copy_to_user((void __user
*)arg
, &rs485
, sizeof(rs485
)))
928 static int max310x_startup(struct uart_port
*port
)
930 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
933 s
->devtype
->power(port
, 1);
935 /* Configure MODE1 register */
936 max310x_port_update(port
, MAX310X_MODE1_REG
,
937 MAX310X_MODE1_TRNSCVCTRL_BIT
, 0);
939 /* Configure MODE2 register & Reset FIFOs*/
940 val
= MAX310X_MODE2_RXEMPTINV_BIT
| MAX310X_MODE2_FIFORST_BIT
;
941 max310x_port_write(port
, MAX310X_MODE2_REG
, val
);
942 max310x_port_update(port
, MAX310X_MODE2_REG
,
943 MAX310X_MODE2_FIFORST_BIT
, 0);
945 /* Configure flow control levels */
946 /* Flow control halt level 96, resume level 48 */
947 max310x_port_write(port
, MAX310X_FLOWLVL_REG
,
948 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
950 /* Clear IRQ status register */
951 max310x_port_read(port
, MAX310X_IRQSTS_REG
);
953 /* Enable RX, TX, CTS change interrupts */
954 val
= MAX310X_IRQ_RXEMPTY_BIT
| MAX310X_IRQ_TXEMPTY_BIT
;
955 max310x_port_write(port
, MAX310X_IRQEN_REG
, val
| MAX310X_IRQ_CTS_BIT
);
960 static void max310x_shutdown(struct uart_port
*port
)
962 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
964 /* Disable all interrupts */
965 max310x_port_write(port
, MAX310X_IRQEN_REG
, 0);
967 s
->devtype
->power(port
, 0);
970 static const char *max310x_type(struct uart_port
*port
)
972 struct max310x_port
*s
= dev_get_drvdata(port
->dev
);
974 return (port
->type
== PORT_MAX310X
) ? s
->devtype
->name
: NULL
;
977 static int max310x_request_port(struct uart_port
*port
)
983 static void max310x_config_port(struct uart_port
*port
, int flags
)
985 if (flags
& UART_CONFIG_TYPE
)
986 port
->type
= PORT_MAX310X
;
989 static int max310x_verify_port(struct uart_port
*port
, struct serial_struct
*s
)
991 if ((s
->type
!= PORT_UNKNOWN
) && (s
->type
!= PORT_MAX310X
))
993 if (s
->irq
!= port
->irq
)
999 static void max310x_null_void(struct uart_port
*port
)
1004 static const struct uart_ops max310x_ops
= {
1005 .tx_empty
= max310x_tx_empty
,
1006 .set_mctrl
= max310x_set_mctrl
,
1007 .get_mctrl
= max310x_get_mctrl
,
1008 .stop_tx
= max310x_null_void
,
1009 .start_tx
= max310x_start_tx
,
1010 .stop_rx
= max310x_null_void
,
1011 .enable_ms
= max310x_null_void
,
1012 .break_ctl
= max310x_break_ctl
,
1013 .startup
= max310x_startup
,
1014 .shutdown
= max310x_shutdown
,
1015 .set_termios
= max310x_set_termios
,
1016 .type
= max310x_type
,
1017 .request_port
= max310x_request_port
,
1018 .release_port
= max310x_null_void
,
1019 .config_port
= max310x_config_port
,
1020 .verify_port
= max310x_verify_port
,
1021 .ioctl
= max310x_ioctl
,
1024 static int __maybe_unused
max310x_suspend(struct device
*dev
)
1026 struct max310x_port
*s
= dev_get_drvdata(dev
);
1029 for (i
= 0; i
< s
->uart
.nr
; i
++) {
1030 uart_suspend_port(&s
->uart
, &s
->p
[i
].port
);
1031 s
->devtype
->power(&s
->p
[i
].port
, 0);
1037 static int __maybe_unused
max310x_resume(struct device
*dev
)
1039 struct max310x_port
*s
= dev_get_drvdata(dev
);
1042 for (i
= 0; i
< s
->uart
.nr
; i
++) {
1043 s
->devtype
->power(&s
->p
[i
].port
, 1);
1044 uart_resume_port(&s
->uart
, &s
->p
[i
].port
);
1050 static SIMPLE_DEV_PM_OPS(max310x_pm_ops
, max310x_suspend
, max310x_resume
);
1052 #ifdef CONFIG_GPIOLIB
1053 static int max310x_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1056 struct max310x_port
*s
= container_of(chip
, struct max310x_port
, gpio
);
1057 struct uart_port
*port
= &s
->p
[offset
/ 4].port
;
1059 val
= max310x_port_read(port
, MAX310X_GPIODATA_REG
);
1061 return !!((val
>> 4) & (1 << (offset
% 4)));
1064 static void max310x_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1066 struct max310x_port
*s
= container_of(chip
, struct max310x_port
, gpio
);
1067 struct uart_port
*port
= &s
->p
[offset
/ 4].port
;
1069 max310x_port_update(port
, MAX310X_GPIODATA_REG
, 1 << (offset
% 4),
1070 value
? 1 << (offset
% 4) : 0);
1073 static int max310x_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1075 struct max310x_port
*s
= container_of(chip
, struct max310x_port
, gpio
);
1076 struct uart_port
*port
= &s
->p
[offset
/ 4].port
;
1078 max310x_port_update(port
, MAX310X_GPIOCFG_REG
, 1 << (offset
% 4), 0);
1083 static int max310x_gpio_direction_output(struct gpio_chip
*chip
,
1084 unsigned offset
, int value
)
1086 struct max310x_port
*s
= container_of(chip
, struct max310x_port
, gpio
);
1087 struct uart_port
*port
= &s
->p
[offset
/ 4].port
;
1089 max310x_port_update(port
, MAX310X_GPIODATA_REG
, 1 << (offset
% 4),
1090 value
? 1 << (offset
% 4) : 0);
1091 max310x_port_update(port
, MAX310X_GPIOCFG_REG
, 1 << (offset
% 4),
1098 static int max310x_probe(struct device
*dev
, struct max310x_devtype
*devtype
,
1099 struct regmap
*regmap
, int irq
, unsigned long flags
)
1101 int i
, ret
, fmin
, fmax
, freq
, uartclk
;
1102 struct clk
*clk_osc
, *clk_xtal
;
1103 struct max310x_port
*s
;
1107 return PTR_ERR(regmap
);
1109 /* Alloc port structure */
1110 s
= devm_kzalloc(dev
, sizeof(*s
) +
1111 sizeof(struct max310x_one
) * devtype
->nr
, GFP_KERNEL
);
1113 dev_err(dev
, "Error allocating port structure\n");
1117 clk_osc
= devm_clk_get(dev
, "osc");
1118 clk_xtal
= devm_clk_get(dev
, "xtal");
1119 if (!IS_ERR(clk_osc
)) {
1123 } else if (!IS_ERR(clk_xtal
)) {
1128 } else if (PTR_ERR(clk_osc
) == -EPROBE_DEFER
||
1129 PTR_ERR(clk_xtal
) == -EPROBE_DEFER
) {
1130 return -EPROBE_DEFER
;
1132 dev_err(dev
, "Cannot get clock\n");
1136 ret
= clk_prepare_enable(s
->clk
);
1140 freq
= clk_get_rate(s
->clk
);
1141 /* Check frequency limits */
1142 if (freq
< fmin
|| freq
> fmax
) {
1148 s
->devtype
= devtype
;
1149 dev_set_drvdata(dev
, s
);
1151 /* Check device to ensure we are talking to what we expect */
1152 ret
= devtype
->detect(dev
);
1156 for (i
= 0; i
< devtype
->nr
; i
++) {
1157 unsigned int offs
= i
<< 5;
1160 regmap_write(s
->regmap
, MAX310X_MODE2_REG
+ offs
,
1161 MAX310X_MODE2_RST_BIT
);
1162 /* Clear port reset */
1163 regmap_write(s
->regmap
, MAX310X_MODE2_REG
+ offs
, 0);
1165 /* Wait for port startup */
1167 regmap_read(s
->regmap
,
1168 MAX310X_BRGDIVLSB_REG
+ offs
, &ret
);
1169 } while (ret
!= 0x01);
1171 regmap_update_bits(s
->regmap
, MAX310X_MODE1_REG
+ offs
,
1172 MAX310X_MODE1_AUTOSLEEP_BIT
,
1173 MAX310X_MODE1_AUTOSLEEP_BIT
);
1176 uartclk
= max310x_set_ref_clk(s
, freq
, xtal
);
1177 dev_dbg(dev
, "Reference clock set to %i Hz\n", uartclk
);
1179 /* Register UART driver */
1180 s
->uart
.owner
= THIS_MODULE
;
1181 s
->uart
.dev_name
= "ttyMAX";
1182 s
->uart
.major
= MAX310X_MAJOR
;
1183 s
->uart
.minor
= MAX310X_MINOR
;
1184 s
->uart
.nr
= devtype
->nr
;
1185 ret
= uart_register_driver(&s
->uart
);
1187 dev_err(dev
, "Registering UART driver failed\n");
1191 #ifdef CONFIG_GPIOLIB
1192 /* Setup GPIO cotroller */
1193 s
->gpio
.owner
= THIS_MODULE
;
1195 s
->gpio
.label
= dev_name(dev
);
1196 s
->gpio
.direction_input
= max310x_gpio_direction_input
;
1197 s
->gpio
.get
= max310x_gpio_get
;
1198 s
->gpio
.direction_output
= max310x_gpio_direction_output
;
1199 s
->gpio
.set
= max310x_gpio_set
;
1201 s
->gpio
.ngpio
= devtype
->nr
* 4;
1202 s
->gpio
.can_sleep
= 1;
1203 ret
= gpiochip_add(&s
->gpio
);
1208 mutex_init(&s
->mutex
);
1210 for (i
= 0; i
< devtype
->nr
; i
++) {
1211 /* Initialize port data */
1212 s
->p
[i
].port
.line
= i
;
1213 s
->p
[i
].port
.dev
= dev
;
1214 s
->p
[i
].port
.irq
= irq
;
1215 s
->p
[i
].port
.type
= PORT_MAX310X
;
1216 s
->p
[i
].port
.fifosize
= MAX310X_FIFO_SIZE
;
1217 s
->p
[i
].port
.flags
= UPF_FIXED_TYPE
| UPF_LOW_LATENCY
;
1218 s
->p
[i
].port
.iotype
= UPIO_PORT
;
1219 s
->p
[i
].port
.iobase
= i
* 0x20;
1220 s
->p
[i
].port
.membase
= (void __iomem
*)~0;
1221 s
->p
[i
].port
.uartclk
= uartclk
;
1222 s
->p
[i
].port
.ops
= &max310x_ops
;
1223 /* Disable all interrupts */
1224 max310x_port_write(&s
->p
[i
].port
, MAX310X_IRQEN_REG
, 0);
1225 /* Clear IRQ status register */
1226 max310x_port_read(&s
->p
[i
].port
, MAX310X_IRQSTS_REG
);
1227 /* Enable IRQ pin */
1228 max310x_port_update(&s
->p
[i
].port
, MAX310X_MODE1_REG
,
1229 MAX310X_MODE1_IRQSEL_BIT
,
1230 MAX310X_MODE1_IRQSEL_BIT
);
1231 /* Initialize queue for start TX */
1232 INIT_WORK(&s
->p
[i
].tx_work
, max310x_wq_proc
);
1233 /* Initialize queue for changing mode */
1234 INIT_WORK(&s
->p
[i
].md_work
, max310x_md_proc
);
1236 uart_add_one_port(&s
->uart
, &s
->p
[i
].port
);
1237 /* Go to suspend mode */
1238 devtype
->power(&s
->p
[i
].port
, 0);
1241 /* Setup interrupt */
1242 ret
= devm_request_threaded_irq(dev
, irq
, NULL
, max310x_ist
,
1243 IRQF_ONESHOT
| flags
, dev_name(dev
), s
);
1247 dev_err(dev
, "Unable to reguest IRQ %i\n", irq
);
1249 mutex_destroy(&s
->mutex
);
1251 #ifdef CONFIG_GPIOLIB
1252 WARN_ON(gpiochip_remove(&s
->gpio
));
1256 uart_unregister_driver(&s
->uart
);
1259 clk_disable_unprepare(s
->clk
);
1264 static int max310x_remove(struct device
*dev
)
1266 struct max310x_port
*s
= dev_get_drvdata(dev
);
1269 #ifdef CONFIG_GPIOLIB
1270 ret
= gpiochip_remove(&s
->gpio
);
1275 for (i
= 0; i
< s
->uart
.nr
; i
++) {
1276 cancel_work_sync(&s
->p
[i
].tx_work
);
1277 cancel_work_sync(&s
->p
[i
].md_work
);
1278 uart_remove_one_port(&s
->uart
, &s
->p
[i
].port
);
1279 s
->devtype
->power(&s
->p
[i
].port
, 0);
1282 mutex_destroy(&s
->mutex
);
1283 uart_unregister_driver(&s
->uart
);
1284 clk_disable_unprepare(s
->clk
);
1289 static const struct of_device_id __maybe_unused max310x_dt_ids
[] = {
1290 { .compatible
= "maxim,max3107", .data
= &max3107_devtype
, },
1291 { .compatible
= "maxim,max3108", .data
= &max3108_devtype
, },
1292 { .compatible
= "maxim,max3109", .data
= &max3109_devtype
, },
1293 { .compatible
= "maxim,max14830", .data
= &max14830_devtype
},
1296 MODULE_DEVICE_TABLE(of
, max310x_dt_ids
);
1298 static struct regmap_config regcfg
= {
1301 .write_flag_mask
= 0x80,
1302 .cache_type
= REGCACHE_RBTREE
,
1303 .writeable_reg
= max310x_reg_writeable
,
1304 .volatile_reg
= max310x_reg_volatile
,
1305 .precious_reg
= max310x_reg_precious
,
1308 #ifdef CONFIG_SPI_MASTER
1309 static int max310x_spi_probe(struct spi_device
*spi
)
1311 struct max310x_devtype
*devtype
;
1312 unsigned long flags
= 0;
1313 struct regmap
*regmap
;
1317 spi
->bits_per_word
= 8;
1318 spi
->mode
= spi
->mode
? : SPI_MODE_0
;
1319 spi
->max_speed_hz
= spi
->max_speed_hz
? : 26000000;
1320 ret
= spi_setup(spi
);
1324 if (spi
->dev
.of_node
) {
1325 const struct of_device_id
*of_id
=
1326 of_match_device(max310x_dt_ids
, &spi
->dev
);
1328 devtype
= (struct max310x_devtype
*)of_id
->data
;
1330 const struct spi_device_id
*id_entry
= spi_get_device_id(spi
);
1332 devtype
= (struct max310x_devtype
*)id_entry
->driver_data
;
1333 flags
= IRQF_TRIGGER_FALLING
;
1336 regcfg
.max_register
= devtype
->nr
* 0x20 - 1;
1337 regmap
= devm_regmap_init_spi(spi
, ®cfg
);
1339 return max310x_probe(&spi
->dev
, devtype
, regmap
, spi
->irq
, flags
);
1342 static int max310x_spi_remove(struct spi_device
*spi
)
1344 return max310x_remove(&spi
->dev
);
1347 static const struct spi_device_id max310x_id_table
[] = {
1348 { "max3107", (kernel_ulong_t
)&max3107_devtype
, },
1349 { "max3108", (kernel_ulong_t
)&max3108_devtype
, },
1350 { "max3109", (kernel_ulong_t
)&max3109_devtype
, },
1351 { "max14830", (kernel_ulong_t
)&max14830_devtype
, },
1354 MODULE_DEVICE_TABLE(spi
, max310x_id_table
);
1356 static struct spi_driver max310x_uart_driver
= {
1358 .name
= MAX310X_NAME
,
1359 .owner
= THIS_MODULE
,
1360 .of_match_table
= of_match_ptr(max310x_dt_ids
),
1361 .pm
= &max310x_pm_ops
,
1363 .probe
= max310x_spi_probe
,
1364 .remove
= max310x_spi_remove
,
1365 .id_table
= max310x_id_table
,
1367 module_spi_driver(max310x_uart_driver
);
1370 MODULE_LICENSE("GPL");
1371 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1372 MODULE_DESCRIPTION("MAX310X serial driver");