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Merge branch 'for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / drivers / tty / serial / meson_uart.c
1 /*
2 * Based on meson_uart.c, by AMLOGIC, INC.
3 *
4 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/clk.h>
18 #include <linux/console.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial.h>
27 #include <linux/serial_core.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30
31 /* Register offsets */
32 #define AML_UART_WFIFO 0x00
33 #define AML_UART_RFIFO 0x04
34 #define AML_UART_CONTROL 0x08
35 #define AML_UART_STATUS 0x0c
36 #define AML_UART_MISC 0x10
37 #define AML_UART_REG5 0x14
38
39 /* AML_UART_CONTROL bits */
40 #define AML_UART_TX_EN BIT(12)
41 #define AML_UART_RX_EN BIT(13)
42 #define AML_UART_TX_RST BIT(22)
43 #define AML_UART_RX_RST BIT(23)
44 #define AML_UART_CLR_ERR BIT(24)
45 #define AML_UART_RX_INT_EN BIT(27)
46 #define AML_UART_TX_INT_EN BIT(28)
47 #define AML_UART_DATA_LEN_MASK (0x03 << 20)
48 #define AML_UART_DATA_LEN_8BIT (0x00 << 20)
49 #define AML_UART_DATA_LEN_7BIT (0x01 << 20)
50 #define AML_UART_DATA_LEN_6BIT (0x02 << 20)
51 #define AML_UART_DATA_LEN_5BIT (0x03 << 20)
52
53 /* AML_UART_STATUS bits */
54 #define AML_UART_PARITY_ERR BIT(16)
55 #define AML_UART_FRAME_ERR BIT(17)
56 #define AML_UART_TX_FIFO_WERR BIT(18)
57 #define AML_UART_RX_EMPTY BIT(20)
58 #define AML_UART_TX_FULL BIT(21)
59 #define AML_UART_TX_EMPTY BIT(22)
60 #define AML_UART_XMIT_BUSY BIT(25)
61 #define AML_UART_ERR (AML_UART_PARITY_ERR | \
62 AML_UART_FRAME_ERR | \
63 AML_UART_TX_FIFO_WERR)
64
65 /* AML_UART_CONTROL bits */
66 #define AML_UART_TWO_WIRE_EN BIT(15)
67 #define AML_UART_PARITY_TYPE BIT(18)
68 #define AML_UART_PARITY_EN BIT(19)
69 #define AML_UART_CLEAR_ERR BIT(24)
70 #define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16)
71 #define AML_UART_STOP_BIN_1SB (0x00 << 16)
72 #define AML_UART_STOP_BIN_2SB (0x01 << 16)
73
74 /* AML_UART_MISC bits */
75 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
76 #define AML_UART_RECV_IRQ(c) ((c) & 0xff)
77
78 /* AML_UART_REG5 bits */
79 #define AML_UART_BAUD_MASK 0x7fffff
80 #define AML_UART_BAUD_USE BIT(23)
81
82 #define AML_UART_PORT_NUM 6
83 #define AML_UART_DEV_NAME "ttyAML"
84
85
86 static struct uart_driver meson_uart_driver;
87
88 static struct uart_port *meson_ports[AML_UART_PORT_NUM];
89
90 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
91 {
92 }
93
94 static unsigned int meson_uart_get_mctrl(struct uart_port *port)
95 {
96 return TIOCM_CTS;
97 }
98
99 static unsigned int meson_uart_tx_empty(struct uart_port *port)
100 {
101 u32 val;
102
103 val = readl(port->membase + AML_UART_STATUS);
104 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
105 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
106 }
107
108 static void meson_uart_stop_tx(struct uart_port *port)
109 {
110 u32 val;
111
112 val = readl(port->membase + AML_UART_CONTROL);
113 val &= ~AML_UART_TX_INT_EN;
114 writel(val, port->membase + AML_UART_CONTROL);
115 }
116
117 static void meson_uart_stop_rx(struct uart_port *port)
118 {
119 u32 val;
120
121 val = readl(port->membase + AML_UART_CONTROL);
122 val &= ~AML_UART_RX_EN;
123 writel(val, port->membase + AML_UART_CONTROL);
124 }
125
126 static void meson_uart_shutdown(struct uart_port *port)
127 {
128 unsigned long flags;
129 u32 val;
130
131 free_irq(port->irq, port);
132
133 spin_lock_irqsave(&port->lock, flags);
134
135 val = readl(port->membase + AML_UART_CONTROL);
136 val &= ~AML_UART_RX_EN;
137 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
138 writel(val, port->membase + AML_UART_CONTROL);
139
140 spin_unlock_irqrestore(&port->lock, flags);
141 }
142
143 static void meson_uart_start_tx(struct uart_port *port)
144 {
145 struct circ_buf *xmit = &port->state->xmit;
146 unsigned int ch;
147 u32 val;
148
149 if (uart_tx_stopped(port)) {
150 meson_uart_stop_tx(port);
151 return;
152 }
153
154 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
155 if (port->x_char) {
156 writel(port->x_char, port->membase + AML_UART_WFIFO);
157 port->icount.tx++;
158 port->x_char = 0;
159 continue;
160 }
161
162 if (uart_circ_empty(xmit))
163 break;
164
165 ch = xmit->buf[xmit->tail];
166 writel(ch, port->membase + AML_UART_WFIFO);
167 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
168 port->icount.tx++;
169 }
170
171 if (!uart_circ_empty(xmit)) {
172 val = readl(port->membase + AML_UART_CONTROL);
173 val |= AML_UART_TX_INT_EN;
174 writel(val, port->membase + AML_UART_CONTROL);
175 }
176
177 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
178 uart_write_wakeup(port);
179 }
180
181 static void meson_receive_chars(struct uart_port *port)
182 {
183 struct tty_port *tport = &port->state->port;
184 char flag;
185 u32 status, ch, mode;
186
187 do {
188 flag = TTY_NORMAL;
189 port->icount.rx++;
190 status = readl(port->membase + AML_UART_STATUS);
191
192 if (status & AML_UART_ERR) {
193 if (status & AML_UART_TX_FIFO_WERR)
194 port->icount.overrun++;
195 else if (status & AML_UART_FRAME_ERR)
196 port->icount.frame++;
197 else if (status & AML_UART_PARITY_ERR)
198 port->icount.frame++;
199
200 mode = readl(port->membase + AML_UART_CONTROL);
201 mode |= AML_UART_CLEAR_ERR;
202 writel(mode, port->membase + AML_UART_CONTROL);
203
204 /* It doesn't clear to 0 automatically */
205 mode &= ~AML_UART_CLEAR_ERR;
206 writel(mode, port->membase + AML_UART_CONTROL);
207
208 status &= port->read_status_mask;
209 if (status & AML_UART_FRAME_ERR)
210 flag = TTY_FRAME;
211 else if (status & AML_UART_PARITY_ERR)
212 flag = TTY_PARITY;
213 }
214
215 ch = readl(port->membase + AML_UART_RFIFO);
216 ch &= 0xff;
217
218 if ((status & port->ignore_status_mask) == 0)
219 tty_insert_flip_char(tport, ch, flag);
220
221 if (status & AML_UART_TX_FIFO_WERR)
222 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
223
224 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
225
226 spin_unlock(&port->lock);
227 tty_flip_buffer_push(tport);
228 spin_lock(&port->lock);
229 }
230
231 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
232 {
233 struct uart_port *port = (struct uart_port *)dev_id;
234
235 spin_lock(&port->lock);
236
237 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
238 meson_receive_chars(port);
239
240 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
241 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
242 meson_uart_start_tx(port);
243 }
244
245 spin_unlock(&port->lock);
246
247 return IRQ_HANDLED;
248 }
249
250 static const char *meson_uart_type(struct uart_port *port)
251 {
252 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
253 }
254
255 static void meson_uart_reset(struct uart_port *port)
256 {
257 u32 val;
258
259 val = readl(port->membase + AML_UART_CONTROL);
260 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
261 writel(val, port->membase + AML_UART_CONTROL);
262
263 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
264 writel(val, port->membase + AML_UART_CONTROL);
265 }
266
267 static int meson_uart_startup(struct uart_port *port)
268 {
269 u32 val;
270 int ret = 0;
271
272 val = readl(port->membase + AML_UART_CONTROL);
273 val |= AML_UART_CLR_ERR;
274 writel(val, port->membase + AML_UART_CONTROL);
275 val &= ~AML_UART_CLR_ERR;
276 writel(val, port->membase + AML_UART_CONTROL);
277
278 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
279 writel(val, port->membase + AML_UART_CONTROL);
280
281 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
282 writel(val, port->membase + AML_UART_CONTROL);
283
284 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
285 writel(val, port->membase + AML_UART_MISC);
286
287 ret = request_irq(port->irq, meson_uart_interrupt, 0,
288 meson_uart_type(port), port);
289
290 return ret;
291 }
292
293 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
294 {
295 u32 val;
296
297 while (!meson_uart_tx_empty(port))
298 cpu_relax();
299
300 val = readl(port->membase + AML_UART_REG5);
301 val &= ~AML_UART_BAUD_MASK;
302 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
303 val |= AML_UART_BAUD_USE;
304 writel(val, port->membase + AML_UART_REG5);
305 }
306
307 static void meson_uart_set_termios(struct uart_port *port,
308 struct ktermios *termios,
309 struct ktermios *old)
310 {
311 unsigned int cflags, iflags, baud;
312 unsigned long flags;
313 u32 val;
314
315 spin_lock_irqsave(&port->lock, flags);
316
317 cflags = termios->c_cflag;
318 iflags = termios->c_iflag;
319
320 val = readl(port->membase + AML_UART_CONTROL);
321
322 val &= ~AML_UART_DATA_LEN_MASK;
323 switch (cflags & CSIZE) {
324 case CS8:
325 val |= AML_UART_DATA_LEN_8BIT;
326 break;
327 case CS7:
328 val |= AML_UART_DATA_LEN_7BIT;
329 break;
330 case CS6:
331 val |= AML_UART_DATA_LEN_6BIT;
332 break;
333 case CS5:
334 val |= AML_UART_DATA_LEN_5BIT;
335 break;
336 }
337
338 if (cflags & PARENB)
339 val |= AML_UART_PARITY_EN;
340 else
341 val &= ~AML_UART_PARITY_EN;
342
343 if (cflags & PARODD)
344 val |= AML_UART_PARITY_TYPE;
345 else
346 val &= ~AML_UART_PARITY_TYPE;
347
348 val &= ~AML_UART_STOP_BIN_LEN_MASK;
349 if (cflags & CSTOPB)
350 val |= AML_UART_STOP_BIN_2SB;
351 else
352 val &= ~AML_UART_STOP_BIN_1SB;
353
354 if (cflags & CRTSCTS)
355 val &= ~AML_UART_TWO_WIRE_EN;
356 else
357 val |= AML_UART_TWO_WIRE_EN;
358
359 writel(val, port->membase + AML_UART_CONTROL);
360
361 baud = uart_get_baud_rate(port, termios, old, 9600, 115200);
362 meson_uart_change_speed(port, baud);
363
364 port->read_status_mask = AML_UART_TX_FIFO_WERR;
365 if (iflags & INPCK)
366 port->read_status_mask |= AML_UART_PARITY_ERR |
367 AML_UART_FRAME_ERR;
368
369 port->ignore_status_mask = 0;
370 if (iflags & IGNPAR)
371 port->ignore_status_mask |= AML_UART_PARITY_ERR |
372 AML_UART_FRAME_ERR;
373
374 uart_update_timeout(port, termios->c_cflag, baud);
375 spin_unlock_irqrestore(&port->lock, flags);
376 }
377
378 static int meson_uart_verify_port(struct uart_port *port,
379 struct serial_struct *ser)
380 {
381 int ret = 0;
382
383 if (port->type != PORT_MESON)
384 ret = -EINVAL;
385 if (port->irq != ser->irq)
386 ret = -EINVAL;
387 if (ser->baud_base < 9600)
388 ret = -EINVAL;
389 return ret;
390 }
391
392 static int meson_uart_res_size(struct uart_port *port)
393 {
394 struct platform_device *pdev = to_platform_device(port->dev);
395 struct resource *res;
396
397 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
398 if (!res) {
399 dev_err(port->dev, "cannot obtain I/O memory region");
400 return -ENODEV;
401 }
402
403 return resource_size(res);
404 }
405
406 static void meson_uart_release_port(struct uart_port *port)
407 {
408 int size = meson_uart_res_size(port);
409
410 if (port->flags & UPF_IOREMAP) {
411 devm_release_mem_region(port->dev, port->mapbase, size);
412 devm_iounmap(port->dev, port->membase);
413 port->membase = NULL;
414 }
415 }
416
417 static int meson_uart_request_port(struct uart_port *port)
418 {
419 int size = meson_uart_res_size(port);
420
421 if (size < 0)
422 return size;
423
424 if (!devm_request_mem_region(port->dev, port->mapbase, size,
425 dev_name(port->dev))) {
426 dev_err(port->dev, "Memory region busy\n");
427 return -EBUSY;
428 }
429
430 if (port->flags & UPF_IOREMAP) {
431 port->membase = devm_ioremap_nocache(port->dev,
432 port->mapbase,
433 size);
434 if (port->membase == NULL)
435 return -ENOMEM;
436 }
437
438 return 0;
439 }
440
441 static void meson_uart_config_port(struct uart_port *port, int flags)
442 {
443 if (flags & UART_CONFIG_TYPE) {
444 port->type = PORT_MESON;
445 meson_uart_request_port(port);
446 }
447 }
448
449 static struct uart_ops meson_uart_ops = {
450 .set_mctrl = meson_uart_set_mctrl,
451 .get_mctrl = meson_uart_get_mctrl,
452 .tx_empty = meson_uart_tx_empty,
453 .start_tx = meson_uart_start_tx,
454 .stop_tx = meson_uart_stop_tx,
455 .stop_rx = meson_uart_stop_rx,
456 .startup = meson_uart_startup,
457 .shutdown = meson_uart_shutdown,
458 .set_termios = meson_uart_set_termios,
459 .type = meson_uart_type,
460 .config_port = meson_uart_config_port,
461 .request_port = meson_uart_request_port,
462 .release_port = meson_uart_release_port,
463 .verify_port = meson_uart_verify_port,
464 };
465
466 #ifdef CONFIG_SERIAL_MESON_CONSOLE
467
468 static void meson_console_putchar(struct uart_port *port, int ch)
469 {
470 if (!port->membase)
471 return;
472
473 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
474 cpu_relax();
475 writel(ch, port->membase + AML_UART_WFIFO);
476 }
477
478 static void meson_serial_console_write(struct console *co, const char *s,
479 u_int count)
480 {
481 struct uart_port *port;
482 unsigned long flags;
483 int locked;
484 u32 val, tmp;
485
486 port = meson_ports[co->index];
487 if (!port)
488 return;
489
490 local_irq_save(flags);
491 if (port->sysrq) {
492 locked = 0;
493 } else if (oops_in_progress) {
494 locked = spin_trylock(&port->lock);
495 } else {
496 spin_lock(&port->lock);
497 locked = 1;
498 }
499
500 val = readl(port->membase + AML_UART_CONTROL);
501 val |= AML_UART_TX_EN;
502 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
503 writel(tmp, port->membase + AML_UART_CONTROL);
504
505 uart_console_write(port, s, count, meson_console_putchar);
506 writel(val, port->membase + AML_UART_CONTROL);
507
508 if (locked)
509 spin_unlock(&port->lock);
510 local_irq_restore(flags);
511 }
512
513 static int meson_serial_console_setup(struct console *co, char *options)
514 {
515 struct uart_port *port;
516 int baud = 115200;
517 int bits = 8;
518 int parity = 'n';
519 int flow = 'n';
520
521 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
522 return -EINVAL;
523
524 port = meson_ports[co->index];
525 if (!port || !port->membase)
526 return -ENODEV;
527
528 if (options)
529 uart_parse_options(options, &baud, &parity, &bits, &flow);
530
531 return uart_set_options(port, co, baud, parity, bits, flow);
532 }
533
534 static struct console meson_serial_console = {
535 .name = AML_UART_DEV_NAME,
536 .write = meson_serial_console_write,
537 .device = uart_console_device,
538 .setup = meson_serial_console_setup,
539 .flags = CON_PRINTBUFFER,
540 .index = -1,
541 .data = &meson_uart_driver,
542 };
543
544 static int __init meson_serial_console_init(void)
545 {
546 register_console(&meson_serial_console);
547 return 0;
548 }
549 console_initcall(meson_serial_console_init);
550
551 #define MESON_SERIAL_CONSOLE (&meson_serial_console)
552 #else
553 #define MESON_SERIAL_CONSOLE NULL
554 #endif
555
556 static struct uart_driver meson_uart_driver = {
557 .owner = THIS_MODULE,
558 .driver_name = "meson_uart",
559 .dev_name = AML_UART_DEV_NAME,
560 .nr = AML_UART_PORT_NUM,
561 .cons = MESON_SERIAL_CONSOLE,
562 };
563
564 static int meson_uart_probe(struct platform_device *pdev)
565 {
566 struct resource *res_mem, *res_irq;
567 struct uart_port *port;
568 struct clk *clk;
569 int ret = 0;
570
571 if (pdev->dev.of_node)
572 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
573
574 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
575 return -EINVAL;
576
577 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
578 if (!res_mem)
579 return -ENODEV;
580
581 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
582 if (!res_irq)
583 return -ENODEV;
584
585 if (meson_ports[pdev->id]) {
586 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
587 return -EBUSY;
588 }
589
590 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
591 if (!port)
592 return -ENOMEM;
593
594 clk = clk_get(&pdev->dev, NULL);
595 if (IS_ERR(clk))
596 return PTR_ERR(clk);
597
598 port->uartclk = clk_get_rate(clk);
599 port->iotype = UPIO_MEM;
600 port->mapbase = res_mem->start;
601 port->irq = res_irq->start;
602 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
603 port->dev = &pdev->dev;
604 port->line = pdev->id;
605 port->type = PORT_MESON;
606 port->x_char = 0;
607 port->ops = &meson_uart_ops;
608 port->fifosize = 64;
609
610 meson_ports[pdev->id] = port;
611 platform_set_drvdata(pdev, port);
612
613 /* reset port before registering (and possibly registering console) */
614 if (meson_uart_request_port(port) >= 0) {
615 meson_uart_reset(port);
616 meson_uart_release_port(port);
617 }
618
619 ret = uart_add_one_port(&meson_uart_driver, port);
620 if (ret)
621 meson_ports[pdev->id] = NULL;
622
623 return ret;
624 }
625
626 static int meson_uart_remove(struct platform_device *pdev)
627 {
628 struct uart_port *port;
629
630 port = platform_get_drvdata(pdev);
631 uart_remove_one_port(&meson_uart_driver, port);
632 meson_ports[pdev->id] = NULL;
633
634 return 0;
635 }
636
637
638 static const struct of_device_id meson_uart_dt_match[] = {
639 { .compatible = "amlogic,meson-uart" },
640 { /* sentinel */ },
641 };
642 MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
643
644 static struct platform_driver meson_uart_platform_driver = {
645 .probe = meson_uart_probe,
646 .remove = meson_uart_remove,
647 .driver = {
648 .name = "meson_uart",
649 .of_match_table = meson_uart_dt_match,
650 },
651 };
652
653 static int __init meson_uart_init(void)
654 {
655 int ret;
656
657 ret = uart_register_driver(&meson_uart_driver);
658 if (ret)
659 return ret;
660
661 ret = platform_driver_register(&meson_uart_platform_driver);
662 if (ret)
663 uart_unregister_driver(&meson_uart_driver);
664
665 return ret;
666 }
667
668 static void __exit meson_uart_exit(void)
669 {
670 platform_driver_unregister(&meson_uart_platform_driver);
671 uart_unregister_driver(&meson_uart_driver);
672 }
673
674 module_init(meson_uart_init);
675 module_exit(meson_uart_exit);
676
677 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
678 MODULE_DESCRIPTION("Amlogic Meson serial port driver");
679 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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