2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #include <linux/tty.h>
59 #include <linux/tty_flip.h>
60 #include <linux/ioport.h>
61 #include <linux/init.h>
62 #include <linux/console.h>
63 #include <linux/sysrq.h>
64 #include <linux/serial.h>
65 #include <linux/serial_core.h>
66 #include <linux/delay.h>
67 #include <linux/device.h>
68 #include <linux/dma-mapping.h>
69 #include <linux/mv643xx.h>
70 #include <linux/platform_device.h>
71 #include <linux/gfp.h>
76 #define MPSC_NUM_CTLRS 2
79 * Descriptors and buffers must be cache line aligned.
80 * Buffers lengths must be multiple of cache line size.
81 * Number of Tx & Rx descriptors must be powers of 2.
83 #define MPSC_RXR_ENTRIES 32
84 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
85 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
86 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
87 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
89 #define MPSC_TXR_ENTRIES 32
90 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
91 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
92 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
93 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
95 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
96 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
98 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
105 } __attribute((packed
));
107 struct mpsc_tx_desc
{
113 } __attribute((packed
));
116 * Some regs that have the erratum that you can't read them are are shared
117 * between the two MPSC controllers. This struct contains those shared regs.
119 struct mpsc_shared_regs
{
120 phys_addr_t mpsc_routing_base_p
;
121 phys_addr_t sdma_intr_base_p
;
123 void __iomem
*mpsc_routing_base
;
124 void __iomem
*sdma_intr_base
;
129 u32 SDMA_INTR_CAUSE_m
;
130 u32 SDMA_INTR_MASK_m
;
133 /* The main driver data structure */
134 struct mpsc_port_info
{
135 struct uart_port port
; /* Overlay uart_port structure */
137 /* Internal driver state for this ctlr */
140 tcflag_t c_iflag
; /* save termios->c_iflag */
141 tcflag_t c_cflag
; /* save termios->c_cflag */
143 /* Info passed in from platform */
144 u8 mirror_regs
; /* Need to mirror regs? */
145 u8 cache_mgmt
; /* Need manual cache mgmt? */
146 u8 brg_can_tune
; /* BRG has baud tuning? */
154 /* Physical addresses of various blocks of registers (from platform) */
155 phys_addr_t mpsc_base_p
;
156 phys_addr_t sdma_base_p
;
157 phys_addr_t brg_base_p
;
159 /* Virtual addresses of various blocks of registers (from platform) */
160 void __iomem
*mpsc_base
;
161 void __iomem
*sdma_base
;
162 void __iomem
*brg_base
;
164 /* Descriptor ring and buffer allocations */
166 dma_addr_t dma_region_p
;
168 dma_addr_t rxr
; /* Rx descriptor ring */
169 dma_addr_t rxr_p
; /* Phys addr of rxr */
170 u8
*rxb
; /* Rx Ring I/O buf */
171 u8
*rxb_p
; /* Phys addr of rxb */
172 u32 rxr_posn
; /* First desc w/ Rx data */
174 dma_addr_t txr
; /* Tx descriptor ring */
175 dma_addr_t txr_p
; /* Phys addr of txr */
176 u8
*txb
; /* Tx Ring I/O buf */
177 u8
*txb_p
; /* Phys addr of txb */
178 int txr_head
; /* Where new data goes */
179 int txr_tail
; /* Where sent data comes off */
180 spinlock_t tx_lock
; /* transmit lock */
182 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
188 struct mpsc_shared_regs
*shared_regs
;
191 /* Hooks to platform-specific code */
192 int mpsc_platform_register_driver(void);
193 void mpsc_platform_unregister_driver(void);
195 /* Hooks back in to mpsc common to be called by platform-specific code */
196 struct mpsc_port_info
*mpsc_device_probe(int index
);
197 struct mpsc_port_info
*mpsc_device_remove(int index
);
199 /* Main MPSC Configuration Register Offsets */
200 #define MPSC_MMCRL 0x0000
201 #define MPSC_MMCRH 0x0004
202 #define MPSC_MPCR 0x0008
203 #define MPSC_CHR_1 0x000c
204 #define MPSC_CHR_2 0x0010
205 #define MPSC_CHR_3 0x0014
206 #define MPSC_CHR_4 0x0018
207 #define MPSC_CHR_5 0x001c
208 #define MPSC_CHR_6 0x0020
209 #define MPSC_CHR_7 0x0024
210 #define MPSC_CHR_8 0x0028
211 #define MPSC_CHR_9 0x002c
212 #define MPSC_CHR_10 0x0030
213 #define MPSC_CHR_11 0x0034
215 #define MPSC_MPCR_FRZ (1 << 9)
216 #define MPSC_MPCR_CL_5 0
217 #define MPSC_MPCR_CL_6 1
218 #define MPSC_MPCR_CL_7 2
219 #define MPSC_MPCR_CL_8 3
220 #define MPSC_MPCR_SBL_1 0
221 #define MPSC_MPCR_SBL_2 1
223 #define MPSC_CHR_2_TEV (1<<1)
224 #define MPSC_CHR_2_TA (1<<7)
225 #define MPSC_CHR_2_TTCS (1<<9)
226 #define MPSC_CHR_2_REV (1<<17)
227 #define MPSC_CHR_2_RA (1<<23)
228 #define MPSC_CHR_2_CRD (1<<25)
229 #define MPSC_CHR_2_EH (1<<31)
230 #define MPSC_CHR_2_PAR_ODD 0
231 #define MPSC_CHR_2_PAR_SPACE 1
232 #define MPSC_CHR_2_PAR_EVEN 2
233 #define MPSC_CHR_2_PAR_MARK 3
235 /* MPSC Signal Routing */
236 #define MPSC_MRR 0x0000
237 #define MPSC_RCRR 0x0004
238 #define MPSC_TCRR 0x0008
240 /* Serial DMA Controller Interface Registers */
241 #define SDMA_SDC 0x0000
242 #define SDMA_SDCM 0x0008
243 #define SDMA_RX_DESC 0x0800
244 #define SDMA_RX_BUF_PTR 0x0808
245 #define SDMA_SCRDP 0x0810
246 #define SDMA_TX_DESC 0x0c00
247 #define SDMA_SCTDP 0x0c10
248 #define SDMA_SFTDP 0x0c14
250 #define SDMA_DESC_CMDSTAT_PE (1<<0)
251 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
252 #define SDMA_DESC_CMDSTAT_FR (1<<3)
253 #define SDMA_DESC_CMDSTAT_OR (1<<6)
254 #define SDMA_DESC_CMDSTAT_BR (1<<9)
255 #define SDMA_DESC_CMDSTAT_MI (1<<10)
256 #define SDMA_DESC_CMDSTAT_A (1<<11)
257 #define SDMA_DESC_CMDSTAT_AM (1<<12)
258 #define SDMA_DESC_CMDSTAT_CT (1<<13)
259 #define SDMA_DESC_CMDSTAT_C (1<<14)
260 #define SDMA_DESC_CMDSTAT_ES (1<<15)
261 #define SDMA_DESC_CMDSTAT_L (1<<16)
262 #define SDMA_DESC_CMDSTAT_F (1<<17)
263 #define SDMA_DESC_CMDSTAT_P (1<<18)
264 #define SDMA_DESC_CMDSTAT_EI (1<<23)
265 #define SDMA_DESC_CMDSTAT_O (1<<31)
267 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
268 | SDMA_DESC_CMDSTAT_EI)
270 #define SDMA_SDC_RFT (1<<0)
271 #define SDMA_SDC_SFM (1<<1)
272 #define SDMA_SDC_BLMR (1<<6)
273 #define SDMA_SDC_BLMT (1<<7)
274 #define SDMA_SDC_POVR (1<<8)
275 #define SDMA_SDC_RIFB (1<<9)
277 #define SDMA_SDCM_ERD (1<<7)
278 #define SDMA_SDCM_AR (1<<15)
279 #define SDMA_SDCM_STD (1<<16)
280 #define SDMA_SDCM_TXD (1<<23)
281 #define SDMA_SDCM_AT (1<<31)
283 #define SDMA_0_CAUSE_RXBUF (1<<0)
284 #define SDMA_0_CAUSE_RXERR (1<<1)
285 #define SDMA_0_CAUSE_TXBUF (1<<2)
286 #define SDMA_0_CAUSE_TXEND (1<<3)
287 #define SDMA_1_CAUSE_RXBUF (1<<8)
288 #define SDMA_1_CAUSE_RXERR (1<<9)
289 #define SDMA_1_CAUSE_TXBUF (1<<10)
290 #define SDMA_1_CAUSE_TXEND (1<<11)
292 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
293 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
294 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
295 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
297 /* SDMA Interrupt registers */
298 #define SDMA_INTR_CAUSE 0x0000
299 #define SDMA_INTR_MASK 0x0080
301 /* Baud Rate Generator Interface Registers */
302 #define BRG_BCR 0x0000
303 #define BRG_BTR 0x0004
306 * Define how this driver is known to the outside (we've been assigned a
307 * range on the "Low-density serial ports" major).
309 #define MPSC_MAJOR 204
310 #define MPSC_MINOR_START 44
311 #define MPSC_DRIVER_NAME "MPSC"
312 #define MPSC_DEV_NAME "ttyMM"
313 #define MPSC_VERSION "1.00"
315 static struct mpsc_port_info mpsc_ports
[MPSC_NUM_CTLRS
];
316 static struct mpsc_shared_regs mpsc_shared_regs
;
317 static struct uart_driver mpsc_reg
;
319 static void mpsc_start_rx(struct mpsc_port_info
*pi
);
320 static void mpsc_free_ring_mem(struct mpsc_port_info
*pi
);
321 static void mpsc_release_port(struct uart_port
*port
);
323 ******************************************************************************
325 * Baud Rate Generator Routines (BRG)
327 ******************************************************************************
329 static void mpsc_brg_init(struct mpsc_port_info
*pi
, u32 clk_src
)
333 v
= (pi
->mirror_regs
) ? pi
->BRG_BCR_m
: readl(pi
->brg_base
+ BRG_BCR
);
334 v
= (v
& ~(0xf << 18)) | ((clk_src
& 0xf) << 18);
336 if (pi
->brg_can_tune
)
341 writel(v
, pi
->brg_base
+ BRG_BCR
);
343 writel(readl(pi
->brg_base
+ BRG_BTR
) & 0xffff0000,
344 pi
->brg_base
+ BRG_BTR
);
347 static void mpsc_brg_enable(struct mpsc_port_info
*pi
)
351 v
= (pi
->mirror_regs
) ? pi
->BRG_BCR_m
: readl(pi
->brg_base
+ BRG_BCR
);
356 writel(v
, pi
->brg_base
+ BRG_BCR
);
359 static void mpsc_brg_disable(struct mpsc_port_info
*pi
)
363 v
= (pi
->mirror_regs
) ? pi
->BRG_BCR_m
: readl(pi
->brg_base
+ BRG_BCR
);
368 writel(v
, pi
->brg_base
+ BRG_BCR
);
372 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
373 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
374 * However, the input clock is divided by 16 in the MPSC b/c of how
375 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
376 * calculation by 16 to account for that. So the real calculation
377 * that accounts for the way the mpsc is set up is:
378 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
380 static void mpsc_set_baudrate(struct mpsc_port_info
*pi
, u32 baud
)
382 u32 cdv
= (pi
->port
.uartclk
/ (baud
<< 5)) - 1;
385 mpsc_brg_disable(pi
);
386 v
= (pi
->mirror_regs
) ? pi
->BRG_BCR_m
: readl(pi
->brg_base
+ BRG_BCR
);
387 v
= (v
& 0xffff0000) | (cdv
& 0xffff);
391 writel(v
, pi
->brg_base
+ BRG_BCR
);
396 ******************************************************************************
398 * Serial DMA Routines (SDMA)
400 ******************************************************************************
403 static void mpsc_sdma_burstsize(struct mpsc_port_info
*pi
, u32 burst_size
)
407 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
408 pi
->port
.line
, burst_size
);
410 burst_size
>>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
413 v
= 0x0; /* 1 64-bit word */
414 else if (burst_size
< 4)
415 v
= 0x1; /* 2 64-bit words */
416 else if (burst_size
< 8)
417 v
= 0x2; /* 4 64-bit words */
419 v
= 0x3; /* 8 64-bit words */
421 writel((readl(pi
->sdma_base
+ SDMA_SDC
) & (0x3 << 12)) | (v
<< 12),
422 pi
->sdma_base
+ SDMA_SDC
);
425 static void mpsc_sdma_init(struct mpsc_port_info
*pi
, u32 burst_size
)
427 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi
->port
.line
,
430 writel((readl(pi
->sdma_base
+ SDMA_SDC
) & 0x3ff) | 0x03f,
431 pi
->sdma_base
+ SDMA_SDC
);
432 mpsc_sdma_burstsize(pi
, burst_size
);
435 static u32
mpsc_sdma_intr_mask(struct mpsc_port_info
*pi
, u32 mask
)
439 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi
->port
.line
, mask
);
441 old
= v
= (pi
->mirror_regs
) ? pi
->shared_regs
->SDMA_INTR_MASK_m
:
442 readl(pi
->shared_regs
->sdma_intr_base
+ SDMA_INTR_MASK
);
450 pi
->shared_regs
->SDMA_INTR_MASK_m
= v
;
451 writel(v
, pi
->shared_regs
->sdma_intr_base
+ SDMA_INTR_MASK
);
458 static void mpsc_sdma_intr_unmask(struct mpsc_port_info
*pi
, u32 mask
)
462 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi
->port
.line
,mask
);
464 v
= (pi
->mirror_regs
) ? pi
->shared_regs
->SDMA_INTR_MASK_m
465 : readl(pi
->shared_regs
->sdma_intr_base
+ SDMA_INTR_MASK
);
473 pi
->shared_regs
->SDMA_INTR_MASK_m
= v
;
474 writel(v
, pi
->shared_regs
->sdma_intr_base
+ SDMA_INTR_MASK
);
477 static void mpsc_sdma_intr_ack(struct mpsc_port_info
*pi
)
479 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi
->port
.line
);
482 pi
->shared_regs
->SDMA_INTR_CAUSE_m
= 0;
483 writeb(0x00, pi
->shared_regs
->sdma_intr_base
+ SDMA_INTR_CAUSE
487 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info
*pi
,
488 struct mpsc_rx_desc
*rxre_p
)
490 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
491 pi
->port
.line
, (u32
)rxre_p
);
493 writel((u32
)rxre_p
, pi
->sdma_base
+ SDMA_SCRDP
);
496 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info
*pi
,
497 struct mpsc_tx_desc
*txre_p
)
499 writel((u32
)txre_p
, pi
->sdma_base
+ SDMA_SFTDP
);
500 writel((u32
)txre_p
, pi
->sdma_base
+ SDMA_SCTDP
);
503 static void mpsc_sdma_cmd(struct mpsc_port_info
*pi
, u32 val
)
507 v
= readl(pi
->sdma_base
+ SDMA_SDCM
);
513 writel(v
, pi
->sdma_base
+ SDMA_SDCM
);
517 static uint
mpsc_sdma_tx_active(struct mpsc_port_info
*pi
)
519 return readl(pi
->sdma_base
+ SDMA_SDCM
) & SDMA_SDCM_TXD
;
522 static void mpsc_sdma_start_tx(struct mpsc_port_info
*pi
)
524 struct mpsc_tx_desc
*txre
, *txre_p
;
526 /* If tx isn't running & there's a desc ready to go, start it */
527 if (!mpsc_sdma_tx_active(pi
)) {
528 txre
= (struct mpsc_tx_desc
*)(pi
->txr
529 + (pi
->txr_tail
* MPSC_TXRE_SIZE
));
530 dma_cache_sync(pi
->port
.dev
, (void *)txre
, MPSC_TXRE_SIZE
,
532 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
533 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
534 invalidate_dcache_range((ulong
)txre
,
535 (ulong
)txre
+ MPSC_TXRE_SIZE
);
538 if (be32_to_cpu(txre
->cmdstat
) & SDMA_DESC_CMDSTAT_O
) {
539 txre_p
= (struct mpsc_tx_desc
*)
540 (pi
->txr_p
+ (pi
->txr_tail
* MPSC_TXRE_SIZE
));
542 mpsc_sdma_set_tx_ring(pi
, txre_p
);
543 mpsc_sdma_cmd(pi
, SDMA_SDCM_STD
| SDMA_SDCM_TXD
);
548 static void mpsc_sdma_stop(struct mpsc_port_info
*pi
)
550 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi
->port
.line
);
552 /* Abort any SDMA transfers */
553 mpsc_sdma_cmd(pi
, 0);
554 mpsc_sdma_cmd(pi
, SDMA_SDCM_AR
| SDMA_SDCM_AT
);
556 /* Clear the SDMA current and first TX and RX pointers */
557 mpsc_sdma_set_tx_ring(pi
, NULL
);
558 mpsc_sdma_set_rx_ring(pi
, NULL
);
560 /* Disable interrupts */
561 mpsc_sdma_intr_mask(pi
, 0xf);
562 mpsc_sdma_intr_ack(pi
);
566 ******************************************************************************
568 * Multi-Protocol Serial Controller Routines (MPSC)
570 ******************************************************************************
573 static void mpsc_hw_init(struct mpsc_port_info
*pi
)
577 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi
->port
.line
);
579 /* Set up clock routing */
580 if (pi
->mirror_regs
) {
581 v
= pi
->shared_regs
->MPSC_MRR_m
;
583 pi
->shared_regs
->MPSC_MRR_m
= v
;
584 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_MRR
);
586 v
= pi
->shared_regs
->MPSC_RCRR_m
;
587 v
= (v
& ~0xf0f) | 0x100;
588 pi
->shared_regs
->MPSC_RCRR_m
= v
;
589 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_RCRR
);
591 v
= pi
->shared_regs
->MPSC_TCRR_m
;
592 v
= (v
& ~0xf0f) | 0x100;
593 pi
->shared_regs
->MPSC_TCRR_m
= v
;
594 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_TCRR
);
596 v
= readl(pi
->shared_regs
->mpsc_routing_base
+ MPSC_MRR
);
598 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_MRR
);
600 v
= readl(pi
->shared_regs
->mpsc_routing_base
+ MPSC_RCRR
);
601 v
= (v
& ~0xf0f) | 0x100;
602 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_RCRR
);
604 v
= readl(pi
->shared_regs
->mpsc_routing_base
+ MPSC_TCRR
);
605 v
= (v
& ~0xf0f) | 0x100;
606 writel(v
, pi
->shared_regs
->mpsc_routing_base
+ MPSC_TCRR
);
609 /* Put MPSC in UART mode & enabel Tx/Rx egines */
610 writel(0x000004c4, pi
->mpsc_base
+ MPSC_MMCRL
);
612 /* No preamble, 16x divider, low-latency, */
613 writel(0x04400400, pi
->mpsc_base
+ MPSC_MMCRH
);
614 mpsc_set_baudrate(pi
, pi
->default_baud
);
616 if (pi
->mirror_regs
) {
617 pi
->MPSC_CHR_1_m
= 0;
618 pi
->MPSC_CHR_2_m
= 0;
620 writel(0, pi
->mpsc_base
+ MPSC_CHR_1
);
621 writel(0, pi
->mpsc_base
+ MPSC_CHR_2
);
622 writel(pi
->mpsc_max_idle
, pi
->mpsc_base
+ MPSC_CHR_3
);
623 writel(0, pi
->mpsc_base
+ MPSC_CHR_4
);
624 writel(0, pi
->mpsc_base
+ MPSC_CHR_5
);
625 writel(0, pi
->mpsc_base
+ MPSC_CHR_6
);
626 writel(0, pi
->mpsc_base
+ MPSC_CHR_7
);
627 writel(0, pi
->mpsc_base
+ MPSC_CHR_8
);
628 writel(0, pi
->mpsc_base
+ MPSC_CHR_9
);
629 writel(0, pi
->mpsc_base
+ MPSC_CHR_10
);
632 static void mpsc_enter_hunt(struct mpsc_port_info
*pi
)
634 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi
->port
.line
);
636 if (pi
->mirror_regs
) {
637 writel(pi
->MPSC_CHR_2_m
| MPSC_CHR_2_EH
,
638 pi
->mpsc_base
+ MPSC_CHR_2
);
639 /* Erratum prevents reading CHR_2 so just delay for a while */
642 writel(readl(pi
->mpsc_base
+ MPSC_CHR_2
) | MPSC_CHR_2_EH
,
643 pi
->mpsc_base
+ MPSC_CHR_2
);
645 while (readl(pi
->mpsc_base
+ MPSC_CHR_2
) & MPSC_CHR_2_EH
)
650 static void mpsc_freeze(struct mpsc_port_info
*pi
)
654 pr_debug("mpsc_freeze[%d]: Freezing\n", pi
->port
.line
);
656 v
= (pi
->mirror_regs
) ? pi
->MPSC_MPCR_m
:
657 readl(pi
->mpsc_base
+ MPSC_MPCR
);
662 writel(v
, pi
->mpsc_base
+ MPSC_MPCR
);
665 static void mpsc_unfreeze(struct mpsc_port_info
*pi
)
669 v
= (pi
->mirror_regs
) ? pi
->MPSC_MPCR_m
:
670 readl(pi
->mpsc_base
+ MPSC_MPCR
);
675 writel(v
, pi
->mpsc_base
+ MPSC_MPCR
);
677 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi
->port
.line
);
680 static void mpsc_set_char_length(struct mpsc_port_info
*pi
, u32 len
)
684 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi
->port
.line
,len
);
686 v
= (pi
->mirror_regs
) ? pi
->MPSC_MPCR_m
:
687 readl(pi
->mpsc_base
+ MPSC_MPCR
);
688 v
= (v
& ~(0x3 << 12)) | ((len
& 0x3) << 12);
692 writel(v
, pi
->mpsc_base
+ MPSC_MPCR
);
695 static void mpsc_set_stop_bit_length(struct mpsc_port_info
*pi
, u32 len
)
699 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
702 v
= (pi
->mirror_regs
) ? pi
->MPSC_MPCR_m
:
703 readl(pi
->mpsc_base
+ MPSC_MPCR
);
705 v
= (v
& ~(1 << 14)) | ((len
& 0x1) << 14);
709 writel(v
, pi
->mpsc_base
+ MPSC_MPCR
);
712 static void mpsc_set_parity(struct mpsc_port_info
*pi
, u32 p
)
716 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi
->port
.line
, p
);
718 v
= (pi
->mirror_regs
) ? pi
->MPSC_CHR_2_m
:
719 readl(pi
->mpsc_base
+ MPSC_CHR_2
);
722 v
= (v
& ~0xc000c) | (p
<< 18) | (p
<< 2);
725 pi
->MPSC_CHR_2_m
= v
;
726 writel(v
, pi
->mpsc_base
+ MPSC_CHR_2
);
730 ******************************************************************************
732 * Driver Init Routines
734 ******************************************************************************
737 static void mpsc_init_hw(struct mpsc_port_info
*pi
)
739 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi
->port
.line
);
741 mpsc_brg_init(pi
, pi
->brg_clk_src
);
743 mpsc_sdma_init(pi
, dma_get_cache_alignment()); /* burst a cacheline */
748 static int mpsc_alloc_ring_mem(struct mpsc_port_info
*pi
)
752 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
755 if (!pi
->dma_region
) {
756 if (!dma_set_mask(pi
->port
.dev
, 0xffffffff)) {
757 printk(KERN_ERR
"MPSC: Inadequate DMA support\n");
759 } else if ((pi
->dma_region
= dma_alloc_noncoherent(pi
->port
.dev
,
761 &pi
->dma_region_p
, GFP_KERNEL
))
763 printk(KERN_ERR
"MPSC: Can't alloc Desc region\n");
771 static void mpsc_free_ring_mem(struct mpsc_port_info
*pi
)
773 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi
->port
.line
);
775 if (pi
->dma_region
) {
776 dma_free_noncoherent(pi
->port
.dev
, MPSC_DMA_ALLOC_SIZE
,
777 pi
->dma_region
, pi
->dma_region_p
);
778 pi
->dma_region
= NULL
;
779 pi
->dma_region_p
= (dma_addr_t
)NULL
;
783 static void mpsc_init_rings(struct mpsc_port_info
*pi
)
785 struct mpsc_rx_desc
*rxre
;
786 struct mpsc_tx_desc
*txre
;
791 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi
->port
.line
);
793 BUG_ON(pi
->dma_region
== NULL
);
795 memset(pi
->dma_region
, 0, MPSC_DMA_ALLOC_SIZE
);
798 * Descriptors & buffers are multiples of cacheline size and must be
801 dp
= ALIGN((u32
)pi
->dma_region
, dma_get_cache_alignment());
802 dp_p
= ALIGN((u32
)pi
->dma_region_p
, dma_get_cache_alignment());
805 * Partition dma region into rx ring descriptor, rx buffers,
806 * tx ring descriptors, and tx buffers.
811 dp_p
+= MPSC_RXR_SIZE
;
814 pi
->rxb_p
= (u8
*)dp_p
;
816 dp_p
+= MPSC_RXB_SIZE
;
823 dp_p
+= MPSC_TXR_SIZE
;
826 pi
->txb_p
= (u8
*)dp_p
;
831 /* Init rx ring descriptors */
837 for (i
= 0; i
< MPSC_RXR_ENTRIES
; i
++) {
838 rxre
= (struct mpsc_rx_desc
*)dp
;
840 rxre
->bufsize
= cpu_to_be16(MPSC_RXBE_SIZE
);
841 rxre
->bytecnt
= cpu_to_be16(0);
842 rxre
->cmdstat
= cpu_to_be32(SDMA_DESC_CMDSTAT_O
843 | SDMA_DESC_CMDSTAT_EI
| SDMA_DESC_CMDSTAT_F
844 | SDMA_DESC_CMDSTAT_L
);
845 rxre
->link
= cpu_to_be32(dp_p
+ MPSC_RXRE_SIZE
);
846 rxre
->buf_ptr
= cpu_to_be32(bp_p
);
848 dp
+= MPSC_RXRE_SIZE
;
849 dp_p
+= MPSC_RXRE_SIZE
;
850 bp
+= MPSC_RXBE_SIZE
;
851 bp_p
+= MPSC_RXBE_SIZE
;
853 rxre
->link
= cpu_to_be32(pi
->rxr_p
); /* Wrap last back to first */
855 /* Init tx ring descriptors */
861 for (i
= 0; i
< MPSC_TXR_ENTRIES
; i
++) {
862 txre
= (struct mpsc_tx_desc
*)dp
;
864 txre
->link
= cpu_to_be32(dp_p
+ MPSC_TXRE_SIZE
);
865 txre
->buf_ptr
= cpu_to_be32(bp_p
);
867 dp
+= MPSC_TXRE_SIZE
;
868 dp_p
+= MPSC_TXRE_SIZE
;
869 bp
+= MPSC_TXBE_SIZE
;
870 bp_p
+= MPSC_TXBE_SIZE
;
872 txre
->link
= cpu_to_be32(pi
->txr_p
); /* Wrap last back to first */
874 dma_cache_sync(pi
->port
.dev
, (void *)pi
->dma_region
,
875 MPSC_DMA_ALLOC_SIZE
, DMA_BIDIRECTIONAL
);
876 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
877 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
878 flush_dcache_range((ulong
)pi
->dma_region
,
879 (ulong
)pi
->dma_region
880 + MPSC_DMA_ALLOC_SIZE
);
886 static void mpsc_uninit_rings(struct mpsc_port_info
*pi
)
888 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi
->port
.line
);
890 BUG_ON(pi
->dma_region
== NULL
);
906 static int mpsc_make_ready(struct mpsc_port_info
*pi
)
910 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi
->port
.line
);
914 rc
= mpsc_alloc_ring_mem(pi
);
924 #ifdef CONFIG_CONSOLE_POLL
925 static int serial_polled
;
929 ******************************************************************************
931 * Interrupt Handling Routines
933 ******************************************************************************
936 static int mpsc_rx_intr(struct mpsc_port_info
*pi
, unsigned long *flags
)
938 struct mpsc_rx_desc
*rxre
;
939 struct tty_port
*port
= &pi
->port
.state
->port
;
940 u32 cmdstat
, bytes_in
, i
;
943 char flag
= TTY_NORMAL
;
945 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi
->port
.line
);
947 rxre
= (struct mpsc_rx_desc
*)(pi
->rxr
+ (pi
->rxr_posn
*MPSC_RXRE_SIZE
));
949 dma_cache_sync(pi
->port
.dev
, (void *)rxre
, MPSC_RXRE_SIZE
,
951 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
952 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
953 invalidate_dcache_range((ulong
)rxre
,
954 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
958 * Loop through Rx descriptors handling ones that have been completed.
960 while (!((cmdstat
= be32_to_cpu(rxre
->cmdstat
))
961 & SDMA_DESC_CMDSTAT_O
)) {
962 bytes_in
= be16_to_cpu(rxre
->bytecnt
);
963 #ifdef CONFIG_CONSOLE_POLL
964 if (unlikely(serial_polled
)) {
969 /* Following use of tty struct directly is deprecated */
970 if (tty_buffer_request_room(port
, bytes_in
) < bytes_in
) {
971 if (port
->low_latency
) {
972 spin_unlock_irqrestore(&pi
->port
.lock
, *flags
);
973 tty_flip_buffer_push(port
);
974 spin_lock_irqsave(&pi
->port
.lock
, *flags
);
977 * If this failed then we will throw away the bytes
978 * but must do so to clear interrupts.
982 bp
= pi
->rxb
+ (pi
->rxr_posn
* MPSC_RXBE_SIZE
);
983 dma_cache_sync(pi
->port
.dev
, (void *)bp
, MPSC_RXBE_SIZE
,
985 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
986 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
987 invalidate_dcache_range((ulong
)bp
,
988 (ulong
)bp
+ MPSC_RXBE_SIZE
);
992 * Other than for parity error, the manual provides little
993 * info on what data will be in a frame flagged by any of
994 * these errors. For parity error, it is the last byte in
995 * the buffer that had the error. As for the rest, I guess
996 * we'll assume there is no data in the buffer.
997 * If there is...it gets lost.
999 if (unlikely(cmdstat
& (SDMA_DESC_CMDSTAT_BR
1000 | SDMA_DESC_CMDSTAT_FR
1001 | SDMA_DESC_CMDSTAT_OR
))) {
1003 pi
->port
.icount
.rx
++;
1005 if (cmdstat
& SDMA_DESC_CMDSTAT_BR
) { /* Break */
1006 pi
->port
.icount
.brk
++;
1008 if (uart_handle_break(&pi
->port
))
1010 } else if (cmdstat
& SDMA_DESC_CMDSTAT_FR
) {
1011 pi
->port
.icount
.frame
++;
1012 } else if (cmdstat
& SDMA_DESC_CMDSTAT_OR
) {
1013 pi
->port
.icount
.overrun
++;
1016 cmdstat
&= pi
->port
.read_status_mask
;
1018 if (cmdstat
& SDMA_DESC_CMDSTAT_BR
)
1020 else if (cmdstat
& SDMA_DESC_CMDSTAT_FR
)
1022 else if (cmdstat
& SDMA_DESC_CMDSTAT_OR
)
1024 else if (cmdstat
& SDMA_DESC_CMDSTAT_PE
)
1028 if (uart_handle_sysrq_char(&pi
->port
, *bp
)) {
1031 #ifdef CONFIG_CONSOLE_POLL
1032 if (unlikely(serial_polled
)) {
1040 if ((unlikely(cmdstat
& (SDMA_DESC_CMDSTAT_BR
1041 | SDMA_DESC_CMDSTAT_FR
1042 | SDMA_DESC_CMDSTAT_OR
)))
1043 && !(cmdstat
& pi
->port
.ignore_status_mask
)) {
1044 tty_insert_flip_char(port
, *bp
, flag
);
1046 for (i
=0; i
<bytes_in
; i
++)
1047 tty_insert_flip_char(port
, *bp
++, TTY_NORMAL
);
1049 pi
->port
.icount
.rx
+= bytes_in
;
1053 rxre
->bytecnt
= cpu_to_be16(0);
1055 rxre
->cmdstat
= cpu_to_be32(SDMA_DESC_CMDSTAT_O
1056 | SDMA_DESC_CMDSTAT_EI
| SDMA_DESC_CMDSTAT_F
1057 | SDMA_DESC_CMDSTAT_L
);
1059 dma_cache_sync(pi
->port
.dev
, (void *)rxre
, MPSC_RXRE_SIZE
,
1061 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1062 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1063 flush_dcache_range((ulong
)rxre
,
1064 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
1067 /* Advance to next descriptor */
1068 pi
->rxr_posn
= (pi
->rxr_posn
+ 1) & (MPSC_RXR_ENTRIES
- 1);
1069 rxre
= (struct mpsc_rx_desc
*)
1070 (pi
->rxr
+ (pi
->rxr_posn
* MPSC_RXRE_SIZE
));
1071 dma_cache_sync(pi
->port
.dev
, (void *)rxre
, MPSC_RXRE_SIZE
,
1073 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1074 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1075 invalidate_dcache_range((ulong
)rxre
,
1076 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
1081 /* Restart rx engine, if its stopped */
1082 if ((readl(pi
->sdma_base
+ SDMA_SDCM
) & SDMA_SDCM_ERD
) == 0)
1085 spin_unlock_irqrestore(&pi
->port
.lock
, *flags
);
1086 tty_flip_buffer_push(port
);
1087 spin_lock_irqsave(&pi
->port
.lock
, *flags
);
1091 static void mpsc_setup_tx_desc(struct mpsc_port_info
*pi
, u32 count
, u32 intr
)
1093 struct mpsc_tx_desc
*txre
;
1095 txre
= (struct mpsc_tx_desc
*)(pi
->txr
1096 + (pi
->txr_head
* MPSC_TXRE_SIZE
));
1098 txre
->bytecnt
= cpu_to_be16(count
);
1099 txre
->shadow
= txre
->bytecnt
;
1100 wmb(); /* ensure cmdstat is last field updated */
1101 txre
->cmdstat
= cpu_to_be32(SDMA_DESC_CMDSTAT_O
| SDMA_DESC_CMDSTAT_F
1102 | SDMA_DESC_CMDSTAT_L
1103 | ((intr
) ? SDMA_DESC_CMDSTAT_EI
: 0));
1105 dma_cache_sync(pi
->port
.dev
, (void *)txre
, MPSC_TXRE_SIZE
,
1107 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1108 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1109 flush_dcache_range((ulong
)txre
,
1110 (ulong
)txre
+ MPSC_TXRE_SIZE
);
1114 static void mpsc_copy_tx_data(struct mpsc_port_info
*pi
)
1116 struct circ_buf
*xmit
= &pi
->port
.state
->xmit
;
1120 /* Make sure the desc ring isn't full */
1121 while (CIRC_CNT(pi
->txr_head
, pi
->txr_tail
, MPSC_TXR_ENTRIES
)
1122 < (MPSC_TXR_ENTRIES
- 1)) {
1123 if (pi
->port
.x_char
) {
1125 * Ideally, we should use the TCS field in
1126 * CHR_1 to put the x_char out immediately but
1127 * errata prevents us from being able to read
1128 * CHR_2 to know that its safe to write to
1129 * CHR_1. Instead, just put it in-band with
1130 * all the other Tx data.
1132 bp
= pi
->txb
+ (pi
->txr_head
* MPSC_TXBE_SIZE
);
1133 *bp
= pi
->port
.x_char
;
1134 pi
->port
.x_char
= 0;
1136 } else if (!uart_circ_empty(xmit
)
1137 && !uart_tx_stopped(&pi
->port
)) {
1138 i
= min((u32
)MPSC_TXBE_SIZE
,
1139 (u32
)uart_circ_chars_pending(xmit
));
1140 i
= min(i
, (u32
)CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
,
1142 bp
= pi
->txb
+ (pi
->txr_head
* MPSC_TXBE_SIZE
);
1143 memcpy(bp
, &xmit
->buf
[xmit
->tail
], i
);
1144 xmit
->tail
= (xmit
->tail
+ i
) & (UART_XMIT_SIZE
- 1);
1146 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1147 uart_write_wakeup(&pi
->port
);
1148 } else { /* All tx data copied into ring bufs */
1152 dma_cache_sync(pi
->port
.dev
, (void *)bp
, MPSC_TXBE_SIZE
,
1154 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1155 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1156 flush_dcache_range((ulong
)bp
,
1157 (ulong
)bp
+ MPSC_TXBE_SIZE
);
1159 mpsc_setup_tx_desc(pi
, i
, 1);
1161 /* Advance to next descriptor */
1162 pi
->txr_head
= (pi
->txr_head
+ 1) & (MPSC_TXR_ENTRIES
- 1);
1166 static int mpsc_tx_intr(struct mpsc_port_info
*pi
)
1168 struct mpsc_tx_desc
*txre
;
1170 unsigned long iflags
;
1172 spin_lock_irqsave(&pi
->tx_lock
, iflags
);
1174 if (!mpsc_sdma_tx_active(pi
)) {
1175 txre
= (struct mpsc_tx_desc
*)(pi
->txr
1176 + (pi
->txr_tail
* MPSC_TXRE_SIZE
));
1178 dma_cache_sync(pi
->port
.dev
, (void *)txre
, MPSC_TXRE_SIZE
,
1180 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1181 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1182 invalidate_dcache_range((ulong
)txre
,
1183 (ulong
)txre
+ MPSC_TXRE_SIZE
);
1186 while (!(be32_to_cpu(txre
->cmdstat
) & SDMA_DESC_CMDSTAT_O
)) {
1188 pi
->port
.icount
.tx
+= be16_to_cpu(txre
->bytecnt
);
1189 pi
->txr_tail
= (pi
->txr_tail
+1) & (MPSC_TXR_ENTRIES
-1);
1191 /* If no more data to tx, fall out of loop */
1192 if (pi
->txr_head
== pi
->txr_tail
)
1195 txre
= (struct mpsc_tx_desc
*)(pi
->txr
1196 + (pi
->txr_tail
* MPSC_TXRE_SIZE
));
1197 dma_cache_sync(pi
->port
.dev
, (void *)txre
,
1198 MPSC_TXRE_SIZE
, DMA_FROM_DEVICE
);
1199 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1200 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1201 invalidate_dcache_range((ulong
)txre
,
1202 (ulong
)txre
+ MPSC_TXRE_SIZE
);
1206 mpsc_copy_tx_data(pi
);
1207 mpsc_sdma_start_tx(pi
); /* start next desc if ready */
1210 spin_unlock_irqrestore(&pi
->tx_lock
, iflags
);
1215 * This is the driver's interrupt handler. To avoid a race, we first clear
1216 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1217 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1219 static irqreturn_t
mpsc_sdma_intr(int irq
, void *dev_id
)
1221 struct mpsc_port_info
*pi
= dev_id
;
1225 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi
->port
.line
);
1227 spin_lock_irqsave(&pi
->port
.lock
, iflags
);
1228 mpsc_sdma_intr_ack(pi
);
1229 if (mpsc_rx_intr(pi
, &iflags
))
1231 if (mpsc_tx_intr(pi
))
1233 spin_unlock_irqrestore(&pi
->port
.lock
, iflags
);
1235 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi
->port
.line
);
1240 ******************************************************************************
1242 * serial_core.c Interface routines
1244 ******************************************************************************
1246 static uint
mpsc_tx_empty(struct uart_port
*port
)
1248 struct mpsc_port_info
*pi
=
1249 container_of(port
, struct mpsc_port_info
, port
);
1253 spin_lock_irqsave(&pi
->port
.lock
, iflags
);
1254 rc
= mpsc_sdma_tx_active(pi
) ? 0 : TIOCSER_TEMT
;
1255 spin_unlock_irqrestore(&pi
->port
.lock
, iflags
);
1260 static void mpsc_set_mctrl(struct uart_port
*port
, uint mctrl
)
1262 /* Have no way to set modem control lines AFAICT */
1265 static uint
mpsc_get_mctrl(struct uart_port
*port
)
1267 struct mpsc_port_info
*pi
=
1268 container_of(port
, struct mpsc_port_info
, port
);
1271 status
= (pi
->mirror_regs
) ? pi
->MPSC_CHR_10_m
1272 : readl(pi
->mpsc_base
+ MPSC_CHR_10
);
1276 mflags
|= TIOCM_CTS
;
1278 mflags
|= TIOCM_CAR
;
1280 return mflags
| TIOCM_DSR
; /* No way to tell if DSR asserted */
1283 static void mpsc_stop_tx(struct uart_port
*port
)
1285 struct mpsc_port_info
*pi
=
1286 container_of(port
, struct mpsc_port_info
, port
);
1288 pr_debug("mpsc_stop_tx[%d]\n", port
->line
);
1293 static void mpsc_start_tx(struct uart_port
*port
)
1295 struct mpsc_port_info
*pi
=
1296 container_of(port
, struct mpsc_port_info
, port
);
1297 unsigned long iflags
;
1299 spin_lock_irqsave(&pi
->tx_lock
, iflags
);
1302 mpsc_copy_tx_data(pi
);
1303 mpsc_sdma_start_tx(pi
);
1305 spin_unlock_irqrestore(&pi
->tx_lock
, iflags
);
1307 pr_debug("mpsc_start_tx[%d]\n", port
->line
);
1310 static void mpsc_start_rx(struct mpsc_port_info
*pi
)
1312 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi
->port
.line
);
1315 mpsc_enter_hunt(pi
);
1316 mpsc_sdma_cmd(pi
, SDMA_SDCM_ERD
);
1320 static void mpsc_stop_rx(struct uart_port
*port
)
1322 struct mpsc_port_info
*pi
=
1323 container_of(port
, struct mpsc_port_info
, port
);
1325 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port
->line
);
1327 if (pi
->mirror_regs
) {
1328 writel(pi
->MPSC_CHR_2_m
| MPSC_CHR_2_RA
,
1329 pi
->mpsc_base
+ MPSC_CHR_2
);
1330 /* Erratum prevents reading CHR_2 so just delay for a while */
1333 writel(readl(pi
->mpsc_base
+ MPSC_CHR_2
) | MPSC_CHR_2_RA
,
1334 pi
->mpsc_base
+ MPSC_CHR_2
);
1336 while (readl(pi
->mpsc_base
+ MPSC_CHR_2
) & MPSC_CHR_2_RA
)
1340 mpsc_sdma_cmd(pi
, SDMA_SDCM_AR
);
1343 static void mpsc_break_ctl(struct uart_port
*port
, int ctl
)
1345 struct mpsc_port_info
*pi
=
1346 container_of(port
, struct mpsc_port_info
, port
);
1350 v
= ctl
? 0x00ff0000 : 0;
1352 spin_lock_irqsave(&pi
->port
.lock
, flags
);
1353 if (pi
->mirror_regs
)
1354 pi
->MPSC_CHR_1_m
= v
;
1355 writel(v
, pi
->mpsc_base
+ MPSC_CHR_1
);
1356 spin_unlock_irqrestore(&pi
->port
.lock
, flags
);
1359 static int mpsc_startup(struct uart_port
*port
)
1361 struct mpsc_port_info
*pi
=
1362 container_of(port
, struct mpsc_port_info
, port
);
1366 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1367 port
->line
, pi
->port
.irq
);
1369 if ((rc
= mpsc_make_ready(pi
)) == 0) {
1370 /* Setup IRQ handler */
1371 mpsc_sdma_intr_ack(pi
);
1373 /* If irq's are shared, need to set flag */
1374 if (mpsc_ports
[0].port
.irq
== mpsc_ports
[1].port
.irq
)
1377 if (request_irq(pi
->port
.irq
, mpsc_sdma_intr
, flag
,
1379 printk(KERN_ERR
"MPSC: Can't get SDMA IRQ %d\n",
1382 mpsc_sdma_intr_unmask(pi
, 0xf);
1383 mpsc_sdma_set_rx_ring(pi
, (struct mpsc_rx_desc
*)(pi
->rxr_p
1384 + (pi
->rxr_posn
* MPSC_RXRE_SIZE
)));
1390 static void mpsc_shutdown(struct uart_port
*port
)
1392 struct mpsc_port_info
*pi
=
1393 container_of(port
, struct mpsc_port_info
, port
);
1395 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port
->line
);
1398 free_irq(pi
->port
.irq
, pi
);
1401 static void mpsc_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1402 struct ktermios
*old
)
1404 struct mpsc_port_info
*pi
=
1405 container_of(port
, struct mpsc_port_info
, port
);
1408 u32 chr_bits
, stop_bits
, par
;
1410 pi
->c_iflag
= termios
->c_iflag
;
1411 pi
->c_cflag
= termios
->c_cflag
;
1413 switch (termios
->c_cflag
& CSIZE
) {
1415 chr_bits
= MPSC_MPCR_CL_5
;
1418 chr_bits
= MPSC_MPCR_CL_6
;
1421 chr_bits
= MPSC_MPCR_CL_7
;
1425 chr_bits
= MPSC_MPCR_CL_8
;
1429 if (termios
->c_cflag
& CSTOPB
)
1430 stop_bits
= MPSC_MPCR_SBL_2
;
1432 stop_bits
= MPSC_MPCR_SBL_1
;
1434 par
= MPSC_CHR_2_PAR_EVEN
;
1435 if (termios
->c_cflag
& PARENB
)
1436 if (termios
->c_cflag
& PARODD
)
1437 par
= MPSC_CHR_2_PAR_ODD
;
1439 if (termios
->c_cflag
& CMSPAR
) {
1440 if (termios
->c_cflag
& PARODD
)
1441 par
= MPSC_CHR_2_PAR_MARK
;
1443 par
= MPSC_CHR_2_PAR_SPACE
;
1447 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
);
1449 spin_lock_irqsave(&pi
->port
.lock
, flags
);
1451 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1453 mpsc_set_char_length(pi
, chr_bits
);
1454 mpsc_set_stop_bit_length(pi
, stop_bits
);
1455 mpsc_set_parity(pi
, par
);
1456 mpsc_set_baudrate(pi
, baud
);
1458 /* Characters/events to read */
1459 pi
->port
.read_status_mask
= SDMA_DESC_CMDSTAT_OR
;
1461 if (termios
->c_iflag
& INPCK
)
1462 pi
->port
.read_status_mask
|= SDMA_DESC_CMDSTAT_PE
1463 | SDMA_DESC_CMDSTAT_FR
;
1465 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1466 pi
->port
.read_status_mask
|= SDMA_DESC_CMDSTAT_BR
;
1468 /* Characters/events to ignore */
1469 pi
->port
.ignore_status_mask
= 0;
1471 if (termios
->c_iflag
& IGNPAR
)
1472 pi
->port
.ignore_status_mask
|= SDMA_DESC_CMDSTAT_PE
1473 | SDMA_DESC_CMDSTAT_FR
;
1475 if (termios
->c_iflag
& IGNBRK
) {
1476 pi
->port
.ignore_status_mask
|= SDMA_DESC_CMDSTAT_BR
;
1478 if (termios
->c_iflag
& IGNPAR
)
1479 pi
->port
.ignore_status_mask
|= SDMA_DESC_CMDSTAT_OR
;
1482 if ((termios
->c_cflag
& CREAD
)) {
1483 if (!pi
->rcv_data
) {
1487 } else if (pi
->rcv_data
) {
1492 spin_unlock_irqrestore(&pi
->port
.lock
, flags
);
1495 static const char *mpsc_type(struct uart_port
*port
)
1497 pr_debug("mpsc_type[%d]: port type: %s\n", port
->line
,MPSC_DRIVER_NAME
);
1498 return MPSC_DRIVER_NAME
;
1501 static int mpsc_request_port(struct uart_port
*port
)
1503 /* Should make chip/platform specific call */
1507 static void mpsc_release_port(struct uart_port
*port
)
1509 struct mpsc_port_info
*pi
=
1510 container_of(port
, struct mpsc_port_info
, port
);
1513 mpsc_uninit_rings(pi
);
1514 mpsc_free_ring_mem(pi
);
1519 static void mpsc_config_port(struct uart_port
*port
, int flags
)
1523 static int mpsc_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1525 struct mpsc_port_info
*pi
=
1526 container_of(port
, struct mpsc_port_info
, port
);
1529 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi
->port
.line
);
1531 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_MPSC
)
1533 else if (pi
->port
.irq
!= ser
->irq
)
1535 else if (ser
->io_type
!= SERIAL_IO_MEM
)
1537 else if (pi
->port
.uartclk
/ 16 != ser
->baud_base
) /* Not sure */
1539 else if ((void *)pi
->port
.mapbase
!= ser
->iomem_base
)
1541 else if (pi
->port
.iobase
!= ser
->port
)
1543 else if (ser
->hub6
!= 0)
1548 #ifdef CONFIG_CONSOLE_POLL
1549 /* Serial polling routines for writing and reading from the uart while
1550 * in an interrupt or debug context.
1553 static char poll_buf
[2048];
1554 static int poll_ptr
;
1555 static int poll_cnt
;
1556 static void mpsc_put_poll_char(struct uart_port
*port
,
1559 static int mpsc_get_poll_char(struct uart_port
*port
)
1561 struct mpsc_port_info
*pi
=
1562 container_of(port
, struct mpsc_port_info
, port
);
1563 struct mpsc_rx_desc
*rxre
;
1564 u32 cmdstat
, bytes_in
, i
;
1570 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi
->port
.line
);
1574 return poll_buf
[poll_ptr
++];
1579 while (poll_cnt
== 0) {
1580 rxre
= (struct mpsc_rx_desc
*)(pi
->rxr
+
1581 (pi
->rxr_posn
*MPSC_RXRE_SIZE
));
1582 dma_cache_sync(pi
->port
.dev
, (void *)rxre
,
1583 MPSC_RXRE_SIZE
, DMA_FROM_DEVICE
);
1584 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1585 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1586 invalidate_dcache_range((ulong
)rxre
,
1587 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
1590 * Loop through Rx descriptors handling ones that have
1593 while (poll_cnt
== 0 &&
1594 !((cmdstat
= be32_to_cpu(rxre
->cmdstat
)) &
1595 SDMA_DESC_CMDSTAT_O
)){
1596 bytes_in
= be16_to_cpu(rxre
->bytecnt
);
1597 bp
= pi
->rxb
+ (pi
->rxr_posn
* MPSC_RXBE_SIZE
);
1598 dma_cache_sync(pi
->port
.dev
, (void *) bp
,
1599 MPSC_RXBE_SIZE
, DMA_FROM_DEVICE
);
1600 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1601 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1602 invalidate_dcache_range((ulong
)bp
,
1603 (ulong
)bp
+ MPSC_RXBE_SIZE
);
1605 if ((unlikely(cmdstat
& (SDMA_DESC_CMDSTAT_BR
|
1606 SDMA_DESC_CMDSTAT_FR
| SDMA_DESC_CMDSTAT_OR
))) &&
1607 !(cmdstat
& pi
->port
.ignore_status_mask
)) {
1608 poll_buf
[poll_cnt
] = *bp
;
1611 for (i
= 0; i
< bytes_in
; i
++) {
1612 poll_buf
[poll_cnt
] = *bp
++;
1615 pi
->port
.icount
.rx
+= bytes_in
;
1617 rxre
->bytecnt
= cpu_to_be16(0);
1619 rxre
->cmdstat
= cpu_to_be32(SDMA_DESC_CMDSTAT_O
|
1620 SDMA_DESC_CMDSTAT_EI
|
1621 SDMA_DESC_CMDSTAT_F
|
1622 SDMA_DESC_CMDSTAT_L
);
1624 dma_cache_sync(pi
->port
.dev
, (void *)rxre
,
1625 MPSC_RXRE_SIZE
, DMA_BIDIRECTIONAL
);
1626 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1627 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1628 flush_dcache_range((ulong
)rxre
,
1629 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
1632 /* Advance to next descriptor */
1633 pi
->rxr_posn
= (pi
->rxr_posn
+ 1) &
1634 (MPSC_RXR_ENTRIES
- 1);
1635 rxre
= (struct mpsc_rx_desc
*)(pi
->rxr
+
1636 (pi
->rxr_posn
* MPSC_RXRE_SIZE
));
1637 dma_cache_sync(pi
->port
.dev
, (void *)rxre
,
1638 MPSC_RXRE_SIZE
, DMA_FROM_DEVICE
);
1639 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1640 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1641 invalidate_dcache_range((ulong
)rxre
,
1642 (ulong
)rxre
+ MPSC_RXRE_SIZE
);
1646 /* Restart rx engine, if its stopped */
1647 if ((readl(pi
->sdma_base
+ SDMA_SDCM
) & SDMA_SDCM_ERD
) == 0)
1652 return poll_buf
[poll_ptr
++];
1659 static void mpsc_put_poll_char(struct uart_port
*port
,
1662 struct mpsc_port_info
*pi
=
1663 container_of(port
, struct mpsc_port_info
, port
);
1666 data
= readl(pi
->mpsc_base
+ MPSC_MPCR
);
1667 writeb(c
, pi
->mpsc_base
+ MPSC_CHR_1
);
1669 data
= readl(pi
->mpsc_base
+ MPSC_CHR_2
);
1670 data
|= MPSC_CHR_2_TTCS
;
1671 writel(data
, pi
->mpsc_base
+ MPSC_CHR_2
);
1674 while (readl(pi
->mpsc_base
+ MPSC_CHR_2
) & MPSC_CHR_2_TTCS
);
1678 static struct uart_ops mpsc_pops
= {
1679 .tx_empty
= mpsc_tx_empty
,
1680 .set_mctrl
= mpsc_set_mctrl
,
1681 .get_mctrl
= mpsc_get_mctrl
,
1682 .stop_tx
= mpsc_stop_tx
,
1683 .start_tx
= mpsc_start_tx
,
1684 .stop_rx
= mpsc_stop_rx
,
1685 .break_ctl
= mpsc_break_ctl
,
1686 .startup
= mpsc_startup
,
1687 .shutdown
= mpsc_shutdown
,
1688 .set_termios
= mpsc_set_termios
,
1690 .release_port
= mpsc_release_port
,
1691 .request_port
= mpsc_request_port
,
1692 .config_port
= mpsc_config_port
,
1693 .verify_port
= mpsc_verify_port
,
1694 #ifdef CONFIG_CONSOLE_POLL
1695 .poll_get_char
= mpsc_get_poll_char
,
1696 .poll_put_char
= mpsc_put_poll_char
,
1701 ******************************************************************************
1703 * Console Interface Routines
1705 ******************************************************************************
1708 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1709 static void mpsc_console_write(struct console
*co
, const char *s
, uint count
)
1711 struct mpsc_port_info
*pi
= &mpsc_ports
[co
->index
];
1712 u8
*bp
, *dp
, add_cr
= 0;
1714 unsigned long iflags
;
1716 spin_lock_irqsave(&pi
->tx_lock
, iflags
);
1718 while (pi
->txr_head
!= pi
->txr_tail
) {
1719 while (mpsc_sdma_tx_active(pi
))
1721 mpsc_sdma_intr_ack(pi
);
1725 while (mpsc_sdma_tx_active(pi
))
1729 bp
= dp
= pi
->txb
+ (pi
->txr_head
* MPSC_TXBE_SIZE
);
1731 for (i
= 0; i
< MPSC_TXBE_SIZE
; i
++) {
1741 if (*(s
++) == '\n') { /* add '\r' after '\n' */
1750 dma_cache_sync(pi
->port
.dev
, (void *)bp
, MPSC_TXBE_SIZE
,
1752 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1753 if (pi
->cache_mgmt
) /* GT642[46]0 Res #COMM-2 */
1754 flush_dcache_range((ulong
)bp
,
1755 (ulong
)bp
+ MPSC_TXBE_SIZE
);
1757 mpsc_setup_tx_desc(pi
, i
, 0);
1758 pi
->txr_head
= (pi
->txr_head
+ 1) & (MPSC_TXR_ENTRIES
- 1);
1759 mpsc_sdma_start_tx(pi
);
1761 while (mpsc_sdma_tx_active(pi
))
1764 pi
->txr_tail
= (pi
->txr_tail
+ 1) & (MPSC_TXR_ENTRIES
- 1);
1767 spin_unlock_irqrestore(&pi
->tx_lock
, iflags
);
1770 static int __init
mpsc_console_setup(struct console
*co
, char *options
)
1772 struct mpsc_port_info
*pi
;
1773 int baud
, bits
, parity
, flow
;
1775 pr_debug("mpsc_console_setup[%d]: options: %s\n", co
->index
, options
);
1777 if (co
->index
>= MPSC_NUM_CTLRS
)
1780 pi
= &mpsc_ports
[co
->index
];
1782 baud
= pi
->default_baud
;
1783 bits
= pi
->default_bits
;
1784 parity
= pi
->default_parity
;
1785 flow
= pi
->default_flow
;
1790 spin_lock_init(&pi
->port
.lock
); /* Temporary fix--copied from 8250.c */
1793 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1795 return uart_set_options(&pi
->port
, co
, baud
, parity
, bits
, flow
);
1798 static struct console mpsc_console
= {
1799 .name
= MPSC_DEV_NAME
,
1800 .write
= mpsc_console_write
,
1801 .device
= uart_console_device
,
1802 .setup
= mpsc_console_setup
,
1803 .flags
= CON_PRINTBUFFER
,
1808 static int __init
mpsc_late_console_init(void)
1810 pr_debug("mpsc_late_console_init: Enter\n");
1812 if (!(mpsc_console
.flags
& CON_ENABLED
))
1813 register_console(&mpsc_console
);
1817 late_initcall(mpsc_late_console_init
);
1819 #define MPSC_CONSOLE &mpsc_console
1821 #define MPSC_CONSOLE NULL
1824 ******************************************************************************
1826 * Dummy Platform Driver to extract & map shared register regions
1828 ******************************************************************************
1830 static void mpsc_resource_err(char *s
)
1832 printk(KERN_WARNING
"MPSC: Platform device resource error in %s\n", s
);
1835 static int mpsc_shared_map_regs(struct platform_device
*pd
)
1839 if ((r
= platform_get_resource(pd
, IORESOURCE_MEM
,
1840 MPSC_ROUTING_BASE_ORDER
))
1841 && request_mem_region(r
->start
,
1842 MPSC_ROUTING_REG_BLOCK_SIZE
,
1843 "mpsc_routing_regs")) {
1844 mpsc_shared_regs
.mpsc_routing_base
= ioremap(r
->start
,
1845 MPSC_ROUTING_REG_BLOCK_SIZE
);
1846 mpsc_shared_regs
.mpsc_routing_base_p
= r
->start
;
1848 mpsc_resource_err("MPSC routing base");
1852 if ((r
= platform_get_resource(pd
, IORESOURCE_MEM
,
1853 MPSC_SDMA_INTR_BASE_ORDER
))
1854 && request_mem_region(r
->start
,
1855 MPSC_SDMA_INTR_REG_BLOCK_SIZE
,
1856 "sdma_intr_regs")) {
1857 mpsc_shared_regs
.sdma_intr_base
= ioremap(r
->start
,
1858 MPSC_SDMA_INTR_REG_BLOCK_SIZE
);
1859 mpsc_shared_regs
.sdma_intr_base_p
= r
->start
;
1861 iounmap(mpsc_shared_regs
.mpsc_routing_base
);
1862 release_mem_region(mpsc_shared_regs
.mpsc_routing_base_p
,
1863 MPSC_ROUTING_REG_BLOCK_SIZE
);
1864 mpsc_resource_err("SDMA intr base");
1871 static void mpsc_shared_unmap_regs(void)
1873 if (!mpsc_shared_regs
.mpsc_routing_base
) {
1874 iounmap(mpsc_shared_regs
.mpsc_routing_base
);
1875 release_mem_region(mpsc_shared_regs
.mpsc_routing_base_p
,
1876 MPSC_ROUTING_REG_BLOCK_SIZE
);
1878 if (!mpsc_shared_regs
.sdma_intr_base
) {
1879 iounmap(mpsc_shared_regs
.sdma_intr_base
);
1880 release_mem_region(mpsc_shared_regs
.sdma_intr_base_p
,
1881 MPSC_SDMA_INTR_REG_BLOCK_SIZE
);
1884 mpsc_shared_regs
.mpsc_routing_base
= NULL
;
1885 mpsc_shared_regs
.sdma_intr_base
= NULL
;
1887 mpsc_shared_regs
.mpsc_routing_base_p
= 0;
1888 mpsc_shared_regs
.sdma_intr_base_p
= 0;
1891 static int mpsc_shared_drv_probe(struct platform_device
*dev
)
1893 struct mpsc_shared_pdata
*pdata
;
1897 rc
= mpsc_shared_map_regs(dev
);
1899 pdata
= (struct mpsc_shared_pdata
*)
1900 dev_get_platdata(&dev
->dev
);
1902 mpsc_shared_regs
.MPSC_MRR_m
= pdata
->mrr_val
;
1903 mpsc_shared_regs
.MPSC_RCRR_m
= pdata
->rcrr_val
;
1904 mpsc_shared_regs
.MPSC_TCRR_m
= pdata
->tcrr_val
;
1905 mpsc_shared_regs
.SDMA_INTR_CAUSE_m
=
1906 pdata
->intr_cause_val
;
1907 mpsc_shared_regs
.SDMA_INTR_MASK_m
=
1908 pdata
->intr_mask_val
;
1917 static int mpsc_shared_drv_remove(struct platform_device
*dev
)
1922 mpsc_shared_unmap_regs();
1923 mpsc_shared_regs
.MPSC_MRR_m
= 0;
1924 mpsc_shared_regs
.MPSC_RCRR_m
= 0;
1925 mpsc_shared_regs
.MPSC_TCRR_m
= 0;
1926 mpsc_shared_regs
.SDMA_INTR_CAUSE_m
= 0;
1927 mpsc_shared_regs
.SDMA_INTR_MASK_m
= 0;
1934 static struct platform_driver mpsc_shared_driver
= {
1935 .probe
= mpsc_shared_drv_probe
,
1936 .remove
= mpsc_shared_drv_remove
,
1938 .name
= MPSC_SHARED_NAME
,
1943 ******************************************************************************
1945 * Driver Interface Routines
1947 ******************************************************************************
1949 static struct uart_driver mpsc_reg
= {
1950 .owner
= THIS_MODULE
,
1951 .driver_name
= MPSC_DRIVER_NAME
,
1952 .dev_name
= MPSC_DEV_NAME
,
1953 .major
= MPSC_MAJOR
,
1954 .minor
= MPSC_MINOR_START
,
1955 .nr
= MPSC_NUM_CTLRS
,
1956 .cons
= MPSC_CONSOLE
,
1959 static int mpsc_drv_map_regs(struct mpsc_port_info
*pi
,
1960 struct platform_device
*pd
)
1964 if ((r
= platform_get_resource(pd
, IORESOURCE_MEM
, MPSC_BASE_ORDER
))
1965 && request_mem_region(r
->start
, MPSC_REG_BLOCK_SIZE
,
1967 pi
->mpsc_base
= ioremap(r
->start
, MPSC_REG_BLOCK_SIZE
);
1968 pi
->mpsc_base_p
= r
->start
;
1970 mpsc_resource_err("MPSC base");
1974 if ((r
= platform_get_resource(pd
, IORESOURCE_MEM
,
1975 MPSC_SDMA_BASE_ORDER
))
1976 && request_mem_region(r
->start
,
1977 MPSC_SDMA_REG_BLOCK_SIZE
, "sdma_regs")) {
1978 pi
->sdma_base
= ioremap(r
->start
,MPSC_SDMA_REG_BLOCK_SIZE
);
1979 pi
->sdma_base_p
= r
->start
;
1981 mpsc_resource_err("SDMA base");
1982 if (pi
->mpsc_base
) {
1983 iounmap(pi
->mpsc_base
);
1984 pi
->mpsc_base
= NULL
;
1989 if ((r
= platform_get_resource(pd
,IORESOURCE_MEM
,MPSC_BRG_BASE_ORDER
))
1990 && request_mem_region(r
->start
,
1991 MPSC_BRG_REG_BLOCK_SIZE
, "brg_regs")) {
1992 pi
->brg_base
= ioremap(r
->start
, MPSC_BRG_REG_BLOCK_SIZE
);
1993 pi
->brg_base_p
= r
->start
;
1995 mpsc_resource_err("BRG base");
1996 if (pi
->mpsc_base
) {
1997 iounmap(pi
->mpsc_base
);
1998 pi
->mpsc_base
= NULL
;
2000 if (pi
->sdma_base
) {
2001 iounmap(pi
->sdma_base
);
2002 pi
->sdma_base
= NULL
;
2012 static void mpsc_drv_unmap_regs(struct mpsc_port_info
*pi
)
2014 if (!pi
->mpsc_base
) {
2015 iounmap(pi
->mpsc_base
);
2016 release_mem_region(pi
->mpsc_base_p
, MPSC_REG_BLOCK_SIZE
);
2018 if (!pi
->sdma_base
) {
2019 iounmap(pi
->sdma_base
);
2020 release_mem_region(pi
->sdma_base_p
, MPSC_SDMA_REG_BLOCK_SIZE
);
2022 if (!pi
->brg_base
) {
2023 iounmap(pi
->brg_base
);
2024 release_mem_region(pi
->brg_base_p
, MPSC_BRG_REG_BLOCK_SIZE
);
2027 pi
->mpsc_base
= NULL
;
2028 pi
->sdma_base
= NULL
;
2029 pi
->brg_base
= NULL
;
2031 pi
->mpsc_base_p
= 0;
2032 pi
->sdma_base_p
= 0;
2036 static void mpsc_drv_get_platform_data(struct mpsc_port_info
*pi
,
2037 struct platform_device
*pd
, int num
)
2039 struct mpsc_pdata
*pdata
;
2041 pdata
= dev_get_platdata(&pd
->dev
);
2043 pi
->port
.uartclk
= pdata
->brg_clk_freq
;
2044 pi
->port
.iotype
= UPIO_MEM
;
2045 pi
->port
.line
= num
;
2046 pi
->port
.type
= PORT_MPSC
;
2047 pi
->port
.fifosize
= MPSC_TXBE_SIZE
;
2048 pi
->port
.membase
= pi
->mpsc_base
;
2049 pi
->port
.mapbase
= (ulong
)pi
->mpsc_base
;
2050 pi
->port
.ops
= &mpsc_pops
;
2052 pi
->mirror_regs
= pdata
->mirror_regs
;
2053 pi
->cache_mgmt
= pdata
->cache_mgmt
;
2054 pi
->brg_can_tune
= pdata
->brg_can_tune
;
2055 pi
->brg_clk_src
= pdata
->brg_clk_src
;
2056 pi
->mpsc_max_idle
= pdata
->max_idle
;
2057 pi
->default_baud
= pdata
->default_baud
;
2058 pi
->default_bits
= pdata
->default_bits
;
2059 pi
->default_parity
= pdata
->default_parity
;
2060 pi
->default_flow
= pdata
->default_flow
;
2062 /* Initial values of mirrored regs */
2063 pi
->MPSC_CHR_1_m
= pdata
->chr_1_val
;
2064 pi
->MPSC_CHR_2_m
= pdata
->chr_2_val
;
2065 pi
->MPSC_CHR_10_m
= pdata
->chr_10_val
;
2066 pi
->MPSC_MPCR_m
= pdata
->mpcr_val
;
2067 pi
->BRG_BCR_m
= pdata
->bcr_val
;
2069 pi
->shared_regs
= &mpsc_shared_regs
;
2071 pi
->port
.irq
= platform_get_irq(pd
, 0);
2074 static int mpsc_drv_probe(struct platform_device
*dev
)
2076 struct mpsc_port_info
*pi
;
2079 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev
->id
);
2081 if (dev
->id
< MPSC_NUM_CTLRS
) {
2082 pi
= &mpsc_ports
[dev
->id
];
2084 rc
= mpsc_drv_map_regs(pi
, dev
);
2086 mpsc_drv_get_platform_data(pi
, dev
, dev
->id
);
2087 pi
->port
.dev
= &dev
->dev
;
2089 rc
= mpsc_make_ready(pi
);
2091 spin_lock_init(&pi
->tx_lock
);
2092 rc
= uart_add_one_port(&mpsc_reg
, &pi
->port
);
2096 mpsc_release_port((struct uart_port
*)
2098 mpsc_drv_unmap_regs(pi
);
2101 mpsc_drv_unmap_regs(pi
);
2109 static struct platform_driver mpsc_driver
= {
2110 .probe
= mpsc_drv_probe
,
2112 .name
= MPSC_CTLR_NAME
,
2113 .suppress_bind_attrs
= true,
2117 static int __init
mpsc_drv_init(void)
2121 printk(KERN_INFO
"Serial: MPSC driver\n");
2123 memset(mpsc_ports
, 0, sizeof(mpsc_ports
));
2124 memset(&mpsc_shared_regs
, 0, sizeof(mpsc_shared_regs
));
2126 rc
= uart_register_driver(&mpsc_reg
);
2128 rc
= platform_driver_register(&mpsc_shared_driver
);
2130 rc
= platform_driver_register(&mpsc_driver
);
2132 platform_driver_unregister(&mpsc_shared_driver
);
2133 uart_unregister_driver(&mpsc_reg
);
2136 uart_unregister_driver(&mpsc_reg
);
2142 device_initcall(mpsc_drv_init
);
2145 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2146 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2147 MODULE_LICENSE("GPL");