projects / deliverable / linux.git / blob
? search:


d08cfd3e1c3af38bf7b6767d0bef2feb3460c6ba
[deliverable/linux.git] / drivers / tty / serial / msm_serial.c
1 /*
2 * Driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
20 #endif
21
22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h>
24 #include <linux/module.h>
25 #include <linux/io.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39
40 #include "msm_serial.h"
41
42 enum {
43 UARTDM_1P1 = 1,
44 UARTDM_1P2,
45 UARTDM_1P3,
46 UARTDM_1P4,
47 };
48
49 struct msm_port {
50 struct uart_port uart;
51 char name[16];
52 struct clk *clk;
53 struct clk *pclk;
54 unsigned int imr;
55 int is_uartdm;
56 unsigned int old_snap_state;
57 bool break_detected;
58 };
59
60 static inline void wait_for_xmitr(struct uart_port *port)
61 {
62 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
63 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
64 break;
65 udelay(1);
66 }
67 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
68 }
69
70 static void msm_stop_tx(struct uart_port *port)
71 {
72 struct msm_port *msm_port = UART_TO_MSM(port);
73
74 msm_port->imr &= ~UART_IMR_TXLEV;
75 msm_write(port, msm_port->imr, UART_IMR);
76 }
77
78 static void msm_start_tx(struct uart_port *port)
79 {
80 struct msm_port *msm_port = UART_TO_MSM(port);
81
82 msm_port->imr |= UART_IMR_TXLEV;
83 msm_write(port, msm_port->imr, UART_IMR);
84 }
85
86 static void msm_stop_rx(struct uart_port *port)
87 {
88 struct msm_port *msm_port = UART_TO_MSM(port);
89
90 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
91 msm_write(port, msm_port->imr, UART_IMR);
92 }
93
94 static void msm_enable_ms(struct uart_port *port)
95 {
96 struct msm_port *msm_port = UART_TO_MSM(port);
97
98 msm_port->imr |= UART_IMR_DELTA_CTS;
99 msm_write(port, msm_port->imr, UART_IMR);
100 }
101
102 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
103 {
104 struct tty_port *tport = &port->state->port;
105 unsigned int sr;
106 int count = 0;
107 struct msm_port *msm_port = UART_TO_MSM(port);
108
109 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
110 port->icount.overrun++;
111 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
112 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
113 }
114
115 if (misr & UART_IMR_RXSTALE) {
116 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
117 msm_port->old_snap_state;
118 msm_port->old_snap_state = 0;
119 } else {
120 count = 4 * (msm_read(port, UART_RFWR));
121 msm_port->old_snap_state += count;
122 }
123
124 /* TODO: Precise error reporting */
125
126 port->icount.rx += count;
127
128 while (count > 0) {
129 unsigned char buf[4];
130 int sysrq, r_count, i;
131
132 sr = msm_read(port, UART_SR);
133 if ((sr & UART_SR_RX_READY) == 0) {
134 msm_port->old_snap_state -= count;
135 break;
136 }
137
138 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
139 r_count = min_t(int, count, sizeof(buf));
140
141 for (i = 0; i < r_count; i++) {
142 char flag = TTY_NORMAL;
143
144 if (msm_port->break_detected && buf[i] == 0) {
145 port->icount.brk++;
146 flag = TTY_BREAK;
147 msm_port->break_detected = false;
148 if (uart_handle_break(port))
149 continue;
150 }
151
152 if (!(port->read_status_mask & UART_SR_RX_BREAK))
153 flag = TTY_NORMAL;
154
155 spin_unlock(&port->lock);
156 sysrq = uart_handle_sysrq_char(port, buf[i]);
157 spin_lock(&port->lock);
158 if (!sysrq)
159 tty_insert_flip_char(tport, buf[i], flag);
160 }
161 count -= r_count;
162 }
163
164 spin_unlock(&port->lock);
165 tty_flip_buffer_push(tport);
166 spin_lock(&port->lock);
167
168 if (misr & (UART_IMR_RXSTALE))
169 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
170 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
171 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
172 }
173
174 static void handle_rx(struct uart_port *port)
175 {
176 struct tty_port *tport = &port->state->port;
177 unsigned int sr;
178
179 /*
180 * Handle overrun. My understanding of the hardware is that overrun
181 * is not tied to the RX buffer, so we handle the case out of band.
182 */
183 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
184 port->icount.overrun++;
185 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
186 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
187 }
188
189 /* and now the main RX loop */
190 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
191 unsigned int c;
192 char flag = TTY_NORMAL;
193 int sysrq;
194
195 c = msm_read(port, UART_RF);
196
197 if (sr & UART_SR_RX_BREAK) {
198 port->icount.brk++;
199 if (uart_handle_break(port))
200 continue;
201 } else if (sr & UART_SR_PAR_FRAME_ERR) {
202 port->icount.frame++;
203 } else {
204 port->icount.rx++;
205 }
206
207 /* Mask conditions we're ignorning. */
208 sr &= port->read_status_mask;
209
210 if (sr & UART_SR_RX_BREAK)
211 flag = TTY_BREAK;
212 else if (sr & UART_SR_PAR_FRAME_ERR)
213 flag = TTY_FRAME;
214
215 spin_unlock(&port->lock);
216 sysrq = uart_handle_sysrq_char(port, c);
217 spin_lock(&port->lock);
218 if (!sysrq)
219 tty_insert_flip_char(tport, c, flag);
220 }
221
222 spin_unlock(&port->lock);
223 tty_flip_buffer_push(tport);
224 spin_lock(&port->lock);
225 }
226
227 static void reset_dm_count(struct uart_port *port, int count)
228 {
229 wait_for_xmitr(port);
230 msm_write(port, count, UARTDM_NCF_TX);
231 msm_read(port, UARTDM_NCF_TX);
232 }
233
234 static void handle_tx(struct uart_port *port)
235 {
236 struct circ_buf *xmit = &port->state->xmit;
237 struct msm_port *msm_port = UART_TO_MSM(port);
238 unsigned int tx_count, num_chars;
239 unsigned int tf_pointer = 0;
240 void __iomem *tf;
241
242 if (msm_port->is_uartdm)
243 tf = port->membase + UARTDM_TF;
244 else
245 tf = port->membase + UART_TF;
246
247 tx_count = uart_circ_chars_pending(xmit);
248 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
249 port->fifosize);
250
251 if (port->x_char) {
252 if (msm_port->is_uartdm)
253 reset_dm_count(port, tx_count + 1);
254
255 iowrite8_rep(tf, &port->x_char, 1);
256 port->icount.tx++;
257 port->x_char = 0;
258 } else if (tx_count && msm_port->is_uartdm) {
259 reset_dm_count(port, tx_count);
260 }
261
262 while (tf_pointer < tx_count) {
263 int i;
264 char buf[4] = { 0 };
265
266 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
267 break;
268
269 if (msm_port->is_uartdm)
270 num_chars = min(tx_count - tf_pointer,
271 (unsigned int)sizeof(buf));
272 else
273 num_chars = 1;
274
275 for (i = 0; i < num_chars; i++) {
276 buf[i] = xmit->buf[xmit->tail + i];
277 port->icount.tx++;
278 }
279
280 iowrite32_rep(tf, buf, 1);
281 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
282 tf_pointer += num_chars;
283 }
284
285 /* disable tx interrupts if nothing more to send */
286 if (uart_circ_empty(xmit))
287 msm_stop_tx(port);
288
289 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
290 uart_write_wakeup(port);
291 }
292
293 static void handle_delta_cts(struct uart_port *port)
294 {
295 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
296 port->icount.cts++;
297 wake_up_interruptible(&port->state->port.delta_msr_wait);
298 }
299
300 static irqreturn_t msm_irq(int irq, void *dev_id)
301 {
302 struct uart_port *port = dev_id;
303 struct msm_port *msm_port = UART_TO_MSM(port);
304 unsigned int misr;
305
306 spin_lock(&port->lock);
307 misr = msm_read(port, UART_MISR);
308 msm_write(port, 0, UART_IMR); /* disable interrupt */
309
310 if (misr & UART_IMR_RXBREAK_START) {
311 msm_port->break_detected = true;
312 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
313 }
314
315 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
316 if (msm_port->is_uartdm)
317 handle_rx_dm(port, misr);
318 else
319 handle_rx(port);
320 }
321 if (misr & UART_IMR_TXLEV)
322 handle_tx(port);
323 if (misr & UART_IMR_DELTA_CTS)
324 handle_delta_cts(port);
325
326 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
327 spin_unlock(&port->lock);
328
329 return IRQ_HANDLED;
330 }
331
332 static unsigned int msm_tx_empty(struct uart_port *port)
333 {
334 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
335 }
336
337 static unsigned int msm_get_mctrl(struct uart_port *port)
338 {
339 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
340 }
341
342 static void msm_reset(struct uart_port *port)
343 {
344 struct msm_port *msm_port = UART_TO_MSM(port);
345
346 /* reset everything */
347 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
348 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
349 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
350 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
351 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
352 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
353
354 /* Disable DM modes */
355 if (msm_port->is_uartdm)
356 msm_write(port, 0, UARTDM_DMEN);
357 }
358
359 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
360 {
361 unsigned int mr;
362
363 mr = msm_read(port, UART_MR1);
364
365 if (!(mctrl & TIOCM_RTS)) {
366 mr &= ~UART_MR1_RX_RDY_CTL;
367 msm_write(port, mr, UART_MR1);
368 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
369 } else {
370 mr |= UART_MR1_RX_RDY_CTL;
371 msm_write(port, mr, UART_MR1);
372 }
373 }
374
375 static void msm_break_ctl(struct uart_port *port, int break_ctl)
376 {
377 if (break_ctl)
378 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
379 else
380 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
381 }
382
383 struct msm_baud_map {
384 u16 divisor;
385 u8 code;
386 u8 rxstale;
387 };
388
389 static const struct msm_baud_map *
390 msm_find_best_baud(struct uart_port *port, unsigned int baud)
391 {
392 unsigned int i, divisor;
393 const struct msm_baud_map *entry;
394 static const struct msm_baud_map table[] = {
395 { 1536, 0x00, 1 },
396 { 768, 0x11, 1 },
397 { 384, 0x22, 1 },
398 { 192, 0x33, 1 },
399 { 96, 0x44, 1 },
400 { 48, 0x55, 1 },
401 { 32, 0x66, 1 },
402 { 24, 0x77, 1 },
403 { 16, 0x88, 1 },
404 { 12, 0x99, 6 },
405 { 8, 0xaa, 6 },
406 { 6, 0xbb, 6 },
407 { 4, 0xcc, 6 },
408 { 3, 0xdd, 8 },
409 { 2, 0xee, 16 },
410 { 1, 0xff, 31 },
411 };
412
413 divisor = uart_get_divisor(port, baud);
414
415 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
416 if (entry->divisor <= divisor)
417 break;
418
419 return entry; /* Default to smallest divider */
420 }
421
422 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
423 {
424 unsigned int rxstale, watermark, mask;
425 struct msm_port *msm_port = UART_TO_MSM(port);
426 const struct msm_baud_map *entry;
427
428 entry = msm_find_best_baud(port, baud);
429
430 msm_write(port, entry->code, UART_CSR);
431
432 /* RX stale watermark */
433 rxstale = entry->rxstale;
434 watermark = UART_IPR_STALE_LSB & rxstale;
435 if (msm_port->is_uartdm) {
436 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
437 } else {
438 watermark |= UART_IPR_RXSTALE_LAST;
439 mask = UART_IPR_STALE_TIMEOUT_MSB;
440 }
441
442 watermark |= mask & (rxstale << 2);
443
444 msm_write(port, watermark, UART_IPR);
445
446 /* set RX watermark */
447 watermark = (port->fifosize * 3) / 4;
448 msm_write(port, watermark, UART_RFWR);
449
450 /* set TX watermark */
451 msm_write(port, 10, UART_TFWR);
452
453 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
454 msm_reset(port);
455
456 /* Enable RX and TX */
457 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
458
459 /* turn on RX and CTS interrupts */
460 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
461 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
462
463 msm_write(port, msm_port->imr, UART_IMR);
464
465 if (msm_port->is_uartdm) {
466 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
467 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
468 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
469 }
470
471 return baud;
472 }
473
474 static void msm_init_clock(struct uart_port *port)
475 {
476 struct msm_port *msm_port = UART_TO_MSM(port);
477
478 clk_prepare_enable(msm_port->clk);
479 clk_prepare_enable(msm_port->pclk);
480 msm_serial_set_mnd_regs(port);
481 }
482
483 static int msm_startup(struct uart_port *port)
484 {
485 struct msm_port *msm_port = UART_TO_MSM(port);
486 unsigned int data, rfr_level, mask;
487 int ret;
488
489 snprintf(msm_port->name, sizeof(msm_port->name),
490 "msm_serial%d", port->line);
491
492 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
493 msm_port->name, port);
494 if (unlikely(ret))
495 return ret;
496
497 msm_init_clock(port);
498
499 if (likely(port->fifosize > 12))
500 rfr_level = port->fifosize - 12;
501 else
502 rfr_level = port->fifosize;
503
504 /* set automatic RFR level */
505 data = msm_read(port, UART_MR1);
506
507 if (msm_port->is_uartdm)
508 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
509 else
510 mask = UART_MR1_AUTO_RFR_LEVEL1;
511
512 data &= ~mask;
513 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
514 data |= mask & (rfr_level << 2);
515 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
516 msm_write(port, data, UART_MR1);
517
518 return 0;
519 }
520
521 static void msm_shutdown(struct uart_port *port)
522 {
523 struct msm_port *msm_port = UART_TO_MSM(port);
524
525 msm_port->imr = 0;
526 msm_write(port, 0, UART_IMR); /* disable interrupts */
527
528 clk_disable_unprepare(msm_port->clk);
529
530 free_irq(port->irq, port);
531 }
532
533 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
534 struct ktermios *old)
535 {
536 unsigned long flags;
537 unsigned int baud, mr;
538
539 spin_lock_irqsave(&port->lock, flags);
540
541 /* calculate and set baud rate */
542 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
543 baud = msm_set_baud_rate(port, baud);
544 if (tty_termios_baud_rate(termios))
545 tty_termios_encode_baud_rate(termios, baud, baud);
546
547 /* calculate parity */
548 mr = msm_read(port, UART_MR2);
549 mr &= ~UART_MR2_PARITY_MODE;
550 if (termios->c_cflag & PARENB) {
551 if (termios->c_cflag & PARODD)
552 mr |= UART_MR2_PARITY_MODE_ODD;
553 else if (termios->c_cflag & CMSPAR)
554 mr |= UART_MR2_PARITY_MODE_SPACE;
555 else
556 mr |= UART_MR2_PARITY_MODE_EVEN;
557 }
558
559 /* calculate bits per char */
560 mr &= ~UART_MR2_BITS_PER_CHAR;
561 switch (termios->c_cflag & CSIZE) {
562 case CS5:
563 mr |= UART_MR2_BITS_PER_CHAR_5;
564 break;
565 case CS6:
566 mr |= UART_MR2_BITS_PER_CHAR_6;
567 break;
568 case CS7:
569 mr |= UART_MR2_BITS_PER_CHAR_7;
570 break;
571 case CS8:
572 default:
573 mr |= UART_MR2_BITS_PER_CHAR_8;
574 break;
575 }
576
577 /* calculate stop bits */
578 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
579 if (termios->c_cflag & CSTOPB)
580 mr |= UART_MR2_STOP_BIT_LEN_TWO;
581 else
582 mr |= UART_MR2_STOP_BIT_LEN_ONE;
583
584 /* set parity, bits per char, and stop bit */
585 msm_write(port, mr, UART_MR2);
586
587 /* calculate and set hardware flow control */
588 mr = msm_read(port, UART_MR1);
589 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
590 if (termios->c_cflag & CRTSCTS) {
591 mr |= UART_MR1_CTS_CTL;
592 mr |= UART_MR1_RX_RDY_CTL;
593 }
594 msm_write(port, mr, UART_MR1);
595
596 /* Configure status bits to ignore based on termio flags. */
597 port->read_status_mask = 0;
598 if (termios->c_iflag & INPCK)
599 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
600 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
601 port->read_status_mask |= UART_SR_RX_BREAK;
602
603 uart_update_timeout(port, termios->c_cflag, baud);
604
605 spin_unlock_irqrestore(&port->lock, flags);
606 }
607
608 static const char *msm_type(struct uart_port *port)
609 {
610 return "MSM";
611 }
612
613 static void msm_release_port(struct uart_port *port)
614 {
615 struct platform_device *pdev = to_platform_device(port->dev);
616 struct resource *uart_resource;
617 resource_size_t size;
618
619 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
620 if (unlikely(!uart_resource))
621 return;
622 size = resource_size(uart_resource);
623
624 release_mem_region(port->mapbase, size);
625 iounmap(port->membase);
626 port->membase = NULL;
627 }
628
629 static int msm_request_port(struct uart_port *port)
630 {
631 struct platform_device *pdev = to_platform_device(port->dev);
632 struct resource *uart_resource;
633 resource_size_t size;
634 int ret;
635
636 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
637 if (unlikely(!uart_resource))
638 return -ENXIO;
639
640 size = resource_size(uart_resource);
641
642 if (!request_mem_region(port->mapbase, size, "msm_serial"))
643 return -EBUSY;
644
645 port->membase = ioremap(port->mapbase, size);
646 if (!port->membase) {
647 ret = -EBUSY;
648 goto fail_release_port;
649 }
650
651 return 0;
652
653 fail_release_port:
654 release_mem_region(port->mapbase, size);
655 return ret;
656 }
657
658 static void msm_config_port(struct uart_port *port, int flags)
659 {
660 int ret;
661
662 if (flags & UART_CONFIG_TYPE) {
663 port->type = PORT_MSM;
664 ret = msm_request_port(port);
665 if (ret)
666 return;
667 }
668 }
669
670 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
671 {
672 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
673 return -EINVAL;
674 if (unlikely(port->irq != ser->irq))
675 return -EINVAL;
676 return 0;
677 }
678
679 static void msm_power(struct uart_port *port, unsigned int state,
680 unsigned int oldstate)
681 {
682 struct msm_port *msm_port = UART_TO_MSM(port);
683
684 switch (state) {
685 case 0:
686 clk_prepare_enable(msm_port->clk);
687 clk_prepare_enable(msm_port->pclk);
688 break;
689 case 3:
690 clk_disable_unprepare(msm_port->clk);
691 clk_disable_unprepare(msm_port->pclk);
692 break;
693 default:
694 pr_err("msm_serial: Unknown PM state %d\n", state);
695 }
696 }
697
698 #ifdef CONFIG_CONSOLE_POLL
699 static int msm_poll_get_char_single(struct uart_port *port)
700 {
701 struct msm_port *msm_port = UART_TO_MSM(port);
702 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
703
704 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
705 return NO_POLL_CHAR;
706
707 return msm_read(port, rf_reg) & 0xff;
708 }
709
710 static int msm_poll_get_char_dm(struct uart_port *port)
711 {
712 int c;
713 static u32 slop;
714 static int count;
715 unsigned char *sp = (unsigned char *)&slop;
716
717 /* Check if a previous read had more than one char */
718 if (count) {
719 c = sp[sizeof(slop) - count];
720 count--;
721 /* Or if FIFO is empty */
722 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
723 /*
724 * If RX packing buffer has less than a word, force stale to
725 * push contents into RX FIFO
726 */
727 count = msm_read(port, UARTDM_RXFS);
728 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
729 if (count) {
730 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
731 slop = msm_read(port, UARTDM_RF);
732 c = sp[0];
733 count--;
734 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
735 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
736 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
737 UART_CR);
738 } else {
739 c = NO_POLL_CHAR;
740 }
741 /* FIFO has a word */
742 } else {
743 slop = msm_read(port, UARTDM_RF);
744 c = sp[0];
745 count = sizeof(slop) - 1;
746 }
747
748 return c;
749 }
750
751 static int msm_poll_get_char(struct uart_port *port)
752 {
753 u32 imr;
754 int c;
755 struct msm_port *msm_port = UART_TO_MSM(port);
756
757 /* Disable all interrupts */
758 imr = msm_read(port, UART_IMR);
759 msm_write(port, 0, UART_IMR);
760
761 if (msm_port->is_uartdm)
762 c = msm_poll_get_char_dm(port);
763 else
764 c = msm_poll_get_char_single(port);
765
766 /* Enable interrupts */
767 msm_write(port, imr, UART_IMR);
768
769 return c;
770 }
771
772 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
773 {
774 u32 imr;
775 struct msm_port *msm_port = UART_TO_MSM(port);
776
777 /* Disable all interrupts */
778 imr = msm_read(port, UART_IMR);
779 msm_write(port, 0, UART_IMR);
780
781 if (msm_port->is_uartdm)
782 reset_dm_count(port, 1);
783
784 /* Wait until FIFO is empty */
785 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
786 cpu_relax();
787
788 /* Write a character */
789 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
790
791 /* Wait until FIFO is empty */
792 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
793 cpu_relax();
794
795 /* Enable interrupts */
796 msm_write(port, imr, UART_IMR);
797 }
798 #endif
799
800 static struct uart_ops msm_uart_pops = {
801 .tx_empty = msm_tx_empty,
802 .set_mctrl = msm_set_mctrl,
803 .get_mctrl = msm_get_mctrl,
804 .stop_tx = msm_stop_tx,
805 .start_tx = msm_start_tx,
806 .stop_rx = msm_stop_rx,
807 .enable_ms = msm_enable_ms,
808 .break_ctl = msm_break_ctl,
809 .startup = msm_startup,
810 .shutdown = msm_shutdown,
811 .set_termios = msm_set_termios,
812 .type = msm_type,
813 .release_port = msm_release_port,
814 .request_port = msm_request_port,
815 .config_port = msm_config_port,
816 .verify_port = msm_verify_port,
817 .pm = msm_power,
818 #ifdef CONFIG_CONSOLE_POLL
819 .poll_get_char = msm_poll_get_char,
820 .poll_put_char = msm_poll_put_char,
821 #endif
822 };
823
824 static struct msm_port msm_uart_ports[] = {
825 {
826 .uart = {
827 .iotype = UPIO_MEM,
828 .ops = &msm_uart_pops,
829 .flags = UPF_BOOT_AUTOCONF,
830 .fifosize = 64,
831 .line = 0,
832 },
833 },
834 {
835 .uart = {
836 .iotype = UPIO_MEM,
837 .ops = &msm_uart_pops,
838 .flags = UPF_BOOT_AUTOCONF,
839 .fifosize = 64,
840 .line = 1,
841 },
842 },
843 {
844 .uart = {
845 .iotype = UPIO_MEM,
846 .ops = &msm_uart_pops,
847 .flags = UPF_BOOT_AUTOCONF,
848 .fifosize = 64,
849 .line = 2,
850 },
851 },
852 };
853
854 #define UART_NR ARRAY_SIZE(msm_uart_ports)
855
856 static inline struct uart_port *get_port_from_line(unsigned int line)
857 {
858 return &msm_uart_ports[line].uart;
859 }
860
861 #ifdef CONFIG_SERIAL_MSM_CONSOLE
862 static void __msm_console_write(struct uart_port *port, const char *s,
863 unsigned int count, bool is_uartdm)
864 {
865 int i;
866 int num_newlines = 0;
867 bool replaced = false;
868 void __iomem *tf;
869
870 if (is_uartdm)
871 tf = port->membase + UARTDM_TF;
872 else
873 tf = port->membase + UART_TF;
874
875 /* Account for newlines that will get a carriage return added */
876 for (i = 0; i < count; i++)
877 if (s[i] == '\n')
878 num_newlines++;
879 count += num_newlines;
880
881 spin_lock(&port->lock);
882 if (is_uartdm)
883 reset_dm_count(port, count);
884
885 i = 0;
886 while (i < count) {
887 int j;
888 unsigned int num_chars;
889 char buf[4] = { 0 };
890
891 if (is_uartdm)
892 num_chars = min(count - i, (unsigned int)sizeof(buf));
893 else
894 num_chars = 1;
895
896 for (j = 0; j < num_chars; j++) {
897 char c = *s;
898
899 if (c == '\n' && !replaced) {
900 buf[j] = '\r';
901 j++;
902 replaced = true;
903 }
904 if (j < num_chars) {
905 buf[j] = c;
906 s++;
907 replaced = false;
908 }
909 }
910
911 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
912 cpu_relax();
913
914 iowrite32_rep(tf, buf, 1);
915 i += num_chars;
916 }
917 spin_unlock(&port->lock);
918 }
919
920 static void msm_console_write(struct console *co, const char *s,
921 unsigned int count)
922 {
923 struct uart_port *port;
924 struct msm_port *msm_port;
925
926 BUG_ON(co->index < 0 || co->index >= UART_NR);
927
928 port = get_port_from_line(co->index);
929 msm_port = UART_TO_MSM(port);
930
931 __msm_console_write(port, s, count, msm_port->is_uartdm);
932 }
933
934 static int __init msm_console_setup(struct console *co, char *options)
935 {
936 struct uart_port *port;
937 int baud = 115200;
938 int bits = 8;
939 int parity = 'n';
940 int flow = 'n';
941
942 if (unlikely(co->index >= UART_NR || co->index < 0))
943 return -ENXIO;
944
945 port = get_port_from_line(co->index);
946
947 if (unlikely(!port->membase))
948 return -ENXIO;
949
950 msm_init_clock(port);
951
952 if (options)
953 uart_parse_options(options, &baud, &parity, &bits, &flow);
954
955 pr_info("msm_serial: console setup on port #%d\n", port->line);
956
957 return uart_set_options(port, co, baud, parity, bits, flow);
958 }
959
960 static void
961 msm_serial_early_write(struct console *con, const char *s, unsigned n)
962 {
963 struct earlycon_device *dev = con->data;
964
965 __msm_console_write(&dev->port, s, n, false);
966 }
967
968 static int __init
969 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
970 {
971 if (!device->port.membase)
972 return -ENODEV;
973
974 device->con->write = msm_serial_early_write;
975 return 0;
976 }
977 EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
978 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
979 msm_serial_early_console_setup);
980
981 static void
982 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
983 {
984 struct earlycon_device *dev = con->data;
985
986 __msm_console_write(&dev->port, s, n, true);
987 }
988
989 static int __init
990 msm_serial_early_console_setup_dm(struct earlycon_device *device,
991 const char *opt)
992 {
993 if (!device->port.membase)
994 return -ENODEV;
995
996 device->con->write = msm_serial_early_write_dm;
997 return 0;
998 }
999 EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
1000 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1001 msm_serial_early_console_setup_dm);
1002
1003 static struct uart_driver msm_uart_driver;
1004
1005 static struct console msm_console = {
1006 .name = "ttyMSM",
1007 .write = msm_console_write,
1008 .device = uart_console_device,
1009 .setup = msm_console_setup,
1010 .flags = CON_PRINTBUFFER,
1011 .index = -1,
1012 .data = &msm_uart_driver,
1013 };
1014
1015 #define MSM_CONSOLE (&msm_console)
1016
1017 #else
1018 #define MSM_CONSOLE NULL
1019 #endif
1020
1021 static struct uart_driver msm_uart_driver = {
1022 .owner = THIS_MODULE,
1023 .driver_name = "msm_serial",
1024 .dev_name = "ttyMSM",
1025 .nr = UART_NR,
1026 .cons = MSM_CONSOLE,
1027 };
1028
1029 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1030
1031 static const struct of_device_id msm_uartdm_table[] = {
1032 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1033 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1034 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1035 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1036 { }
1037 };
1038
1039 static int msm_serial_probe(struct platform_device *pdev)
1040 {
1041 struct msm_port *msm_port;
1042 struct resource *resource;
1043 struct uart_port *port;
1044 const struct of_device_id *id;
1045 int irq, line;
1046
1047 if (pdev->dev.of_node)
1048 line = of_alias_get_id(pdev->dev.of_node, "serial");
1049 else
1050 line = pdev->id;
1051
1052 if (line < 0)
1053 line = atomic_inc_return(&msm_uart_next_id) - 1;
1054
1055 if (unlikely(line < 0 || line >= UART_NR))
1056 return -ENXIO;
1057
1058 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1059
1060 port = get_port_from_line(line);
1061 port->dev = &pdev->dev;
1062 msm_port = UART_TO_MSM(port);
1063
1064 id = of_match_device(msm_uartdm_table, &pdev->dev);
1065 if (id)
1066 msm_port->is_uartdm = (unsigned long)id->data;
1067 else
1068 msm_port->is_uartdm = 0;
1069
1070 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1071 if (IS_ERR(msm_port->clk))
1072 return PTR_ERR(msm_port->clk);
1073
1074 if (msm_port->is_uartdm) {
1075 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1076 if (IS_ERR(msm_port->pclk))
1077 return PTR_ERR(msm_port->pclk);
1078
1079 clk_set_rate(msm_port->clk, 1843200);
1080 }
1081
1082 port->uartclk = clk_get_rate(msm_port->clk);
1083 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1084
1085 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 if (unlikely(!resource))
1087 return -ENXIO;
1088 port->mapbase = resource->start;
1089
1090 irq = platform_get_irq(pdev, 0);
1091 if (unlikely(irq < 0))
1092 return -ENXIO;
1093 port->irq = irq;
1094
1095 platform_set_drvdata(pdev, port);
1096
1097 return uart_add_one_port(&msm_uart_driver, port);
1098 }
1099
1100 static int msm_serial_remove(struct platform_device *pdev)
1101 {
1102 struct uart_port *port = platform_get_drvdata(pdev);
1103
1104 uart_remove_one_port(&msm_uart_driver, port);
1105
1106 return 0;
1107 }
1108
1109 static const struct of_device_id msm_match_table[] = {
1110 { .compatible = "qcom,msm-uart" },
1111 { .compatible = "qcom,msm-uartdm" },
1112 {}
1113 };
1114
1115 static struct platform_driver msm_platform_driver = {
1116 .remove = msm_serial_remove,
1117 .probe = msm_serial_probe,
1118 .driver = {
1119 .name = "msm_serial",
1120 .of_match_table = msm_match_table,
1121 },
1122 };
1123
1124 static int __init msm_serial_init(void)
1125 {
1126 int ret;
1127
1128 ret = uart_register_driver(&msm_uart_driver);
1129 if (unlikely(ret))
1130 return ret;
1131
1132 ret = platform_driver_register(&msm_platform_driver);
1133 if (unlikely(ret))
1134 uart_unregister_driver(&msm_uart_driver);
1135
1136 pr_info("msm_serial: driver initialized\n");
1137
1138 return ret;
1139 }
1140
1141 static void __exit msm_serial_exit(void)
1142 {
1143 platform_driver_unregister(&msm_platform_driver);
1144 uart_unregister_driver(&msm_uart_driver);
1145 }
1146
1147 module_init(msm_serial_init);
1148 module_exit(msm_serial_exit);
1149
1150 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1151 MODULE_DESCRIPTION("Driver for msm7x serial device");
1152 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.114853 seconds and 4 git commands to generate.