drivers/tty/serial/msm_serial.h

   1 /*
   2  * Copyright (C) 2007 Google, Inc.
   3  * Author: Robert Love <rlove@google.com>
   4  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
  17 #define __DRIVERS_SERIAL_MSM_SERIAL_H
  18
  19 #define UART_MR1                        0x0000
  20
  21 #define UART_MR1_AUTO_RFR_LEVEL0        0x3F
  22 #define UART_MR1_AUTO_RFR_LEVEL1        0x3FF00
  23 #define UART_DM_MR1_AUTO_RFR_LEVEL1     0xFFFFFF00
  24 #define UART_MR1_RX_RDY_CTL             BIT(7)
  25 #define UART_MR1_CTS_CTL                BIT(6)
  26
  27 #define UART_MR2                        0x0004
  28 #define UART_MR2_ERROR_MODE             BIT(6)
  29 #define UART_MR2_BITS_PER_CHAR          0x30
  30 #define UART_MR2_BITS_PER_CHAR_5        (0x0 << 4)
  31 #define UART_MR2_BITS_PER_CHAR_6        (0x1 << 4)
  32 #define UART_MR2_BITS_PER_CHAR_7        (0x2 << 4)
  33 #define UART_MR2_BITS_PER_CHAR_8        (0x3 << 4)
  34 #define UART_MR2_STOP_BIT_LEN_ONE       (0x1 << 2)
  35 #define UART_MR2_STOP_BIT_LEN_TWO       (0x3 << 2)
  36 #define UART_MR2_PARITY_MODE_NONE       0x0
  37 #define UART_MR2_PARITY_MODE_ODD        0x1
  38 #define UART_MR2_PARITY_MODE_EVEN       0x2
  39 #define UART_MR2_PARITY_MODE_SPACE      0x3
  40 #define UART_MR2_PARITY_MODE            0x3
  41
  42 #define UART_CSR                        0x0008
  43
  44 #define UART_TF         0x000C
  45 #define UARTDM_TF       0x0070
  46
  47 #define UART_CR                         0x0010
  48 #define UART_CR_CMD_NULL                (0 << 4)
  49 #define UART_CR_CMD_RESET_RX            (1 << 4)
  50 #define UART_CR_CMD_RESET_TX            (2 << 4)
  51 #define UART_CR_CMD_RESET_ERR           (3 << 4)
  52 #define UART_CR_CMD_RESET_BREAK_INT     (4 << 4)
  53 #define UART_CR_CMD_START_BREAK         (5 << 4)
  54 #define UART_CR_CMD_STOP_BREAK          (6 << 4)
  55 #define UART_CR_CMD_RESET_CTS           (7 << 4)
  56 #define UART_CR_CMD_RESET_STALE_INT     (8 << 4)
  57 #define UART_CR_CMD_PACKET_MODE         (9 << 4)
  58 #define UART_CR_CMD_MODE_RESET          (12 << 4)
  59 #define UART_CR_CMD_SET_RFR             (13 << 4)
  60 #define UART_CR_CMD_RESET_RFR           (14 << 4)
  61 #define UART_CR_CMD_PROTECTION_EN       (16 << 4)
  62 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
  63 #define UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
  64 #define UART_CR_CMD_FORCE_STALE         (4 << 8)
  65 #define UART_CR_CMD_RESET_TX_READY      (3 << 8)
  66 #define UART_CR_TX_DISABLE              BIT(3)
  67 #define UART_CR_TX_ENABLE               BIT(2)
  68 #define UART_CR_RX_DISABLE              BIT(1)
  69 #define UART_CR_RX_ENABLE               BIT(0)
  70 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
  71
  72 #define UART_IMR                0x0014
  73 #define UART_IMR_TXLEV                  BIT(0)
  74 #define UART_IMR_RXSTALE                BIT(3)
  75 #define UART_IMR_RXLEV                  BIT(4)
  76 #define UART_IMR_DELTA_CTS              BIT(5)
  77 #define UART_IMR_CURRENT_CTS            BIT(6)
  78 #define UART_IMR_RXBREAK_START          BIT(10)
  79
  80 #define UART_IPR_RXSTALE_LAST           0x20
  81 #define UART_IPR_STALE_LSB              0x1F
  82 #define UART_IPR_STALE_TIMEOUT_MSB      0x3FF80
  83 #define UART_DM_IPR_STALE_TIMEOUT_MSB   0xFFFFFF80
  84
  85 #define UART_IPR        0x0018
  86 #define UART_TFWR       0x001C
  87 #define UART_RFWR       0x0020
  88 #define UART_HCR        0x0024
  89
  90 #define UART_MREG               0x0028
  91 #define UART_NREG               0x002C
  92 #define UART_DREG               0x0030
  93 #define UART_MNDREG             0x0034
  94 #define UART_IRDA               0x0038
  95 #define UART_MISR_MODE          0x0040
  96 #define UART_MISR_RESET         0x0044
  97 #define UART_MISR_EXPORT        0x0048
  98 #define UART_MISR_VAL           0x004C
  99 #define UART_TEST_CTRL          0x0050
 100
 101 #define UART_SR                 0x0008
 102 #define UART_SR_HUNT_CHAR       BIT(7)
 103 #define UART_SR_RX_BREAK        BIT(6)
 104 #define UART_SR_PAR_FRAME_ERR   BIT(5)
 105 #define UART_SR_OVERRUN         BIT(4)
 106 #define UART_SR_TX_EMPTY        BIT(3)
 107 #define UART_SR_TX_READY        BIT(2)
 108 #define UART_SR_RX_FULL         BIT(1)
 109 #define UART_SR_RX_READY        BIT(0)
 110
 111 #define UART_RF                 0x000C
 112 #define UARTDM_RF               0x0070
 113 #define UART_MISR               0x0010
 114 #define UART_ISR                0x0014
 115 #define UART_ISR_TX_READY       BIT(7)
 116
 117 #define UARTDM_RXFS             0x50
 118 #define UARTDM_RXFS_BUF_SHIFT   0x7
 119 #define UARTDM_RXFS_BUF_MASK    0x7
 120
 121 #define UARTDM_DMEN             0x3C
 122 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
 123 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
 124
 125 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2)        /* UARTDM_1P4 */
 126 #define UARTDM_DMEN_TX_DM_ENABLE  BIT(0)        /* < UARTDM_1P4 */
 127
 128 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3)        /* UARTDM_1P4 */
 129 #define UARTDM_DMEN_RX_DM_ENABLE  BIT(1)        /* < UARTDM_1P4 */
 130
 131 #define UARTDM_DMRX             0x34
 132 #define UARTDM_NCF_TX           0x40
 133 #define UARTDM_RX_TOTAL_SNAP    0x38
 134
 135 #define UART_TO_MSM(uart_port)  ((struct msm_port *) uart_port)
 136
 137 static inline
 138 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
 139 {
 140         writel_relaxed(val, port->membase + off);
 141 }
 142
 143 static inline
 144 unsigned int msm_read(struct uart_port *port, unsigned int off)
 145 {
 146         return readl_relaxed(port->membase + off);
 147 }
 148
 149 /*
 150  * Setup the MND registers to use the TCXO clock.
 151  */
 152 static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
 153 {
 154         msm_write(port, 0x06, UART_MREG);
 155         msm_write(port, 0xF1, UART_NREG);
 156         msm_write(port, 0x0F, UART_DREG);
 157         msm_write(port, 0x1A, UART_MNDREG);
 158         port->uartclk = 1843200;
 159 }
 160
 161 /*
 162  * Setup the MND registers to use the TCXO clock divided by 4.
 163  */
 164 static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
 165 {
 166         msm_write(port, 0x18, UART_MREG);
 167         msm_write(port, 0xF6, UART_NREG);
 168         msm_write(port, 0x0F, UART_DREG);
 169         msm_write(port, 0x0A, UART_MNDREG);
 170         port->uartclk = 1843200;
 171 }
 172
 173 static inline
 174 void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
 175 {
 176         if (port->uartclk == 19200000)
 177                 msm_serial_set_mnd_regs_tcxo(port);
 178         else if (port->uartclk == 4800000)
 179                 msm_serial_set_mnd_regs_tcxoby4(port);
 180 }
 181
 182 #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
 183
 184 #endif  /* __DRIVERS_SERIAL_MSM_SERIAL_H */