2 * Freescale STMP37XX/STMP378X Application UART driver
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25 #include <linux/tty.h>
26 #include <linux/tty_driver.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/device.h>
32 #include <linux/clk.h>
33 #include <linux/delay.h>
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/of_device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/fsl/mxs-dma.h>
40 #include <asm/cacheflush.h>
42 #define MXS_AUART_PORTS 5
44 #define AUART_CTRL0 0x00000000
45 #define AUART_CTRL0_SET 0x00000004
46 #define AUART_CTRL0_CLR 0x00000008
47 #define AUART_CTRL0_TOG 0x0000000c
48 #define AUART_CTRL1 0x00000010
49 #define AUART_CTRL1_SET 0x00000014
50 #define AUART_CTRL1_CLR 0x00000018
51 #define AUART_CTRL1_TOG 0x0000001c
52 #define AUART_CTRL2 0x00000020
53 #define AUART_CTRL2_SET 0x00000024
54 #define AUART_CTRL2_CLR 0x00000028
55 #define AUART_CTRL2_TOG 0x0000002c
56 #define AUART_LINECTRL 0x00000030
57 #define AUART_LINECTRL_SET 0x00000034
58 #define AUART_LINECTRL_CLR 0x00000038
59 #define AUART_LINECTRL_TOG 0x0000003c
60 #define AUART_LINECTRL2 0x00000040
61 #define AUART_LINECTRL2_SET 0x00000044
62 #define AUART_LINECTRL2_CLR 0x00000048
63 #define AUART_LINECTRL2_TOG 0x0000004c
64 #define AUART_INTR 0x00000050
65 #define AUART_INTR_SET 0x00000054
66 #define AUART_INTR_CLR 0x00000058
67 #define AUART_INTR_TOG 0x0000005c
68 #define AUART_DATA 0x00000060
69 #define AUART_STAT 0x00000070
70 #define AUART_DEBUG 0x00000080
71 #define AUART_VERSION 0x00000090
72 #define AUART_AUTOBAUD 0x000000a0
74 #define AUART_CTRL0_SFTRST (1 << 31)
75 #define AUART_CTRL0_CLKGATE (1 << 30)
76 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
77 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
78 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
80 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
82 #define AUART_CTRL2_DMAONERR (1 << 26)
83 #define AUART_CTRL2_TXDMAE (1 << 25)
84 #define AUART_CTRL2_RXDMAE (1 << 24)
86 #define AUART_CTRL2_CTSEN (1 << 15)
87 #define AUART_CTRL2_RTSEN (1 << 14)
88 #define AUART_CTRL2_RTS (1 << 11)
89 #define AUART_CTRL2_RXE (1 << 9)
90 #define AUART_CTRL2_TXE (1 << 8)
91 #define AUART_CTRL2_UARTEN (1 << 0)
93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
94 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
95 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
98 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
99 #define AUART_LINECTRL_WLEN_MASK 0x00000060
100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101 #define AUART_LINECTRL_FEN (1 << 4)
102 #define AUART_LINECTRL_STP2 (1 << 3)
103 #define AUART_LINECTRL_EPS (1 << 2)
104 #define AUART_LINECTRL_PEN (1 << 1)
105 #define AUART_LINECTRL_BRK (1 << 0)
107 #define AUART_INTR_RTIEN (1 << 22)
108 #define AUART_INTR_TXIEN (1 << 21)
109 #define AUART_INTR_RXIEN (1 << 20)
110 #define AUART_INTR_CTSMIEN (1 << 17)
111 #define AUART_INTR_RTIS (1 << 6)
112 #define AUART_INTR_TXIS (1 << 5)
113 #define AUART_INTR_RXIS (1 << 4)
114 #define AUART_INTR_CTSMIS (1 << 1)
116 #define AUART_STAT_BUSY (1 << 29)
117 #define AUART_STAT_CTS (1 << 28)
118 #define AUART_STAT_TXFE (1 << 27)
119 #define AUART_STAT_TXFF (1 << 25)
120 #define AUART_STAT_RXFE (1 << 24)
121 #define AUART_STAT_OERR (1 << 19)
122 #define AUART_STAT_BERR (1 << 18)
123 #define AUART_STAT_PERR (1 << 17)
124 #define AUART_STAT_FERR (1 << 16)
125 #define AUART_STAT_RXCOUNT_MASK 0xffff
127 static struct uart_driver auart_driver
;
129 enum mxs_auart_type
{
134 struct mxs_auart_port
{
135 struct uart_port port
;
137 #define MXS_AUART_DMA_CONFIG 0x1
138 #define MXS_AUART_DMA_ENABLED 0x2
139 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
140 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
143 enum mxs_auart_type devtype
;
151 struct mxs_dma_data dma_data
;
152 int dma_channel_rx
, dma_channel_tx
;
153 int dma_irq_rx
, dma_irq_tx
;
156 struct scatterlist tx_sgl
;
157 struct dma_chan
*tx_dma_chan
;
160 struct scatterlist rx_sgl
;
161 struct dma_chan
*rx_dma_chan
;
165 static struct platform_device_id mxs_auart_devtype
[] = {
166 { .name
= "mxs-auart-imx23", .driver_data
= IMX23_AUART
},
167 { .name
= "mxs-auart-imx28", .driver_data
= IMX28_AUART
},
170 MODULE_DEVICE_TABLE(platform
, mxs_auart_devtype
);
172 static struct of_device_id mxs_auart_dt_ids
[] = {
174 .compatible
= "fsl,imx28-auart",
175 .data
= &mxs_auart_devtype
[IMX28_AUART
]
177 .compatible
= "fsl,imx23-auart",
178 .data
= &mxs_auart_devtype
[IMX23_AUART
]
179 }, { /* sentinel */ }
181 MODULE_DEVICE_TABLE(of
, mxs_auart_dt_ids
);
183 static inline int is_imx28_auart(struct mxs_auart_port
*s
)
185 return s
->devtype
== IMX28_AUART
;
188 static inline bool auart_dma_enabled(struct mxs_auart_port
*s
)
190 return s
->flags
& MXS_AUART_DMA_ENABLED
;
193 static void mxs_auart_stop_tx(struct uart_port
*u
);
195 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
197 static void mxs_auart_tx_chars(struct mxs_auart_port
*s
);
199 static void dma_tx_callback(void *param
)
201 struct mxs_auart_port
*s
= param
;
202 struct circ_buf
*xmit
= &s
->port
.state
->xmit
;
204 dma_unmap_sg(s
->dev
, &s
->tx_sgl
, 1, DMA_TO_DEVICE
);
206 /* clear the bit used to serialize the DMA tx. */
207 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
208 smp_mb__after_clear_bit();
210 /* wake up the possible processes. */
211 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
212 uart_write_wakeup(&s
->port
);
214 mxs_auart_tx_chars(s
);
217 static int mxs_auart_dma_tx(struct mxs_auart_port
*s
, int size
)
219 struct dma_async_tx_descriptor
*desc
;
220 struct scatterlist
*sgl
= &s
->tx_sgl
;
221 struct dma_chan
*channel
= s
->tx_dma_chan
;
224 /* [1] : send PIO. Note, the first pio word is CTRL1. */
225 pio
= AUART_CTRL1_XFER_COUNT(size
);
226 desc
= dmaengine_prep_slave_sg(channel
, (struct scatterlist
*)&pio
,
227 1, DMA_TRANS_NONE
, 0);
229 dev_err(s
->dev
, "step 1 error\n");
233 /* [2] : set DMA buffer. */
234 sg_init_one(sgl
, s
->tx_dma_buf
, size
);
235 dma_map_sg(s
->dev
, sgl
, 1, DMA_TO_DEVICE
);
236 desc
= dmaengine_prep_slave_sg(channel
, sgl
,
237 1, DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
239 dev_err(s
->dev
, "step 2 error\n");
243 /* [3] : submit the DMA */
244 desc
->callback
= dma_tx_callback
;
245 desc
->callback_param
= s
;
246 dmaengine_submit(desc
);
247 dma_async_issue_pending(channel
);
251 static void mxs_auart_tx_chars(struct mxs_auart_port
*s
)
253 struct circ_buf
*xmit
= &s
->port
.state
->xmit
;
255 if (auart_dma_enabled(s
)) {
258 void *buffer
= s
->tx_dma_buf
;
260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
))
263 while (!uart_circ_empty(xmit
) && !uart_tx_stopped(&s
->port
)) {
264 size
= min_t(u32
, UART_XMIT_SIZE
- i
,
265 CIRC_CNT_TO_END(xmit
->head
,
268 memcpy(buffer
+ i
, xmit
->buf
+ xmit
->tail
, size
);
269 xmit
->tail
= (xmit
->tail
+ size
) & (UART_XMIT_SIZE
- 1);
272 if (i
>= UART_XMIT_SIZE
)
276 if (uart_tx_stopped(&s
->port
))
277 mxs_auart_stop_tx(&s
->port
);
280 mxs_auart_dma_tx(s
, i
);
282 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
283 smp_mb__after_clear_bit();
289 while (!(readl(s
->port
.membase
+ AUART_STAT
) &
291 if (s
->port
.x_char
) {
293 writel(s
->port
.x_char
,
294 s
->port
.membase
+ AUART_DATA
);
298 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&s
->port
)) {
300 writel(xmit
->buf
[xmit
->tail
],
301 s
->port
.membase
+ AUART_DATA
);
302 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
306 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
307 uart_write_wakeup(&s
->port
);
309 if (uart_circ_empty(&(s
->port
.state
->xmit
)))
310 writel(AUART_INTR_TXIEN
,
311 s
->port
.membase
+ AUART_INTR_CLR
);
313 writel(AUART_INTR_TXIEN
,
314 s
->port
.membase
+ AUART_INTR_SET
);
316 if (uart_tx_stopped(&s
->port
))
317 mxs_auart_stop_tx(&s
->port
);
320 static void mxs_auart_rx_char(struct mxs_auart_port
*s
)
326 c
= readl(s
->port
.membase
+ AUART_DATA
);
327 stat
= readl(s
->port
.membase
+ AUART_STAT
);
332 if (stat
& AUART_STAT_BERR
) {
333 s
->port
.icount
.brk
++;
334 if (uart_handle_break(&s
->port
))
336 } else if (stat
& AUART_STAT_PERR
) {
337 s
->port
.icount
.parity
++;
338 } else if (stat
& AUART_STAT_FERR
) {
339 s
->port
.icount
.frame
++;
343 * Mask off conditions which should be ingored.
345 stat
&= s
->port
.read_status_mask
;
347 if (stat
& AUART_STAT_BERR
) {
349 } else if (stat
& AUART_STAT_PERR
)
351 else if (stat
& AUART_STAT_FERR
)
354 if (stat
& AUART_STAT_OERR
)
355 s
->port
.icount
.overrun
++;
357 if (uart_handle_sysrq_char(&s
->port
, c
))
360 uart_insert_char(&s
->port
, stat
, AUART_STAT_OERR
, c
, flag
);
362 writel(stat
, s
->port
.membase
+ AUART_STAT
);
365 static void mxs_auart_rx_chars(struct mxs_auart_port
*s
)
367 struct tty_struct
*tty
= s
->port
.state
->port
.tty
;
371 stat
= readl(s
->port
.membase
+ AUART_STAT
);
372 if (stat
& AUART_STAT_RXFE
)
374 mxs_auart_rx_char(s
);
377 writel(stat
, s
->port
.membase
+ AUART_STAT
);
378 tty_flip_buffer_push(tty
);
381 static int mxs_auart_request_port(struct uart_port
*u
)
386 static int mxs_auart_verify_port(struct uart_port
*u
,
387 struct serial_struct
*ser
)
389 if (u
->type
!= PORT_UNKNOWN
&& u
->type
!= PORT_IMX
)
394 static void mxs_auart_config_port(struct uart_port
*u
, int flags
)
398 static const char *mxs_auart_type(struct uart_port
*u
)
400 struct mxs_auart_port
*s
= to_auart_port(u
);
402 return dev_name(s
->dev
);
405 static void mxs_auart_release_port(struct uart_port
*u
)
409 static void mxs_auart_set_mctrl(struct uart_port
*u
, unsigned mctrl
)
411 struct mxs_auart_port
*s
= to_auart_port(u
);
413 u32 ctrl
= readl(u
->membase
+ AUART_CTRL2
);
415 ctrl
&= ~AUART_CTRL2_RTSEN
;
416 if (mctrl
& TIOCM_RTS
) {
417 if (tty_port_cts_enabled(&u
->state
->port
))
418 ctrl
|= AUART_CTRL2_RTSEN
;
422 writel(ctrl
, u
->membase
+ AUART_CTRL2
);
425 static u32
mxs_auart_get_mctrl(struct uart_port
*u
)
427 struct mxs_auart_port
*s
= to_auart_port(u
);
428 u32 stat
= readl(u
->membase
+ AUART_STAT
);
429 int ctrl2
= readl(u
->membase
+ AUART_CTRL2
);
433 if (stat
& AUART_STAT_CTS
)
436 if (ctrl2
& AUART_CTRL2_RTS
)
442 static bool mxs_auart_dma_filter(struct dma_chan
*chan
, void *param
)
444 struct mxs_auart_port
*s
= param
;
446 if (!mxs_dma_is_apbx(chan
))
449 if (s
->dma_channel
== chan
->chan_id
) {
450 chan
->private = &s
->dma_data
;
456 static int mxs_auart_dma_prep_rx(struct mxs_auart_port
*s
);
457 static void dma_rx_callback(void *arg
)
459 struct mxs_auart_port
*s
= (struct mxs_auart_port
*) arg
;
460 struct tty_struct
*tty
= s
->port
.state
->port
.tty
;
464 stat
= readl(s
->port
.membase
+ AUART_STAT
);
465 stat
&= ~(AUART_STAT_OERR
| AUART_STAT_BERR
|
466 AUART_STAT_PERR
| AUART_STAT_FERR
);
468 count
= stat
& AUART_STAT_RXCOUNT_MASK
;
469 tty_insert_flip_string(tty
, s
->rx_dma_buf
, count
);
471 writel(stat
, s
->port
.membase
+ AUART_STAT
);
472 tty_flip_buffer_push(tty
);
474 /* start the next DMA for RX. */
475 mxs_auart_dma_prep_rx(s
);
478 static int mxs_auart_dma_prep_rx(struct mxs_auart_port
*s
)
480 struct dma_async_tx_descriptor
*desc
;
481 struct scatterlist
*sgl
= &s
->rx_sgl
;
482 struct dma_chan
*channel
= s
->rx_dma_chan
;
486 pio
[0] = AUART_CTRL0_RXTO_ENABLE
487 | AUART_CTRL0_RXTIMEOUT(0x80)
488 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE
);
489 desc
= dmaengine_prep_slave_sg(channel
, (struct scatterlist
*)pio
,
490 1, DMA_TRANS_NONE
, 0);
492 dev_err(s
->dev
, "step 1 error\n");
496 /* [2] : send DMA request */
497 sg_init_one(sgl
, s
->rx_dma_buf
, UART_XMIT_SIZE
);
498 dma_map_sg(s
->dev
, sgl
, 1, DMA_FROM_DEVICE
);
499 desc
= dmaengine_prep_slave_sg(channel
, sgl
, 1, DMA_DEV_TO_MEM
,
500 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
502 dev_err(s
->dev
, "step 2 error\n");
506 /* [3] : submit the DMA, but do not issue it. */
507 desc
->callback
= dma_rx_callback
;
508 desc
->callback_param
= s
;
509 dmaengine_submit(desc
);
510 dma_async_issue_pending(channel
);
514 static void mxs_auart_dma_exit_channel(struct mxs_auart_port
*s
)
516 if (s
->tx_dma_chan
) {
517 dma_release_channel(s
->tx_dma_chan
);
518 s
->tx_dma_chan
= NULL
;
520 if (s
->rx_dma_chan
) {
521 dma_release_channel(s
->rx_dma_chan
);
522 s
->rx_dma_chan
= NULL
;
525 kfree(s
->tx_dma_buf
);
526 kfree(s
->rx_dma_buf
);
527 s
->tx_dma_buf
= NULL
;
528 s
->rx_dma_buf
= NULL
;
531 static void mxs_auart_dma_exit(struct mxs_auart_port
*s
)
534 writel(AUART_CTRL2_TXDMAE
| AUART_CTRL2_RXDMAE
| AUART_CTRL2_DMAONERR
,
535 s
->port
.membase
+ AUART_CTRL2_CLR
);
537 mxs_auart_dma_exit_channel(s
);
538 s
->flags
&= ~MXS_AUART_DMA_ENABLED
;
539 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
540 clear_bit(MXS_AUART_DMA_RX_READY
, &s
->flags
);
543 static int mxs_auart_dma_init(struct mxs_auart_port
*s
)
547 if (auart_dma_enabled(s
))
550 /* We do not get the right DMA channels. */
551 if (s
->dma_channel_rx
== -1 || s
->dma_channel_rx
== -1)
556 dma_cap_set(DMA_SLAVE
, mask
);
557 s
->dma_channel
= s
->dma_channel_rx
;
558 s
->dma_data
.chan_irq
= s
->dma_irq_rx
;
559 s
->rx_dma_chan
= dma_request_channel(mask
, mxs_auart_dma_filter
, s
);
562 s
->rx_dma_buf
= kzalloc(UART_XMIT_SIZE
, GFP_KERNEL
| GFP_DMA
);
567 s
->dma_channel
= s
->dma_channel_tx
;
568 s
->dma_data
.chan_irq
= s
->dma_irq_tx
;
569 s
->tx_dma_chan
= dma_request_channel(mask
, mxs_auart_dma_filter
, s
);
572 s
->tx_dma_buf
= kzalloc(UART_XMIT_SIZE
, GFP_KERNEL
| GFP_DMA
);
577 s
->flags
|= MXS_AUART_DMA_ENABLED
;
578 dev_dbg(s
->dev
, "enabled the DMA support.");
583 mxs_auart_dma_exit_channel(s
);
588 static void mxs_auart_settermios(struct uart_port
*u
,
589 struct ktermios
*termios
,
590 struct ktermios
*old
)
592 struct mxs_auart_port
*s
= to_auart_port(u
);
593 u32 bm
, ctrl
, ctrl2
, div
;
594 unsigned int cflag
, baud
;
596 cflag
= termios
->c_cflag
;
598 ctrl
= AUART_LINECTRL_FEN
;
599 ctrl2
= readl(u
->membase
+ AUART_CTRL2
);
602 switch (cflag
& CSIZE
) {
619 ctrl
|= AUART_LINECTRL_WLEN(bm
);
622 if (cflag
& PARENB
) {
623 ctrl
|= AUART_LINECTRL_PEN
;
624 if ((cflag
& PARODD
) == 0)
625 ctrl
|= AUART_LINECTRL_EPS
;
628 u
->read_status_mask
= 0;
630 if (termios
->c_iflag
& INPCK
)
631 u
->read_status_mask
|= AUART_STAT_PERR
;
632 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
633 u
->read_status_mask
|= AUART_STAT_BERR
;
636 * Characters to ignore
638 u
->ignore_status_mask
= 0;
639 if (termios
->c_iflag
& IGNPAR
)
640 u
->ignore_status_mask
|= AUART_STAT_PERR
;
641 if (termios
->c_iflag
& IGNBRK
) {
642 u
->ignore_status_mask
|= AUART_STAT_BERR
;
644 * If we're ignoring parity and break indicators,
645 * ignore overruns too (for real raw support).
647 if (termios
->c_iflag
& IGNPAR
)
648 u
->ignore_status_mask
|= AUART_STAT_OERR
;
652 * ignore all characters if CREAD is not set
655 ctrl2
|= AUART_CTRL2_RXE
;
657 ctrl2
&= ~AUART_CTRL2_RXE
;
659 /* figure out the stop bits requested */
661 ctrl
|= AUART_LINECTRL_STP2
;
663 /* figure out the hardware flow control settings */
664 if (cflag
& CRTSCTS
) {
666 * The DMA has a bug(see errata:2836) in mx23.
667 * So we can not implement the DMA for auart in mx23,
668 * we can only implement the DMA support for auart
671 if (is_imx28_auart(s
) && (s
->flags
& MXS_AUART_DMA_CONFIG
)) {
672 if (!mxs_auart_dma_init(s
))
673 /* enable DMA tranfer */
674 ctrl2
|= AUART_CTRL2_TXDMAE
| AUART_CTRL2_RXDMAE
675 | AUART_CTRL2_DMAONERR
;
677 ctrl2
|= AUART_CTRL2_CTSEN
| AUART_CTRL2_RTSEN
;
679 ctrl2
&= ~(AUART_CTRL2_CTSEN
| AUART_CTRL2_RTSEN
);
683 baud
= uart_get_baud_rate(u
, termios
, old
, 0, u
->uartclk
);
684 div
= u
->uartclk
* 32 / baud
;
685 ctrl
|= AUART_LINECTRL_BAUD_DIVFRAC(div
& 0x3F);
686 ctrl
|= AUART_LINECTRL_BAUD_DIVINT(div
>> 6);
688 writel(ctrl
, u
->membase
+ AUART_LINECTRL
);
689 writel(ctrl2
, u
->membase
+ AUART_CTRL2
);
691 uart_update_timeout(u
, termios
->c_cflag
, baud
);
693 /* prepare for the DMA RX. */
694 if (auart_dma_enabled(s
) &&
695 !test_and_set_bit(MXS_AUART_DMA_RX_READY
, &s
->flags
)) {
696 if (!mxs_auart_dma_prep_rx(s
)) {
697 /* Disable the normal RX interrupt. */
698 writel(AUART_INTR_RXIEN
, u
->membase
+ AUART_INTR_CLR
);
700 mxs_auart_dma_exit(s
);
701 dev_err(s
->dev
, "We can not start up the DMA.\n");
706 static irqreturn_t
mxs_auart_irq_handle(int irq
, void *context
)
709 struct mxs_auart_port
*s
= context
;
710 u32 stat
= readl(s
->port
.membase
+ AUART_STAT
);
712 istatus
= istat
= readl(s
->port
.membase
+ AUART_INTR
);
714 if (istat
& AUART_INTR_CTSMIS
) {
715 uart_handle_cts_change(&s
->port
, stat
& AUART_STAT_CTS
);
716 writel(AUART_INTR_CTSMIS
,
717 s
->port
.membase
+ AUART_INTR_CLR
);
718 istat
&= ~AUART_INTR_CTSMIS
;
721 if (istat
& (AUART_INTR_RTIS
| AUART_INTR_RXIS
)) {
722 mxs_auart_rx_chars(s
);
723 istat
&= ~(AUART_INTR_RTIS
| AUART_INTR_RXIS
);
726 if (istat
& AUART_INTR_TXIS
) {
727 mxs_auart_tx_chars(s
);
728 istat
&= ~AUART_INTR_TXIS
;
731 writel(istatus
& (AUART_INTR_RTIS
734 | AUART_INTR_CTSMIS
),
735 s
->port
.membase
+ AUART_INTR_CLR
);
740 static void mxs_auart_reset(struct uart_port
*u
)
745 writel(AUART_CTRL0_SFTRST
, u
->membase
+ AUART_CTRL0_CLR
);
747 for (i
= 0; i
< 10000; i
++) {
748 reg
= readl(u
->membase
+ AUART_CTRL0
);
749 if (!(reg
& AUART_CTRL0_SFTRST
))
753 writel(AUART_CTRL0_CLKGATE
, u
->membase
+ AUART_CTRL0_CLR
);
756 static int mxs_auart_startup(struct uart_port
*u
)
758 struct mxs_auart_port
*s
= to_auart_port(u
);
760 clk_prepare_enable(s
->clk
);
762 writel(AUART_CTRL0_CLKGATE
, u
->membase
+ AUART_CTRL0_CLR
);
764 writel(AUART_CTRL2_UARTEN
, u
->membase
+ AUART_CTRL2_SET
);
766 writel(AUART_INTR_RXIEN
| AUART_INTR_RTIEN
| AUART_INTR_CTSMIEN
,
767 u
->membase
+ AUART_INTR
);
770 * Enable fifo so all four bytes of a DMA word are written to
771 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
773 writel(AUART_LINECTRL_FEN
, u
->membase
+ AUART_LINECTRL_SET
);
778 static void mxs_auart_shutdown(struct uart_port
*u
)
780 struct mxs_auart_port
*s
= to_auart_port(u
);
782 if (auart_dma_enabled(s
))
783 mxs_auart_dma_exit(s
);
785 writel(AUART_CTRL2_UARTEN
, u
->membase
+ AUART_CTRL2_CLR
);
787 writel(AUART_INTR_RXIEN
| AUART_INTR_RTIEN
| AUART_INTR_CTSMIEN
,
788 u
->membase
+ AUART_INTR_CLR
);
790 writel(AUART_CTRL0_CLKGATE
, u
->membase
+ AUART_CTRL0_SET
);
792 clk_disable_unprepare(s
->clk
);
795 static unsigned int mxs_auart_tx_empty(struct uart_port
*u
)
797 if (readl(u
->membase
+ AUART_STAT
) & AUART_STAT_TXFE
)
803 static void mxs_auart_start_tx(struct uart_port
*u
)
805 struct mxs_auart_port
*s
= to_auart_port(u
);
807 /* enable transmitter */
808 writel(AUART_CTRL2_TXE
, u
->membase
+ AUART_CTRL2_SET
);
810 mxs_auart_tx_chars(s
);
813 static void mxs_auart_stop_tx(struct uart_port
*u
)
815 writel(AUART_CTRL2_TXE
, u
->membase
+ AUART_CTRL2_CLR
);
818 static void mxs_auart_stop_rx(struct uart_port
*u
)
820 writel(AUART_CTRL2_RXE
, u
->membase
+ AUART_CTRL2_CLR
);
823 static void mxs_auart_break_ctl(struct uart_port
*u
, int ctl
)
826 writel(AUART_LINECTRL_BRK
,
827 u
->membase
+ AUART_LINECTRL_SET
);
829 writel(AUART_LINECTRL_BRK
,
830 u
->membase
+ AUART_LINECTRL_CLR
);
833 static void mxs_auart_enable_ms(struct uart_port
*port
)
838 static struct uart_ops mxs_auart_ops
= {
839 .tx_empty
= mxs_auart_tx_empty
,
840 .start_tx
= mxs_auart_start_tx
,
841 .stop_tx
= mxs_auart_stop_tx
,
842 .stop_rx
= mxs_auart_stop_rx
,
843 .enable_ms
= mxs_auart_enable_ms
,
844 .break_ctl
= mxs_auart_break_ctl
,
845 .set_mctrl
= mxs_auart_set_mctrl
,
846 .get_mctrl
= mxs_auart_get_mctrl
,
847 .startup
= mxs_auart_startup
,
848 .shutdown
= mxs_auart_shutdown
,
849 .set_termios
= mxs_auart_settermios
,
850 .type
= mxs_auart_type
,
851 .release_port
= mxs_auart_release_port
,
852 .request_port
= mxs_auart_request_port
,
853 .config_port
= mxs_auart_config_port
,
854 .verify_port
= mxs_auart_verify_port
,
857 static struct mxs_auart_port
*auart_port
[MXS_AUART_PORTS
];
859 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
860 static void mxs_auart_console_putchar(struct uart_port
*port
, int ch
)
862 unsigned int to
= 1000;
864 while (readl(port
->membase
+ AUART_STAT
) & AUART_STAT_TXFF
) {
870 writel(ch
, port
->membase
+ AUART_DATA
);
874 auart_console_write(struct console
*co
, const char *str
, unsigned int count
)
876 struct mxs_auart_port
*s
;
877 struct uart_port
*port
;
878 unsigned int old_ctrl0
, old_ctrl2
;
879 unsigned int to
= 1000;
881 if (co
->index
> MXS_AUART_PORTS
|| co
->index
< 0)
884 s
= auart_port
[co
->index
];
889 /* First save the CR then disable the interrupts */
890 old_ctrl2
= readl(port
->membase
+ AUART_CTRL2
);
891 old_ctrl0
= readl(port
->membase
+ AUART_CTRL0
);
893 writel(AUART_CTRL0_CLKGATE
,
894 port
->membase
+ AUART_CTRL0_CLR
);
895 writel(AUART_CTRL2_UARTEN
| AUART_CTRL2_TXE
,
896 port
->membase
+ AUART_CTRL2_SET
);
898 uart_console_write(port
, str
, count
, mxs_auart_console_putchar
);
901 * Finally, wait for transmitter to become empty
902 * and restore the TCR
904 while (readl(port
->membase
+ AUART_STAT
) & AUART_STAT_BUSY
) {
910 writel(old_ctrl0
, port
->membase
+ AUART_CTRL0
);
911 writel(old_ctrl2
, port
->membase
+ AUART_CTRL2
);
917 auart_console_get_options(struct uart_port
*port
, int *baud
,
918 int *parity
, int *bits
)
920 unsigned int lcr_h
, quot
;
922 if (!(readl(port
->membase
+ AUART_CTRL2
) & AUART_CTRL2_UARTEN
))
925 lcr_h
= readl(port
->membase
+ AUART_LINECTRL
);
928 if (lcr_h
& AUART_LINECTRL_PEN
) {
929 if (lcr_h
& AUART_LINECTRL_EPS
)
935 if ((lcr_h
& AUART_LINECTRL_WLEN_MASK
) == AUART_LINECTRL_WLEN(2))
940 quot
= ((readl(port
->membase
+ AUART_LINECTRL
)
941 & AUART_LINECTRL_BAUD_DIVINT_MASK
))
942 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT
- 6);
943 quot
|= ((readl(port
->membase
+ AUART_LINECTRL
)
944 & AUART_LINECTRL_BAUD_DIVFRAC_MASK
))
945 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT
;
949 *baud
= (port
->uartclk
<< 2) / quot
;
953 auart_console_setup(struct console
*co
, char *options
)
955 struct mxs_auart_port
*s
;
963 * Check whether an invalid uart number has been specified, and
964 * if so, search for the first available port that does have
967 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(auart_port
))
969 s
= auart_port
[co
->index
];
973 clk_prepare_enable(s
->clk
);
976 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
978 auart_console_get_options(&s
->port
, &baud
, &parity
, &bits
);
980 ret
= uart_set_options(&s
->port
, co
, baud
, parity
, bits
, flow
);
982 clk_disable_unprepare(s
->clk
);
987 static struct console auart_console
= {
989 .write
= auart_console_write
,
990 .device
= uart_console_device
,
991 .setup
= auart_console_setup
,
992 .flags
= CON_PRINTBUFFER
,
994 .data
= &auart_driver
,
998 static struct uart_driver auart_driver
= {
999 .owner
= THIS_MODULE
,
1000 .driver_name
= "ttyAPP",
1001 .dev_name
= "ttyAPP",
1004 .nr
= MXS_AUART_PORTS
,
1005 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1006 .cons
= &auart_console
,
1011 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1012 * could successfully get all information from dt or a negative errno.
1014 static int serial_mxs_probe_dt(struct mxs_auart_port
*s
,
1015 struct platform_device
*pdev
)
1017 struct device_node
*np
= pdev
->dev
.of_node
;
1022 /* no device tree device */
1025 ret
= of_alias_get_id(np
, "serial");
1027 dev_err(&pdev
->dev
, "failed to get alias id: %d\n", ret
);
1032 s
->dma_irq_rx
= platform_get_irq(pdev
, 1);
1033 s
->dma_irq_tx
= platform_get_irq(pdev
, 2);
1035 ret
= of_property_read_u32_array(np
, "fsl,auart-dma-channel",
1038 s
->dma_channel_rx
= dma_channel
[0];
1039 s
->dma_channel_tx
= dma_channel
[1];
1041 s
->flags
|= MXS_AUART_DMA_CONFIG
;
1043 s
->dma_channel_rx
= -1;
1044 s
->dma_channel_tx
= -1;
1049 static int mxs_auart_probe(struct platform_device
*pdev
)
1051 const struct of_device_id
*of_id
=
1052 of_match_device(mxs_auart_dt_ids
, &pdev
->dev
);
1053 struct mxs_auart_port
*s
;
1057 struct pinctrl
*pinctrl
;
1059 s
= kzalloc(sizeof(struct mxs_auart_port
), GFP_KERNEL
);
1065 ret
= serial_mxs_probe_dt(s
, pdev
);
1067 s
->port
.line
= pdev
->id
< 0 ? 0 : pdev
->id
;
1071 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
1072 if (IS_ERR(pinctrl
)) {
1073 ret
= PTR_ERR(pinctrl
);
1078 pdev
->id_entry
= of_id
->data
;
1079 s
->devtype
= pdev
->id_entry
->driver_data
;
1082 s
->clk
= clk_get(&pdev
->dev
, NULL
);
1083 if (IS_ERR(s
->clk
)) {
1084 ret
= PTR_ERR(s
->clk
);
1088 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1094 s
->port
.mapbase
= r
->start
;
1095 s
->port
.membase
= ioremap(r
->start
, resource_size(r
));
1096 s
->port
.ops
= &mxs_auart_ops
;
1097 s
->port
.iotype
= UPIO_MEM
;
1098 s
->port
.fifosize
= 16;
1099 s
->port
.uartclk
= clk_get_rate(s
->clk
);
1100 s
->port
.type
= PORT_IMX
;
1101 s
->port
.dev
= s
->dev
= get_device(&pdev
->dev
);
1105 s
->irq
= platform_get_irq(pdev
, 0);
1106 s
->port
.irq
= s
->irq
;
1107 ret
= request_irq(s
->irq
, mxs_auart_irq_handle
, 0, dev_name(&pdev
->dev
), s
);
1111 platform_set_drvdata(pdev
, s
);
1113 auart_port
[s
->port
.line
] = s
;
1115 mxs_auart_reset(&s
->port
);
1117 ret
= uart_add_one_port(&auart_driver
, &s
->port
);
1121 version
= readl(s
->port
.membase
+ AUART_VERSION
);
1122 dev_info(&pdev
->dev
, "Found APPUART %d.%d.%d\n",
1123 (version
>> 24) & 0xff,
1124 (version
>> 16) & 0xff, version
& 0xffff);
1129 auart_port
[pdev
->id
] = NULL
;
1130 free_irq(s
->irq
, s
);
1140 static int mxs_auart_remove(struct platform_device
*pdev
)
1142 struct mxs_auart_port
*s
= platform_get_drvdata(pdev
);
1144 uart_remove_one_port(&auart_driver
, &s
->port
);
1146 auart_port
[pdev
->id
] = NULL
;
1150 free_irq(s
->irq
, s
);
1156 static struct platform_driver mxs_auart_driver
= {
1157 .probe
= mxs_auart_probe
,
1158 .remove
= mxs_auart_remove
,
1160 .name
= "mxs-auart",
1161 .owner
= THIS_MODULE
,
1162 .of_match_table
= mxs_auart_dt_ids
,
1166 static int __init
mxs_auart_init(void)
1170 r
= uart_register_driver(&auart_driver
);
1174 r
= platform_driver_register(&mxs_auart_driver
);
1180 uart_unregister_driver(&auart_driver
);
1185 static void __exit
mxs_auart_exit(void)
1187 platform_driver_unregister(&mxs_auart_driver
);
1188 uart_unregister_driver(&auart_driver
);
1191 module_init(mxs_auart_init
);
1192 module_exit(mxs_auart_exit
);
1193 MODULE_LICENSE("GPL");
1194 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1195 MODULE_ALIAS("platform:mxs-auart");