920468bf4e8336c538e34b36937edde06b63686c
[deliverable/linux.git] / drivers / tty / serial / of_serial.c
1 /*
2 * Serial Port driver for Open Firmware platform devices
3 *
4 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12 #include <linux/console.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/nwpserial.h>
22 #include <linux/clk.h>
23
24 #ifdef CONFIG_SERIAL_8250_MODULE
25 #define CONFIG_SERIAL_8250 CONFIG_SERIAL_8250_MODULE
26 #endif
27
28 #include "8250/8250.h"
29
30 struct of_serial_info {
31 struct clk *clk;
32 int type;
33 int line;
34 };
35
36 #ifdef CONFIG_ARCH_TEGRA
37 void tegra_serial_handle_break(struct uart_port *p)
38 {
39 unsigned int status, tmout = 10000;
40
41 do {
42 status = p->serial_in(p, UART_LSR);
43 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
44 status = p->serial_in(p, UART_RX);
45 else
46 break;
47 if (--tmout == 0)
48 break;
49 udelay(1);
50 } while (1);
51 }
52 #else
53 static inline void tegra_serial_handle_break(struct uart_port *port)
54 {
55 }
56 #endif
57
58 /*
59 * Fill a struct uart_port for a given device node
60 */
61 static int of_platform_serial_setup(struct platform_device *ofdev,
62 int type, struct uart_port *port,
63 struct of_serial_info *info)
64 {
65 struct resource resource;
66 struct device_node *np = ofdev->dev.of_node;
67 u32 clk, spd, prop;
68 int ret;
69
70 memset(port, 0, sizeof *port);
71 if (of_property_read_u32(np, "clock-frequency", &clk)) {
72
73 /* Get clk rate through clk driver if present */
74 info->clk = devm_clk_get(&ofdev->dev, NULL);
75 if (IS_ERR(info->clk)) {
76 dev_warn(&ofdev->dev,
77 "clk or clock-frequency not defined\n");
78 return PTR_ERR(info->clk);
79 }
80
81 ret = clk_prepare_enable(info->clk);
82 if (ret < 0)
83 return ret;
84
85 clk = clk_get_rate(info->clk);
86 }
87 /* If current-speed was set, then try not to change it. */
88 if (of_property_read_u32(np, "current-speed", &spd) == 0)
89 port->custom_divisor = clk / (16 * spd);
90
91 ret = of_address_to_resource(np, 0, &resource);
92 if (ret) {
93 dev_warn(&ofdev->dev, "invalid address\n");
94 goto out;
95 }
96
97 spin_lock_init(&port->lock);
98 port->mapbase = resource.start;
99 port->mapsize = resource_size(&resource);
100
101 /* Check for shifted address mapping */
102 if (of_property_read_u32(np, "reg-offset", &prop) == 0)
103 port->mapbase += prop;
104
105 /* Check for registers offset within the devices address range */
106 if (of_property_read_u32(np, "reg-shift", &prop) == 0)
107 port->regshift = prop;
108
109 /* Check for fifo size */
110 if (of_property_read_u32(np, "fifo-size", &prop) == 0)
111 port->fifosize = prop;
112
113 /* Check for a fixed line number */
114 ret = of_alias_get_id(np, "serial");
115 if (ret >= 0)
116 port->line = ret;
117
118 port->irq = irq_of_parse_and_map(np, 0);
119 port->iotype = UPIO_MEM;
120 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
121 switch (prop) {
122 case 1:
123 port->iotype = UPIO_MEM;
124 break;
125 case 2:
126 port->iotype = UPIO_MEM16;
127 break;
128 case 4:
129 port->iotype = of_device_is_big_endian(np) ?
130 UPIO_MEM32BE : UPIO_MEM32;
131 break;
132 default:
133 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
134 prop);
135 ret = -EINVAL;
136 goto out;
137 }
138 }
139
140 port->type = type;
141 port->uartclk = clk;
142 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
143 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
144
145 if (of_find_property(np, "no-loopback-test", NULL))
146 port->flags |= UPF_SKIP_TEST;
147
148 port->dev = &ofdev->dev;
149
150 switch (type) {
151 case PORT_TEGRA:
152 port->handle_break = tegra_serial_handle_break;
153 break;
154
155 case PORT_RT2880:
156 port->iotype = UPIO_AU;
157 break;
158 }
159
160 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
161 (of_device_is_compatible(np, "fsl,ns16550") ||
162 of_device_is_compatible(np, "fsl,16550-FIFO64")))
163 port->handle_irq = fsl8250_handle_irq;
164
165 return 0;
166 out:
167 if (info->clk)
168 clk_disable_unprepare(info->clk);
169 return ret;
170 }
171
172 /*
173 * Try to register a serial port
174 */
175 static const struct of_device_id of_platform_serial_table[];
176 static int of_platform_serial_probe(struct platform_device *ofdev)
177 {
178 const struct of_device_id *match;
179 struct of_serial_info *info;
180 struct uart_port port;
181 int port_type;
182 int ret;
183
184 match = of_match_device(of_platform_serial_table, &ofdev->dev);
185 if (!match)
186 return -EINVAL;
187
188 if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
189 return -EBUSY;
190
191 info = kzalloc(sizeof(*info), GFP_KERNEL);
192 if (info == NULL)
193 return -ENOMEM;
194
195 port_type = (unsigned long)match->data;
196 ret = of_platform_serial_setup(ofdev, port_type, &port, info);
197 if (ret)
198 goto out;
199
200 switch (port_type) {
201 #ifdef CONFIG_SERIAL_8250
202 case PORT_8250 ... PORT_MAX_8250:
203 {
204 struct uart_8250_port port8250;
205 memset(&port8250, 0, sizeof(port8250));
206 port8250.port = port;
207
208 if (port.fifosize)
209 port8250.capabilities = UART_CAP_FIFO;
210
211 if (of_property_read_bool(ofdev->dev.of_node,
212 "auto-flow-control"))
213 port8250.capabilities |= UART_CAP_AFE;
214
215 ret = serial8250_register_8250_port(&port8250);
216 break;
217 }
218 #endif
219 default:
220 /* need to add code for these */
221 case PORT_UNKNOWN:
222 dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
223 ret = -ENODEV;
224 break;
225 }
226 if (ret < 0)
227 goto out;
228
229 info->type = port_type;
230 info->line = ret;
231 platform_set_drvdata(ofdev, info);
232 return 0;
233 out:
234 kfree(info);
235 irq_dispose_mapping(port.irq);
236 return ret;
237 }
238
239 /*
240 * Release a line
241 */
242 static int of_platform_serial_remove(struct platform_device *ofdev)
243 {
244 struct of_serial_info *info = platform_get_drvdata(ofdev);
245 switch (info->type) {
246 #ifdef CONFIG_SERIAL_8250
247 case PORT_8250 ... PORT_MAX_8250:
248 serial8250_unregister_port(info->line);
249 break;
250 #endif
251 default:
252 /* need to add code for these */
253 break;
254 }
255
256 if (info->clk)
257 clk_disable_unprepare(info->clk);
258 kfree(info);
259 return 0;
260 }
261
262 #ifdef CONFIG_PM_SLEEP
263 #ifdef CONFIG_SERIAL_8250
264 static void of_serial_suspend_8250(struct of_serial_info *info)
265 {
266 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
267 struct uart_port *port = &port8250->port;
268
269 serial8250_suspend_port(info->line);
270 if (info->clk && (!uart_console(port) || console_suspend_enabled))
271 clk_disable_unprepare(info->clk);
272 }
273
274 static void of_serial_resume_8250(struct of_serial_info *info)
275 {
276 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
277 struct uart_port *port = &port8250->port;
278
279 if (info->clk && (!uart_console(port) || console_suspend_enabled))
280 clk_prepare_enable(info->clk);
281
282 serial8250_resume_port(info->line);
283 }
284 #else
285 static inline void of_serial_suspend_8250(struct of_serial_info *info)
286 {
287 }
288
289 static inline void of_serial_resume_8250(struct of_serial_info *info)
290 {
291 }
292 #endif
293
294 static int of_serial_suspend(struct device *dev)
295 {
296 struct of_serial_info *info = dev_get_drvdata(dev);
297
298 switch (info->type) {
299 case PORT_8250 ... PORT_MAX_8250:
300 of_serial_suspend_8250(info);
301 break;
302 default:
303 break;
304 }
305
306 return 0;
307 }
308
309 static int of_serial_resume(struct device *dev)
310 {
311 struct of_serial_info *info = dev_get_drvdata(dev);
312
313 switch (info->type) {
314 case PORT_8250 ... PORT_MAX_8250:
315 of_serial_resume_8250(info);
316 break;
317 default:
318 break;
319 }
320
321 return 0;
322 }
323 #endif
324 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
325
326 /*
327 * A few common types, add more as needed.
328 */
329 static const struct of_device_id of_platform_serial_table[] = {
330 { .compatible = "ns8250", .data = (void *)PORT_8250, },
331 { .compatible = "ns16450", .data = (void *)PORT_16450, },
332 { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
333 { .compatible = "ns16550", .data = (void *)PORT_16550, },
334 { .compatible = "ns16750", .data = (void *)PORT_16750, },
335 { .compatible = "ns16850", .data = (void *)PORT_16850, },
336 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
337 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
338 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
339 { .compatible = "altr,16550-FIFO32",
340 .data = (void *)PORT_ALTR_16550_F32, },
341 { .compatible = "altr,16550-FIFO64",
342 .data = (void *)PORT_ALTR_16550_F64, },
343 { .compatible = "altr,16550-FIFO128",
344 .data = (void *)PORT_ALTR_16550_F128, },
345 { .compatible = "mrvl,mmp-uart",
346 .data = (void *)PORT_XSCALE, },
347 { .compatible = "mrvl,pxa-uart",
348 .data = (void *)PORT_XSCALE, },
349 { /* end of list */ },
350 };
351 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
352
353 static struct platform_driver of_platform_serial_driver = {
354 .driver = {
355 .name = "of_serial",
356 .of_match_table = of_platform_serial_table,
357 },
358 .probe = of_platform_serial_probe,
359 .remove = of_platform_serial_remove,
360 };
361
362 module_platform_driver(of_platform_serial_driver);
363
364 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
365 MODULE_LICENSE("GPL");
366 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
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