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serial: omap: define helpers for pdata function pointers
[deliverable/linux.git] / drivers / tty / serial / omap-serial.c
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42 #include <linux/gpio.h>
43
44 #include <plat/dma.h>
45 #include <plat/dmtimer.h>
46 #include <plat/omap-serial.h>
47
48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
49
50 #define OMAP_UART_REV_42 0x0402
51 #define OMAP_UART_REV_46 0x0406
52 #define OMAP_UART_REV_52 0x0502
53 #define OMAP_UART_REV_63 0x0603
54
55 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
56
57 /* SCR register bitmasks */
58 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
59
60 /* FCR register bitmasks */
61 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
62 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
63
64 /* MVR register bitmasks */
65 #define OMAP_UART_MVR_SCHEME_SHIFT 30
66
67 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
68 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
69 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
70
71 #define OMAP_UART_MVR_MAJ_MASK 0x700
72 #define OMAP_UART_MVR_MAJ_SHIFT 8
73 #define OMAP_UART_MVR_MIN_MASK 0x3f
74
75 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
76
77 /* Forward declaration of functions */
78 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
79 static void serial_omap_rxdma_poll(unsigned long uart_no);
80 static int serial_omap_start_rxdma(struct uart_omap_port *up);
81 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
82
83 static struct workqueue_struct *serial_omap_uart_wq;
84
85 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
86 {
87 offset <<= up->port.regshift;
88 return readw(up->port.membase + offset);
89 }
90
91 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
92 {
93 offset <<= up->port.regshift;
94 writew(value, up->port.membase + offset);
95 }
96
97 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
98 {
99 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
100 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
101 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
102 serial_out(up, UART_FCR, 0);
103 }
104
105 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
106 {
107 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
108
109 if (!pdata->get_context_loss_count)
110 return 0;
111
112 return pdata->get_context_loss_count(&up->pdev->dev);
113 }
114
115 static void serial_omap_set_forceidle(struct uart_omap_port *up)
116 {
117 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
118
119 if (pdata->set_forceidle)
120 pdata->set_forceidle(up->pdev);
121 }
122
123 static void serial_omap_set_noidle(struct uart_omap_port *up)
124 {
125 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
126
127 if (pdata->set_noidle)
128 pdata->set_noidle(up->pdev);
129 }
130
131 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
132 {
133 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
134
135 if (pdata->enable_wakeup)
136 pdata->enable_wakeup(up->pdev, enable);
137 }
138
139 /*
140 * serial_omap_get_divisor - calculate divisor value
141 * @port: uart port info
142 * @baud: baudrate for which divisor needs to be calculated.
143 *
144 * We have written our own function to get the divisor so as to support
145 * 13x mode. 3Mbps Baudrate as an different divisor.
146 * Reference OMAP TRM Chapter 17:
147 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
148 * referring to oversampling - divisor value
149 * baudrate 460,800 to 3,686,400 all have divisor 13
150 * except 3,000,000 which has divisor value 16
151 */
152 static unsigned int
153 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
154 {
155 unsigned int divisor;
156
157 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
158 divisor = 13;
159 else
160 divisor = 16;
161 return port->uartclk/(baud * divisor);
162 }
163
164 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
165 {
166 if (up->uart_dma.rx_dma_used) {
167 del_timer(&up->uart_dma.rx_timer);
168 omap_stop_dma(up->uart_dma.rx_dma_channel);
169 omap_free_dma(up->uart_dma.rx_dma_channel);
170 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
171 up->uart_dma.rx_dma_used = false;
172 pm_runtime_mark_last_busy(&up->pdev->dev);
173 pm_runtime_put_autosuspend(&up->pdev->dev);
174 }
175 }
176
177 static void serial_omap_enable_ms(struct uart_port *port)
178 {
179 struct uart_omap_port *up = to_uart_omap_port(port);
180
181 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
182
183 pm_runtime_get_sync(&up->pdev->dev);
184 up->ier |= UART_IER_MSI;
185 serial_out(up, UART_IER, up->ier);
186 pm_runtime_put(&up->pdev->dev);
187 }
188
189 static void serial_omap_stop_tx(struct uart_port *port)
190 {
191 struct uart_omap_port *up = to_uart_omap_port(port);
192 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
193
194 if (up->use_dma &&
195 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
196 /*
197 * Check if dma is still active. If yes do nothing,
198 * return. Else stop dma
199 */
200 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
201 return;
202 omap_stop_dma(up->uart_dma.tx_dma_channel);
203 omap_free_dma(up->uart_dma.tx_dma_channel);
204 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
205 pm_runtime_mark_last_busy(&up->pdev->dev);
206 pm_runtime_put_autosuspend(&up->pdev->dev);
207 }
208
209 pm_runtime_get_sync(&up->pdev->dev);
210 if (up->ier & UART_IER_THRI) {
211 up->ier &= ~UART_IER_THRI;
212 serial_out(up, UART_IER, up->ier);
213 }
214
215 if (!up->use_dma && pdata)
216 serial_omap_set_forceidle(up);
217
218 pm_runtime_mark_last_busy(&up->pdev->dev);
219 pm_runtime_put_autosuspend(&up->pdev->dev);
220 }
221
222 static void serial_omap_stop_rx(struct uart_port *port)
223 {
224 struct uart_omap_port *up = to_uart_omap_port(port);
225
226 pm_runtime_get_sync(&up->pdev->dev);
227 if (up->use_dma)
228 serial_omap_stop_rxdma(up);
229 up->ier &= ~UART_IER_RLSI;
230 up->port.read_status_mask &= ~UART_LSR_DR;
231 serial_out(up, UART_IER, up->ier);
232 pm_runtime_mark_last_busy(&up->pdev->dev);
233 pm_runtime_put_autosuspend(&up->pdev->dev);
234 }
235
236 static inline void receive_chars(struct uart_omap_port *up,
237 unsigned int *status)
238 {
239 struct tty_struct *tty = up->port.state->port.tty;
240 unsigned int flag, lsr = *status;
241 unsigned char ch = 0;
242 int max_count = 256;
243
244 do {
245 if (likely(lsr & UART_LSR_DR))
246 ch = serial_in(up, UART_RX);
247 flag = TTY_NORMAL;
248 up->port.icount.rx++;
249
250 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
251 /*
252 * For statistics only
253 */
254 if (lsr & UART_LSR_BI) {
255 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
256 up->port.icount.brk++;
257 /*
258 * We do the SysRQ and SAK checking
259 * here because otherwise the break
260 * may get masked by ignore_status_mask
261 * or read_status_mask.
262 */
263 if (uart_handle_break(&up->port))
264 goto ignore_char;
265 } else if (lsr & UART_LSR_PE) {
266 up->port.icount.parity++;
267 } else if (lsr & UART_LSR_FE) {
268 up->port.icount.frame++;
269 }
270
271 if (lsr & UART_LSR_OE)
272 up->port.icount.overrun++;
273
274 /*
275 * Mask off conditions which should be ignored.
276 */
277 lsr &= up->port.read_status_mask;
278
279 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
280 if (up->port.line == up->port.cons->index) {
281 /* Recover the break flag from console xmit */
282 lsr |= up->lsr_break_flag;
283 }
284 #endif
285 if (lsr & UART_LSR_BI)
286 flag = TTY_BREAK;
287 else if (lsr & UART_LSR_PE)
288 flag = TTY_PARITY;
289 else if (lsr & UART_LSR_FE)
290 flag = TTY_FRAME;
291 }
292
293 if (uart_handle_sysrq_char(&up->port, ch))
294 goto ignore_char;
295 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
296 ignore_char:
297 lsr = serial_in(up, UART_LSR);
298 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
299 spin_unlock(&up->port.lock);
300 tty_flip_buffer_push(tty);
301 spin_lock(&up->port.lock);
302 }
303
304 static void transmit_chars(struct uart_omap_port *up)
305 {
306 struct circ_buf *xmit = &up->port.state->xmit;
307 int count;
308
309 if (up->port.x_char) {
310 serial_out(up, UART_TX, up->port.x_char);
311 up->port.icount.tx++;
312 up->port.x_char = 0;
313 return;
314 }
315 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
316 serial_omap_stop_tx(&up->port);
317 return;
318 }
319 count = up->port.fifosize / 4;
320 do {
321 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
322 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
323 up->port.icount.tx++;
324 if (uart_circ_empty(xmit))
325 break;
326 } while (--count > 0);
327
328 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
329 uart_write_wakeup(&up->port);
330
331 if (uart_circ_empty(xmit))
332 serial_omap_stop_tx(&up->port);
333 }
334
335 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
336 {
337 if (!(up->ier & UART_IER_THRI)) {
338 up->ier |= UART_IER_THRI;
339 serial_out(up, UART_IER, up->ier);
340 }
341 }
342
343 static void serial_omap_start_tx(struct uart_port *port)
344 {
345 struct uart_omap_port *up = to_uart_omap_port(port);
346 struct circ_buf *xmit;
347 unsigned int start;
348 int ret = 0;
349
350 if (!up->use_dma) {
351 pm_runtime_get_sync(&up->pdev->dev);
352 serial_omap_enable_ier_thri(up);
353 serial_omap_set_noidle(up);
354 pm_runtime_mark_last_busy(&up->pdev->dev);
355 pm_runtime_put_autosuspend(&up->pdev->dev);
356 return;
357 }
358
359 if (up->uart_dma.tx_dma_used)
360 return;
361
362 xmit = &up->port.state->xmit;
363
364 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
365 pm_runtime_get_sync(&up->pdev->dev);
366 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
367 "UART Tx DMA",
368 (void *)uart_tx_dma_callback, up,
369 &(up->uart_dma.tx_dma_channel));
370
371 if (ret < 0) {
372 serial_omap_enable_ier_thri(up);
373 return;
374 }
375 }
376 spin_lock(&(up->uart_dma.tx_lock));
377 up->uart_dma.tx_dma_used = true;
378 spin_unlock(&(up->uart_dma.tx_lock));
379
380 start = up->uart_dma.tx_buf_dma_phys +
381 (xmit->tail & (UART_XMIT_SIZE - 1));
382
383 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
384 /*
385 * It is a circular buffer. See if the buffer has wounded back.
386 * If yes it will have to be transferred in two separate dma
387 * transfers
388 */
389 if (start + up->uart_dma.tx_buf_size >=
390 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
391 up->uart_dma.tx_buf_size =
392 (up->uart_dma.tx_buf_dma_phys +
393 UART_XMIT_SIZE) - start;
394
395 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
396 OMAP_DMA_AMODE_CONSTANT,
397 up->uart_dma.uart_base, 0, 0);
398 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
399 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
400 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
401 OMAP_DMA_DATA_TYPE_S8,
402 up->uart_dma.tx_buf_size, 1,
403 OMAP_DMA_SYNC_ELEMENT,
404 up->uart_dma.uart_dma_tx, 0);
405 /* FIXME: Cache maintenance needed here? */
406 omap_start_dma(up->uart_dma.tx_dma_channel);
407 }
408
409 static unsigned int check_modem_status(struct uart_omap_port *up)
410 {
411 unsigned int status;
412
413 status = serial_in(up, UART_MSR);
414 status |= up->msr_saved_flags;
415 up->msr_saved_flags = 0;
416 if ((status & UART_MSR_ANY_DELTA) == 0)
417 return status;
418
419 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
420 up->port.state != NULL) {
421 if (status & UART_MSR_TERI)
422 up->port.icount.rng++;
423 if (status & UART_MSR_DDSR)
424 up->port.icount.dsr++;
425 if (status & UART_MSR_DDCD)
426 uart_handle_dcd_change
427 (&up->port, status & UART_MSR_DCD);
428 if (status & UART_MSR_DCTS)
429 uart_handle_cts_change
430 (&up->port, status & UART_MSR_CTS);
431 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
432 }
433
434 return status;
435 }
436
437 /**
438 * serial_omap_irq() - This handles the interrupt from one port
439 * @irq: uart port irq number
440 * @dev_id: uart port info
441 */
442 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
443 {
444 struct uart_omap_port *up = dev_id;
445 unsigned int iir, lsr;
446 unsigned long flags;
447
448 pm_runtime_get_sync(&up->pdev->dev);
449 iir = serial_in(up, UART_IIR);
450 if (iir & UART_IIR_NO_INT) {
451 pm_runtime_mark_last_busy(&up->pdev->dev);
452 pm_runtime_put_autosuspend(&up->pdev->dev);
453 return IRQ_NONE;
454 }
455
456 spin_lock_irqsave(&up->port.lock, flags);
457 lsr = serial_in(up, UART_LSR);
458 if (iir & UART_IIR_RLSI) {
459 if (!up->use_dma) {
460 if (lsr & UART_LSR_DR)
461 receive_chars(up, &lsr);
462 } else {
463 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
464 serial_out(up, UART_IER, up->ier);
465 if ((serial_omap_start_rxdma(up) != 0) &&
466 (lsr & UART_LSR_DR))
467 receive_chars(up, &lsr);
468 }
469 }
470
471 check_modem_status(up);
472 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
473 transmit_chars(up);
474
475 spin_unlock_irqrestore(&up->port.lock, flags);
476 pm_runtime_mark_last_busy(&up->pdev->dev);
477 pm_runtime_put_autosuspend(&up->pdev->dev);
478
479 up->port_activity = jiffies;
480 return IRQ_HANDLED;
481 }
482
483 static unsigned int serial_omap_tx_empty(struct uart_port *port)
484 {
485 struct uart_omap_port *up = to_uart_omap_port(port);
486 unsigned long flags = 0;
487 unsigned int ret = 0;
488
489 pm_runtime_get_sync(&up->pdev->dev);
490 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
491 spin_lock_irqsave(&up->port.lock, flags);
492 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
493 spin_unlock_irqrestore(&up->port.lock, flags);
494 pm_runtime_put(&up->pdev->dev);
495 return ret;
496 }
497
498 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
499 {
500 struct uart_omap_port *up = to_uart_omap_port(port);
501 unsigned int status;
502 unsigned int ret = 0;
503
504 pm_runtime_get_sync(&up->pdev->dev);
505 status = check_modem_status(up);
506 pm_runtime_put(&up->pdev->dev);
507
508 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
509
510 if (status & UART_MSR_DCD)
511 ret |= TIOCM_CAR;
512 if (status & UART_MSR_RI)
513 ret |= TIOCM_RNG;
514 if (status & UART_MSR_DSR)
515 ret |= TIOCM_DSR;
516 if (status & UART_MSR_CTS)
517 ret |= TIOCM_CTS;
518 return ret;
519 }
520
521 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
522 {
523 struct uart_omap_port *up = to_uart_omap_port(port);
524 unsigned char mcr = 0;
525
526 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
527 if (mctrl & TIOCM_RTS)
528 mcr |= UART_MCR_RTS;
529 if (mctrl & TIOCM_DTR)
530 mcr |= UART_MCR_DTR;
531 if (mctrl & TIOCM_OUT1)
532 mcr |= UART_MCR_OUT1;
533 if (mctrl & TIOCM_OUT2)
534 mcr |= UART_MCR_OUT2;
535 if (mctrl & TIOCM_LOOP)
536 mcr |= UART_MCR_LOOP;
537
538 pm_runtime_get_sync(&up->pdev->dev);
539 up->mcr = serial_in(up, UART_MCR);
540 up->mcr |= mcr;
541 serial_out(up, UART_MCR, up->mcr);
542 pm_runtime_put(&up->pdev->dev);
543
544 if (gpio_is_valid(up->DTR_gpio) &&
545 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
546 up->DTR_active = !up->DTR_active;
547 if (gpio_cansleep(up->DTR_gpio))
548 schedule_work(&up->qos_work);
549 else
550 gpio_set_value(up->DTR_gpio,
551 up->DTR_active != up->DTR_inverted);
552 }
553 }
554
555 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
556 {
557 struct uart_omap_port *up = to_uart_omap_port(port);
558 unsigned long flags = 0;
559
560 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
561 pm_runtime_get_sync(&up->pdev->dev);
562 spin_lock_irqsave(&up->port.lock, flags);
563 if (break_state == -1)
564 up->lcr |= UART_LCR_SBC;
565 else
566 up->lcr &= ~UART_LCR_SBC;
567 serial_out(up, UART_LCR, up->lcr);
568 spin_unlock_irqrestore(&up->port.lock, flags);
569 pm_runtime_put(&up->pdev->dev);
570 }
571
572 static int serial_omap_startup(struct uart_port *port)
573 {
574 struct uart_omap_port *up = to_uart_omap_port(port);
575 unsigned long flags = 0;
576 int retval;
577
578 /*
579 * Allocate the IRQ
580 */
581 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
582 up->name, up);
583 if (retval)
584 return retval;
585
586 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
587
588 pm_runtime_get_sync(&up->pdev->dev);
589 /*
590 * Clear the FIFO buffers and disable them.
591 * (they will be reenabled in set_termios())
592 */
593 serial_omap_clear_fifos(up);
594 /* For Hardware flow control */
595 serial_out(up, UART_MCR, UART_MCR_RTS);
596
597 /*
598 * Clear the interrupt registers.
599 */
600 (void) serial_in(up, UART_LSR);
601 if (serial_in(up, UART_LSR) & UART_LSR_DR)
602 (void) serial_in(up, UART_RX);
603 (void) serial_in(up, UART_IIR);
604 (void) serial_in(up, UART_MSR);
605
606 /*
607 * Now, initialize the UART
608 */
609 serial_out(up, UART_LCR, UART_LCR_WLEN8);
610 spin_lock_irqsave(&up->port.lock, flags);
611 /*
612 * Most PC uarts need OUT2 raised to enable interrupts.
613 */
614 up->port.mctrl |= TIOCM_OUT2;
615 serial_omap_set_mctrl(&up->port, up->port.mctrl);
616 spin_unlock_irqrestore(&up->port.lock, flags);
617
618 up->msr_saved_flags = 0;
619 if (up->use_dma) {
620 free_page((unsigned long)up->port.state->xmit.buf);
621 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
622 UART_XMIT_SIZE,
623 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
624 0);
625 init_timer(&(up->uart_dma.rx_timer));
626 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
627 up->uart_dma.rx_timer.data = up->port.line;
628 /* Currently the buffer size is 4KB. Can increase it */
629 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
630 up->uart_dma.rx_buf_size,
631 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
632 }
633 /*
634 * Finally, enable interrupts. Note: Modem status interrupts
635 * are set via set_termios(), which will be occurring imminently
636 * anyway, so we don't enable them here.
637 */
638 up->ier = UART_IER_RLSI | UART_IER_RDI;
639 serial_out(up, UART_IER, up->ier);
640
641 /* Enable module level wake up */
642 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
643
644 pm_runtime_mark_last_busy(&up->pdev->dev);
645 pm_runtime_put_autosuspend(&up->pdev->dev);
646 up->port_activity = jiffies;
647 return 0;
648 }
649
650 static void serial_omap_shutdown(struct uart_port *port)
651 {
652 struct uart_omap_port *up = to_uart_omap_port(port);
653 unsigned long flags = 0;
654
655 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
656
657 pm_runtime_get_sync(&up->pdev->dev);
658 /*
659 * Disable interrupts from this port
660 */
661 up->ier = 0;
662 serial_out(up, UART_IER, 0);
663
664 spin_lock_irqsave(&up->port.lock, flags);
665 up->port.mctrl &= ~TIOCM_OUT2;
666 serial_omap_set_mctrl(&up->port, up->port.mctrl);
667 spin_unlock_irqrestore(&up->port.lock, flags);
668
669 /*
670 * Disable break condition and FIFOs
671 */
672 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
673 serial_omap_clear_fifos(up);
674
675 /*
676 * Read data port to reset things, and then free the irq
677 */
678 if (serial_in(up, UART_LSR) & UART_LSR_DR)
679 (void) serial_in(up, UART_RX);
680 if (up->use_dma) {
681 dma_free_coherent(up->port.dev,
682 UART_XMIT_SIZE, up->port.state->xmit.buf,
683 up->uart_dma.tx_buf_dma_phys);
684 up->port.state->xmit.buf = NULL;
685 serial_omap_stop_rx(port);
686 dma_free_coherent(up->port.dev,
687 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
688 up->uart_dma.rx_buf_dma_phys);
689 up->uart_dma.rx_buf = NULL;
690 }
691
692 pm_runtime_put(&up->pdev->dev);
693 free_irq(up->port.irq, up);
694 }
695
696 static inline void
697 serial_omap_configure_xonxoff
698 (struct uart_omap_port *up, struct ktermios *termios)
699 {
700 up->lcr = serial_in(up, UART_LCR);
701 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
702 up->efr = serial_in(up, UART_EFR);
703 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
704
705 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
706 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
707
708 /* clear SW control mode bits */
709 up->efr &= OMAP_UART_SW_CLR;
710
711 /*
712 * IXON Flag:
713 * Enable XON/XOFF flow control on output.
714 * Transmit XON1, XOFF1
715 */
716 if (termios->c_iflag & IXON)
717 up->efr |= OMAP_UART_SW_TX;
718
719 /*
720 * IXOFF Flag:
721 * Enable XON/XOFF flow control on input.
722 * Receiver compares XON1, XOFF1.
723 */
724 if (termios->c_iflag & IXOFF)
725 up->efr |= OMAP_UART_SW_RX;
726
727 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
728 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
729
730 up->mcr = serial_in(up, UART_MCR);
731
732 /*
733 * IXANY Flag:
734 * Enable any character to restart output.
735 * Operation resumes after receiving any
736 * character after recognition of the XOFF character
737 */
738 if (termios->c_iflag & IXANY)
739 up->mcr |= UART_MCR_XONANY;
740
741 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
742 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
743 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
744 /* Enable special char function UARTi.EFR_REG[5] and
745 * load the new software flow control mode IXON or IXOFF
746 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
747 */
748 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
749 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
750
751 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
752 serial_out(up, UART_LCR, up->lcr);
753 }
754
755 static void serial_omap_uart_qos_work(struct work_struct *work)
756 {
757 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
758 qos_work);
759
760 pm_qos_update_request(&up->pm_qos_request, up->latency);
761 if (gpio_is_valid(up->DTR_gpio))
762 gpio_set_value_cansleep(up->DTR_gpio,
763 up->DTR_active != up->DTR_inverted);
764 }
765
766 static void
767 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
768 struct ktermios *old)
769 {
770 struct uart_omap_port *up = to_uart_omap_port(port);
771 unsigned char cval = 0;
772 unsigned char efr = 0;
773 unsigned long flags = 0;
774 unsigned int baud, quot;
775
776 switch (termios->c_cflag & CSIZE) {
777 case CS5:
778 cval = UART_LCR_WLEN5;
779 break;
780 case CS6:
781 cval = UART_LCR_WLEN6;
782 break;
783 case CS7:
784 cval = UART_LCR_WLEN7;
785 break;
786 default:
787 case CS8:
788 cval = UART_LCR_WLEN8;
789 break;
790 }
791
792 if (termios->c_cflag & CSTOPB)
793 cval |= UART_LCR_STOP;
794 if (termios->c_cflag & PARENB)
795 cval |= UART_LCR_PARITY;
796 if (!(termios->c_cflag & PARODD))
797 cval |= UART_LCR_EPAR;
798
799 /*
800 * Ask the core to calculate the divisor for us.
801 */
802
803 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
804 quot = serial_omap_get_divisor(port, baud);
805
806 /* calculate wakeup latency constraint */
807 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
808 up->latency = up->calc_latency;
809 schedule_work(&up->qos_work);
810
811 up->dll = quot & 0xff;
812 up->dlh = quot >> 8;
813 up->mdr1 = UART_OMAP_MDR1_DISABLE;
814
815 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
816 UART_FCR_ENABLE_FIFO;
817 if (up->use_dma)
818 up->fcr |= UART_FCR_DMA_SELECT;
819
820 /*
821 * Ok, we're now changing the port state. Do it with
822 * interrupts disabled.
823 */
824 pm_runtime_get_sync(&up->pdev->dev);
825 spin_lock_irqsave(&up->port.lock, flags);
826
827 /*
828 * Update the per-port timeout.
829 */
830 uart_update_timeout(port, termios->c_cflag, baud);
831
832 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
833 if (termios->c_iflag & INPCK)
834 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
835 if (termios->c_iflag & (BRKINT | PARMRK))
836 up->port.read_status_mask |= UART_LSR_BI;
837
838 /*
839 * Characters to ignore
840 */
841 up->port.ignore_status_mask = 0;
842 if (termios->c_iflag & IGNPAR)
843 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
844 if (termios->c_iflag & IGNBRK) {
845 up->port.ignore_status_mask |= UART_LSR_BI;
846 /*
847 * If we're ignoring parity and break indicators,
848 * ignore overruns too (for real raw support).
849 */
850 if (termios->c_iflag & IGNPAR)
851 up->port.ignore_status_mask |= UART_LSR_OE;
852 }
853
854 /*
855 * ignore all characters if CREAD is not set
856 */
857 if ((termios->c_cflag & CREAD) == 0)
858 up->port.ignore_status_mask |= UART_LSR_DR;
859
860 /*
861 * Modem status interrupts
862 */
863 up->ier &= ~UART_IER_MSI;
864 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
865 up->ier |= UART_IER_MSI;
866 serial_out(up, UART_IER, up->ier);
867 serial_out(up, UART_LCR, cval); /* reset DLAB */
868 up->lcr = cval;
869 up->scr = OMAP_UART_SCR_TX_EMPTY;
870
871 /* FIFOs and DMA Settings */
872
873 /* FCR can be changed only when the
874 * baud clock is not running
875 * DLL_REG and DLH_REG set to 0.
876 */
877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
878 serial_out(up, UART_DLL, 0);
879 serial_out(up, UART_DLM, 0);
880 serial_out(up, UART_LCR, 0);
881
882 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
883
884 up->efr = serial_in(up, UART_EFR);
885 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
886
887 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
888 up->mcr = serial_in(up, UART_MCR);
889 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
890 /* FIFO ENABLE, DMA MODE */
891
892 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
893
894 if (up->use_dma) {
895 serial_out(up, UART_TI752_TLR, 0);
896 up->scr |= UART_FCR_TRIGGER_4;
897 } else {
898 /* Set receive FIFO threshold to 1 byte */
899 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
900 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
901 }
902
903 serial_out(up, UART_FCR, up->fcr);
904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
905
906 serial_out(up, UART_OMAP_SCR, up->scr);
907
908 serial_out(up, UART_EFR, up->efr);
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
910 serial_out(up, UART_MCR, up->mcr);
911
912 /* Protocol, Baud Rate, and Interrupt Settings */
913
914 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
915 serial_omap_mdr1_errataset(up, up->mdr1);
916 else
917 serial_out(up, UART_OMAP_MDR1, up->mdr1);
918
919 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
920
921 up->efr = serial_in(up, UART_EFR);
922 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
923
924 serial_out(up, UART_LCR, 0);
925 serial_out(up, UART_IER, 0);
926 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
927
928 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
929 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
930
931 serial_out(up, UART_LCR, 0);
932 serial_out(up, UART_IER, up->ier);
933 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
934
935 serial_out(up, UART_EFR, up->efr);
936 serial_out(up, UART_LCR, cval);
937
938 if (baud > 230400 && baud != 3000000)
939 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
940 else
941 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
942
943 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
944 serial_omap_mdr1_errataset(up, up->mdr1);
945 else
946 serial_out(up, UART_OMAP_MDR1, up->mdr1);
947
948 /* Hardware Flow Control Configuration */
949
950 if (termios->c_cflag & CRTSCTS) {
951 efr |= (UART_EFR_CTS | UART_EFR_RTS);
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
953
954 up->mcr = serial_in(up, UART_MCR);
955 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
956
957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
958 up->efr = serial_in(up, UART_EFR);
959 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
960
961 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
962 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
965 serial_out(up, UART_LCR, cval);
966 }
967
968 serial_omap_set_mctrl(&up->port, up->port.mctrl);
969 /* Software Flow Control Configuration */
970 serial_omap_configure_xonxoff(up, termios);
971
972 spin_unlock_irqrestore(&up->port.lock, flags);
973 pm_runtime_put(&up->pdev->dev);
974 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
975 }
976
977 static void
978 serial_omap_pm(struct uart_port *port, unsigned int state,
979 unsigned int oldstate)
980 {
981 struct uart_omap_port *up = to_uart_omap_port(port);
982 unsigned char efr;
983
984 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
985
986 pm_runtime_get_sync(&up->pdev->dev);
987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
988 efr = serial_in(up, UART_EFR);
989 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
990 serial_out(up, UART_LCR, 0);
991
992 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
994 serial_out(up, UART_EFR, efr);
995 serial_out(up, UART_LCR, 0);
996
997 if (!device_may_wakeup(&up->pdev->dev)) {
998 if (!state)
999 pm_runtime_forbid(&up->pdev->dev);
1000 else
1001 pm_runtime_allow(&up->pdev->dev);
1002 }
1003
1004 pm_runtime_put(&up->pdev->dev);
1005 }
1006
1007 static void serial_omap_release_port(struct uart_port *port)
1008 {
1009 dev_dbg(port->dev, "serial_omap_release_port+\n");
1010 }
1011
1012 static int serial_omap_request_port(struct uart_port *port)
1013 {
1014 dev_dbg(port->dev, "serial_omap_request_port+\n");
1015 return 0;
1016 }
1017
1018 static void serial_omap_config_port(struct uart_port *port, int flags)
1019 {
1020 struct uart_omap_port *up = to_uart_omap_port(port);
1021
1022 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1023 up->port.line);
1024 up->port.type = PORT_OMAP;
1025 }
1026
1027 static int
1028 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1029 {
1030 /* we don't want the core code to modify any port params */
1031 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1032 return -EINVAL;
1033 }
1034
1035 static const char *
1036 serial_omap_type(struct uart_port *port)
1037 {
1038 struct uart_omap_port *up = to_uart_omap_port(port);
1039
1040 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1041 return up->name;
1042 }
1043
1044 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1045
1046 static inline void wait_for_xmitr(struct uart_omap_port *up)
1047 {
1048 unsigned int status, tmout = 10000;
1049
1050 /* Wait up to 10ms for the character(s) to be sent. */
1051 do {
1052 status = serial_in(up, UART_LSR);
1053
1054 if (status & UART_LSR_BI)
1055 up->lsr_break_flag = UART_LSR_BI;
1056
1057 if (--tmout == 0)
1058 break;
1059 udelay(1);
1060 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1061
1062 /* Wait up to 1s for flow control if necessary */
1063 if (up->port.flags & UPF_CONS_FLOW) {
1064 tmout = 1000000;
1065 for (tmout = 1000000; tmout; tmout--) {
1066 unsigned int msr = serial_in(up, UART_MSR);
1067
1068 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1069 if (msr & UART_MSR_CTS)
1070 break;
1071
1072 udelay(1);
1073 }
1074 }
1075 }
1076
1077 #ifdef CONFIG_CONSOLE_POLL
1078
1079 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1080 {
1081 struct uart_omap_port *up = to_uart_omap_port(port);
1082
1083 pm_runtime_get_sync(&up->pdev->dev);
1084 wait_for_xmitr(up);
1085 serial_out(up, UART_TX, ch);
1086 pm_runtime_put(&up->pdev->dev);
1087 }
1088
1089 static int serial_omap_poll_get_char(struct uart_port *port)
1090 {
1091 struct uart_omap_port *up = to_uart_omap_port(port);
1092 unsigned int status;
1093
1094 pm_runtime_get_sync(&up->pdev->dev);
1095 status = serial_in(up, UART_LSR);
1096 if (!(status & UART_LSR_DR))
1097 return NO_POLL_CHAR;
1098
1099 status = serial_in(up, UART_RX);
1100 pm_runtime_put(&up->pdev->dev);
1101 return status;
1102 }
1103
1104 #endif /* CONFIG_CONSOLE_POLL */
1105
1106 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1107
1108 static struct uart_omap_port *serial_omap_console_ports[4];
1109
1110 static struct uart_driver serial_omap_reg;
1111
1112 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1113 {
1114 struct uart_omap_port *up = to_uart_omap_port(port);
1115
1116 wait_for_xmitr(up);
1117 serial_out(up, UART_TX, ch);
1118 }
1119
1120 static void
1121 serial_omap_console_write(struct console *co, const char *s,
1122 unsigned int count)
1123 {
1124 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1125 unsigned long flags;
1126 unsigned int ier;
1127 int locked = 1;
1128
1129 pm_runtime_get_sync(&up->pdev->dev);
1130
1131 local_irq_save(flags);
1132 if (up->port.sysrq)
1133 locked = 0;
1134 else if (oops_in_progress)
1135 locked = spin_trylock(&up->port.lock);
1136 else
1137 spin_lock(&up->port.lock);
1138
1139 /*
1140 * First save the IER then disable the interrupts
1141 */
1142 ier = serial_in(up, UART_IER);
1143 serial_out(up, UART_IER, 0);
1144
1145 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1146
1147 /*
1148 * Finally, wait for transmitter to become empty
1149 * and restore the IER
1150 */
1151 wait_for_xmitr(up);
1152 serial_out(up, UART_IER, ier);
1153 /*
1154 * The receive handling will happen properly because the
1155 * receive ready bit will still be set; it is not cleared
1156 * on read. However, modem control will not, we must
1157 * call it if we have saved something in the saved flags
1158 * while processing with interrupts off.
1159 */
1160 if (up->msr_saved_flags)
1161 check_modem_status(up);
1162
1163 pm_runtime_mark_last_busy(&up->pdev->dev);
1164 pm_runtime_put_autosuspend(&up->pdev->dev);
1165 if (locked)
1166 spin_unlock(&up->port.lock);
1167 local_irq_restore(flags);
1168 }
1169
1170 static int __init
1171 serial_omap_console_setup(struct console *co, char *options)
1172 {
1173 struct uart_omap_port *up;
1174 int baud = 115200;
1175 int bits = 8;
1176 int parity = 'n';
1177 int flow = 'n';
1178
1179 if (serial_omap_console_ports[co->index] == NULL)
1180 return -ENODEV;
1181 up = serial_omap_console_ports[co->index];
1182
1183 if (options)
1184 uart_parse_options(options, &baud, &parity, &bits, &flow);
1185
1186 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1187 }
1188
1189 static struct console serial_omap_console = {
1190 .name = OMAP_SERIAL_NAME,
1191 .write = serial_omap_console_write,
1192 .device = uart_console_device,
1193 .setup = serial_omap_console_setup,
1194 .flags = CON_PRINTBUFFER,
1195 .index = -1,
1196 .data = &serial_omap_reg,
1197 };
1198
1199 static void serial_omap_add_console_port(struct uart_omap_port *up)
1200 {
1201 serial_omap_console_ports[up->port.line] = up;
1202 }
1203
1204 #define OMAP_CONSOLE (&serial_omap_console)
1205
1206 #else
1207
1208 #define OMAP_CONSOLE NULL
1209
1210 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1211 {}
1212
1213 #endif
1214
1215 static struct uart_ops serial_omap_pops = {
1216 .tx_empty = serial_omap_tx_empty,
1217 .set_mctrl = serial_omap_set_mctrl,
1218 .get_mctrl = serial_omap_get_mctrl,
1219 .stop_tx = serial_omap_stop_tx,
1220 .start_tx = serial_omap_start_tx,
1221 .stop_rx = serial_omap_stop_rx,
1222 .enable_ms = serial_omap_enable_ms,
1223 .break_ctl = serial_omap_break_ctl,
1224 .startup = serial_omap_startup,
1225 .shutdown = serial_omap_shutdown,
1226 .set_termios = serial_omap_set_termios,
1227 .pm = serial_omap_pm,
1228 .type = serial_omap_type,
1229 .release_port = serial_omap_release_port,
1230 .request_port = serial_omap_request_port,
1231 .config_port = serial_omap_config_port,
1232 .verify_port = serial_omap_verify_port,
1233 #ifdef CONFIG_CONSOLE_POLL
1234 .poll_put_char = serial_omap_poll_put_char,
1235 .poll_get_char = serial_omap_poll_get_char,
1236 #endif
1237 };
1238
1239 static struct uart_driver serial_omap_reg = {
1240 .owner = THIS_MODULE,
1241 .driver_name = "OMAP-SERIAL",
1242 .dev_name = OMAP_SERIAL_NAME,
1243 .nr = OMAP_MAX_HSUART_PORTS,
1244 .cons = OMAP_CONSOLE,
1245 };
1246
1247 #ifdef CONFIG_PM_SLEEP
1248 static int serial_omap_suspend(struct device *dev)
1249 {
1250 struct uart_omap_port *up = dev_get_drvdata(dev);
1251
1252 if (up) {
1253 uart_suspend_port(&serial_omap_reg, &up->port);
1254 flush_work_sync(&up->qos_work);
1255 }
1256
1257 return 0;
1258 }
1259
1260 static int serial_omap_resume(struct device *dev)
1261 {
1262 struct uart_omap_port *up = dev_get_drvdata(dev);
1263
1264 if (up)
1265 uart_resume_port(&serial_omap_reg, &up->port);
1266 return 0;
1267 }
1268 #endif
1269
1270 static void serial_omap_rxdma_poll(unsigned long uart_no)
1271 {
1272 struct uart_omap_port *up = ui[uart_no];
1273 unsigned int curr_dma_pos, curr_transmitted_size;
1274 int ret = 0;
1275
1276 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1277 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1278 (curr_dma_pos == 0)) {
1279 if (jiffies_to_msecs(jiffies - up->port_activity) <
1280 up->uart_dma.rx_timeout) {
1281 mod_timer(&up->uart_dma.rx_timer, jiffies +
1282 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1283 } else {
1284 serial_omap_stop_rxdma(up);
1285 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1286 serial_out(up, UART_IER, up->ier);
1287 }
1288 return;
1289 }
1290
1291 curr_transmitted_size = curr_dma_pos -
1292 up->uart_dma.prev_rx_dma_pos;
1293 up->port.icount.rx += curr_transmitted_size;
1294 tty_insert_flip_string(up->port.state->port.tty,
1295 up->uart_dma.rx_buf +
1296 (up->uart_dma.prev_rx_dma_pos -
1297 up->uart_dma.rx_buf_dma_phys),
1298 curr_transmitted_size);
1299 tty_flip_buffer_push(up->port.state->port.tty);
1300 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1301 if (up->uart_dma.rx_buf_size +
1302 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1303 ret = serial_omap_start_rxdma(up);
1304 if (ret < 0) {
1305 serial_omap_stop_rxdma(up);
1306 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1307 serial_out(up, UART_IER, up->ier);
1308 }
1309 } else {
1310 mod_timer(&up->uart_dma.rx_timer, jiffies +
1311 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1312 }
1313 up->port_activity = jiffies;
1314 }
1315
1316 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1317 {
1318 return;
1319 }
1320
1321 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1322 {
1323 int ret = 0;
1324
1325 if (up->uart_dma.rx_dma_channel == -1) {
1326 pm_runtime_get_sync(&up->pdev->dev);
1327 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1328 "UART Rx DMA",
1329 (void *)uart_rx_dma_callback, up,
1330 &(up->uart_dma.rx_dma_channel));
1331 if (ret < 0)
1332 return ret;
1333
1334 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1335 OMAP_DMA_AMODE_CONSTANT,
1336 up->uart_dma.uart_base, 0, 0);
1337 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1338 OMAP_DMA_AMODE_POST_INC,
1339 up->uart_dma.rx_buf_dma_phys, 0, 0);
1340 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1341 OMAP_DMA_DATA_TYPE_S8,
1342 up->uart_dma.rx_buf_size, 1,
1343 OMAP_DMA_SYNC_ELEMENT,
1344 up->uart_dma.uart_dma_rx, 0);
1345 }
1346 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1347 /* FIXME: Cache maintenance needed here? */
1348 omap_start_dma(up->uart_dma.rx_dma_channel);
1349 mod_timer(&up->uart_dma.rx_timer, jiffies +
1350 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1351 up->uart_dma.rx_dma_used = true;
1352 return ret;
1353 }
1354
1355 static void serial_omap_continue_tx(struct uart_omap_port *up)
1356 {
1357 struct circ_buf *xmit = &up->port.state->xmit;
1358 unsigned int start = up->uart_dma.tx_buf_dma_phys
1359 + (xmit->tail & (UART_XMIT_SIZE - 1));
1360
1361 if (uart_circ_empty(xmit))
1362 return;
1363
1364 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1365 /*
1366 * It is a circular buffer. See if the buffer has wounded back.
1367 * If yes it will have to be transferred in two separate dma
1368 * transfers
1369 */
1370 if (start + up->uart_dma.tx_buf_size >=
1371 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1372 up->uart_dma.tx_buf_size =
1373 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1374 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1375 OMAP_DMA_AMODE_CONSTANT,
1376 up->uart_dma.uart_base, 0, 0);
1377 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1378 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1379 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1380 OMAP_DMA_DATA_TYPE_S8,
1381 up->uart_dma.tx_buf_size, 1,
1382 OMAP_DMA_SYNC_ELEMENT,
1383 up->uart_dma.uart_dma_tx, 0);
1384 /* FIXME: Cache maintenance needed here? */
1385 omap_start_dma(up->uart_dma.tx_dma_channel);
1386 }
1387
1388 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1389 {
1390 struct uart_omap_port *up = data;
1391 struct circ_buf *xmit = &up->port.state->xmit;
1392
1393 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1394 (UART_XMIT_SIZE - 1);
1395 up->port.icount.tx += up->uart_dma.tx_buf_size;
1396
1397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1398 uart_write_wakeup(&up->port);
1399
1400 if (uart_circ_empty(xmit)) {
1401 spin_lock(&(up->uart_dma.tx_lock));
1402 serial_omap_stop_tx(&up->port);
1403 up->uart_dma.tx_dma_used = false;
1404 spin_unlock(&(up->uart_dma.tx_lock));
1405 } else {
1406 omap_stop_dma(up->uart_dma.tx_dma_channel);
1407 serial_omap_continue_tx(up);
1408 }
1409 up->port_activity = jiffies;
1410 return;
1411 }
1412
1413 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1414 {
1415 u32 mvr, scheme;
1416 u16 revision, major, minor;
1417
1418 mvr = serial_in(up, UART_OMAP_MVER);
1419
1420 /* Check revision register scheme */
1421 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1422
1423 switch (scheme) {
1424 case 0: /* Legacy Scheme: OMAP2/3 */
1425 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1426 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1427 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1428 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1429 break;
1430 case 1:
1431 /* New Scheme: OMAP4+ */
1432 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1433 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1434 OMAP_UART_MVR_MAJ_SHIFT;
1435 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1436 break;
1437 default:
1438 dev_warn(&up->pdev->dev,
1439 "Unknown %s revision, defaulting to highest\n",
1440 up->name);
1441 /* highest possible revision */
1442 major = 0xff;
1443 minor = 0xff;
1444 }
1445
1446 /* normalize revision for the driver */
1447 revision = UART_BUILD_REVISION(major, minor);
1448
1449 switch (revision) {
1450 case OMAP_UART_REV_46:
1451 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1452 UART_ERRATA_i291_DMA_FORCEIDLE);
1453 break;
1454 case OMAP_UART_REV_52:
1455 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1456 UART_ERRATA_i291_DMA_FORCEIDLE);
1457 break;
1458 case OMAP_UART_REV_63:
1459 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1460 break;
1461 default:
1462 break;
1463 }
1464 }
1465
1466 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1467 {
1468 struct omap_uart_port_info *omap_up_info;
1469
1470 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1471 if (!omap_up_info)
1472 return NULL; /* out of memory */
1473
1474 of_property_read_u32(dev->of_node, "clock-frequency",
1475 &omap_up_info->uartclk);
1476 return omap_up_info;
1477 }
1478
1479 static int serial_omap_probe(struct platform_device *pdev)
1480 {
1481 struct uart_omap_port *up;
1482 struct resource *mem, *irq, *dma_tx, *dma_rx;
1483 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1484 int ret;
1485
1486 if (pdev->dev.of_node)
1487 omap_up_info = of_get_uart_port_info(&pdev->dev);
1488
1489 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1490 if (!mem) {
1491 dev_err(&pdev->dev, "no mem resource?\n");
1492 return -ENODEV;
1493 }
1494
1495 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1496 if (!irq) {
1497 dev_err(&pdev->dev, "no irq resource?\n");
1498 return -ENODEV;
1499 }
1500
1501 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1502 pdev->dev.driver->name)) {
1503 dev_err(&pdev->dev, "memory region already claimed\n");
1504 return -EBUSY;
1505 }
1506
1507 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1508 if (!dma_rx)
1509 return -ENXIO;
1510
1511 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1512 if (!dma_tx)
1513 return -ENXIO;
1514
1515 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1516 omap_up_info->DTR_present) {
1517 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1518 if (ret < 0)
1519 return ret;
1520 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1521 omap_up_info->DTR_inverted);
1522 if (ret < 0)
1523 return ret;
1524 }
1525
1526 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1527 if (!up)
1528 return -ENOMEM;
1529
1530 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1531 omap_up_info->DTR_present) {
1532 up->DTR_gpio = omap_up_info->DTR_gpio;
1533 up->DTR_inverted = omap_up_info->DTR_inverted;
1534 } else
1535 up->DTR_gpio = -EINVAL;
1536 up->DTR_active = 0;
1537
1538 up->pdev = pdev;
1539 up->port.dev = &pdev->dev;
1540 up->port.type = PORT_OMAP;
1541 up->port.iotype = UPIO_MEM;
1542 up->port.irq = irq->start;
1543
1544 up->port.regshift = 2;
1545 up->port.fifosize = 64;
1546 up->port.ops = &serial_omap_pops;
1547
1548 if (pdev->dev.of_node)
1549 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1550 else
1551 up->port.line = pdev->id;
1552
1553 if (up->port.line < 0) {
1554 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1555 up->port.line);
1556 ret = -ENODEV;
1557 goto err_port_line;
1558 }
1559
1560 sprintf(up->name, "OMAP UART%d", up->port.line);
1561 up->port.mapbase = mem->start;
1562 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1563 resource_size(mem));
1564 if (!up->port.membase) {
1565 dev_err(&pdev->dev, "can't ioremap UART\n");
1566 ret = -ENOMEM;
1567 goto err_ioremap;
1568 }
1569
1570 up->port.flags = omap_up_info->flags;
1571 up->port.uartclk = omap_up_info->uartclk;
1572 if (!up->port.uartclk) {
1573 up->port.uartclk = DEFAULT_CLK_SPEED;
1574 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1575 "%d\n", DEFAULT_CLK_SPEED);
1576 }
1577 up->uart_dma.uart_base = mem->start;
1578
1579 if (omap_up_info->dma_enabled) {
1580 up->uart_dma.uart_dma_tx = dma_tx->start;
1581 up->uart_dma.uart_dma_rx = dma_rx->start;
1582 up->use_dma = 1;
1583 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1584 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1585 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1586 spin_lock_init(&(up->uart_dma.tx_lock));
1587 spin_lock_init(&(up->uart_dma.rx_lock));
1588 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1589 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1590 }
1591
1592 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1593 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1594 pm_qos_add_request(&up->pm_qos_request,
1595 PM_QOS_CPU_DMA_LATENCY, up->latency);
1596 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1597 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1598
1599 pm_runtime_use_autosuspend(&pdev->dev);
1600 pm_runtime_set_autosuspend_delay(&pdev->dev,
1601 omap_up_info->autosuspend_timeout);
1602
1603 pm_runtime_irq_safe(&pdev->dev);
1604 pm_runtime_enable(&pdev->dev);
1605 pm_runtime_get_sync(&pdev->dev);
1606
1607 omap_serial_fill_features_erratas(up);
1608
1609 ui[up->port.line] = up;
1610 serial_omap_add_console_port(up);
1611
1612 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1613 if (ret != 0)
1614 goto err_add_port;
1615
1616 pm_runtime_put(&pdev->dev);
1617 platform_set_drvdata(pdev, up);
1618 return 0;
1619
1620 err_add_port:
1621 pm_runtime_put(&pdev->dev);
1622 pm_runtime_disable(&pdev->dev);
1623 err_ioremap:
1624 err_port_line:
1625 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1626 pdev->id, __func__, ret);
1627 return ret;
1628 }
1629
1630 static int serial_omap_remove(struct platform_device *dev)
1631 {
1632 struct uart_omap_port *up = platform_get_drvdata(dev);
1633
1634 if (up) {
1635 pm_runtime_disable(&up->pdev->dev);
1636 uart_remove_one_port(&serial_omap_reg, &up->port);
1637 pm_qos_remove_request(&up->pm_qos_request);
1638 }
1639
1640 platform_set_drvdata(dev, NULL);
1641 return 0;
1642 }
1643
1644 /*
1645 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1646 * The access to uart register after MDR1 Access
1647 * causes UART to corrupt data.
1648 *
1649 * Need a delay =
1650 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1651 * give 10 times as much
1652 */
1653 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1654 {
1655 u8 timeout = 255;
1656
1657 serial_out(up, UART_OMAP_MDR1, mdr1);
1658 udelay(2);
1659 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1660 UART_FCR_CLEAR_RCVR);
1661 /*
1662 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1663 * TX_FIFO_E bit is 1.
1664 */
1665 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1666 (UART_LSR_THRE | UART_LSR_DR))) {
1667 timeout--;
1668 if (!timeout) {
1669 /* Should *never* happen. we warn and carry on */
1670 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1671 serial_in(up, UART_LSR));
1672 break;
1673 }
1674 udelay(1);
1675 }
1676 }
1677
1678 #ifdef CONFIG_PM_RUNTIME
1679 static void serial_omap_restore_context(struct uart_omap_port *up)
1680 {
1681 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1682 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1683 else
1684 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1685
1686 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1687 serial_out(up, UART_EFR, UART_EFR_ECB);
1688 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1689 serial_out(up, UART_IER, 0x0);
1690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1691 serial_out(up, UART_DLL, up->dll);
1692 serial_out(up, UART_DLM, up->dlh);
1693 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1694 serial_out(up, UART_IER, up->ier);
1695 serial_out(up, UART_FCR, up->fcr);
1696 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1697 serial_out(up, UART_MCR, up->mcr);
1698 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1699 serial_out(up, UART_OMAP_SCR, up->scr);
1700 serial_out(up, UART_EFR, up->efr);
1701 serial_out(up, UART_LCR, up->lcr);
1702 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1703 serial_omap_mdr1_errataset(up, up->mdr1);
1704 else
1705 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1706 }
1707
1708 static int serial_omap_runtime_suspend(struct device *dev)
1709 {
1710 struct uart_omap_port *up = dev_get_drvdata(dev);
1711 struct omap_uart_port_info *pdata = dev->platform_data;
1712
1713 if (!up)
1714 return -EINVAL;
1715
1716 if (!pdata)
1717 return 0;
1718
1719 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1720
1721 if (device_may_wakeup(dev)) {
1722 if (!up->wakeups_enabled) {
1723 serial_omap_enable_wakeup(up, true);
1724 up->wakeups_enabled = true;
1725 }
1726 } else {
1727 if (up->wakeups_enabled) {
1728 serial_omap_enable_wakeup(up, false);
1729 up->wakeups_enabled = false;
1730 }
1731 }
1732
1733 /* Errata i291 */
1734 if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1735 serial_omap_set_forceidle(up);
1736
1737 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1738 schedule_work(&up->qos_work);
1739
1740 return 0;
1741 }
1742
1743 static int serial_omap_runtime_resume(struct device *dev)
1744 {
1745 struct uart_omap_port *up = dev_get_drvdata(dev);
1746 struct omap_uart_port_info *pdata = dev->platform_data;
1747
1748 if (up && pdata) {
1749 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1750
1751 if (up->context_loss_cnt != loss_cnt)
1752 serial_omap_restore_context(up);
1753
1754 /* Errata i291 */
1755 if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
1756 up->use_dma)
1757 serial_omap_set_noidle(up);
1758
1759 up->latency = up->calc_latency;
1760 schedule_work(&up->qos_work);
1761 }
1762
1763 return 0;
1764 }
1765 #endif
1766
1767 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1768 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1769 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1770 serial_omap_runtime_resume, NULL)
1771 };
1772
1773 #if defined(CONFIG_OF)
1774 static const struct of_device_id omap_serial_of_match[] = {
1775 { .compatible = "ti,omap2-uart" },
1776 { .compatible = "ti,omap3-uart" },
1777 { .compatible = "ti,omap4-uart" },
1778 {},
1779 };
1780 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1781 #endif
1782
1783 static struct platform_driver serial_omap_driver = {
1784 .probe = serial_omap_probe,
1785 .remove = serial_omap_remove,
1786 .driver = {
1787 .name = DRIVER_NAME,
1788 .pm = &serial_omap_dev_pm_ops,
1789 .of_match_table = of_match_ptr(omap_serial_of_match),
1790 },
1791 };
1792
1793 static int __init serial_omap_init(void)
1794 {
1795 int ret;
1796
1797 ret = uart_register_driver(&serial_omap_reg);
1798 if (ret != 0)
1799 return ret;
1800 ret = platform_driver_register(&serial_omap_driver);
1801 if (ret != 0)
1802 uart_unregister_driver(&serial_omap_reg);
1803 return ret;
1804 }
1805
1806 static void __exit serial_omap_exit(void)
1807 {
1808 platform_driver_unregister(&serial_omap_driver);
1809 uart_unregister_driver(&serial_omap_reg);
1810 }
1811
1812 module_init(serial_omap_init);
1813 module_exit(serial_omap_exit);
1814
1815 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1816 MODULE_LICENSE("GPL");
1817 MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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