2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/clk.h>
37 #include <linux/serial_core.h>
38 #include <linux/irq.h>
39 #include <linux/pm_runtime.h>
41 #include <linux/gpio.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
46 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
48 #define OMAP_UART_REV_42 0x0402
49 #define OMAP_UART_REV_46 0x0406
50 #define OMAP_UART_REV_52 0x0502
51 #define OMAP_UART_REV_63 0x0603
53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
55 /* SCR register bitmasks */
56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
58 /* FCR register bitmasks */
59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
62 /* MVR register bitmasks */
63 #define OMAP_UART_MVR_SCHEME_SHIFT 30
65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
69 #define OMAP_UART_MVR_MAJ_MASK 0x700
70 #define OMAP_UART_MVR_MAJ_SHIFT 8
71 #define OMAP_UART_MVR_MIN_MASK 0x3f
73 static struct uart_omap_port
*ui
[OMAP_MAX_HSUART_PORTS
];
75 /* Forward declaration of functions */
76 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
);
78 static struct workqueue_struct
*serial_omap_uart_wq
;
80 static inline unsigned int serial_in(struct uart_omap_port
*up
, int offset
)
82 offset
<<= up
->port
.regshift
;
83 return readw(up
->port
.membase
+ offset
);
86 static inline void serial_out(struct uart_omap_port
*up
, int offset
, int value
)
88 offset
<<= up
->port
.regshift
;
89 writew(value
, up
->port
.membase
+ offset
);
92 static inline void serial_omap_clear_fifos(struct uart_omap_port
*up
)
94 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
95 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
96 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
97 serial_out(up
, UART_FCR
, 0);
100 static int serial_omap_get_context_loss_count(struct uart_omap_port
*up
)
102 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
104 if (!pdata
->get_context_loss_count
)
107 return pdata
->get_context_loss_count(up
->dev
);
110 static void serial_omap_set_forceidle(struct uart_omap_port
*up
)
112 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
114 if (pdata
->set_forceidle
)
115 pdata
->set_forceidle(up
->dev
);
118 static void serial_omap_set_noidle(struct uart_omap_port
*up
)
120 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
122 if (pdata
->set_noidle
)
123 pdata
->set_noidle(up
->dev
);
126 static void serial_omap_enable_wakeup(struct uart_omap_port
*up
, bool enable
)
128 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
130 if (pdata
->enable_wakeup
)
131 pdata
->enable_wakeup(up
->dev
, enable
);
135 * serial_omap_get_divisor - calculate divisor value
136 * @port: uart port info
137 * @baud: baudrate for which divisor needs to be calculated.
139 * We have written our own function to get the divisor so as to support
140 * 13x mode. 3Mbps Baudrate as an different divisor.
141 * Reference OMAP TRM Chapter 17:
142 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
143 * referring to oversampling - divisor value
144 * baudrate 460,800 to 3,686,400 all have divisor 13
145 * except 3,000,000 which has divisor value 16
148 serial_omap_get_divisor(struct uart_port
*port
, unsigned int baud
)
150 unsigned int divisor
;
152 if (baud
> OMAP_MODE13X_SPEED
&& baud
!= 3000000)
156 return port
->uartclk
/(baud
* divisor
);
159 static void serial_omap_enable_ms(struct uart_port
*port
)
161 struct uart_omap_port
*up
= to_uart_omap_port(port
);
163 dev_dbg(up
->port
.dev
, "serial_omap_enable_ms+%d\n", up
->port
.line
);
165 pm_runtime_get_sync(up
->dev
);
166 up
->ier
|= UART_IER_MSI
;
167 serial_out(up
, UART_IER
, up
->ier
);
168 pm_runtime_mark_last_busy(up
->dev
);
169 pm_runtime_put_autosuspend(up
->dev
);
172 static void serial_omap_stop_tx(struct uart_port
*port
)
174 struct uart_omap_port
*up
= to_uart_omap_port(port
);
176 pm_runtime_get_sync(up
->dev
);
177 if (up
->ier
& UART_IER_THRI
) {
178 up
->ier
&= ~UART_IER_THRI
;
179 serial_out(up
, UART_IER
, up
->ier
);
182 serial_omap_set_forceidle(up
);
184 pm_runtime_mark_last_busy(up
->dev
);
185 pm_runtime_put_autosuspend(up
->dev
);
188 static void serial_omap_stop_rx(struct uart_port
*port
)
190 struct uart_omap_port
*up
= to_uart_omap_port(port
);
192 pm_runtime_get_sync(up
->dev
);
193 up
->ier
&= ~UART_IER_RLSI
;
194 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
195 serial_out(up
, UART_IER
, up
->ier
);
196 pm_runtime_mark_last_busy(up
->dev
);
197 pm_runtime_put_autosuspend(up
->dev
);
200 static void transmit_chars(struct uart_omap_port
*up
, unsigned int lsr
)
202 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
205 if (!(lsr
& UART_LSR_THRE
))
208 if (up
->port
.x_char
) {
209 serial_out(up
, UART_TX
, up
->port
.x_char
);
210 up
->port
.icount
.tx
++;
214 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
215 serial_omap_stop_tx(&up
->port
);
218 count
= up
->port
.fifosize
/ 4;
220 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
221 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
222 up
->port
.icount
.tx
++;
223 if (uart_circ_empty(xmit
))
225 } while (--count
> 0);
227 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
228 uart_write_wakeup(&up
->port
);
230 if (uart_circ_empty(xmit
))
231 serial_omap_stop_tx(&up
->port
);
234 static inline void serial_omap_enable_ier_thri(struct uart_omap_port
*up
)
236 if (!(up
->ier
& UART_IER_THRI
)) {
237 up
->ier
|= UART_IER_THRI
;
238 serial_out(up
, UART_IER
, up
->ier
);
242 static void serial_omap_start_tx(struct uart_port
*port
)
244 struct uart_omap_port
*up
= to_uart_omap_port(port
);
246 pm_runtime_get_sync(up
->dev
);
247 serial_omap_enable_ier_thri(up
);
248 serial_omap_set_noidle(up
);
249 pm_runtime_mark_last_busy(up
->dev
);
250 pm_runtime_put_autosuspend(up
->dev
);
253 static unsigned int check_modem_status(struct uart_omap_port
*up
)
257 status
= serial_in(up
, UART_MSR
);
258 status
|= up
->msr_saved_flags
;
259 up
->msr_saved_flags
= 0;
260 if ((status
& UART_MSR_ANY_DELTA
) == 0)
263 if (status
& UART_MSR_ANY_DELTA
&& up
->ier
& UART_IER_MSI
&&
264 up
->port
.state
!= NULL
) {
265 if (status
& UART_MSR_TERI
)
266 up
->port
.icount
.rng
++;
267 if (status
& UART_MSR_DDSR
)
268 up
->port
.icount
.dsr
++;
269 if (status
& UART_MSR_DDCD
)
270 uart_handle_dcd_change
271 (&up
->port
, status
& UART_MSR_DCD
);
272 if (status
& UART_MSR_DCTS
)
273 uart_handle_cts_change
274 (&up
->port
, status
& UART_MSR_CTS
);
275 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
281 static void serial_omap_rlsi(struct uart_omap_port
*up
, unsigned int lsr
)
285 up
->port
.icount
.rx
++;
288 if (lsr
& UART_LSR_BI
) {
290 lsr
&= ~(UART_LSR_FE
| UART_LSR_PE
);
291 up
->port
.icount
.brk
++;
293 * We do the SysRQ and SAK checking
294 * here because otherwise the break
295 * may get masked by ignore_status_mask
296 * or read_status_mask.
298 if (uart_handle_break(&up
->port
))
303 if (lsr
& UART_LSR_PE
) {
305 up
->port
.icount
.parity
++;
308 if (lsr
& UART_LSR_FE
) {
310 up
->port
.icount
.frame
++;
313 if (lsr
& UART_LSR_OE
)
314 up
->port
.icount
.overrun
++;
316 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
317 if (up
->port
.line
== up
->port
.cons
->index
) {
318 /* Recover the break flag from console xmit */
319 lsr
|= up
->lsr_break_flag
;
322 uart_insert_char(&up
->port
, lsr
, UART_LSR_OE
, 0, flag
);
325 static void serial_omap_rdi(struct uart_omap_port
*up
, unsigned int lsr
)
327 unsigned char ch
= 0;
330 if (!(lsr
& UART_LSR_DR
))
333 ch
= serial_in(up
, UART_RX
);
335 up
->port
.icount
.rx
++;
337 if (uart_handle_sysrq_char(&up
->port
, ch
))
340 uart_insert_char(&up
->port
, lsr
, UART_LSR_OE
, ch
, flag
);
344 * serial_omap_irq() - This handles the interrupt from one port
345 * @irq: uart port irq number
346 * @dev_id: uart port info
348 static inline irqreturn_t
serial_omap_irq(int irq
, void *dev_id
)
350 struct uart_omap_port
*up
= dev_id
;
351 struct tty_struct
*tty
= up
->port
.state
->port
.tty
;
352 unsigned int iir
, lsr
;
354 irqreturn_t ret
= IRQ_NONE
;
357 spin_lock(&up
->port
.lock
);
358 pm_runtime_get_sync(up
->dev
);
361 iir
= serial_in(up
, UART_IIR
);
362 if (iir
& UART_IIR_NO_INT
)
366 lsr
= serial_in(up
, UART_LSR
);
368 /* extract IRQ type from IIR register */
373 check_modem_status(up
);
376 transmit_chars(up
, lsr
);
378 case UART_IIR_RX_TIMEOUT
:
381 serial_omap_rdi(up
, lsr
);
384 serial_omap_rlsi(up
, lsr
);
386 case UART_IIR_CTS_RTS_DSR
:
387 /* simply try again */
394 } while (!(iir
& UART_IIR_NO_INT
) && max_count
--);
396 spin_unlock(&up
->port
.lock
);
398 tty_flip_buffer_push(tty
);
400 pm_runtime_mark_last_busy(up
->dev
);
401 pm_runtime_put_autosuspend(up
->dev
);
402 up
->port_activity
= jiffies
;
407 static unsigned int serial_omap_tx_empty(struct uart_port
*port
)
409 struct uart_omap_port
*up
= to_uart_omap_port(port
);
410 unsigned long flags
= 0;
411 unsigned int ret
= 0;
413 pm_runtime_get_sync(up
->dev
);
414 dev_dbg(up
->port
.dev
, "serial_omap_tx_empty+%d\n", up
->port
.line
);
415 spin_lock_irqsave(&up
->port
.lock
, flags
);
416 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
417 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
418 pm_runtime_mark_last_busy(up
->dev
);
419 pm_runtime_put_autosuspend(up
->dev
);
423 static unsigned int serial_omap_get_mctrl(struct uart_port
*port
)
425 struct uart_omap_port
*up
= to_uart_omap_port(port
);
427 unsigned int ret
= 0;
429 pm_runtime_get_sync(up
->dev
);
430 status
= check_modem_status(up
);
431 pm_runtime_mark_last_busy(up
->dev
);
432 pm_runtime_put_autosuspend(up
->dev
);
434 dev_dbg(up
->port
.dev
, "serial_omap_get_mctrl+%d\n", up
->port
.line
);
436 if (status
& UART_MSR_DCD
)
438 if (status
& UART_MSR_RI
)
440 if (status
& UART_MSR_DSR
)
442 if (status
& UART_MSR_CTS
)
447 static void serial_omap_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
449 struct uart_omap_port
*up
= to_uart_omap_port(port
);
450 unsigned char mcr
= 0;
452 dev_dbg(up
->port
.dev
, "serial_omap_set_mctrl+%d\n", up
->port
.line
);
453 if (mctrl
& TIOCM_RTS
)
455 if (mctrl
& TIOCM_DTR
)
457 if (mctrl
& TIOCM_OUT1
)
458 mcr
|= UART_MCR_OUT1
;
459 if (mctrl
& TIOCM_OUT2
)
460 mcr
|= UART_MCR_OUT2
;
461 if (mctrl
& TIOCM_LOOP
)
462 mcr
|= UART_MCR_LOOP
;
464 pm_runtime_get_sync(up
->dev
);
465 up
->mcr
= serial_in(up
, UART_MCR
);
467 serial_out(up
, UART_MCR
, up
->mcr
);
468 pm_runtime_mark_last_busy(up
->dev
);
469 pm_runtime_put_autosuspend(up
->dev
);
471 if (gpio_is_valid(up
->DTR_gpio
) &&
472 !!(mctrl
& TIOCM_DTR
) != up
->DTR_active
) {
473 up
->DTR_active
= !up
->DTR_active
;
474 if (gpio_cansleep(up
->DTR_gpio
))
475 schedule_work(&up
->qos_work
);
477 gpio_set_value(up
->DTR_gpio
,
478 up
->DTR_active
!= up
->DTR_inverted
);
482 static void serial_omap_break_ctl(struct uart_port
*port
, int break_state
)
484 struct uart_omap_port
*up
= to_uart_omap_port(port
);
485 unsigned long flags
= 0;
487 dev_dbg(up
->port
.dev
, "serial_omap_break_ctl+%d\n", up
->port
.line
);
488 pm_runtime_get_sync(up
->dev
);
489 spin_lock_irqsave(&up
->port
.lock
, flags
);
490 if (break_state
== -1)
491 up
->lcr
|= UART_LCR_SBC
;
493 up
->lcr
&= ~UART_LCR_SBC
;
494 serial_out(up
, UART_LCR
, up
->lcr
);
495 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
496 pm_runtime_mark_last_busy(up
->dev
);
497 pm_runtime_put_autosuspend(up
->dev
);
500 static int serial_omap_startup(struct uart_port
*port
)
502 struct uart_omap_port
*up
= to_uart_omap_port(port
);
503 unsigned long flags
= 0;
509 retval
= request_irq(up
->port
.irq
, serial_omap_irq
, up
->port
.irqflags
,
514 dev_dbg(up
->port
.dev
, "serial_omap_startup+%d\n", up
->port
.line
);
516 pm_runtime_get_sync(up
->dev
);
518 * Clear the FIFO buffers and disable them.
519 * (they will be reenabled in set_termios())
521 serial_omap_clear_fifos(up
);
522 /* For Hardware flow control */
523 serial_out(up
, UART_MCR
, UART_MCR_RTS
);
526 * Clear the interrupt registers.
528 (void) serial_in(up
, UART_LSR
);
529 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
530 (void) serial_in(up
, UART_RX
);
531 (void) serial_in(up
, UART_IIR
);
532 (void) serial_in(up
, UART_MSR
);
535 * Now, initialize the UART
537 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
538 spin_lock_irqsave(&up
->port
.lock
, flags
);
540 * Most PC uarts need OUT2 raised to enable interrupts.
542 up
->port
.mctrl
|= TIOCM_OUT2
;
543 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
544 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
546 up
->msr_saved_flags
= 0;
548 * Finally, enable interrupts. Note: Modem status interrupts
549 * are set via set_termios(), which will be occurring imminently
550 * anyway, so we don't enable them here.
552 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
;
553 serial_out(up
, UART_IER
, up
->ier
);
555 /* Enable module level wake up */
556 serial_out(up
, UART_OMAP_WER
, OMAP_UART_WER_MOD_WKUP
);
558 pm_runtime_mark_last_busy(up
->dev
);
559 pm_runtime_put_autosuspend(up
->dev
);
560 up
->port_activity
= jiffies
;
564 static void serial_omap_shutdown(struct uart_port
*port
)
566 struct uart_omap_port
*up
= to_uart_omap_port(port
);
567 unsigned long flags
= 0;
569 dev_dbg(up
->port
.dev
, "serial_omap_shutdown+%d\n", up
->port
.line
);
571 pm_runtime_get_sync(up
->dev
);
573 * Disable interrupts from this port
576 serial_out(up
, UART_IER
, 0);
578 spin_lock_irqsave(&up
->port
.lock
, flags
);
579 up
->port
.mctrl
&= ~TIOCM_OUT2
;
580 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
581 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
584 * Disable break condition and FIFOs
586 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
587 serial_omap_clear_fifos(up
);
590 * Read data port to reset things, and then free the irq
592 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
593 (void) serial_in(up
, UART_RX
);
595 pm_runtime_mark_last_busy(up
->dev
);
596 pm_runtime_put_autosuspend(up
->dev
);
597 free_irq(up
->port
.irq
, up
);
601 serial_omap_configure_xonxoff
602 (struct uart_omap_port
*up
, struct ktermios
*termios
)
604 up
->lcr
= serial_in(up
, UART_LCR
);
605 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
606 up
->efr
= serial_in(up
, UART_EFR
);
607 serial_out(up
, UART_EFR
, up
->efr
& ~UART_EFR_ECB
);
609 serial_out(up
, UART_XON1
, termios
->c_cc
[VSTART
]);
610 serial_out(up
, UART_XOFF1
, termios
->c_cc
[VSTOP
]);
612 /* clear SW control mode bits */
613 up
->efr
&= OMAP_UART_SW_CLR
;
617 * Enable XON/XOFF flow control on output.
618 * Transmit XON1, XOFF1
620 if (termios
->c_iflag
& IXON
)
621 up
->efr
|= OMAP_UART_SW_TX
;
625 * Enable XON/XOFF flow control on input.
626 * Receiver compares XON1, XOFF1.
628 if (termios
->c_iflag
& IXOFF
)
629 up
->efr
|= OMAP_UART_SW_RX
;
631 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
632 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
634 up
->mcr
= serial_in(up
, UART_MCR
);
638 * Enable any character to restart output.
639 * Operation resumes after receiving any
640 * character after recognition of the XOFF character
642 if (termios
->c_iflag
& IXANY
)
643 up
->mcr
|= UART_MCR_XONANY
;
645 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
646 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
647 serial_out(up
, UART_TI752_TCR
, OMAP_UART_TCR_TRIG
);
648 /* Enable special char function UARTi.EFR_REG[5] and
649 * load the new software flow control mode IXON or IXOFF
650 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
652 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_SCD
);
653 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
655 serial_out(up
, UART_MCR
, up
->mcr
& ~UART_MCR_TCRTLR
);
656 serial_out(up
, UART_LCR
, up
->lcr
);
659 static void serial_omap_uart_qos_work(struct work_struct
*work
)
661 struct uart_omap_port
*up
= container_of(work
, struct uart_omap_port
,
664 pm_qos_update_request(&up
->pm_qos_request
, up
->latency
);
665 if (gpio_is_valid(up
->DTR_gpio
))
666 gpio_set_value_cansleep(up
->DTR_gpio
,
667 up
->DTR_active
!= up
->DTR_inverted
);
671 serial_omap_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
672 struct ktermios
*old
)
674 struct uart_omap_port
*up
= to_uart_omap_port(port
);
675 unsigned char cval
= 0;
676 unsigned char efr
= 0;
677 unsigned long flags
= 0;
678 unsigned int baud
, quot
;
680 switch (termios
->c_cflag
& CSIZE
) {
682 cval
= UART_LCR_WLEN5
;
685 cval
= UART_LCR_WLEN6
;
688 cval
= UART_LCR_WLEN7
;
692 cval
= UART_LCR_WLEN8
;
696 if (termios
->c_cflag
& CSTOPB
)
697 cval
|= UART_LCR_STOP
;
698 if (termios
->c_cflag
& PARENB
)
699 cval
|= UART_LCR_PARITY
;
700 if (!(termios
->c_cflag
& PARODD
))
701 cval
|= UART_LCR_EPAR
;
704 * Ask the core to calculate the divisor for us.
707 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/13);
708 quot
= serial_omap_get_divisor(port
, baud
);
710 /* calculate wakeup latency constraint */
711 up
->calc_latency
= (USEC_PER_SEC
* up
->port
.fifosize
) / (baud
/ 8);
712 up
->latency
= up
->calc_latency
;
713 schedule_work(&up
->qos_work
);
715 up
->dll
= quot
& 0xff;
717 up
->mdr1
= UART_OMAP_MDR1_DISABLE
;
719 up
->fcr
= UART_FCR_R_TRIG_01
| UART_FCR_T_TRIG_01
|
720 UART_FCR_ENABLE_FIFO
;
723 * Ok, we're now changing the port state. Do it with
724 * interrupts disabled.
726 pm_runtime_get_sync(up
->dev
);
727 spin_lock_irqsave(&up
->port
.lock
, flags
);
730 * Update the per-port timeout.
732 uart_update_timeout(port
, termios
->c_cflag
, baud
);
734 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
735 if (termios
->c_iflag
& INPCK
)
736 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
737 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
738 up
->port
.read_status_mask
|= UART_LSR_BI
;
741 * Characters to ignore
743 up
->port
.ignore_status_mask
= 0;
744 if (termios
->c_iflag
& IGNPAR
)
745 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
746 if (termios
->c_iflag
& IGNBRK
) {
747 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
749 * If we're ignoring parity and break indicators,
750 * ignore overruns too (for real raw support).
752 if (termios
->c_iflag
& IGNPAR
)
753 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
757 * ignore all characters if CREAD is not set
759 if ((termios
->c_cflag
& CREAD
) == 0)
760 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
763 * Modem status interrupts
765 up
->ier
&= ~UART_IER_MSI
;
766 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
767 up
->ier
|= UART_IER_MSI
;
768 serial_out(up
, UART_IER
, up
->ier
);
769 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
771 up
->scr
= OMAP_UART_SCR_TX_EMPTY
;
773 /* FIFOs and DMA Settings */
775 /* FCR can be changed only when the
776 * baud clock is not running
777 * DLL_REG and DLH_REG set to 0.
779 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
780 serial_out(up
, UART_DLL
, 0);
781 serial_out(up
, UART_DLM
, 0);
782 serial_out(up
, UART_LCR
, 0);
784 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
786 up
->efr
= serial_in(up
, UART_EFR
);
787 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
789 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
790 up
->mcr
= serial_in(up
, UART_MCR
);
791 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
792 /* FIFO ENABLE, DMA MODE */
794 up
->scr
|= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
;
796 /* Set receive FIFO threshold to 1 byte */
797 up
->fcr
&= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK
;
798 up
->fcr
|= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT
);
800 serial_out(up
, UART_FCR
, up
->fcr
);
801 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
803 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
805 serial_out(up
, UART_EFR
, up
->efr
);
806 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
807 serial_out(up
, UART_MCR
, up
->mcr
);
809 /* Protocol, Baud Rate, and Interrupt Settings */
811 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
812 serial_omap_mdr1_errataset(up
, up
->mdr1
);
814 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
816 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
818 up
->efr
= serial_in(up
, UART_EFR
);
819 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
821 serial_out(up
, UART_LCR
, 0);
822 serial_out(up
, UART_IER
, 0);
823 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
825 serial_out(up
, UART_DLL
, up
->dll
); /* LS of divisor */
826 serial_out(up
, UART_DLM
, up
->dlh
); /* MS of divisor */
828 serial_out(up
, UART_LCR
, 0);
829 serial_out(up
, UART_IER
, up
->ier
);
830 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
832 serial_out(up
, UART_EFR
, up
->efr
);
833 serial_out(up
, UART_LCR
, cval
);
835 if (baud
> 230400 && baud
!= 3000000)
836 up
->mdr1
= UART_OMAP_MDR1_13X_MODE
;
838 up
->mdr1
= UART_OMAP_MDR1_16X_MODE
;
840 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
841 serial_omap_mdr1_errataset(up
, up
->mdr1
);
843 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
845 /* Hardware Flow Control Configuration */
847 if (termios
->c_cflag
& CRTSCTS
) {
848 efr
|= (UART_EFR_CTS
| UART_EFR_RTS
);
849 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
851 up
->mcr
= serial_in(up
, UART_MCR
);
852 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
854 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
855 up
->efr
= serial_in(up
, UART_EFR
);
856 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
858 serial_out(up
, UART_TI752_TCR
, OMAP_UART_TCR_TRIG
);
859 serial_out(up
, UART_EFR
, efr
); /* Enable AUTORTS and AUTOCTS */
860 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
861 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_RTS
);
862 serial_out(up
, UART_LCR
, cval
);
865 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
866 /* Software Flow Control Configuration */
867 serial_omap_configure_xonxoff(up
, termios
);
869 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
870 pm_runtime_mark_last_busy(up
->dev
);
871 pm_runtime_put_autosuspend(up
->dev
);
872 dev_dbg(up
->port
.dev
, "serial_omap_set_termios+%d\n", up
->port
.line
);
876 serial_omap_pm(struct uart_port
*port
, unsigned int state
,
877 unsigned int oldstate
)
879 struct uart_omap_port
*up
= to_uart_omap_port(port
);
882 dev_dbg(up
->port
.dev
, "serial_omap_pm+%d\n", up
->port
.line
);
884 pm_runtime_get_sync(up
->dev
);
885 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
886 efr
= serial_in(up
, UART_EFR
);
887 serial_out(up
, UART_EFR
, efr
| UART_EFR_ECB
);
888 serial_out(up
, UART_LCR
, 0);
890 serial_out(up
, UART_IER
, (state
!= 0) ? UART_IERX_SLEEP
: 0);
891 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
892 serial_out(up
, UART_EFR
, efr
);
893 serial_out(up
, UART_LCR
, 0);
895 if (!device_may_wakeup(up
->dev
)) {
897 pm_runtime_forbid(up
->dev
);
899 pm_runtime_allow(up
->dev
);
902 pm_runtime_mark_last_busy(up
->dev
);
903 pm_runtime_put_autosuspend(up
->dev
);
906 static void serial_omap_release_port(struct uart_port
*port
)
908 dev_dbg(port
->dev
, "serial_omap_release_port+\n");
911 static int serial_omap_request_port(struct uart_port
*port
)
913 dev_dbg(port
->dev
, "serial_omap_request_port+\n");
917 static void serial_omap_config_port(struct uart_port
*port
, int flags
)
919 struct uart_omap_port
*up
= to_uart_omap_port(port
);
921 dev_dbg(up
->port
.dev
, "serial_omap_config_port+%d\n",
923 up
->port
.type
= PORT_OMAP
;
927 serial_omap_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
929 /* we don't want the core code to modify any port params */
930 dev_dbg(port
->dev
, "serial_omap_verify_port+\n");
935 serial_omap_type(struct uart_port
*port
)
937 struct uart_omap_port
*up
= to_uart_omap_port(port
);
939 dev_dbg(up
->port
.dev
, "serial_omap_type+%d\n", up
->port
.line
);
943 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
945 static inline void wait_for_xmitr(struct uart_omap_port
*up
)
947 unsigned int status
, tmout
= 10000;
949 /* Wait up to 10ms for the character(s) to be sent. */
951 status
= serial_in(up
, UART_LSR
);
953 if (status
& UART_LSR_BI
)
954 up
->lsr_break_flag
= UART_LSR_BI
;
959 } while ((status
& BOTH_EMPTY
) != BOTH_EMPTY
);
961 /* Wait up to 1s for flow control if necessary */
962 if (up
->port
.flags
& UPF_CONS_FLOW
) {
964 for (tmout
= 1000000; tmout
; tmout
--) {
965 unsigned int msr
= serial_in(up
, UART_MSR
);
967 up
->msr_saved_flags
|= msr
& MSR_SAVE_FLAGS
;
968 if (msr
& UART_MSR_CTS
)
976 #ifdef CONFIG_CONSOLE_POLL
978 static void serial_omap_poll_put_char(struct uart_port
*port
, unsigned char ch
)
980 struct uart_omap_port
*up
= to_uart_omap_port(port
);
982 pm_runtime_get_sync(up
->dev
);
984 serial_out(up
, UART_TX
, ch
);
985 pm_runtime_mark_last_busy(up
->dev
);
986 pm_runtime_put_autosuspend(up
->dev
);
989 static int serial_omap_poll_get_char(struct uart_port
*port
)
991 struct uart_omap_port
*up
= to_uart_omap_port(port
);
994 pm_runtime_get_sync(up
->dev
);
995 status
= serial_in(up
, UART_LSR
);
996 if (!(status
& UART_LSR_DR
))
999 status
= serial_in(up
, UART_RX
);
1000 pm_runtime_mark_last_busy(up
->dev
);
1001 pm_runtime_put_autosuspend(up
->dev
);
1005 #endif /* CONFIG_CONSOLE_POLL */
1007 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1009 static struct uart_omap_port
*serial_omap_console_ports
[4];
1011 static struct uart_driver serial_omap_reg
;
1013 static void serial_omap_console_putchar(struct uart_port
*port
, int ch
)
1015 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1018 serial_out(up
, UART_TX
, ch
);
1022 serial_omap_console_write(struct console
*co
, const char *s
,
1025 struct uart_omap_port
*up
= serial_omap_console_ports
[co
->index
];
1026 unsigned long flags
;
1030 pm_runtime_get_sync(up
->dev
);
1032 local_irq_save(flags
);
1035 else if (oops_in_progress
)
1036 locked
= spin_trylock(&up
->port
.lock
);
1038 spin_lock(&up
->port
.lock
);
1041 * First save the IER then disable the interrupts
1043 ier
= serial_in(up
, UART_IER
);
1044 serial_out(up
, UART_IER
, 0);
1046 uart_console_write(&up
->port
, s
, count
, serial_omap_console_putchar
);
1049 * Finally, wait for transmitter to become empty
1050 * and restore the IER
1053 serial_out(up
, UART_IER
, ier
);
1055 * The receive handling will happen properly because the
1056 * receive ready bit will still be set; it is not cleared
1057 * on read. However, modem control will not, we must
1058 * call it if we have saved something in the saved flags
1059 * while processing with interrupts off.
1061 if (up
->msr_saved_flags
)
1062 check_modem_status(up
);
1064 pm_runtime_mark_last_busy(up
->dev
);
1065 pm_runtime_put_autosuspend(up
->dev
);
1067 spin_unlock(&up
->port
.lock
);
1068 local_irq_restore(flags
);
1072 serial_omap_console_setup(struct console
*co
, char *options
)
1074 struct uart_omap_port
*up
;
1080 if (serial_omap_console_ports
[co
->index
] == NULL
)
1082 up
= serial_omap_console_ports
[co
->index
];
1085 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1087 return uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1090 static struct console serial_omap_console
= {
1091 .name
= OMAP_SERIAL_NAME
,
1092 .write
= serial_omap_console_write
,
1093 .device
= uart_console_device
,
1094 .setup
= serial_omap_console_setup
,
1095 .flags
= CON_PRINTBUFFER
,
1097 .data
= &serial_omap_reg
,
1100 static void serial_omap_add_console_port(struct uart_omap_port
*up
)
1102 serial_omap_console_ports
[up
->port
.line
] = up
;
1105 #define OMAP_CONSOLE (&serial_omap_console)
1109 #define OMAP_CONSOLE NULL
1111 static inline void serial_omap_add_console_port(struct uart_omap_port
*up
)
1116 static struct uart_ops serial_omap_pops
= {
1117 .tx_empty
= serial_omap_tx_empty
,
1118 .set_mctrl
= serial_omap_set_mctrl
,
1119 .get_mctrl
= serial_omap_get_mctrl
,
1120 .stop_tx
= serial_omap_stop_tx
,
1121 .start_tx
= serial_omap_start_tx
,
1122 .stop_rx
= serial_omap_stop_rx
,
1123 .enable_ms
= serial_omap_enable_ms
,
1124 .break_ctl
= serial_omap_break_ctl
,
1125 .startup
= serial_omap_startup
,
1126 .shutdown
= serial_omap_shutdown
,
1127 .set_termios
= serial_omap_set_termios
,
1128 .pm
= serial_omap_pm
,
1129 .type
= serial_omap_type
,
1130 .release_port
= serial_omap_release_port
,
1131 .request_port
= serial_omap_request_port
,
1132 .config_port
= serial_omap_config_port
,
1133 .verify_port
= serial_omap_verify_port
,
1134 #ifdef CONFIG_CONSOLE_POLL
1135 .poll_put_char
= serial_omap_poll_put_char
,
1136 .poll_get_char
= serial_omap_poll_get_char
,
1140 static struct uart_driver serial_omap_reg
= {
1141 .owner
= THIS_MODULE
,
1142 .driver_name
= "OMAP-SERIAL",
1143 .dev_name
= OMAP_SERIAL_NAME
,
1144 .nr
= OMAP_MAX_HSUART_PORTS
,
1145 .cons
= OMAP_CONSOLE
,
1148 #ifdef CONFIG_PM_SLEEP
1149 static int serial_omap_suspend(struct device
*dev
)
1151 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1154 uart_suspend_port(&serial_omap_reg
, &up
->port
);
1155 flush_work_sync(&up
->qos_work
);
1161 static int serial_omap_resume(struct device
*dev
)
1163 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1166 uart_resume_port(&serial_omap_reg
, &up
->port
);
1171 static void __devinit
omap_serial_fill_features_erratas(struct uart_omap_port
*up
)
1174 u16 revision
, major
, minor
;
1176 mvr
= serial_in(up
, UART_OMAP_MVER
);
1178 /* Check revision register scheme */
1179 scheme
= mvr
>> OMAP_UART_MVR_SCHEME_SHIFT
;
1182 case 0: /* Legacy Scheme: OMAP2/3 */
1183 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1184 major
= (mvr
& OMAP_UART_LEGACY_MVR_MAJ_MASK
) >>
1185 OMAP_UART_LEGACY_MVR_MAJ_SHIFT
;
1186 minor
= (mvr
& OMAP_UART_LEGACY_MVR_MIN_MASK
);
1189 /* New Scheme: OMAP4+ */
1190 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1191 major
= (mvr
& OMAP_UART_MVR_MAJ_MASK
) >>
1192 OMAP_UART_MVR_MAJ_SHIFT
;
1193 minor
= (mvr
& OMAP_UART_MVR_MIN_MASK
);
1197 "Unknown %s revision, defaulting to highest\n",
1199 /* highest possible revision */
1204 /* normalize revision for the driver */
1205 revision
= UART_BUILD_REVISION(major
, minor
);
1208 case OMAP_UART_REV_46
:
1209 up
->errata
|= (UART_ERRATA_i202_MDR1_ACCESS
|
1210 UART_ERRATA_i291_DMA_FORCEIDLE
);
1212 case OMAP_UART_REV_52
:
1213 up
->errata
|= (UART_ERRATA_i202_MDR1_ACCESS
|
1214 UART_ERRATA_i291_DMA_FORCEIDLE
);
1216 case OMAP_UART_REV_63
:
1217 up
->errata
|= UART_ERRATA_i202_MDR1_ACCESS
;
1224 static __devinit
struct omap_uart_port_info
*of_get_uart_port_info(struct device
*dev
)
1226 struct omap_uart_port_info
*omap_up_info
;
1228 omap_up_info
= devm_kzalloc(dev
, sizeof(*omap_up_info
), GFP_KERNEL
);
1230 return NULL
; /* out of memory */
1232 of_property_read_u32(dev
->of_node
, "clock-frequency",
1233 &omap_up_info
->uartclk
);
1234 return omap_up_info
;
1237 static int __devinit
serial_omap_probe(struct platform_device
*pdev
)
1239 struct uart_omap_port
*up
;
1240 struct resource
*mem
, *irq
;
1241 struct omap_uart_port_info
*omap_up_info
= pdev
->dev
.platform_data
;
1244 if (pdev
->dev
.of_node
)
1245 omap_up_info
= of_get_uart_port_info(&pdev
->dev
);
1247 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1249 dev_err(&pdev
->dev
, "no mem resource?\n");
1253 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1255 dev_err(&pdev
->dev
, "no irq resource?\n");
1259 if (!devm_request_mem_region(&pdev
->dev
, mem
->start
, resource_size(mem
),
1260 pdev
->dev
.driver
->name
)) {
1261 dev_err(&pdev
->dev
, "memory region already claimed\n");
1265 if (gpio_is_valid(omap_up_info
->DTR_gpio
) &&
1266 omap_up_info
->DTR_present
) {
1267 ret
= gpio_request(omap_up_info
->DTR_gpio
, "omap-serial");
1270 ret
= gpio_direction_output(omap_up_info
->DTR_gpio
,
1271 omap_up_info
->DTR_inverted
);
1276 up
= devm_kzalloc(&pdev
->dev
, sizeof(*up
), GFP_KERNEL
);
1280 if (gpio_is_valid(omap_up_info
->DTR_gpio
) &&
1281 omap_up_info
->DTR_present
) {
1282 up
->DTR_gpio
= omap_up_info
->DTR_gpio
;
1283 up
->DTR_inverted
= omap_up_info
->DTR_inverted
;
1285 up
->DTR_gpio
= -EINVAL
;
1288 up
->dev
= &pdev
->dev
;
1289 up
->port
.dev
= &pdev
->dev
;
1290 up
->port
.type
= PORT_OMAP
;
1291 up
->port
.iotype
= UPIO_MEM
;
1292 up
->port
.irq
= irq
->start
;
1294 up
->port
.regshift
= 2;
1295 up
->port
.fifosize
= 64;
1296 up
->port
.ops
= &serial_omap_pops
;
1298 if (pdev
->dev
.of_node
)
1299 up
->port
.line
= of_alias_get_id(pdev
->dev
.of_node
, "serial");
1301 up
->port
.line
= pdev
->id
;
1303 if (up
->port
.line
< 0) {
1304 dev_err(&pdev
->dev
, "failed to get alias/pdev id, errno %d\n",
1310 sprintf(up
->name
, "OMAP UART%d", up
->port
.line
);
1311 up
->port
.mapbase
= mem
->start
;
1312 up
->port
.membase
= devm_ioremap(&pdev
->dev
, mem
->start
,
1313 resource_size(mem
));
1314 if (!up
->port
.membase
) {
1315 dev_err(&pdev
->dev
, "can't ioremap UART\n");
1320 up
->port
.flags
= omap_up_info
->flags
;
1321 up
->port
.uartclk
= omap_up_info
->uartclk
;
1322 if (!up
->port
.uartclk
) {
1323 up
->port
.uartclk
= DEFAULT_CLK_SPEED
;
1324 dev_warn(&pdev
->dev
, "No clock speed specified: using default:"
1325 "%d\n", DEFAULT_CLK_SPEED
);
1328 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1329 up
->calc_latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1330 pm_qos_add_request(&up
->pm_qos_request
,
1331 PM_QOS_CPU_DMA_LATENCY
, up
->latency
);
1332 serial_omap_uart_wq
= create_singlethread_workqueue(up
->name
);
1333 INIT_WORK(&up
->qos_work
, serial_omap_uart_qos_work
);
1335 platform_set_drvdata(pdev
, up
);
1336 pm_runtime_enable(&pdev
->dev
);
1337 pm_runtime_use_autosuspend(&pdev
->dev
);
1338 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1339 omap_up_info
->autosuspend_timeout
);
1341 pm_runtime_irq_safe(&pdev
->dev
);
1342 pm_runtime_get_sync(&pdev
->dev
);
1344 omap_serial_fill_features_erratas(up
);
1346 ui
[up
->port
.line
] = up
;
1347 serial_omap_add_console_port(up
);
1349 ret
= uart_add_one_port(&serial_omap_reg
, &up
->port
);
1353 pm_runtime_mark_last_busy(up
->dev
);
1354 pm_runtime_put_autosuspend(up
->dev
);
1358 pm_runtime_put(&pdev
->dev
);
1359 pm_runtime_disable(&pdev
->dev
);
1362 dev_err(&pdev
->dev
, "[UART%d]: failure [%s]: %d\n",
1363 pdev
->id
, __func__
, ret
);
1367 static int __devexit
serial_omap_remove(struct platform_device
*dev
)
1369 struct uart_omap_port
*up
= platform_get_drvdata(dev
);
1371 pm_runtime_put_sync(up
->dev
);
1372 pm_runtime_disable(up
->dev
);
1373 uart_remove_one_port(&serial_omap_reg
, &up
->port
);
1374 pm_qos_remove_request(&up
->pm_qos_request
);
1380 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1381 * The access to uart register after MDR1 Access
1382 * causes UART to corrupt data.
1385 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1386 * give 10 times as much
1388 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
)
1392 serial_out(up
, UART_OMAP_MDR1
, mdr1
);
1394 serial_out(up
, UART_FCR
, up
->fcr
| UART_FCR_CLEAR_XMIT
|
1395 UART_FCR_CLEAR_RCVR
);
1397 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1398 * TX_FIFO_E bit is 1.
1400 while (UART_LSR_THRE
!= (serial_in(up
, UART_LSR
) &
1401 (UART_LSR_THRE
| UART_LSR_DR
))) {
1404 /* Should *never* happen. we warn and carry on */
1405 dev_crit(up
->dev
, "Errata i202: timedout %x\n",
1406 serial_in(up
, UART_LSR
));
1413 #ifdef CONFIG_PM_RUNTIME
1414 static void serial_omap_restore_context(struct uart_omap_port
*up
)
1416 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1417 serial_omap_mdr1_errataset(up
, UART_OMAP_MDR1_DISABLE
);
1419 serial_out(up
, UART_OMAP_MDR1
, UART_OMAP_MDR1_DISABLE
);
1421 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1422 serial_out(up
, UART_EFR
, UART_EFR_ECB
);
1423 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1424 serial_out(up
, UART_IER
, 0x0);
1425 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1426 serial_out(up
, UART_DLL
, up
->dll
);
1427 serial_out(up
, UART_DLM
, up
->dlh
);
1428 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1429 serial_out(up
, UART_IER
, up
->ier
);
1430 serial_out(up
, UART_FCR
, up
->fcr
);
1431 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1432 serial_out(up
, UART_MCR
, up
->mcr
);
1433 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1434 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
1435 serial_out(up
, UART_EFR
, up
->efr
);
1436 serial_out(up
, UART_LCR
, up
->lcr
);
1437 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1438 serial_omap_mdr1_errataset(up
, up
->mdr1
);
1440 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
1443 static int serial_omap_runtime_suspend(struct device
*dev
)
1445 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1446 struct omap_uart_port_info
*pdata
= dev
->platform_data
;
1454 up
->context_loss_cnt
= serial_omap_get_context_loss_count(up
);
1456 if (device_may_wakeup(dev
)) {
1457 if (!up
->wakeups_enabled
) {
1458 serial_omap_enable_wakeup(up
, true);
1459 up
->wakeups_enabled
= true;
1462 if (up
->wakeups_enabled
) {
1463 serial_omap_enable_wakeup(up
, false);
1464 up
->wakeups_enabled
= false;
1468 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1469 schedule_work(&up
->qos_work
);
1474 static int serial_omap_runtime_resume(struct device
*dev
)
1476 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1477 struct omap_uart_port_info
*pdata
= dev
->platform_data
;
1480 u32 loss_cnt
= serial_omap_get_context_loss_count(up
);
1482 if (up
->context_loss_cnt
!= loss_cnt
)
1483 serial_omap_restore_context(up
);
1485 up
->latency
= up
->calc_latency
;
1486 schedule_work(&up
->qos_work
);
1493 static const struct dev_pm_ops serial_omap_dev_pm_ops
= {
1494 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend
, serial_omap_resume
)
1495 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend
,
1496 serial_omap_runtime_resume
, NULL
)
1499 #if defined(CONFIG_OF)
1500 static const struct of_device_id omap_serial_of_match
[] = {
1501 { .compatible
= "ti,omap2-uart" },
1502 { .compatible
= "ti,omap3-uart" },
1503 { .compatible
= "ti,omap4-uart" },
1506 MODULE_DEVICE_TABLE(of
, omap_serial_of_match
);
1509 static struct platform_driver serial_omap_driver
= {
1510 .probe
= serial_omap_probe
,
1511 .remove
= __devexit_p(serial_omap_remove
),
1513 .name
= DRIVER_NAME
,
1514 .pm
= &serial_omap_dev_pm_ops
,
1515 .of_match_table
= of_match_ptr(omap_serial_of_match
),
1519 static int __init
serial_omap_init(void)
1523 ret
= uart_register_driver(&serial_omap_reg
);
1526 ret
= platform_driver_register(&serial_omap_driver
);
1528 uart_unregister_driver(&serial_omap_reg
);
1532 static void __exit
serial_omap_exit(void)
1534 platform_driver_unregister(&serial_omap_driver
);
1535 uart_unregister_driver(&serial_omap_reg
);
1538 module_init(serial_omap_init
);
1539 module_exit(serial_omap_exit
);
1541 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1542 MODULE_LICENSE("GPL");
1543 MODULE_AUTHOR("Texas Instruments Inc");