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[deliverable/linux.git] / drivers / tty / serial / omap-serial.c
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/clk.h>
37 #include <linux/serial_core.h>
38 #include <linux/irq.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/of.h>
41 #include <linux/gpio.h>
42
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
45
46 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
47
48 #define OMAP_UART_REV_42 0x0402
49 #define OMAP_UART_REV_46 0x0406
50 #define OMAP_UART_REV_52 0x0502
51 #define OMAP_UART_REV_63 0x0603
52
53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
54
55 /* SCR register bitmasks */
56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
57
58 /* FCR register bitmasks */
59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
61
62 /* MVR register bitmasks */
63 #define OMAP_UART_MVR_SCHEME_SHIFT 30
64
65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
68
69 #define OMAP_UART_MVR_MAJ_MASK 0x700
70 #define OMAP_UART_MVR_MAJ_SHIFT 8
71 #define OMAP_UART_MVR_MIN_MASK 0x3f
72
73 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
74
75 /* Forward declaration of functions */
76 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
77
78 static struct workqueue_struct *serial_omap_uart_wq;
79
80 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
81 {
82 offset <<= up->port.regshift;
83 return readw(up->port.membase + offset);
84 }
85
86 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
87 {
88 offset <<= up->port.regshift;
89 writew(value, up->port.membase + offset);
90 }
91
92 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
93 {
94 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
95 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
96 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
97 serial_out(up, UART_FCR, 0);
98 }
99
100 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
101 {
102 struct omap_uart_port_info *pdata = up->dev->platform_data;
103
104 if (!pdata->get_context_loss_count)
105 return 0;
106
107 return pdata->get_context_loss_count(up->dev);
108 }
109
110 static void serial_omap_set_forceidle(struct uart_omap_port *up)
111 {
112 struct omap_uart_port_info *pdata = up->dev->platform_data;
113
114 if (pdata->set_forceidle)
115 pdata->set_forceidle(up->dev);
116 }
117
118 static void serial_omap_set_noidle(struct uart_omap_port *up)
119 {
120 struct omap_uart_port_info *pdata = up->dev->platform_data;
121
122 if (pdata->set_noidle)
123 pdata->set_noidle(up->dev);
124 }
125
126 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
127 {
128 struct omap_uart_port_info *pdata = up->dev->platform_data;
129
130 if (pdata->enable_wakeup)
131 pdata->enable_wakeup(up->dev, enable);
132 }
133
134 /*
135 * serial_omap_get_divisor - calculate divisor value
136 * @port: uart port info
137 * @baud: baudrate for which divisor needs to be calculated.
138 *
139 * We have written our own function to get the divisor so as to support
140 * 13x mode. 3Mbps Baudrate as an different divisor.
141 * Reference OMAP TRM Chapter 17:
142 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
143 * referring to oversampling - divisor value
144 * baudrate 460,800 to 3,686,400 all have divisor 13
145 * except 3,000,000 which has divisor value 16
146 */
147 static unsigned int
148 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
149 {
150 unsigned int divisor;
151
152 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
153 divisor = 13;
154 else
155 divisor = 16;
156 return port->uartclk/(baud * divisor);
157 }
158
159 static void serial_omap_enable_ms(struct uart_port *port)
160 {
161 struct uart_omap_port *up = to_uart_omap_port(port);
162
163 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
164
165 pm_runtime_get_sync(up->dev);
166 up->ier |= UART_IER_MSI;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_put(up->dev);
169 }
170
171 static void serial_omap_stop_tx(struct uart_port *port)
172 {
173 struct uart_omap_port *up = to_uart_omap_port(port);
174
175 pm_runtime_get_sync(up->dev);
176 if (up->ier & UART_IER_THRI) {
177 up->ier &= ~UART_IER_THRI;
178 serial_out(up, UART_IER, up->ier);
179 }
180
181 serial_omap_set_forceidle(up);
182
183 pm_runtime_mark_last_busy(up->dev);
184 pm_runtime_put_autosuspend(up->dev);
185 }
186
187 static void serial_omap_stop_rx(struct uart_port *port)
188 {
189 struct uart_omap_port *up = to_uart_omap_port(port);
190
191 pm_runtime_get_sync(up->dev);
192 up->ier &= ~UART_IER_RLSI;
193 up->port.read_status_mask &= ~UART_LSR_DR;
194 serial_out(up, UART_IER, up->ier);
195 pm_runtime_mark_last_busy(up->dev);
196 pm_runtime_put_autosuspend(up->dev);
197 }
198
199 static void transmit_chars(struct uart_omap_port *up)
200 {
201 struct circ_buf *xmit = &up->port.state->xmit;
202 int count;
203
204 if (up->port.x_char) {
205 serial_out(up, UART_TX, up->port.x_char);
206 up->port.icount.tx++;
207 up->port.x_char = 0;
208 return;
209 }
210 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
211 serial_omap_stop_tx(&up->port);
212 return;
213 }
214 count = up->port.fifosize / 4;
215 do {
216 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
217 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
218 up->port.icount.tx++;
219 if (uart_circ_empty(xmit))
220 break;
221 } while (--count > 0);
222
223 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
224 uart_write_wakeup(&up->port);
225
226 if (uart_circ_empty(xmit))
227 serial_omap_stop_tx(&up->port);
228 }
229
230 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
231 {
232 if (!(up->ier & UART_IER_THRI)) {
233 up->ier |= UART_IER_THRI;
234 serial_out(up, UART_IER, up->ier);
235 }
236 }
237
238 static void serial_omap_start_tx(struct uart_port *port)
239 {
240 struct uart_omap_port *up = to_uart_omap_port(port);
241
242 pm_runtime_get_sync(up->dev);
243 serial_omap_enable_ier_thri(up);
244 serial_omap_set_noidle(up);
245 pm_runtime_mark_last_busy(up->dev);
246 pm_runtime_put_autosuspend(up->dev);
247 }
248
249 static unsigned int check_modem_status(struct uart_omap_port *up)
250 {
251 unsigned int status;
252
253 status = serial_in(up, UART_MSR);
254 status |= up->msr_saved_flags;
255 up->msr_saved_flags = 0;
256 if ((status & UART_MSR_ANY_DELTA) == 0)
257 return status;
258
259 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
260 up->port.state != NULL) {
261 if (status & UART_MSR_TERI)
262 up->port.icount.rng++;
263 if (status & UART_MSR_DDSR)
264 up->port.icount.dsr++;
265 if (status & UART_MSR_DDCD)
266 uart_handle_dcd_change
267 (&up->port, status & UART_MSR_DCD);
268 if (status & UART_MSR_DCTS)
269 uart_handle_cts_change
270 (&up->port, status & UART_MSR_CTS);
271 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
272 }
273
274 return status;
275 }
276
277 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
278 {
279 unsigned int flag;
280
281 up->port.icount.rx++;
282 flag = TTY_NORMAL;
283
284 if (lsr & UART_LSR_BI) {
285 flag = TTY_BREAK;
286 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
287 up->port.icount.brk++;
288 /*
289 * We do the SysRQ and SAK checking
290 * here because otherwise the break
291 * may get masked by ignore_status_mask
292 * or read_status_mask.
293 */
294 if (uart_handle_break(&up->port))
295 return;
296
297 }
298
299 if (lsr & UART_LSR_PE) {
300 flag = TTY_PARITY;
301 up->port.icount.parity++;
302 }
303
304 if (lsr & UART_LSR_FE) {
305 flag = TTY_FRAME;
306 up->port.icount.frame++;
307 }
308
309 if (lsr & UART_LSR_OE)
310 up->port.icount.overrun++;
311
312 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
313 if (up->port.line == up->port.cons->index) {
314 /* Recover the break flag from console xmit */
315 lsr |= up->lsr_break_flag;
316 }
317 #endif
318 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
319 }
320
321 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
322 {
323 unsigned char ch = 0;
324 unsigned int flag;
325
326 if (!(lsr & UART_LSR_DR))
327 return;
328
329 ch = serial_in(up, UART_RX);
330 flag = TTY_NORMAL;
331 up->port.icount.rx++;
332
333 if (uart_handle_sysrq_char(&up->port, ch))
334 return;
335
336 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
337 }
338
339 /**
340 * serial_omap_irq() - This handles the interrupt from one port
341 * @irq: uart port irq number
342 * @dev_id: uart port info
343 */
344 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
345 {
346 struct uart_omap_port *up = dev_id;
347 struct tty_struct *tty = up->port.state->port.tty;
348 unsigned int iir, lsr;
349 unsigned int type;
350 unsigned long flags;
351 irqreturn_t ret = IRQ_NONE;
352 int max_count = 256;
353
354 spin_lock_irqsave(&up->port.lock, flags);
355 pm_runtime_get_sync(up->dev);
356
357 do {
358 iir = serial_in(up, UART_IIR);
359 if (iir & UART_IIR_NO_INT)
360 break;
361
362 ret = IRQ_HANDLED;
363 lsr = serial_in(up, UART_LSR);
364
365 /* extract IRQ type from IIR register */
366 type = iir & 0x3e;
367
368 switch (type) {
369 case UART_IIR_MSI:
370 check_modem_status(up);
371 break;
372 case UART_IIR_THRI:
373 if (lsr & UART_LSR_THRE)
374 transmit_chars(up);
375 break;
376 case UART_IIR_RX_TIMEOUT:
377 /* FALLTHROUGH */
378 case UART_IIR_RDI:
379 serial_omap_rdi(up, lsr);
380 break;
381 case UART_IIR_RLSI:
382 serial_omap_rlsi(up, lsr);
383 break;
384 case UART_IIR_CTS_RTS_DSR:
385 /* simply try again */
386 break;
387 case UART_IIR_XOFF:
388 /* FALLTHROUGH */
389 default:
390 break;
391 }
392 } while (!(iir & UART_IIR_NO_INT) && max_count--);
393
394 spin_unlock_irqrestore(&up->port.lock, flags);
395
396 tty_flip_buffer_push(tty);
397
398 pm_runtime_mark_last_busy(up->dev);
399 pm_runtime_put_autosuspend(up->dev);
400 up->port_activity = jiffies;
401
402 return ret;
403 }
404
405 static unsigned int serial_omap_tx_empty(struct uart_port *port)
406 {
407 struct uart_omap_port *up = to_uart_omap_port(port);
408 unsigned long flags = 0;
409 unsigned int ret = 0;
410
411 pm_runtime_get_sync(up->dev);
412 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
413 spin_lock_irqsave(&up->port.lock, flags);
414 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
415 spin_unlock_irqrestore(&up->port.lock, flags);
416 pm_runtime_put(up->dev);
417 return ret;
418 }
419
420 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
421 {
422 struct uart_omap_port *up = to_uart_omap_port(port);
423 unsigned int status;
424 unsigned int ret = 0;
425
426 pm_runtime_get_sync(up->dev);
427 status = check_modem_status(up);
428 pm_runtime_put(up->dev);
429
430 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
431
432 if (status & UART_MSR_DCD)
433 ret |= TIOCM_CAR;
434 if (status & UART_MSR_RI)
435 ret |= TIOCM_RNG;
436 if (status & UART_MSR_DSR)
437 ret |= TIOCM_DSR;
438 if (status & UART_MSR_CTS)
439 ret |= TIOCM_CTS;
440 return ret;
441 }
442
443 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
444 {
445 struct uart_omap_port *up = to_uart_omap_port(port);
446 unsigned char mcr = 0;
447
448 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
449 if (mctrl & TIOCM_RTS)
450 mcr |= UART_MCR_RTS;
451 if (mctrl & TIOCM_DTR)
452 mcr |= UART_MCR_DTR;
453 if (mctrl & TIOCM_OUT1)
454 mcr |= UART_MCR_OUT1;
455 if (mctrl & TIOCM_OUT2)
456 mcr |= UART_MCR_OUT2;
457 if (mctrl & TIOCM_LOOP)
458 mcr |= UART_MCR_LOOP;
459
460 pm_runtime_get_sync(up->dev);
461 up->mcr = serial_in(up, UART_MCR);
462 up->mcr |= mcr;
463 serial_out(up, UART_MCR, up->mcr);
464 pm_runtime_put(up->dev);
465
466 if (gpio_is_valid(up->DTR_gpio) &&
467 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
468 up->DTR_active = !up->DTR_active;
469 if (gpio_cansleep(up->DTR_gpio))
470 schedule_work(&up->qos_work);
471 else
472 gpio_set_value(up->DTR_gpio,
473 up->DTR_active != up->DTR_inverted);
474 }
475 }
476
477 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
478 {
479 struct uart_omap_port *up = to_uart_omap_port(port);
480 unsigned long flags = 0;
481
482 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
483 pm_runtime_get_sync(up->dev);
484 spin_lock_irqsave(&up->port.lock, flags);
485 if (break_state == -1)
486 up->lcr |= UART_LCR_SBC;
487 else
488 up->lcr &= ~UART_LCR_SBC;
489 serial_out(up, UART_LCR, up->lcr);
490 spin_unlock_irqrestore(&up->port.lock, flags);
491 pm_runtime_put(up->dev);
492 }
493
494 static int serial_omap_startup(struct uart_port *port)
495 {
496 struct uart_omap_port *up = to_uart_omap_port(port);
497 unsigned long flags = 0;
498 int retval;
499
500 /*
501 * Allocate the IRQ
502 */
503 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
504 up->name, up);
505 if (retval)
506 return retval;
507
508 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
509
510 pm_runtime_get_sync(up->dev);
511 /*
512 * Clear the FIFO buffers and disable them.
513 * (they will be reenabled in set_termios())
514 */
515 serial_omap_clear_fifos(up);
516 /* For Hardware flow control */
517 serial_out(up, UART_MCR, UART_MCR_RTS);
518
519 /*
520 * Clear the interrupt registers.
521 */
522 (void) serial_in(up, UART_LSR);
523 if (serial_in(up, UART_LSR) & UART_LSR_DR)
524 (void) serial_in(up, UART_RX);
525 (void) serial_in(up, UART_IIR);
526 (void) serial_in(up, UART_MSR);
527
528 /*
529 * Now, initialize the UART
530 */
531 serial_out(up, UART_LCR, UART_LCR_WLEN8);
532 spin_lock_irqsave(&up->port.lock, flags);
533 /*
534 * Most PC uarts need OUT2 raised to enable interrupts.
535 */
536 up->port.mctrl |= TIOCM_OUT2;
537 serial_omap_set_mctrl(&up->port, up->port.mctrl);
538 spin_unlock_irqrestore(&up->port.lock, flags);
539
540 up->msr_saved_flags = 0;
541 /*
542 * Finally, enable interrupts. Note: Modem status interrupts
543 * are set via set_termios(), which will be occurring imminently
544 * anyway, so we don't enable them here.
545 */
546 up->ier = UART_IER_RLSI | UART_IER_RDI;
547 serial_out(up, UART_IER, up->ier);
548
549 /* Enable module level wake up */
550 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
551
552 pm_runtime_mark_last_busy(up->dev);
553 pm_runtime_put_autosuspend(up->dev);
554 up->port_activity = jiffies;
555 return 0;
556 }
557
558 static void serial_omap_shutdown(struct uart_port *port)
559 {
560 struct uart_omap_port *up = to_uart_omap_port(port);
561 unsigned long flags = 0;
562
563 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
564
565 pm_runtime_get_sync(up->dev);
566 /*
567 * Disable interrupts from this port
568 */
569 up->ier = 0;
570 serial_out(up, UART_IER, 0);
571
572 spin_lock_irqsave(&up->port.lock, flags);
573 up->port.mctrl &= ~TIOCM_OUT2;
574 serial_omap_set_mctrl(&up->port, up->port.mctrl);
575 spin_unlock_irqrestore(&up->port.lock, flags);
576
577 /*
578 * Disable break condition and FIFOs
579 */
580 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
581 serial_omap_clear_fifos(up);
582
583 /*
584 * Read data port to reset things, and then free the irq
585 */
586 if (serial_in(up, UART_LSR) & UART_LSR_DR)
587 (void) serial_in(up, UART_RX);
588
589 pm_runtime_put(up->dev);
590 free_irq(up->port.irq, up);
591 }
592
593 static inline void
594 serial_omap_configure_xonxoff
595 (struct uart_omap_port *up, struct ktermios *termios)
596 {
597 up->lcr = serial_in(up, UART_LCR);
598 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
599 up->efr = serial_in(up, UART_EFR);
600 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
601
602 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
603 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
604
605 /* clear SW control mode bits */
606 up->efr &= OMAP_UART_SW_CLR;
607
608 /*
609 * IXON Flag:
610 * Enable XON/XOFF flow control on output.
611 * Transmit XON1, XOFF1
612 */
613 if (termios->c_iflag & IXON)
614 up->efr |= OMAP_UART_SW_TX;
615
616 /*
617 * IXOFF Flag:
618 * Enable XON/XOFF flow control on input.
619 * Receiver compares XON1, XOFF1.
620 */
621 if (termios->c_iflag & IXOFF)
622 up->efr |= OMAP_UART_SW_RX;
623
624 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
625 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
626
627 up->mcr = serial_in(up, UART_MCR);
628
629 /*
630 * IXANY Flag:
631 * Enable any character to restart output.
632 * Operation resumes after receiving any
633 * character after recognition of the XOFF character
634 */
635 if (termios->c_iflag & IXANY)
636 up->mcr |= UART_MCR_XONANY;
637
638 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
639 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
640 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
641 /* Enable special char function UARTi.EFR_REG[5] and
642 * load the new software flow control mode IXON or IXOFF
643 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
644 */
645 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
646 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
647
648 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
649 serial_out(up, UART_LCR, up->lcr);
650 }
651
652 static void serial_omap_uart_qos_work(struct work_struct *work)
653 {
654 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
655 qos_work);
656
657 pm_qos_update_request(&up->pm_qos_request, up->latency);
658 if (gpio_is_valid(up->DTR_gpio))
659 gpio_set_value_cansleep(up->DTR_gpio,
660 up->DTR_active != up->DTR_inverted);
661 }
662
663 static void
664 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
665 struct ktermios *old)
666 {
667 struct uart_omap_port *up = to_uart_omap_port(port);
668 unsigned char cval = 0;
669 unsigned char efr = 0;
670 unsigned long flags = 0;
671 unsigned int baud, quot;
672
673 switch (termios->c_cflag & CSIZE) {
674 case CS5:
675 cval = UART_LCR_WLEN5;
676 break;
677 case CS6:
678 cval = UART_LCR_WLEN6;
679 break;
680 case CS7:
681 cval = UART_LCR_WLEN7;
682 break;
683 default:
684 case CS8:
685 cval = UART_LCR_WLEN8;
686 break;
687 }
688
689 if (termios->c_cflag & CSTOPB)
690 cval |= UART_LCR_STOP;
691 if (termios->c_cflag & PARENB)
692 cval |= UART_LCR_PARITY;
693 if (!(termios->c_cflag & PARODD))
694 cval |= UART_LCR_EPAR;
695
696 /*
697 * Ask the core to calculate the divisor for us.
698 */
699
700 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
701 quot = serial_omap_get_divisor(port, baud);
702
703 /* calculate wakeup latency constraint */
704 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
705 up->latency = up->calc_latency;
706 schedule_work(&up->qos_work);
707
708 up->dll = quot & 0xff;
709 up->dlh = quot >> 8;
710 up->mdr1 = UART_OMAP_MDR1_DISABLE;
711
712 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
713 UART_FCR_ENABLE_FIFO;
714
715 /*
716 * Ok, we're now changing the port state. Do it with
717 * interrupts disabled.
718 */
719 pm_runtime_get_sync(up->dev);
720 spin_lock_irqsave(&up->port.lock, flags);
721
722 /*
723 * Update the per-port timeout.
724 */
725 uart_update_timeout(port, termios->c_cflag, baud);
726
727 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
728 if (termios->c_iflag & INPCK)
729 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
730 if (termios->c_iflag & (BRKINT | PARMRK))
731 up->port.read_status_mask |= UART_LSR_BI;
732
733 /*
734 * Characters to ignore
735 */
736 up->port.ignore_status_mask = 0;
737 if (termios->c_iflag & IGNPAR)
738 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
739 if (termios->c_iflag & IGNBRK) {
740 up->port.ignore_status_mask |= UART_LSR_BI;
741 /*
742 * If we're ignoring parity and break indicators,
743 * ignore overruns too (for real raw support).
744 */
745 if (termios->c_iflag & IGNPAR)
746 up->port.ignore_status_mask |= UART_LSR_OE;
747 }
748
749 /*
750 * ignore all characters if CREAD is not set
751 */
752 if ((termios->c_cflag & CREAD) == 0)
753 up->port.ignore_status_mask |= UART_LSR_DR;
754
755 /*
756 * Modem status interrupts
757 */
758 up->ier &= ~UART_IER_MSI;
759 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
760 up->ier |= UART_IER_MSI;
761 serial_out(up, UART_IER, up->ier);
762 serial_out(up, UART_LCR, cval); /* reset DLAB */
763 up->lcr = cval;
764 up->scr = OMAP_UART_SCR_TX_EMPTY;
765
766 /* FIFOs and DMA Settings */
767
768 /* FCR can be changed only when the
769 * baud clock is not running
770 * DLL_REG and DLH_REG set to 0.
771 */
772 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
773 serial_out(up, UART_DLL, 0);
774 serial_out(up, UART_DLM, 0);
775 serial_out(up, UART_LCR, 0);
776
777 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
778
779 up->efr = serial_in(up, UART_EFR);
780 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
781
782 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
783 up->mcr = serial_in(up, UART_MCR);
784 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
785 /* FIFO ENABLE, DMA MODE */
786
787 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
788
789 /* Set receive FIFO threshold to 1 byte */
790 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
791 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
792
793 serial_out(up, UART_FCR, up->fcr);
794 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
795
796 serial_out(up, UART_OMAP_SCR, up->scr);
797
798 serial_out(up, UART_EFR, up->efr);
799 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
800 serial_out(up, UART_MCR, up->mcr);
801
802 /* Protocol, Baud Rate, and Interrupt Settings */
803
804 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
805 serial_omap_mdr1_errataset(up, up->mdr1);
806 else
807 serial_out(up, UART_OMAP_MDR1, up->mdr1);
808
809 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
810
811 up->efr = serial_in(up, UART_EFR);
812 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
813
814 serial_out(up, UART_LCR, 0);
815 serial_out(up, UART_IER, 0);
816 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
817
818 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
819 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
820
821 serial_out(up, UART_LCR, 0);
822 serial_out(up, UART_IER, up->ier);
823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
824
825 serial_out(up, UART_EFR, up->efr);
826 serial_out(up, UART_LCR, cval);
827
828 if (baud > 230400 && baud != 3000000)
829 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
830 else
831 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
832
833 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
834 serial_omap_mdr1_errataset(up, up->mdr1);
835 else
836 serial_out(up, UART_OMAP_MDR1, up->mdr1);
837
838 /* Hardware Flow Control Configuration */
839
840 if (termios->c_cflag & CRTSCTS) {
841 efr |= (UART_EFR_CTS | UART_EFR_RTS);
842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
843
844 up->mcr = serial_in(up, UART_MCR);
845 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
846
847 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
848 up->efr = serial_in(up, UART_EFR);
849 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
850
851 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
852 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
853 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
854 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
855 serial_out(up, UART_LCR, cval);
856 }
857
858 serial_omap_set_mctrl(&up->port, up->port.mctrl);
859 /* Software Flow Control Configuration */
860 serial_omap_configure_xonxoff(up, termios);
861
862 spin_unlock_irqrestore(&up->port.lock, flags);
863 pm_runtime_put(up->dev);
864 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
865 }
866
867 static void
868 serial_omap_pm(struct uart_port *port, unsigned int state,
869 unsigned int oldstate)
870 {
871 struct uart_omap_port *up = to_uart_omap_port(port);
872 unsigned char efr;
873
874 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
875
876 pm_runtime_get_sync(up->dev);
877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
878 efr = serial_in(up, UART_EFR);
879 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
880 serial_out(up, UART_LCR, 0);
881
882 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
883 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
884 serial_out(up, UART_EFR, efr);
885 serial_out(up, UART_LCR, 0);
886
887 if (!device_may_wakeup(up->dev)) {
888 if (!state)
889 pm_runtime_forbid(up->dev);
890 else
891 pm_runtime_allow(up->dev);
892 }
893
894 pm_runtime_put(up->dev);
895 }
896
897 static void serial_omap_release_port(struct uart_port *port)
898 {
899 dev_dbg(port->dev, "serial_omap_release_port+\n");
900 }
901
902 static int serial_omap_request_port(struct uart_port *port)
903 {
904 dev_dbg(port->dev, "serial_omap_request_port+\n");
905 return 0;
906 }
907
908 static void serial_omap_config_port(struct uart_port *port, int flags)
909 {
910 struct uart_omap_port *up = to_uart_omap_port(port);
911
912 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
913 up->port.line);
914 up->port.type = PORT_OMAP;
915 }
916
917 static int
918 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
919 {
920 /* we don't want the core code to modify any port params */
921 dev_dbg(port->dev, "serial_omap_verify_port+\n");
922 return -EINVAL;
923 }
924
925 static const char *
926 serial_omap_type(struct uart_port *port)
927 {
928 struct uart_omap_port *up = to_uart_omap_port(port);
929
930 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
931 return up->name;
932 }
933
934 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
935
936 static inline void wait_for_xmitr(struct uart_omap_port *up)
937 {
938 unsigned int status, tmout = 10000;
939
940 /* Wait up to 10ms for the character(s) to be sent. */
941 do {
942 status = serial_in(up, UART_LSR);
943
944 if (status & UART_LSR_BI)
945 up->lsr_break_flag = UART_LSR_BI;
946
947 if (--tmout == 0)
948 break;
949 udelay(1);
950 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
951
952 /* Wait up to 1s for flow control if necessary */
953 if (up->port.flags & UPF_CONS_FLOW) {
954 tmout = 1000000;
955 for (tmout = 1000000; tmout; tmout--) {
956 unsigned int msr = serial_in(up, UART_MSR);
957
958 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
959 if (msr & UART_MSR_CTS)
960 break;
961
962 udelay(1);
963 }
964 }
965 }
966
967 #ifdef CONFIG_CONSOLE_POLL
968
969 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
970 {
971 struct uart_omap_port *up = to_uart_omap_port(port);
972
973 pm_runtime_get_sync(up->dev);
974 wait_for_xmitr(up);
975 serial_out(up, UART_TX, ch);
976 pm_runtime_put(up->dev);
977 }
978
979 static int serial_omap_poll_get_char(struct uart_port *port)
980 {
981 struct uart_omap_port *up = to_uart_omap_port(port);
982 unsigned int status;
983
984 pm_runtime_get_sync(up->dev);
985 status = serial_in(up, UART_LSR);
986 if (!(status & UART_LSR_DR))
987 return NO_POLL_CHAR;
988
989 status = serial_in(up, UART_RX);
990 pm_runtime_put(up->dev);
991 return status;
992 }
993
994 #endif /* CONFIG_CONSOLE_POLL */
995
996 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
997
998 static struct uart_omap_port *serial_omap_console_ports[4];
999
1000 static struct uart_driver serial_omap_reg;
1001
1002 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1003 {
1004 struct uart_omap_port *up = to_uart_omap_port(port);
1005
1006 wait_for_xmitr(up);
1007 serial_out(up, UART_TX, ch);
1008 }
1009
1010 static void
1011 serial_omap_console_write(struct console *co, const char *s,
1012 unsigned int count)
1013 {
1014 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1015 unsigned long flags;
1016 unsigned int ier;
1017 int locked = 1;
1018
1019 pm_runtime_get_sync(up->dev);
1020
1021 local_irq_save(flags);
1022 if (up->port.sysrq)
1023 locked = 0;
1024 else if (oops_in_progress)
1025 locked = spin_trylock(&up->port.lock);
1026 else
1027 spin_lock(&up->port.lock);
1028
1029 /*
1030 * First save the IER then disable the interrupts
1031 */
1032 ier = serial_in(up, UART_IER);
1033 serial_out(up, UART_IER, 0);
1034
1035 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1036
1037 /*
1038 * Finally, wait for transmitter to become empty
1039 * and restore the IER
1040 */
1041 wait_for_xmitr(up);
1042 serial_out(up, UART_IER, ier);
1043 /*
1044 * The receive handling will happen properly because the
1045 * receive ready bit will still be set; it is not cleared
1046 * on read. However, modem control will not, we must
1047 * call it if we have saved something in the saved flags
1048 * while processing with interrupts off.
1049 */
1050 if (up->msr_saved_flags)
1051 check_modem_status(up);
1052
1053 pm_runtime_mark_last_busy(up->dev);
1054 pm_runtime_put_autosuspend(up->dev);
1055 if (locked)
1056 spin_unlock(&up->port.lock);
1057 local_irq_restore(flags);
1058 }
1059
1060 static int __init
1061 serial_omap_console_setup(struct console *co, char *options)
1062 {
1063 struct uart_omap_port *up;
1064 int baud = 115200;
1065 int bits = 8;
1066 int parity = 'n';
1067 int flow = 'n';
1068
1069 if (serial_omap_console_ports[co->index] == NULL)
1070 return -ENODEV;
1071 up = serial_omap_console_ports[co->index];
1072
1073 if (options)
1074 uart_parse_options(options, &baud, &parity, &bits, &flow);
1075
1076 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1077 }
1078
1079 static struct console serial_omap_console = {
1080 .name = OMAP_SERIAL_NAME,
1081 .write = serial_omap_console_write,
1082 .device = uart_console_device,
1083 .setup = serial_omap_console_setup,
1084 .flags = CON_PRINTBUFFER,
1085 .index = -1,
1086 .data = &serial_omap_reg,
1087 };
1088
1089 static void serial_omap_add_console_port(struct uart_omap_port *up)
1090 {
1091 serial_omap_console_ports[up->port.line] = up;
1092 }
1093
1094 #define OMAP_CONSOLE (&serial_omap_console)
1095
1096 #else
1097
1098 #define OMAP_CONSOLE NULL
1099
1100 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1101 {}
1102
1103 #endif
1104
1105 static struct uart_ops serial_omap_pops = {
1106 .tx_empty = serial_omap_tx_empty,
1107 .set_mctrl = serial_omap_set_mctrl,
1108 .get_mctrl = serial_omap_get_mctrl,
1109 .stop_tx = serial_omap_stop_tx,
1110 .start_tx = serial_omap_start_tx,
1111 .stop_rx = serial_omap_stop_rx,
1112 .enable_ms = serial_omap_enable_ms,
1113 .break_ctl = serial_omap_break_ctl,
1114 .startup = serial_omap_startup,
1115 .shutdown = serial_omap_shutdown,
1116 .set_termios = serial_omap_set_termios,
1117 .pm = serial_omap_pm,
1118 .type = serial_omap_type,
1119 .release_port = serial_omap_release_port,
1120 .request_port = serial_omap_request_port,
1121 .config_port = serial_omap_config_port,
1122 .verify_port = serial_omap_verify_port,
1123 #ifdef CONFIG_CONSOLE_POLL
1124 .poll_put_char = serial_omap_poll_put_char,
1125 .poll_get_char = serial_omap_poll_get_char,
1126 #endif
1127 };
1128
1129 static struct uart_driver serial_omap_reg = {
1130 .owner = THIS_MODULE,
1131 .driver_name = "OMAP-SERIAL",
1132 .dev_name = OMAP_SERIAL_NAME,
1133 .nr = OMAP_MAX_HSUART_PORTS,
1134 .cons = OMAP_CONSOLE,
1135 };
1136
1137 #ifdef CONFIG_PM_SLEEP
1138 static int serial_omap_suspend(struct device *dev)
1139 {
1140 struct uart_omap_port *up = dev_get_drvdata(dev);
1141
1142 if (up) {
1143 uart_suspend_port(&serial_omap_reg, &up->port);
1144 flush_work_sync(&up->qos_work);
1145 }
1146
1147 return 0;
1148 }
1149
1150 static int serial_omap_resume(struct device *dev)
1151 {
1152 struct uart_omap_port *up = dev_get_drvdata(dev);
1153
1154 if (up)
1155 uart_resume_port(&serial_omap_reg, &up->port);
1156 return 0;
1157 }
1158 #endif
1159
1160 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1161 {
1162 u32 mvr, scheme;
1163 u16 revision, major, minor;
1164
1165 mvr = serial_in(up, UART_OMAP_MVER);
1166
1167 /* Check revision register scheme */
1168 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1169
1170 switch (scheme) {
1171 case 0: /* Legacy Scheme: OMAP2/3 */
1172 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1173 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1174 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1175 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1176 break;
1177 case 1:
1178 /* New Scheme: OMAP4+ */
1179 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1180 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1181 OMAP_UART_MVR_MAJ_SHIFT;
1182 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1183 break;
1184 default:
1185 dev_warn(up->dev,
1186 "Unknown %s revision, defaulting to highest\n",
1187 up->name);
1188 /* highest possible revision */
1189 major = 0xff;
1190 minor = 0xff;
1191 }
1192
1193 /* normalize revision for the driver */
1194 revision = UART_BUILD_REVISION(major, minor);
1195
1196 switch (revision) {
1197 case OMAP_UART_REV_46:
1198 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1199 UART_ERRATA_i291_DMA_FORCEIDLE);
1200 break;
1201 case OMAP_UART_REV_52:
1202 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1203 UART_ERRATA_i291_DMA_FORCEIDLE);
1204 break;
1205 case OMAP_UART_REV_63:
1206 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1207 break;
1208 default:
1209 break;
1210 }
1211 }
1212
1213 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1214 {
1215 struct omap_uart_port_info *omap_up_info;
1216
1217 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1218 if (!omap_up_info)
1219 return NULL; /* out of memory */
1220
1221 of_property_read_u32(dev->of_node, "clock-frequency",
1222 &omap_up_info->uartclk);
1223 return omap_up_info;
1224 }
1225
1226 static int serial_omap_probe(struct platform_device *pdev)
1227 {
1228 struct uart_omap_port *up;
1229 struct resource *mem, *irq;
1230 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1231 int ret;
1232
1233 if (pdev->dev.of_node)
1234 omap_up_info = of_get_uart_port_info(&pdev->dev);
1235
1236 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1237 if (!mem) {
1238 dev_err(&pdev->dev, "no mem resource?\n");
1239 return -ENODEV;
1240 }
1241
1242 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1243 if (!irq) {
1244 dev_err(&pdev->dev, "no irq resource?\n");
1245 return -ENODEV;
1246 }
1247
1248 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1249 pdev->dev.driver->name)) {
1250 dev_err(&pdev->dev, "memory region already claimed\n");
1251 return -EBUSY;
1252 }
1253
1254 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1255 omap_up_info->DTR_present) {
1256 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1257 if (ret < 0)
1258 return ret;
1259 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1260 omap_up_info->DTR_inverted);
1261 if (ret < 0)
1262 return ret;
1263 }
1264
1265 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1266 if (!up)
1267 return -ENOMEM;
1268
1269 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1270 omap_up_info->DTR_present) {
1271 up->DTR_gpio = omap_up_info->DTR_gpio;
1272 up->DTR_inverted = omap_up_info->DTR_inverted;
1273 } else
1274 up->DTR_gpio = -EINVAL;
1275 up->DTR_active = 0;
1276
1277 up->dev = &pdev->dev;
1278 up->port.dev = &pdev->dev;
1279 up->port.type = PORT_OMAP;
1280 up->port.iotype = UPIO_MEM;
1281 up->port.irq = irq->start;
1282
1283 up->port.regshift = 2;
1284 up->port.fifosize = 64;
1285 up->port.ops = &serial_omap_pops;
1286
1287 if (pdev->dev.of_node)
1288 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1289 else
1290 up->port.line = pdev->id;
1291
1292 if (up->port.line < 0) {
1293 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1294 up->port.line);
1295 ret = -ENODEV;
1296 goto err_port_line;
1297 }
1298
1299 sprintf(up->name, "OMAP UART%d", up->port.line);
1300 up->port.mapbase = mem->start;
1301 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1302 resource_size(mem));
1303 if (!up->port.membase) {
1304 dev_err(&pdev->dev, "can't ioremap UART\n");
1305 ret = -ENOMEM;
1306 goto err_ioremap;
1307 }
1308
1309 up->port.flags = omap_up_info->flags;
1310 up->port.uartclk = omap_up_info->uartclk;
1311 if (!up->port.uartclk) {
1312 up->port.uartclk = DEFAULT_CLK_SPEED;
1313 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1314 "%d\n", DEFAULT_CLK_SPEED);
1315 }
1316
1317 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1318 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1319 pm_qos_add_request(&up->pm_qos_request,
1320 PM_QOS_CPU_DMA_LATENCY, up->latency);
1321 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1322 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1323
1324 pm_runtime_use_autosuspend(&pdev->dev);
1325 pm_runtime_set_autosuspend_delay(&pdev->dev,
1326 omap_up_info->autosuspend_timeout);
1327
1328 pm_runtime_irq_safe(&pdev->dev);
1329 pm_runtime_enable(&pdev->dev);
1330 pm_runtime_get_sync(&pdev->dev);
1331
1332 omap_serial_fill_features_erratas(up);
1333
1334 ui[up->port.line] = up;
1335 serial_omap_add_console_port(up);
1336
1337 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1338 if (ret != 0)
1339 goto err_add_port;
1340
1341 pm_runtime_put(&pdev->dev);
1342 platform_set_drvdata(pdev, up);
1343 return 0;
1344
1345 err_add_port:
1346 pm_runtime_put(&pdev->dev);
1347 pm_runtime_disable(&pdev->dev);
1348 err_ioremap:
1349 err_port_line:
1350 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1351 pdev->id, __func__, ret);
1352 return ret;
1353 }
1354
1355 static int serial_omap_remove(struct platform_device *dev)
1356 {
1357 struct uart_omap_port *up = platform_get_drvdata(dev);
1358
1359 if (up) {
1360 pm_runtime_disable(up->dev);
1361 uart_remove_one_port(&serial_omap_reg, &up->port);
1362 pm_qos_remove_request(&up->pm_qos_request);
1363 }
1364
1365 platform_set_drvdata(dev, NULL);
1366 return 0;
1367 }
1368
1369 /*
1370 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1371 * The access to uart register after MDR1 Access
1372 * causes UART to corrupt data.
1373 *
1374 * Need a delay =
1375 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1376 * give 10 times as much
1377 */
1378 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1379 {
1380 u8 timeout = 255;
1381
1382 serial_out(up, UART_OMAP_MDR1, mdr1);
1383 udelay(2);
1384 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1385 UART_FCR_CLEAR_RCVR);
1386 /*
1387 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1388 * TX_FIFO_E bit is 1.
1389 */
1390 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1391 (UART_LSR_THRE | UART_LSR_DR))) {
1392 timeout--;
1393 if (!timeout) {
1394 /* Should *never* happen. we warn and carry on */
1395 dev_crit(up->dev, "Errata i202: timedout %x\n",
1396 serial_in(up, UART_LSR));
1397 break;
1398 }
1399 udelay(1);
1400 }
1401 }
1402
1403 #ifdef CONFIG_PM_RUNTIME
1404 static void serial_omap_restore_context(struct uart_omap_port *up)
1405 {
1406 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1407 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1408 else
1409 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1410
1411 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1412 serial_out(up, UART_EFR, UART_EFR_ECB);
1413 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1414 serial_out(up, UART_IER, 0x0);
1415 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1416 serial_out(up, UART_DLL, up->dll);
1417 serial_out(up, UART_DLM, up->dlh);
1418 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1419 serial_out(up, UART_IER, up->ier);
1420 serial_out(up, UART_FCR, up->fcr);
1421 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1422 serial_out(up, UART_MCR, up->mcr);
1423 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1424 serial_out(up, UART_OMAP_SCR, up->scr);
1425 serial_out(up, UART_EFR, up->efr);
1426 serial_out(up, UART_LCR, up->lcr);
1427 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1428 serial_omap_mdr1_errataset(up, up->mdr1);
1429 else
1430 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1431 }
1432
1433 static int serial_omap_runtime_suspend(struct device *dev)
1434 {
1435 struct uart_omap_port *up = dev_get_drvdata(dev);
1436 struct omap_uart_port_info *pdata = dev->platform_data;
1437
1438 if (!up)
1439 return -EINVAL;
1440
1441 if (!pdata)
1442 return 0;
1443
1444 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1445
1446 if (device_may_wakeup(dev)) {
1447 if (!up->wakeups_enabled) {
1448 serial_omap_enable_wakeup(up, true);
1449 up->wakeups_enabled = true;
1450 }
1451 } else {
1452 if (up->wakeups_enabled) {
1453 serial_omap_enable_wakeup(up, false);
1454 up->wakeups_enabled = false;
1455 }
1456 }
1457
1458 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1459 schedule_work(&up->qos_work);
1460
1461 return 0;
1462 }
1463
1464 static int serial_omap_runtime_resume(struct device *dev)
1465 {
1466 struct uart_omap_port *up = dev_get_drvdata(dev);
1467 struct omap_uart_port_info *pdata = dev->platform_data;
1468
1469 if (up && pdata) {
1470 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1471
1472 if (up->context_loss_cnt != loss_cnt)
1473 serial_omap_restore_context(up);
1474
1475 up->latency = up->calc_latency;
1476 schedule_work(&up->qos_work);
1477 }
1478
1479 return 0;
1480 }
1481 #endif
1482
1483 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1484 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1485 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1486 serial_omap_runtime_resume, NULL)
1487 };
1488
1489 #if defined(CONFIG_OF)
1490 static const struct of_device_id omap_serial_of_match[] = {
1491 { .compatible = "ti,omap2-uart" },
1492 { .compatible = "ti,omap3-uart" },
1493 { .compatible = "ti,omap4-uart" },
1494 {},
1495 };
1496 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1497 #endif
1498
1499 static struct platform_driver serial_omap_driver = {
1500 .probe = serial_omap_probe,
1501 .remove = serial_omap_remove,
1502 .driver = {
1503 .name = DRIVER_NAME,
1504 .pm = &serial_omap_dev_pm_ops,
1505 .of_match_table = of_match_ptr(omap_serial_of_match),
1506 },
1507 };
1508
1509 static int __init serial_omap_init(void)
1510 {
1511 int ret;
1512
1513 ret = uart_register_driver(&serial_omap_reg);
1514 if (ret != 0)
1515 return ret;
1516 ret = platform_driver_register(&serial_omap_driver);
1517 if (ret != 0)
1518 uart_unregister_driver(&serial_omap_reg);
1519 return ret;
1520 }
1521
1522 static void __exit serial_omap_exit(void)
1523 {
1524 platform_driver_unregister(&serial_omap_driver);
1525 uart_unregister_driver(&serial_omap_reg);
1526 }
1527
1528 module_init(serial_omap_init);
1529 module_exit(serial_omap_exit);
1530
1531 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1532 MODULE_LICENSE("GPL");
1533 MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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