serial: omap: unlock the port lock
[deliverable/linux.git] / drivers / tty / serial / omap-serial.c
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/clk.h>
37 #include <linux/serial_core.h>
38 #include <linux/irq.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/of.h>
41 #include <linux/gpio.h>
42
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
45
46 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
47
48 #define OMAP_UART_REV_42 0x0402
49 #define OMAP_UART_REV_46 0x0406
50 #define OMAP_UART_REV_52 0x0502
51 #define OMAP_UART_REV_63 0x0603
52
53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
54
55 /* SCR register bitmasks */
56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
57
58 /* FCR register bitmasks */
59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
61
62 /* MVR register bitmasks */
63 #define OMAP_UART_MVR_SCHEME_SHIFT 30
64
65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
68
69 #define OMAP_UART_MVR_MAJ_MASK 0x700
70 #define OMAP_UART_MVR_MAJ_SHIFT 8
71 #define OMAP_UART_MVR_MIN_MASK 0x3f
72
73 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
74
75 /* Forward declaration of functions */
76 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
77
78 static struct workqueue_struct *serial_omap_uart_wq;
79
80 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
81 {
82 offset <<= up->port.regshift;
83 return readw(up->port.membase + offset);
84 }
85
86 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
87 {
88 offset <<= up->port.regshift;
89 writew(value, up->port.membase + offset);
90 }
91
92 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
93 {
94 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
95 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
96 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
97 serial_out(up, UART_FCR, 0);
98 }
99
100 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
101 {
102 struct omap_uart_port_info *pdata = up->dev->platform_data;
103
104 if (!pdata->get_context_loss_count)
105 return 0;
106
107 return pdata->get_context_loss_count(up->dev);
108 }
109
110 static void serial_omap_set_forceidle(struct uart_omap_port *up)
111 {
112 struct omap_uart_port_info *pdata = up->dev->platform_data;
113
114 if (pdata->set_forceidle)
115 pdata->set_forceidle(up->dev);
116 }
117
118 static void serial_omap_set_noidle(struct uart_omap_port *up)
119 {
120 struct omap_uart_port_info *pdata = up->dev->platform_data;
121
122 if (pdata->set_noidle)
123 pdata->set_noidle(up->dev);
124 }
125
126 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
127 {
128 struct omap_uart_port_info *pdata = up->dev->platform_data;
129
130 if (pdata->enable_wakeup)
131 pdata->enable_wakeup(up->dev, enable);
132 }
133
134 /*
135 * serial_omap_get_divisor - calculate divisor value
136 * @port: uart port info
137 * @baud: baudrate for which divisor needs to be calculated.
138 *
139 * We have written our own function to get the divisor so as to support
140 * 13x mode. 3Mbps Baudrate as an different divisor.
141 * Reference OMAP TRM Chapter 17:
142 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
143 * referring to oversampling - divisor value
144 * baudrate 460,800 to 3,686,400 all have divisor 13
145 * except 3,000,000 which has divisor value 16
146 */
147 static unsigned int
148 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
149 {
150 unsigned int divisor;
151
152 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
153 divisor = 13;
154 else
155 divisor = 16;
156 return port->uartclk/(baud * divisor);
157 }
158
159 static void serial_omap_enable_ms(struct uart_port *port)
160 {
161 struct uart_omap_port *up = to_uart_omap_port(port);
162
163 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
164
165 pm_runtime_get_sync(up->dev);
166 up->ier |= UART_IER_MSI;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(up->dev);
169 pm_runtime_put_autosuspend(up->dev);
170 }
171
172 static void serial_omap_stop_tx(struct uart_port *port)
173 {
174 struct uart_omap_port *up = to_uart_omap_port(port);
175
176 pm_runtime_get_sync(up->dev);
177 if (up->ier & UART_IER_THRI) {
178 up->ier &= ~UART_IER_THRI;
179 serial_out(up, UART_IER, up->ier);
180 }
181
182 serial_omap_set_forceidle(up);
183
184 pm_runtime_mark_last_busy(up->dev);
185 pm_runtime_put_autosuspend(up->dev);
186 }
187
188 static void serial_omap_stop_rx(struct uart_port *port)
189 {
190 struct uart_omap_port *up = to_uart_omap_port(port);
191
192 pm_runtime_get_sync(up->dev);
193 up->ier &= ~UART_IER_RLSI;
194 up->port.read_status_mask &= ~UART_LSR_DR;
195 serial_out(up, UART_IER, up->ier);
196 pm_runtime_mark_last_busy(up->dev);
197 pm_runtime_put_autosuspend(up->dev);
198 }
199
200 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
201 {
202 struct circ_buf *xmit = &up->port.state->xmit;
203 int count;
204
205 if (!(lsr & UART_LSR_THRE))
206 return;
207
208 if (up->port.x_char) {
209 serial_out(up, UART_TX, up->port.x_char);
210 up->port.icount.tx++;
211 up->port.x_char = 0;
212 return;
213 }
214 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
215 serial_omap_stop_tx(&up->port);
216 return;
217 }
218 count = up->port.fifosize / 4;
219 do {
220 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
221 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
222 up->port.icount.tx++;
223 if (uart_circ_empty(xmit))
224 break;
225 } while (--count > 0);
226
227 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
228 spin_unlock(&up->port.lock);
229 uart_write_wakeup(&up->port);
230 spin_lock(&up->port.lock);
231 }
232
233 if (uart_circ_empty(xmit))
234 serial_omap_stop_tx(&up->port);
235 }
236
237 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
238 {
239 if (!(up->ier & UART_IER_THRI)) {
240 up->ier |= UART_IER_THRI;
241 serial_out(up, UART_IER, up->ier);
242 }
243 }
244
245 static void serial_omap_start_tx(struct uart_port *port)
246 {
247 struct uart_omap_port *up = to_uart_omap_port(port);
248
249 pm_runtime_get_sync(up->dev);
250 serial_omap_enable_ier_thri(up);
251 serial_omap_set_noidle(up);
252 pm_runtime_mark_last_busy(up->dev);
253 pm_runtime_put_autosuspend(up->dev);
254 }
255
256 static unsigned int check_modem_status(struct uart_omap_port *up)
257 {
258 unsigned int status;
259
260 status = serial_in(up, UART_MSR);
261 status |= up->msr_saved_flags;
262 up->msr_saved_flags = 0;
263 if ((status & UART_MSR_ANY_DELTA) == 0)
264 return status;
265
266 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
267 up->port.state != NULL) {
268 if (status & UART_MSR_TERI)
269 up->port.icount.rng++;
270 if (status & UART_MSR_DDSR)
271 up->port.icount.dsr++;
272 if (status & UART_MSR_DDCD)
273 uart_handle_dcd_change
274 (&up->port, status & UART_MSR_DCD);
275 if (status & UART_MSR_DCTS)
276 uart_handle_cts_change
277 (&up->port, status & UART_MSR_CTS);
278 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
279 }
280
281 return status;
282 }
283
284 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
285 {
286 unsigned int flag;
287
288 up->port.icount.rx++;
289 flag = TTY_NORMAL;
290
291 if (lsr & UART_LSR_BI) {
292 flag = TTY_BREAK;
293 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
294 up->port.icount.brk++;
295 /*
296 * We do the SysRQ and SAK checking
297 * here because otherwise the break
298 * may get masked by ignore_status_mask
299 * or read_status_mask.
300 */
301 if (uart_handle_break(&up->port))
302 return;
303
304 }
305
306 if (lsr & UART_LSR_PE) {
307 flag = TTY_PARITY;
308 up->port.icount.parity++;
309 }
310
311 if (lsr & UART_LSR_FE) {
312 flag = TTY_FRAME;
313 up->port.icount.frame++;
314 }
315
316 if (lsr & UART_LSR_OE)
317 up->port.icount.overrun++;
318
319 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
320 if (up->port.line == up->port.cons->index) {
321 /* Recover the break flag from console xmit */
322 lsr |= up->lsr_break_flag;
323 }
324 #endif
325 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
326 }
327
328 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
329 {
330 unsigned char ch = 0;
331 unsigned int flag;
332
333 if (!(lsr & UART_LSR_DR))
334 return;
335
336 ch = serial_in(up, UART_RX);
337 flag = TTY_NORMAL;
338 up->port.icount.rx++;
339
340 if (uart_handle_sysrq_char(&up->port, ch))
341 return;
342
343 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
344 }
345
346 /**
347 * serial_omap_irq() - This handles the interrupt from one port
348 * @irq: uart port irq number
349 * @dev_id: uart port info
350 */
351 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
352 {
353 struct uart_omap_port *up = dev_id;
354 struct tty_struct *tty = up->port.state->port.tty;
355 unsigned int iir, lsr;
356 unsigned int type;
357 irqreturn_t ret = IRQ_NONE;
358 int max_count = 256;
359
360 spin_lock(&up->port.lock);
361 pm_runtime_get_sync(up->dev);
362
363 do {
364 iir = serial_in(up, UART_IIR);
365 if (iir & UART_IIR_NO_INT)
366 break;
367
368 ret = IRQ_HANDLED;
369 lsr = serial_in(up, UART_LSR);
370
371 /* extract IRQ type from IIR register */
372 type = iir & 0x3e;
373
374 switch (type) {
375 case UART_IIR_MSI:
376 check_modem_status(up);
377 break;
378 case UART_IIR_THRI:
379 transmit_chars(up, lsr);
380 break;
381 case UART_IIR_RX_TIMEOUT:
382 /* FALLTHROUGH */
383 case UART_IIR_RDI:
384 serial_omap_rdi(up, lsr);
385 break;
386 case UART_IIR_RLSI:
387 serial_omap_rlsi(up, lsr);
388 break;
389 case UART_IIR_CTS_RTS_DSR:
390 /* simply try again */
391 break;
392 case UART_IIR_XOFF:
393 /* FALLTHROUGH */
394 default:
395 break;
396 }
397 } while (!(iir & UART_IIR_NO_INT) && max_count--);
398
399 spin_unlock(&up->port.lock);
400
401 tty_flip_buffer_push(tty);
402
403 pm_runtime_mark_last_busy(up->dev);
404 pm_runtime_put_autosuspend(up->dev);
405 up->port_activity = jiffies;
406
407 return ret;
408 }
409
410 static unsigned int serial_omap_tx_empty(struct uart_port *port)
411 {
412 struct uart_omap_port *up = to_uart_omap_port(port);
413 unsigned long flags = 0;
414 unsigned int ret = 0;
415
416 pm_runtime_get_sync(up->dev);
417 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
418 spin_lock_irqsave(&up->port.lock, flags);
419 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
420 spin_unlock_irqrestore(&up->port.lock, flags);
421 pm_runtime_mark_last_busy(up->dev);
422 pm_runtime_put_autosuspend(up->dev);
423 return ret;
424 }
425
426 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
427 {
428 struct uart_omap_port *up = to_uart_omap_port(port);
429 unsigned int status;
430 unsigned int ret = 0;
431
432 pm_runtime_get_sync(up->dev);
433 status = check_modem_status(up);
434 pm_runtime_mark_last_busy(up->dev);
435 pm_runtime_put_autosuspend(up->dev);
436
437 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
438
439 if (status & UART_MSR_DCD)
440 ret |= TIOCM_CAR;
441 if (status & UART_MSR_RI)
442 ret |= TIOCM_RNG;
443 if (status & UART_MSR_DSR)
444 ret |= TIOCM_DSR;
445 if (status & UART_MSR_CTS)
446 ret |= TIOCM_CTS;
447 return ret;
448 }
449
450 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
451 {
452 struct uart_omap_port *up = to_uart_omap_port(port);
453 unsigned char mcr = 0;
454
455 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
456 if (mctrl & TIOCM_RTS)
457 mcr |= UART_MCR_RTS;
458 if (mctrl & TIOCM_DTR)
459 mcr |= UART_MCR_DTR;
460 if (mctrl & TIOCM_OUT1)
461 mcr |= UART_MCR_OUT1;
462 if (mctrl & TIOCM_OUT2)
463 mcr |= UART_MCR_OUT2;
464 if (mctrl & TIOCM_LOOP)
465 mcr |= UART_MCR_LOOP;
466
467 pm_runtime_get_sync(up->dev);
468 up->mcr = serial_in(up, UART_MCR);
469 up->mcr |= mcr;
470 serial_out(up, UART_MCR, up->mcr);
471 pm_runtime_mark_last_busy(up->dev);
472 pm_runtime_put_autosuspend(up->dev);
473
474 if (gpio_is_valid(up->DTR_gpio) &&
475 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
476 up->DTR_active = !up->DTR_active;
477 if (gpio_cansleep(up->DTR_gpio))
478 schedule_work(&up->qos_work);
479 else
480 gpio_set_value(up->DTR_gpio,
481 up->DTR_active != up->DTR_inverted);
482 }
483 }
484
485 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
486 {
487 struct uart_omap_port *up = to_uart_omap_port(port);
488 unsigned long flags = 0;
489
490 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
491 pm_runtime_get_sync(up->dev);
492 spin_lock_irqsave(&up->port.lock, flags);
493 if (break_state == -1)
494 up->lcr |= UART_LCR_SBC;
495 else
496 up->lcr &= ~UART_LCR_SBC;
497 serial_out(up, UART_LCR, up->lcr);
498 spin_unlock_irqrestore(&up->port.lock, flags);
499 pm_runtime_mark_last_busy(up->dev);
500 pm_runtime_put_autosuspend(up->dev);
501 }
502
503 static int serial_omap_startup(struct uart_port *port)
504 {
505 struct uart_omap_port *up = to_uart_omap_port(port);
506 unsigned long flags = 0;
507 int retval;
508
509 /*
510 * Allocate the IRQ
511 */
512 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
513 up->name, up);
514 if (retval)
515 return retval;
516
517 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
518
519 pm_runtime_get_sync(up->dev);
520 /*
521 * Clear the FIFO buffers and disable them.
522 * (they will be reenabled in set_termios())
523 */
524 serial_omap_clear_fifos(up);
525 /* For Hardware flow control */
526 serial_out(up, UART_MCR, UART_MCR_RTS);
527
528 /*
529 * Clear the interrupt registers.
530 */
531 (void) serial_in(up, UART_LSR);
532 if (serial_in(up, UART_LSR) & UART_LSR_DR)
533 (void) serial_in(up, UART_RX);
534 (void) serial_in(up, UART_IIR);
535 (void) serial_in(up, UART_MSR);
536
537 /*
538 * Now, initialize the UART
539 */
540 serial_out(up, UART_LCR, UART_LCR_WLEN8);
541 spin_lock_irqsave(&up->port.lock, flags);
542 /*
543 * Most PC uarts need OUT2 raised to enable interrupts.
544 */
545 up->port.mctrl |= TIOCM_OUT2;
546 serial_omap_set_mctrl(&up->port, up->port.mctrl);
547 spin_unlock_irqrestore(&up->port.lock, flags);
548
549 up->msr_saved_flags = 0;
550 /*
551 * Finally, enable interrupts. Note: Modem status interrupts
552 * are set via set_termios(), which will be occurring imminently
553 * anyway, so we don't enable them here.
554 */
555 up->ier = UART_IER_RLSI | UART_IER_RDI;
556 serial_out(up, UART_IER, up->ier);
557
558 /* Enable module level wake up */
559 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
560
561 pm_runtime_mark_last_busy(up->dev);
562 pm_runtime_put_autosuspend(up->dev);
563 up->port_activity = jiffies;
564 return 0;
565 }
566
567 static void serial_omap_shutdown(struct uart_port *port)
568 {
569 struct uart_omap_port *up = to_uart_omap_port(port);
570 unsigned long flags = 0;
571
572 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
573
574 pm_runtime_get_sync(up->dev);
575 /*
576 * Disable interrupts from this port
577 */
578 up->ier = 0;
579 serial_out(up, UART_IER, 0);
580
581 spin_lock_irqsave(&up->port.lock, flags);
582 up->port.mctrl &= ~TIOCM_OUT2;
583 serial_omap_set_mctrl(&up->port, up->port.mctrl);
584 spin_unlock_irqrestore(&up->port.lock, flags);
585
586 /*
587 * Disable break condition and FIFOs
588 */
589 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
590 serial_omap_clear_fifos(up);
591
592 /*
593 * Read data port to reset things, and then free the irq
594 */
595 if (serial_in(up, UART_LSR) & UART_LSR_DR)
596 (void) serial_in(up, UART_RX);
597
598 pm_runtime_mark_last_busy(up->dev);
599 pm_runtime_put_autosuspend(up->dev);
600 free_irq(up->port.irq, up);
601 }
602
603 static inline void
604 serial_omap_configure_xonxoff
605 (struct uart_omap_port *up, struct ktermios *termios)
606 {
607 up->lcr = serial_in(up, UART_LCR);
608 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
609 up->efr = serial_in(up, UART_EFR);
610 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
611
612 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
613 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
614
615 /* clear SW control mode bits */
616 up->efr &= OMAP_UART_SW_CLR;
617
618 /*
619 * IXON Flag:
620 * Enable XON/XOFF flow control on output.
621 * Transmit XON1, XOFF1
622 */
623 if (termios->c_iflag & IXON)
624 up->efr |= OMAP_UART_SW_TX;
625
626 /*
627 * IXOFF Flag:
628 * Enable XON/XOFF flow control on input.
629 * Receiver compares XON1, XOFF1.
630 */
631 if (termios->c_iflag & IXOFF)
632 up->efr |= OMAP_UART_SW_RX;
633
634 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
635 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
636
637 up->mcr = serial_in(up, UART_MCR);
638
639 /*
640 * IXANY Flag:
641 * Enable any character to restart output.
642 * Operation resumes after receiving any
643 * character after recognition of the XOFF character
644 */
645 if (termios->c_iflag & IXANY)
646 up->mcr |= UART_MCR_XONANY;
647
648 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
649 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
650 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
651 /* Enable special char function UARTi.EFR_REG[5] and
652 * load the new software flow control mode IXON or IXOFF
653 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
654 */
655 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
656 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
657
658 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
659 serial_out(up, UART_LCR, up->lcr);
660 }
661
662 static void serial_omap_uart_qos_work(struct work_struct *work)
663 {
664 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
665 qos_work);
666
667 pm_qos_update_request(&up->pm_qos_request, up->latency);
668 if (gpio_is_valid(up->DTR_gpio))
669 gpio_set_value_cansleep(up->DTR_gpio,
670 up->DTR_active != up->DTR_inverted);
671 }
672
673 static void
674 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
675 struct ktermios *old)
676 {
677 struct uart_omap_port *up = to_uart_omap_port(port);
678 unsigned char cval = 0;
679 unsigned char efr = 0;
680 unsigned long flags = 0;
681 unsigned int baud, quot;
682
683 switch (termios->c_cflag & CSIZE) {
684 case CS5:
685 cval = UART_LCR_WLEN5;
686 break;
687 case CS6:
688 cval = UART_LCR_WLEN6;
689 break;
690 case CS7:
691 cval = UART_LCR_WLEN7;
692 break;
693 default:
694 case CS8:
695 cval = UART_LCR_WLEN8;
696 break;
697 }
698
699 if (termios->c_cflag & CSTOPB)
700 cval |= UART_LCR_STOP;
701 if (termios->c_cflag & PARENB)
702 cval |= UART_LCR_PARITY;
703 if (!(termios->c_cflag & PARODD))
704 cval |= UART_LCR_EPAR;
705
706 /*
707 * Ask the core to calculate the divisor for us.
708 */
709
710 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
711 quot = serial_omap_get_divisor(port, baud);
712
713 /* calculate wakeup latency constraint */
714 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
715 up->latency = up->calc_latency;
716 schedule_work(&up->qos_work);
717
718 up->dll = quot & 0xff;
719 up->dlh = quot >> 8;
720 up->mdr1 = UART_OMAP_MDR1_DISABLE;
721
722 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
723 UART_FCR_ENABLE_FIFO;
724
725 /*
726 * Ok, we're now changing the port state. Do it with
727 * interrupts disabled.
728 */
729 pm_runtime_get_sync(up->dev);
730 spin_lock_irqsave(&up->port.lock, flags);
731
732 /*
733 * Update the per-port timeout.
734 */
735 uart_update_timeout(port, termios->c_cflag, baud);
736
737 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
738 if (termios->c_iflag & INPCK)
739 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
740 if (termios->c_iflag & (BRKINT | PARMRK))
741 up->port.read_status_mask |= UART_LSR_BI;
742
743 /*
744 * Characters to ignore
745 */
746 up->port.ignore_status_mask = 0;
747 if (termios->c_iflag & IGNPAR)
748 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
749 if (termios->c_iflag & IGNBRK) {
750 up->port.ignore_status_mask |= UART_LSR_BI;
751 /*
752 * If we're ignoring parity and break indicators,
753 * ignore overruns too (for real raw support).
754 */
755 if (termios->c_iflag & IGNPAR)
756 up->port.ignore_status_mask |= UART_LSR_OE;
757 }
758
759 /*
760 * ignore all characters if CREAD is not set
761 */
762 if ((termios->c_cflag & CREAD) == 0)
763 up->port.ignore_status_mask |= UART_LSR_DR;
764
765 /*
766 * Modem status interrupts
767 */
768 up->ier &= ~UART_IER_MSI;
769 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
770 up->ier |= UART_IER_MSI;
771 serial_out(up, UART_IER, up->ier);
772 serial_out(up, UART_LCR, cval); /* reset DLAB */
773 up->lcr = cval;
774 up->scr = OMAP_UART_SCR_TX_EMPTY;
775
776 /* FIFOs and DMA Settings */
777
778 /* FCR can be changed only when the
779 * baud clock is not running
780 * DLL_REG and DLH_REG set to 0.
781 */
782 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
783 serial_out(up, UART_DLL, 0);
784 serial_out(up, UART_DLM, 0);
785 serial_out(up, UART_LCR, 0);
786
787 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
788
789 up->efr = serial_in(up, UART_EFR);
790 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
791
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 up->mcr = serial_in(up, UART_MCR);
794 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
795 /* FIFO ENABLE, DMA MODE */
796
797 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
798
799 /* Set receive FIFO threshold to 1 byte */
800 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
801 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
802
803 serial_out(up, UART_FCR, up->fcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
805
806 serial_out(up, UART_OMAP_SCR, up->scr);
807
808 serial_out(up, UART_EFR, up->efr);
809 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
810 serial_out(up, UART_MCR, up->mcr);
811
812 /* Protocol, Baud Rate, and Interrupt Settings */
813
814 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
815 serial_omap_mdr1_errataset(up, up->mdr1);
816 else
817 serial_out(up, UART_OMAP_MDR1, up->mdr1);
818
819 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
820
821 up->efr = serial_in(up, UART_EFR);
822 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
823
824 serial_out(up, UART_LCR, 0);
825 serial_out(up, UART_IER, 0);
826 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
827
828 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
829 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
830
831 serial_out(up, UART_LCR, 0);
832 serial_out(up, UART_IER, up->ier);
833 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
834
835 serial_out(up, UART_EFR, up->efr);
836 serial_out(up, UART_LCR, cval);
837
838 if (baud > 230400 && baud != 3000000)
839 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
840 else
841 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
842
843 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
844 serial_omap_mdr1_errataset(up, up->mdr1);
845 else
846 serial_out(up, UART_OMAP_MDR1, up->mdr1);
847
848 /* Hardware Flow Control Configuration */
849
850 if (termios->c_cflag & CRTSCTS) {
851 efr |= (UART_EFR_CTS | UART_EFR_RTS);
852 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
853
854 up->mcr = serial_in(up, UART_MCR);
855 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
856
857 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
858 up->efr = serial_in(up, UART_EFR);
859 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
860
861 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
862 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
863 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
864 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
865 serial_out(up, UART_LCR, cval);
866 }
867
868 serial_omap_set_mctrl(&up->port, up->port.mctrl);
869 /* Software Flow Control Configuration */
870 serial_omap_configure_xonxoff(up, termios);
871
872 spin_unlock_irqrestore(&up->port.lock, flags);
873 pm_runtime_mark_last_busy(up->dev);
874 pm_runtime_put_autosuspend(up->dev);
875 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
876 }
877
878 static void
879 serial_omap_pm(struct uart_port *port, unsigned int state,
880 unsigned int oldstate)
881 {
882 struct uart_omap_port *up = to_uart_omap_port(port);
883 unsigned char efr;
884
885 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
886
887 pm_runtime_get_sync(up->dev);
888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
889 efr = serial_in(up, UART_EFR);
890 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
891 serial_out(up, UART_LCR, 0);
892
893 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
895 serial_out(up, UART_EFR, efr);
896 serial_out(up, UART_LCR, 0);
897
898 if (!device_may_wakeup(up->dev)) {
899 if (!state)
900 pm_runtime_forbid(up->dev);
901 else
902 pm_runtime_allow(up->dev);
903 }
904
905 pm_runtime_mark_last_busy(up->dev);
906 pm_runtime_put_autosuspend(up->dev);
907 }
908
909 static void serial_omap_release_port(struct uart_port *port)
910 {
911 dev_dbg(port->dev, "serial_omap_release_port+\n");
912 }
913
914 static int serial_omap_request_port(struct uart_port *port)
915 {
916 dev_dbg(port->dev, "serial_omap_request_port+\n");
917 return 0;
918 }
919
920 static void serial_omap_config_port(struct uart_port *port, int flags)
921 {
922 struct uart_omap_port *up = to_uart_omap_port(port);
923
924 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
925 up->port.line);
926 up->port.type = PORT_OMAP;
927 }
928
929 static int
930 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
931 {
932 /* we don't want the core code to modify any port params */
933 dev_dbg(port->dev, "serial_omap_verify_port+\n");
934 return -EINVAL;
935 }
936
937 static const char *
938 serial_omap_type(struct uart_port *port)
939 {
940 struct uart_omap_port *up = to_uart_omap_port(port);
941
942 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
943 return up->name;
944 }
945
946 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
947
948 static inline void wait_for_xmitr(struct uart_omap_port *up)
949 {
950 unsigned int status, tmout = 10000;
951
952 /* Wait up to 10ms for the character(s) to be sent. */
953 do {
954 status = serial_in(up, UART_LSR);
955
956 if (status & UART_LSR_BI)
957 up->lsr_break_flag = UART_LSR_BI;
958
959 if (--tmout == 0)
960 break;
961 udelay(1);
962 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
963
964 /* Wait up to 1s for flow control if necessary */
965 if (up->port.flags & UPF_CONS_FLOW) {
966 tmout = 1000000;
967 for (tmout = 1000000; tmout; tmout--) {
968 unsigned int msr = serial_in(up, UART_MSR);
969
970 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
971 if (msr & UART_MSR_CTS)
972 break;
973
974 udelay(1);
975 }
976 }
977 }
978
979 #ifdef CONFIG_CONSOLE_POLL
980
981 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
982 {
983 struct uart_omap_port *up = to_uart_omap_port(port);
984
985 pm_runtime_get_sync(up->dev);
986 wait_for_xmitr(up);
987 serial_out(up, UART_TX, ch);
988 pm_runtime_mark_last_busy(up->dev);
989 pm_runtime_put_autosuspend(up->dev);
990 }
991
992 static int serial_omap_poll_get_char(struct uart_port *port)
993 {
994 struct uart_omap_port *up = to_uart_omap_port(port);
995 unsigned int status;
996
997 pm_runtime_get_sync(up->dev);
998 status = serial_in(up, UART_LSR);
999 if (!(status & UART_LSR_DR))
1000 return NO_POLL_CHAR;
1001
1002 status = serial_in(up, UART_RX);
1003 pm_runtime_mark_last_busy(up->dev);
1004 pm_runtime_put_autosuspend(up->dev);
1005 return status;
1006 }
1007
1008 #endif /* CONFIG_CONSOLE_POLL */
1009
1010 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1011
1012 static struct uart_omap_port *serial_omap_console_ports[4];
1013
1014 static struct uart_driver serial_omap_reg;
1015
1016 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1017 {
1018 struct uart_omap_port *up = to_uart_omap_port(port);
1019
1020 wait_for_xmitr(up);
1021 serial_out(up, UART_TX, ch);
1022 }
1023
1024 static void
1025 serial_omap_console_write(struct console *co, const char *s,
1026 unsigned int count)
1027 {
1028 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1029 unsigned long flags;
1030 unsigned int ier;
1031 int locked = 1;
1032
1033 pm_runtime_get_sync(up->dev);
1034
1035 local_irq_save(flags);
1036 if (up->port.sysrq)
1037 locked = 0;
1038 else if (oops_in_progress)
1039 locked = spin_trylock(&up->port.lock);
1040 else
1041 spin_lock(&up->port.lock);
1042
1043 /*
1044 * First save the IER then disable the interrupts
1045 */
1046 ier = serial_in(up, UART_IER);
1047 serial_out(up, UART_IER, 0);
1048
1049 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1050
1051 /*
1052 * Finally, wait for transmitter to become empty
1053 * and restore the IER
1054 */
1055 wait_for_xmitr(up);
1056 serial_out(up, UART_IER, ier);
1057 /*
1058 * The receive handling will happen properly because the
1059 * receive ready bit will still be set; it is not cleared
1060 * on read. However, modem control will not, we must
1061 * call it if we have saved something in the saved flags
1062 * while processing with interrupts off.
1063 */
1064 if (up->msr_saved_flags)
1065 check_modem_status(up);
1066
1067 pm_runtime_mark_last_busy(up->dev);
1068 pm_runtime_put_autosuspend(up->dev);
1069 if (locked)
1070 spin_unlock(&up->port.lock);
1071 local_irq_restore(flags);
1072 }
1073
1074 static int __init
1075 serial_omap_console_setup(struct console *co, char *options)
1076 {
1077 struct uart_omap_port *up;
1078 int baud = 115200;
1079 int bits = 8;
1080 int parity = 'n';
1081 int flow = 'n';
1082
1083 if (serial_omap_console_ports[co->index] == NULL)
1084 return -ENODEV;
1085 up = serial_omap_console_ports[co->index];
1086
1087 if (options)
1088 uart_parse_options(options, &baud, &parity, &bits, &flow);
1089
1090 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1091 }
1092
1093 static struct console serial_omap_console = {
1094 .name = OMAP_SERIAL_NAME,
1095 .write = serial_omap_console_write,
1096 .device = uart_console_device,
1097 .setup = serial_omap_console_setup,
1098 .flags = CON_PRINTBUFFER,
1099 .index = -1,
1100 .data = &serial_omap_reg,
1101 };
1102
1103 static void serial_omap_add_console_port(struct uart_omap_port *up)
1104 {
1105 serial_omap_console_ports[up->port.line] = up;
1106 }
1107
1108 #define OMAP_CONSOLE (&serial_omap_console)
1109
1110 #else
1111
1112 #define OMAP_CONSOLE NULL
1113
1114 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1115 {}
1116
1117 #endif
1118
1119 static struct uart_ops serial_omap_pops = {
1120 .tx_empty = serial_omap_tx_empty,
1121 .set_mctrl = serial_omap_set_mctrl,
1122 .get_mctrl = serial_omap_get_mctrl,
1123 .stop_tx = serial_omap_stop_tx,
1124 .start_tx = serial_omap_start_tx,
1125 .stop_rx = serial_omap_stop_rx,
1126 .enable_ms = serial_omap_enable_ms,
1127 .break_ctl = serial_omap_break_ctl,
1128 .startup = serial_omap_startup,
1129 .shutdown = serial_omap_shutdown,
1130 .set_termios = serial_omap_set_termios,
1131 .pm = serial_omap_pm,
1132 .type = serial_omap_type,
1133 .release_port = serial_omap_release_port,
1134 .request_port = serial_omap_request_port,
1135 .config_port = serial_omap_config_port,
1136 .verify_port = serial_omap_verify_port,
1137 #ifdef CONFIG_CONSOLE_POLL
1138 .poll_put_char = serial_omap_poll_put_char,
1139 .poll_get_char = serial_omap_poll_get_char,
1140 #endif
1141 };
1142
1143 static struct uart_driver serial_omap_reg = {
1144 .owner = THIS_MODULE,
1145 .driver_name = "OMAP-SERIAL",
1146 .dev_name = OMAP_SERIAL_NAME,
1147 .nr = OMAP_MAX_HSUART_PORTS,
1148 .cons = OMAP_CONSOLE,
1149 };
1150
1151 #ifdef CONFIG_PM_SLEEP
1152 static int serial_omap_suspend(struct device *dev)
1153 {
1154 struct uart_omap_port *up = dev_get_drvdata(dev);
1155
1156 if (up) {
1157 uart_suspend_port(&serial_omap_reg, &up->port);
1158 flush_work_sync(&up->qos_work);
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int serial_omap_resume(struct device *dev)
1165 {
1166 struct uart_omap_port *up = dev_get_drvdata(dev);
1167
1168 if (up)
1169 uart_resume_port(&serial_omap_reg, &up->port);
1170 return 0;
1171 }
1172 #endif
1173
1174 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1175 {
1176 u32 mvr, scheme;
1177 u16 revision, major, minor;
1178
1179 mvr = serial_in(up, UART_OMAP_MVER);
1180
1181 /* Check revision register scheme */
1182 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1183
1184 switch (scheme) {
1185 case 0: /* Legacy Scheme: OMAP2/3 */
1186 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1187 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1188 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1189 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1190 break;
1191 case 1:
1192 /* New Scheme: OMAP4+ */
1193 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1194 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1195 OMAP_UART_MVR_MAJ_SHIFT;
1196 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1197 break;
1198 default:
1199 dev_warn(up->dev,
1200 "Unknown %s revision, defaulting to highest\n",
1201 up->name);
1202 /* highest possible revision */
1203 major = 0xff;
1204 minor = 0xff;
1205 }
1206
1207 /* normalize revision for the driver */
1208 revision = UART_BUILD_REVISION(major, minor);
1209
1210 switch (revision) {
1211 case OMAP_UART_REV_46:
1212 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1213 UART_ERRATA_i291_DMA_FORCEIDLE);
1214 break;
1215 case OMAP_UART_REV_52:
1216 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1217 UART_ERRATA_i291_DMA_FORCEIDLE);
1218 break;
1219 case OMAP_UART_REV_63:
1220 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1221 break;
1222 default:
1223 break;
1224 }
1225 }
1226
1227 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1228 {
1229 struct omap_uart_port_info *omap_up_info;
1230
1231 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1232 if (!omap_up_info)
1233 return NULL; /* out of memory */
1234
1235 of_property_read_u32(dev->of_node, "clock-frequency",
1236 &omap_up_info->uartclk);
1237 return omap_up_info;
1238 }
1239
1240 static int __devinit serial_omap_probe(struct platform_device *pdev)
1241 {
1242 struct uart_omap_port *up;
1243 struct resource *mem, *irq;
1244 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1245 int ret;
1246
1247 if (pdev->dev.of_node)
1248 omap_up_info = of_get_uart_port_info(&pdev->dev);
1249
1250 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1251 if (!mem) {
1252 dev_err(&pdev->dev, "no mem resource?\n");
1253 return -ENODEV;
1254 }
1255
1256 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1257 if (!irq) {
1258 dev_err(&pdev->dev, "no irq resource?\n");
1259 return -ENODEV;
1260 }
1261
1262 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1263 pdev->dev.driver->name)) {
1264 dev_err(&pdev->dev, "memory region already claimed\n");
1265 return -EBUSY;
1266 }
1267
1268 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1269 omap_up_info->DTR_present) {
1270 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1271 if (ret < 0)
1272 return ret;
1273 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1274 omap_up_info->DTR_inverted);
1275 if (ret < 0)
1276 return ret;
1277 }
1278
1279 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1280 if (!up)
1281 return -ENOMEM;
1282
1283 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1284 omap_up_info->DTR_present) {
1285 up->DTR_gpio = omap_up_info->DTR_gpio;
1286 up->DTR_inverted = omap_up_info->DTR_inverted;
1287 } else
1288 up->DTR_gpio = -EINVAL;
1289 up->DTR_active = 0;
1290
1291 up->dev = &pdev->dev;
1292 up->port.dev = &pdev->dev;
1293 up->port.type = PORT_OMAP;
1294 up->port.iotype = UPIO_MEM;
1295 up->port.irq = irq->start;
1296
1297 up->port.regshift = 2;
1298 up->port.fifosize = 64;
1299 up->port.ops = &serial_omap_pops;
1300
1301 if (pdev->dev.of_node)
1302 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1303 else
1304 up->port.line = pdev->id;
1305
1306 if (up->port.line < 0) {
1307 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1308 up->port.line);
1309 ret = -ENODEV;
1310 goto err_port_line;
1311 }
1312
1313 sprintf(up->name, "OMAP UART%d", up->port.line);
1314 up->port.mapbase = mem->start;
1315 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1316 resource_size(mem));
1317 if (!up->port.membase) {
1318 dev_err(&pdev->dev, "can't ioremap UART\n");
1319 ret = -ENOMEM;
1320 goto err_ioremap;
1321 }
1322
1323 up->port.flags = omap_up_info->flags;
1324 up->port.uartclk = omap_up_info->uartclk;
1325 if (!up->port.uartclk) {
1326 up->port.uartclk = DEFAULT_CLK_SPEED;
1327 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1328 "%d\n", DEFAULT_CLK_SPEED);
1329 }
1330
1331 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1332 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1333 pm_qos_add_request(&up->pm_qos_request,
1334 PM_QOS_CPU_DMA_LATENCY, up->latency);
1335 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1336 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1337
1338 platform_set_drvdata(pdev, up);
1339 pm_runtime_enable(&pdev->dev);
1340 pm_runtime_use_autosuspend(&pdev->dev);
1341 pm_runtime_set_autosuspend_delay(&pdev->dev,
1342 omap_up_info->autosuspend_timeout);
1343
1344 pm_runtime_irq_safe(&pdev->dev);
1345 pm_runtime_get_sync(&pdev->dev);
1346
1347 omap_serial_fill_features_erratas(up);
1348
1349 ui[up->port.line] = up;
1350 serial_omap_add_console_port(up);
1351
1352 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1353 if (ret != 0)
1354 goto err_add_port;
1355
1356 pm_runtime_mark_last_busy(up->dev);
1357 pm_runtime_put_autosuspend(up->dev);
1358 return 0;
1359
1360 err_add_port:
1361 pm_runtime_put(&pdev->dev);
1362 pm_runtime_disable(&pdev->dev);
1363 err_ioremap:
1364 err_port_line:
1365 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1366 pdev->id, __func__, ret);
1367 return ret;
1368 }
1369
1370 static int __devexit serial_omap_remove(struct platform_device *dev)
1371 {
1372 struct uart_omap_port *up = platform_get_drvdata(dev);
1373
1374 pm_runtime_put_sync(up->dev);
1375 pm_runtime_disable(up->dev);
1376 uart_remove_one_port(&serial_omap_reg, &up->port);
1377 pm_qos_remove_request(&up->pm_qos_request);
1378
1379 return 0;
1380 }
1381
1382 /*
1383 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1384 * The access to uart register after MDR1 Access
1385 * causes UART to corrupt data.
1386 *
1387 * Need a delay =
1388 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1389 * give 10 times as much
1390 */
1391 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1392 {
1393 u8 timeout = 255;
1394
1395 serial_out(up, UART_OMAP_MDR1, mdr1);
1396 udelay(2);
1397 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1398 UART_FCR_CLEAR_RCVR);
1399 /*
1400 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1401 * TX_FIFO_E bit is 1.
1402 */
1403 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1404 (UART_LSR_THRE | UART_LSR_DR))) {
1405 timeout--;
1406 if (!timeout) {
1407 /* Should *never* happen. we warn and carry on */
1408 dev_crit(up->dev, "Errata i202: timedout %x\n",
1409 serial_in(up, UART_LSR));
1410 break;
1411 }
1412 udelay(1);
1413 }
1414 }
1415
1416 #ifdef CONFIG_PM_RUNTIME
1417 static void serial_omap_restore_context(struct uart_omap_port *up)
1418 {
1419 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1420 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1421 else
1422 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1423
1424 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1425 serial_out(up, UART_EFR, UART_EFR_ECB);
1426 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1427 serial_out(up, UART_IER, 0x0);
1428 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1429 serial_out(up, UART_DLL, up->dll);
1430 serial_out(up, UART_DLM, up->dlh);
1431 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1432 serial_out(up, UART_IER, up->ier);
1433 serial_out(up, UART_FCR, up->fcr);
1434 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1435 serial_out(up, UART_MCR, up->mcr);
1436 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1437 serial_out(up, UART_OMAP_SCR, up->scr);
1438 serial_out(up, UART_EFR, up->efr);
1439 serial_out(up, UART_LCR, up->lcr);
1440 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1441 serial_omap_mdr1_errataset(up, up->mdr1);
1442 else
1443 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1444 }
1445
1446 static int serial_omap_runtime_suspend(struct device *dev)
1447 {
1448 struct uart_omap_port *up = dev_get_drvdata(dev);
1449 struct omap_uart_port_info *pdata = dev->platform_data;
1450
1451 if (!up)
1452 return -EINVAL;
1453
1454 if (!pdata)
1455 return 0;
1456
1457 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1458
1459 if (device_may_wakeup(dev)) {
1460 if (!up->wakeups_enabled) {
1461 serial_omap_enable_wakeup(up, true);
1462 up->wakeups_enabled = true;
1463 }
1464 } else {
1465 if (up->wakeups_enabled) {
1466 serial_omap_enable_wakeup(up, false);
1467 up->wakeups_enabled = false;
1468 }
1469 }
1470
1471 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1472 schedule_work(&up->qos_work);
1473
1474 return 0;
1475 }
1476
1477 static int serial_omap_runtime_resume(struct device *dev)
1478 {
1479 struct uart_omap_port *up = dev_get_drvdata(dev);
1480 struct omap_uart_port_info *pdata = dev->platform_data;
1481
1482 if (up && pdata) {
1483 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1484
1485 if (up->context_loss_cnt != loss_cnt)
1486 serial_omap_restore_context(up);
1487
1488 up->latency = up->calc_latency;
1489 schedule_work(&up->qos_work);
1490 }
1491
1492 return 0;
1493 }
1494 #endif
1495
1496 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1497 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1498 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1499 serial_omap_runtime_resume, NULL)
1500 };
1501
1502 #if defined(CONFIG_OF)
1503 static const struct of_device_id omap_serial_of_match[] = {
1504 { .compatible = "ti,omap2-uart" },
1505 { .compatible = "ti,omap3-uart" },
1506 { .compatible = "ti,omap4-uart" },
1507 {},
1508 };
1509 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1510 #endif
1511
1512 static struct platform_driver serial_omap_driver = {
1513 .probe = serial_omap_probe,
1514 .remove = __devexit_p(serial_omap_remove),
1515 .driver = {
1516 .name = DRIVER_NAME,
1517 .pm = &serial_omap_dev_pm_ops,
1518 .of_match_table = of_match_ptr(omap_serial_of_match),
1519 },
1520 };
1521
1522 static int __init serial_omap_init(void)
1523 {
1524 int ret;
1525
1526 ret = uart_register_driver(&serial_omap_reg);
1527 if (ret != 0)
1528 return ret;
1529 ret = platform_driver_register(&serial_omap_driver);
1530 if (ret != 0)
1531 uart_unregister_driver(&serial_omap_reg);
1532 return ret;
1533 }
1534
1535 static void __exit serial_omap_exit(void)
1536 {
1537 platform_driver_unregister(&serial_omap_driver);
1538 uart_unregister_driver(&serial_omap_reg);
1539 }
1540
1541 module_init(serial_omap_init);
1542 module_exit(serial_omap_exit);
1543
1544 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1545 MODULE_LICENSE("GPL");
1546 MODULE_AUTHOR("Texas Instruments Inc");
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