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pch_uart: Add MSI support
[deliverable/linux.git] / drivers / tty / serial / pch_uart.c
1 /*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/dmi.h>
26
27 #include <linux/dmaengine.h>
28 #include <linux/pch_dma.h>
29
30 enum {
31 PCH_UART_HANDLED_RX_INT_SHIFT,
32 PCH_UART_HANDLED_TX_INT_SHIFT,
33 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
34 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
35 PCH_UART_HANDLED_MS_INT_SHIFT,
36 };
37
38 enum {
39 PCH_UART_8LINE,
40 PCH_UART_2LINE,
41 };
42
43 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
44
45 /* Set the max number of UART port
46 * Intel EG20T PCH: 4 port
47 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
48 */
49 #define PCH_UART_NR 4
50
51 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
52 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
53 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
54 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
55 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
56 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
57 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
58
59 #define PCH_UART_RBR 0x00
60 #define PCH_UART_THR 0x00
61
62 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
63 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
64 #define PCH_UART_IER_ERBFI 0x00000001
65 #define PCH_UART_IER_ETBEI 0x00000002
66 #define PCH_UART_IER_ELSI 0x00000004
67 #define PCH_UART_IER_EDSSI 0x00000008
68
69 #define PCH_UART_IIR_IP 0x00000001
70 #define PCH_UART_IIR_IID 0x00000006
71 #define PCH_UART_IIR_MSI 0x00000000
72 #define PCH_UART_IIR_TRI 0x00000002
73 #define PCH_UART_IIR_RRI 0x00000004
74 #define PCH_UART_IIR_REI 0x00000006
75 #define PCH_UART_IIR_TOI 0x00000008
76 #define PCH_UART_IIR_FIFO256 0x00000020
77 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
78 #define PCH_UART_IIR_FE 0x000000C0
79
80 #define PCH_UART_FCR_FIFOE 0x00000001
81 #define PCH_UART_FCR_RFR 0x00000002
82 #define PCH_UART_FCR_TFR 0x00000004
83 #define PCH_UART_FCR_DMS 0x00000008
84 #define PCH_UART_FCR_FIFO256 0x00000020
85 #define PCH_UART_FCR_RFTL 0x000000C0
86
87 #define PCH_UART_FCR_RFTL1 0x00000000
88 #define PCH_UART_FCR_RFTL64 0x00000040
89 #define PCH_UART_FCR_RFTL128 0x00000080
90 #define PCH_UART_FCR_RFTL224 0x000000C0
91 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
92 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
93 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
94 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
95 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
96 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
97 #define PCH_UART_FCR_RFTL_SHIFT 6
98
99 #define PCH_UART_LCR_WLS 0x00000003
100 #define PCH_UART_LCR_STB 0x00000004
101 #define PCH_UART_LCR_PEN 0x00000008
102 #define PCH_UART_LCR_EPS 0x00000010
103 #define PCH_UART_LCR_SP 0x00000020
104 #define PCH_UART_LCR_SB 0x00000040
105 #define PCH_UART_LCR_DLAB 0x00000080
106 #define PCH_UART_LCR_NP 0x00000000
107 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
108 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
109 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
110 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
111 PCH_UART_LCR_SP)
112
113 #define PCH_UART_LCR_5BIT 0x00000000
114 #define PCH_UART_LCR_6BIT 0x00000001
115 #define PCH_UART_LCR_7BIT 0x00000002
116 #define PCH_UART_LCR_8BIT 0x00000003
117
118 #define PCH_UART_MCR_DTR 0x00000001
119 #define PCH_UART_MCR_RTS 0x00000002
120 #define PCH_UART_MCR_OUT 0x0000000C
121 #define PCH_UART_MCR_LOOP 0x00000010
122 #define PCH_UART_MCR_AFE 0x00000020
123
124 #define PCH_UART_LSR_DR 0x00000001
125 #define PCH_UART_LSR_ERR (1<<7)
126
127 #define PCH_UART_MSR_DCTS 0x00000001
128 #define PCH_UART_MSR_DDSR 0x00000002
129 #define PCH_UART_MSR_TERI 0x00000004
130 #define PCH_UART_MSR_DDCD 0x00000008
131 #define PCH_UART_MSR_CTS 0x00000010
132 #define PCH_UART_MSR_DSR 0x00000020
133 #define PCH_UART_MSR_RI 0x00000040
134 #define PCH_UART_MSR_DCD 0x00000080
135 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
136 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
137
138 #define PCH_UART_DLL 0x00
139 #define PCH_UART_DLM 0x01
140
141 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
142 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
143 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
144 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
145 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
146
147 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
148 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
149 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
150 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
151 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
152 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
153 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
154 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
155 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
156 #define PCH_UART_HAL_STB1 0
157 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
158
159 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
160 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
161 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
162 PCH_UART_HAL_CLR_RX_FIFO)
163
164 #define PCH_UART_HAL_DMA_MODE0 0
165 #define PCH_UART_HAL_FIFO_DIS 0
166 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
167 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
168 PCH_UART_FCR_FIFO256)
169 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
170 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
171 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
172 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
173 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
174 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
175 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
176 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
177 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
178 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
179 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
180 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
181 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
182 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
183
184 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
185 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
186 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
187 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
188 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
189
190 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
191 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
192 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
193 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
194 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
195
196 #define PCI_VENDOR_ID_ROHM 0x10DB
197
198 struct pch_uart_buffer {
199 unsigned char *buf;
200 int size;
201 };
202
203 struct eg20t_port {
204 struct uart_port port;
205 int port_type;
206 void __iomem *membase;
207 resource_size_t mapbase;
208 unsigned int iobase;
209 struct pci_dev *pdev;
210 int fifo_size;
211 int base_baud;
212 int start_tx;
213 int start_rx;
214 int tx_empty;
215 int int_dis_flag;
216 int trigger;
217 int trigger_level;
218 struct pch_uart_buffer rxbuf;
219 unsigned int dmsr;
220 unsigned int fcr;
221 unsigned int mcr;
222 unsigned int use_dma;
223 unsigned int use_dma_flag;
224 struct dma_async_tx_descriptor *desc_tx;
225 struct dma_async_tx_descriptor *desc_rx;
226 struct pch_dma_slave param_tx;
227 struct pch_dma_slave param_rx;
228 struct dma_chan *chan_tx;
229 struct dma_chan *chan_rx;
230 struct scatterlist *sg_tx_p;
231 int nent;
232 struct scatterlist sg_rx;
233 int tx_dma_use;
234 void *rx_buf_virt;
235 dma_addr_t rx_buf_dma;
236 };
237
238 /**
239 * struct pch_uart_driver_data - private data structure for UART-DMA
240 * @port_type: The number of DMA channel
241 * @line_no: UART port line number (0, 1, 2...)
242 */
243 struct pch_uart_driver_data {
244 int port_type;
245 int line_no;
246 };
247
248 enum pch_uart_num_t {
249 pch_et20t_uart0 = 0,
250 pch_et20t_uart1,
251 pch_et20t_uart2,
252 pch_et20t_uart3,
253 pch_ml7213_uart0,
254 pch_ml7213_uart1,
255 pch_ml7213_uart2,
256 pch_ml7223_uart0,
257 pch_ml7223_uart1,
258 };
259
260 static struct pch_uart_driver_data drv_dat[] = {
261 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
262 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
263 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
264 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
265 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
266 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
267 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
268 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
269 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
270 };
271
272 static unsigned int default_baud = 9600;
273 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
274 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
275 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
276 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
277
278 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
279 int base_baud)
280 {
281 struct eg20t_port *priv = pci_get_drvdata(pdev);
282
283 priv->trigger_level = 1;
284 priv->fcr = 0;
285 }
286
287 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
288 {
289 unsigned int msr = ioread8(base + UART_MSR);
290 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
291
292 return msr;
293 }
294
295 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
296 unsigned int flag)
297 {
298 u8 ier = ioread8(priv->membase + UART_IER);
299 ier |= flag & PCH_UART_IER_MASK;
300 iowrite8(ier, priv->membase + UART_IER);
301 }
302
303 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
304 unsigned int flag)
305 {
306 u8 ier = ioread8(priv->membase + UART_IER);
307 ier &= ~(flag & PCH_UART_IER_MASK);
308 iowrite8(ier, priv->membase + UART_IER);
309 }
310
311 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
312 unsigned int parity, unsigned int bits,
313 unsigned int stb)
314 {
315 unsigned int dll, dlm, lcr;
316 int div;
317
318 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
319 if (div < 0 || USHRT_MAX <= div) {
320 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
321 return -EINVAL;
322 }
323
324 dll = (unsigned int)div & 0x00FFU;
325 dlm = ((unsigned int)div >> 8) & 0x00FFU;
326
327 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
328 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
329 return -EINVAL;
330 }
331
332 if (bits & ~PCH_UART_LCR_WLS) {
333 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
334 return -EINVAL;
335 }
336
337 if (stb & ~PCH_UART_LCR_STB) {
338 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
339 return -EINVAL;
340 }
341
342 lcr = parity;
343 lcr |= bits;
344 lcr |= stb;
345
346 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
347 __func__, baud, div, lcr, jiffies);
348 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
349 iowrite8(dll, priv->membase + PCH_UART_DLL);
350 iowrite8(dlm, priv->membase + PCH_UART_DLM);
351 iowrite8(lcr, priv->membase + UART_LCR);
352
353 return 0;
354 }
355
356 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
357 unsigned int flag)
358 {
359 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
360 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
361 __func__, flag);
362 return -EINVAL;
363 }
364
365 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
366 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
367 priv->membase + UART_FCR);
368 iowrite8(priv->fcr, priv->membase + UART_FCR);
369
370 return 0;
371 }
372
373 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
374 unsigned int dmamode,
375 unsigned int fifo_size, unsigned int trigger)
376 {
377 u8 fcr;
378
379 if (dmamode & ~PCH_UART_FCR_DMS) {
380 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
381 __func__, dmamode);
382 return -EINVAL;
383 }
384
385 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
386 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
387 __func__, fifo_size);
388 return -EINVAL;
389 }
390
391 if (trigger & ~PCH_UART_FCR_RFTL) {
392 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
393 __func__, trigger);
394 return -EINVAL;
395 }
396
397 switch (priv->fifo_size) {
398 case 256:
399 priv->trigger_level =
400 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
401 break;
402 case 64:
403 priv->trigger_level =
404 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
405 break;
406 case 16:
407 priv->trigger_level =
408 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
409 break;
410 default:
411 priv->trigger_level =
412 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
413 break;
414 }
415 fcr =
416 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
417 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
418 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
419 priv->membase + UART_FCR);
420 iowrite8(fcr, priv->membase + UART_FCR);
421 priv->fcr = fcr;
422
423 return 0;
424 }
425
426 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
427 {
428 priv->dmsr = 0;
429 return get_msr(priv, priv->membase);
430 }
431
432 static void pch_uart_hal_write(struct eg20t_port *priv,
433 const unsigned char *buf, int tx_size)
434 {
435 int i;
436 unsigned int thr;
437
438 for (i = 0; i < tx_size;) {
439 thr = buf[i++];
440 iowrite8(thr, priv->membase + PCH_UART_THR);
441 }
442 }
443
444 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
445 int rx_size)
446 {
447 int i;
448 u8 rbr, lsr;
449
450 lsr = ioread8(priv->membase + UART_LSR);
451 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
452 i < rx_size && lsr & UART_LSR_DR;
453 lsr = ioread8(priv->membase + UART_LSR)) {
454 rbr = ioread8(priv->membase + PCH_UART_RBR);
455 buf[i++] = rbr;
456 }
457 return i;
458 }
459
460 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
461 {
462 unsigned int iir;
463 int ret;
464
465 iir = ioread8(priv->membase + UART_IIR);
466 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
467 return ret;
468 }
469
470 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
471 {
472 return ioread8(priv->membase + UART_LSR);
473 }
474
475 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
476 {
477 unsigned int lcr;
478
479 lcr = ioread8(priv->membase + UART_LCR);
480 if (on)
481 lcr |= PCH_UART_LCR_SB;
482 else
483 lcr &= ~PCH_UART_LCR_SB;
484
485 iowrite8(lcr, priv->membase + UART_LCR);
486 }
487
488 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
489 int size)
490 {
491 struct uart_port *port;
492 struct tty_struct *tty;
493
494 port = &priv->port;
495 tty = tty_port_tty_get(&port->state->port);
496 if (!tty) {
497 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
498 return -EBUSY;
499 }
500
501 tty_insert_flip_string(tty, buf, size);
502 tty_flip_buffer_push(tty);
503 tty_kref_put(tty);
504
505 return 0;
506 }
507
508 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
509 {
510 int ret;
511 struct uart_port *port = &priv->port;
512
513 if (port->x_char) {
514 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
515 __func__, port->x_char, jiffies);
516 buf[0] = port->x_char;
517 port->x_char = 0;
518 ret = 1;
519 } else {
520 ret = 0;
521 }
522
523 return ret;
524 }
525
526 static int dma_push_rx(struct eg20t_port *priv, int size)
527 {
528 struct tty_struct *tty;
529 int room;
530 struct uart_port *port = &priv->port;
531
532 port = &priv->port;
533 tty = tty_port_tty_get(&port->state->port);
534 if (!tty) {
535 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
536 return 0;
537 }
538
539 room = tty_buffer_request_room(tty, size);
540
541 if (room < size)
542 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
543 size - room);
544 if (!room)
545 return room;
546
547 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
548
549 port->icount.rx += room;
550 tty_kref_put(tty);
551
552 return room;
553 }
554
555 static void pch_free_dma(struct uart_port *port)
556 {
557 struct eg20t_port *priv;
558 priv = container_of(port, struct eg20t_port, port);
559
560 if (priv->chan_tx) {
561 dma_release_channel(priv->chan_tx);
562 priv->chan_tx = NULL;
563 }
564 if (priv->chan_rx) {
565 dma_release_channel(priv->chan_rx);
566 priv->chan_rx = NULL;
567 }
568 if (sg_dma_address(&priv->sg_rx))
569 dma_free_coherent(port->dev, port->fifosize,
570 sg_virt(&priv->sg_rx),
571 sg_dma_address(&priv->sg_rx));
572
573 return;
574 }
575
576 static bool filter(struct dma_chan *chan, void *slave)
577 {
578 struct pch_dma_slave *param = slave;
579
580 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
581 chan->device->dev)) {
582 chan->private = param;
583 return true;
584 } else {
585 return false;
586 }
587 }
588
589 static void pch_request_dma(struct uart_port *port)
590 {
591 dma_cap_mask_t mask;
592 struct dma_chan *chan;
593 struct pci_dev *dma_dev;
594 struct pch_dma_slave *param;
595 struct eg20t_port *priv =
596 container_of(port, struct eg20t_port, port);
597 dma_cap_zero(mask);
598 dma_cap_set(DMA_SLAVE, mask);
599
600 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
601 information */
602 /* Set Tx DMA */
603 param = &priv->param_tx;
604 param->dma_dev = &dma_dev->dev;
605 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
606
607 param->tx_reg = port->mapbase + UART_TX;
608 chan = dma_request_channel(mask, filter, param);
609 if (!chan) {
610 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
611 __func__);
612 return;
613 }
614 priv->chan_tx = chan;
615
616 /* Set Rx DMA */
617 param = &priv->param_rx;
618 param->dma_dev = &dma_dev->dev;
619 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
620
621 param->rx_reg = port->mapbase + UART_RX;
622 chan = dma_request_channel(mask, filter, param);
623 if (!chan) {
624 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
625 __func__);
626 dma_release_channel(priv->chan_tx);
627 return;
628 }
629
630 /* Get Consistent memory for DMA */
631 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
632 &priv->rx_buf_dma, GFP_KERNEL);
633 priv->chan_rx = chan;
634 }
635
636 static void pch_dma_rx_complete(void *arg)
637 {
638 struct eg20t_port *priv = arg;
639 struct uart_port *port = &priv->port;
640 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
641 int count;
642
643 if (!tty) {
644 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
645 return;
646 }
647
648 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
649 count = dma_push_rx(priv, priv->trigger_level);
650 if (count)
651 tty_flip_buffer_push(tty);
652 tty_kref_put(tty);
653 async_tx_ack(priv->desc_rx);
654 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
655 }
656
657 static void pch_dma_tx_complete(void *arg)
658 {
659 struct eg20t_port *priv = arg;
660 struct uart_port *port = &priv->port;
661 struct circ_buf *xmit = &port->state->xmit;
662 struct scatterlist *sg = priv->sg_tx_p;
663 int i;
664
665 for (i = 0; i < priv->nent; i++, sg++) {
666 xmit->tail += sg_dma_len(sg);
667 port->icount.tx += sg_dma_len(sg);
668 }
669 xmit->tail &= UART_XMIT_SIZE - 1;
670 async_tx_ack(priv->desc_tx);
671 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
672 priv->tx_dma_use = 0;
673 priv->nent = 0;
674 kfree(priv->sg_tx_p);
675 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
676 }
677
678 static int pop_tx(struct eg20t_port *priv, int size)
679 {
680 int count = 0;
681 struct uart_port *port = &priv->port;
682 struct circ_buf *xmit = &port->state->xmit;
683
684 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
685 goto pop_tx_end;
686
687 do {
688 int cnt_to_end =
689 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
690 int sz = min(size - count, cnt_to_end);
691 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
692 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
693 count += sz;
694 } while (!uart_circ_empty(xmit) && count < size);
695
696 pop_tx_end:
697 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
698 count, size - count, jiffies);
699
700 return count;
701 }
702
703 static int handle_rx_to(struct eg20t_port *priv)
704 {
705 struct pch_uart_buffer *buf;
706 int rx_size;
707 int ret;
708 if (!priv->start_rx) {
709 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
710 return 0;
711 }
712 buf = &priv->rxbuf;
713 do {
714 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
715 ret = push_rx(priv, buf->buf, rx_size);
716 if (ret)
717 return 0;
718 } while (rx_size == buf->size);
719
720 return PCH_UART_HANDLED_RX_INT;
721 }
722
723 static int handle_rx(struct eg20t_port *priv)
724 {
725 return handle_rx_to(priv);
726 }
727
728 static int dma_handle_rx(struct eg20t_port *priv)
729 {
730 struct uart_port *port = &priv->port;
731 struct dma_async_tx_descriptor *desc;
732 struct scatterlist *sg;
733
734 priv = container_of(port, struct eg20t_port, port);
735 sg = &priv->sg_rx;
736
737 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
738
739 sg_dma_len(sg) = priv->trigger_level;
740
741 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
742 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
743 ~PAGE_MASK);
744
745 sg_dma_address(sg) = priv->rx_buf_dma;
746
747 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
748 sg, 1, DMA_FROM_DEVICE,
749 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
750
751 if (!desc)
752 return 0;
753
754 priv->desc_rx = desc;
755 desc->callback = pch_dma_rx_complete;
756 desc->callback_param = priv;
757 desc->tx_submit(desc);
758 dma_async_issue_pending(priv->chan_rx);
759
760 return PCH_UART_HANDLED_RX_INT;
761 }
762
763 static unsigned int handle_tx(struct eg20t_port *priv)
764 {
765 struct uart_port *port = &priv->port;
766 struct circ_buf *xmit = &port->state->xmit;
767 int fifo_size;
768 int tx_size;
769 int size;
770 int tx_empty;
771
772 if (!priv->start_tx) {
773 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
774 __func__, jiffies);
775 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
776 priv->tx_empty = 1;
777 return 0;
778 }
779
780 fifo_size = max(priv->fifo_size, 1);
781 tx_empty = 1;
782 if (pop_tx_x(priv, xmit->buf)) {
783 pch_uart_hal_write(priv, xmit->buf, 1);
784 port->icount.tx++;
785 tx_empty = 0;
786 fifo_size--;
787 }
788 size = min(xmit->head - xmit->tail, fifo_size);
789 if (size < 0)
790 size = fifo_size;
791
792 tx_size = pop_tx(priv, size);
793 if (tx_size > 0) {
794 port->icount.tx += tx_size;
795 tx_empty = 0;
796 }
797
798 priv->tx_empty = tx_empty;
799
800 if (tx_empty) {
801 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
802 uart_write_wakeup(port);
803 }
804
805 return PCH_UART_HANDLED_TX_INT;
806 }
807
808 static unsigned int dma_handle_tx(struct eg20t_port *priv)
809 {
810 struct uart_port *port = &priv->port;
811 struct circ_buf *xmit = &port->state->xmit;
812 struct scatterlist *sg;
813 int nent;
814 int fifo_size;
815 int tx_empty;
816 struct dma_async_tx_descriptor *desc;
817 int num;
818 int i;
819 int bytes;
820 int size;
821 int rem;
822
823 if (!priv->start_tx) {
824 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
825 __func__, jiffies);
826 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
827 priv->tx_empty = 1;
828 return 0;
829 }
830
831 if (priv->tx_dma_use) {
832 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
833 __func__, jiffies);
834 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
835 priv->tx_empty = 1;
836 return 0;
837 }
838
839 fifo_size = max(priv->fifo_size, 1);
840 tx_empty = 1;
841 if (pop_tx_x(priv, xmit->buf)) {
842 pch_uart_hal_write(priv, xmit->buf, 1);
843 port->icount.tx++;
844 tx_empty = 0;
845 fifo_size--;
846 }
847
848 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
849 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
850 xmit->tail, UART_XMIT_SIZE));
851 if (!bytes) {
852 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
853 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
854 uart_write_wakeup(port);
855 return 0;
856 }
857
858 if (bytes > fifo_size) {
859 num = bytes / fifo_size + 1;
860 size = fifo_size;
861 rem = bytes % fifo_size;
862 } else {
863 num = 1;
864 size = bytes;
865 rem = bytes;
866 }
867
868 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
869 __func__, num, size, rem);
870
871 priv->tx_dma_use = 1;
872
873 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
874
875 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
876 sg = priv->sg_tx_p;
877
878 for (i = 0; i < num; i++, sg++) {
879 if (i == (num - 1))
880 sg_set_page(sg, virt_to_page(xmit->buf),
881 rem, fifo_size * i);
882 else
883 sg_set_page(sg, virt_to_page(xmit->buf),
884 size, fifo_size * i);
885 }
886
887 sg = priv->sg_tx_p;
888 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
889 if (!nent) {
890 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
891 return 0;
892 }
893 priv->nent = nent;
894
895 for (i = 0; i < nent; i++, sg++) {
896 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
897 fifo_size * i;
898 sg_dma_address(sg) = (sg_dma_address(sg) &
899 ~(UART_XMIT_SIZE - 1)) + sg->offset;
900 if (i == (nent - 1))
901 sg_dma_len(sg) = rem;
902 else
903 sg_dma_len(sg) = size;
904 }
905
906 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
907 priv->sg_tx_p, nent, DMA_TO_DEVICE,
908 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
909 if (!desc) {
910 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
911 __func__);
912 return 0;
913 }
914 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
915 priv->desc_tx = desc;
916 desc->callback = pch_dma_tx_complete;
917 desc->callback_param = priv;
918
919 desc->tx_submit(desc);
920
921 dma_async_issue_pending(priv->chan_tx);
922
923 return PCH_UART_HANDLED_TX_INT;
924 }
925
926 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
927 {
928 u8 fcr = ioread8(priv->membase + UART_FCR);
929
930 /* Reset FIFO */
931 fcr |= UART_FCR_CLEAR_RCVR;
932 iowrite8(fcr, priv->membase + UART_FCR);
933
934 if (lsr & PCH_UART_LSR_ERR)
935 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
936
937 if (lsr & UART_LSR_FE)
938 dev_err(&priv->pdev->dev, "Framing Error\n");
939
940 if (lsr & UART_LSR_PE)
941 dev_err(&priv->pdev->dev, "Parity Error\n");
942
943 if (lsr & UART_LSR_OE)
944 dev_err(&priv->pdev->dev, "Overrun Error\n");
945 }
946
947 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
948 {
949 struct eg20t_port *priv = dev_id;
950 unsigned int handled;
951 u8 lsr;
952 int ret = 0;
953 unsigned int iid;
954 unsigned long flags;
955
956 spin_lock_irqsave(&priv->port.lock, flags);
957 handled = 0;
958 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
959 switch (iid) {
960 case PCH_UART_IID_RLS: /* Receiver Line Status */
961 lsr = pch_uart_hal_get_line_status(priv);
962 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
963 UART_LSR_PE | UART_LSR_OE)) {
964 pch_uart_err_ir(priv, lsr);
965 ret = PCH_UART_HANDLED_RX_ERR_INT;
966 }
967 break;
968 case PCH_UART_IID_RDR: /* Received Data Ready */
969 if (priv->use_dma) {
970 pch_uart_hal_disable_interrupt(priv,
971 PCH_UART_HAL_RX_INT);
972 ret = dma_handle_rx(priv);
973 if (!ret)
974 pch_uart_hal_enable_interrupt(priv,
975 PCH_UART_HAL_RX_INT);
976 } else {
977 ret = handle_rx(priv);
978 }
979 break;
980 case PCH_UART_IID_RDR_TO: /* Received Data Ready
981 (FIFO Timeout) */
982 ret = handle_rx_to(priv);
983 break;
984 case PCH_UART_IID_THRE: /* Transmitter Holding Register
985 Empty */
986 if (priv->use_dma)
987 ret = dma_handle_tx(priv);
988 else
989 ret = handle_tx(priv);
990 break;
991 case PCH_UART_IID_MS: /* Modem Status */
992 ret = PCH_UART_HANDLED_MS_INT;
993 break;
994 default: /* Never junp to this label */
995 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
996 iid, jiffies);
997 ret = -1;
998 break;
999 }
1000 handled |= (unsigned int)ret;
1001 }
1002 if (handled == 0 && iid <= 1) {
1003 if (priv->int_dis_flag)
1004 priv->int_dis_flag = 0;
1005 }
1006
1007 spin_unlock_irqrestore(&priv->port.lock, flags);
1008 return IRQ_RETVAL(handled);
1009 }
1010
1011 /* This function tests whether the transmitter fifo and shifter for the port
1012 described by 'port' is empty. */
1013 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1014 {
1015 struct eg20t_port *priv;
1016 int ret;
1017 priv = container_of(port, struct eg20t_port, port);
1018 if (priv->tx_empty)
1019 ret = TIOCSER_TEMT;
1020 else
1021 ret = 0;
1022
1023 return ret;
1024 }
1025
1026 /* Returns the current state of modem control inputs. */
1027 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1028 {
1029 struct eg20t_port *priv;
1030 u8 modem;
1031 unsigned int ret = 0;
1032
1033 priv = container_of(port, struct eg20t_port, port);
1034 modem = pch_uart_hal_get_modem(priv);
1035
1036 if (modem & UART_MSR_DCD)
1037 ret |= TIOCM_CAR;
1038
1039 if (modem & UART_MSR_RI)
1040 ret |= TIOCM_RNG;
1041
1042 if (modem & UART_MSR_DSR)
1043 ret |= TIOCM_DSR;
1044
1045 if (modem & UART_MSR_CTS)
1046 ret |= TIOCM_CTS;
1047
1048 return ret;
1049 }
1050
1051 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1052 {
1053 u32 mcr = 0;
1054 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1055
1056 if (mctrl & TIOCM_DTR)
1057 mcr |= UART_MCR_DTR;
1058 if (mctrl & TIOCM_RTS)
1059 mcr |= UART_MCR_RTS;
1060 if (mctrl & TIOCM_LOOP)
1061 mcr |= UART_MCR_LOOP;
1062
1063 if (priv->mcr & UART_MCR_AFE)
1064 mcr |= UART_MCR_AFE;
1065
1066 if (mctrl)
1067 iowrite8(mcr, priv->membase + UART_MCR);
1068 }
1069
1070 static void pch_uart_stop_tx(struct uart_port *port)
1071 {
1072 struct eg20t_port *priv;
1073 priv = container_of(port, struct eg20t_port, port);
1074 priv->start_tx = 0;
1075 priv->tx_dma_use = 0;
1076 }
1077
1078 static void pch_uart_start_tx(struct uart_port *port)
1079 {
1080 struct eg20t_port *priv;
1081
1082 priv = container_of(port, struct eg20t_port, port);
1083
1084 if (priv->use_dma) {
1085 if (priv->tx_dma_use) {
1086 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1087 __func__);
1088 return;
1089 }
1090 }
1091
1092 priv->start_tx = 1;
1093 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1094 }
1095
1096 static void pch_uart_stop_rx(struct uart_port *port)
1097 {
1098 struct eg20t_port *priv;
1099 priv = container_of(port, struct eg20t_port, port);
1100 priv->start_rx = 0;
1101 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1102 priv->int_dis_flag = 1;
1103 }
1104
1105 /* Enable the modem status interrupts. */
1106 static void pch_uart_enable_ms(struct uart_port *port)
1107 {
1108 struct eg20t_port *priv;
1109 priv = container_of(port, struct eg20t_port, port);
1110 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1111 }
1112
1113 /* Control the transmission of a break signal. */
1114 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1115 {
1116 struct eg20t_port *priv;
1117 unsigned long flags;
1118
1119 priv = container_of(port, struct eg20t_port, port);
1120 spin_lock_irqsave(&port->lock, flags);
1121 pch_uart_hal_set_break(priv, ctl);
1122 spin_unlock_irqrestore(&port->lock, flags);
1123 }
1124
1125 /* Grab any interrupt resources and initialise any low level driver state. */
1126 static int pch_uart_startup(struct uart_port *port)
1127 {
1128 struct eg20t_port *priv;
1129 int ret;
1130 int fifo_size;
1131 int trigger_level;
1132
1133 priv = container_of(port, struct eg20t_port, port);
1134 priv->tx_empty = 1;
1135
1136 if (port->uartclk)
1137 priv->base_baud = port->uartclk;
1138 else
1139 port->uartclk = priv->base_baud;
1140
1141 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1142 ret = pch_uart_hal_set_line(priv, default_baud,
1143 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1144 PCH_UART_HAL_STB1);
1145 if (ret)
1146 return ret;
1147
1148 switch (priv->fifo_size) {
1149 case 256:
1150 fifo_size = PCH_UART_HAL_FIFO256;
1151 break;
1152 case 64:
1153 fifo_size = PCH_UART_HAL_FIFO64;
1154 break;
1155 case 16:
1156 fifo_size = PCH_UART_HAL_FIFO16;
1157 case 1:
1158 default:
1159 fifo_size = PCH_UART_HAL_FIFO_DIS;
1160 break;
1161 }
1162
1163 switch (priv->trigger) {
1164 case PCH_UART_HAL_TRIGGER1:
1165 trigger_level = 1;
1166 break;
1167 case PCH_UART_HAL_TRIGGER_L:
1168 trigger_level = priv->fifo_size / 4;
1169 break;
1170 case PCH_UART_HAL_TRIGGER_M:
1171 trigger_level = priv->fifo_size / 2;
1172 break;
1173 case PCH_UART_HAL_TRIGGER_H:
1174 default:
1175 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1176 break;
1177 }
1178
1179 priv->trigger_level = trigger_level;
1180 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1181 fifo_size, priv->trigger);
1182 if (ret < 0)
1183 return ret;
1184
1185 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1186 KBUILD_MODNAME, priv);
1187 if (ret < 0)
1188 return ret;
1189
1190 if (priv->use_dma)
1191 pch_request_dma(port);
1192
1193 priv->start_rx = 1;
1194 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1195 uart_update_timeout(port, CS8, default_baud);
1196
1197 return 0;
1198 }
1199
1200 static void pch_uart_shutdown(struct uart_port *port)
1201 {
1202 struct eg20t_port *priv;
1203 int ret;
1204
1205 priv = container_of(port, struct eg20t_port, port);
1206 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1207 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1208 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1209 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1210 if (ret)
1211 dev_err(priv->port.dev,
1212 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1213
1214 if (priv->use_dma_flag)
1215 pch_free_dma(port);
1216
1217 free_irq(priv->port.irq, priv);
1218 }
1219
1220 /* Change the port parameters, including word length, parity, stop
1221 *bits. Update read_status_mask and ignore_status_mask to indicate
1222 *the types of events we are interested in receiving. */
1223 static void pch_uart_set_termios(struct uart_port *port,
1224 struct ktermios *termios, struct ktermios *old)
1225 {
1226 int baud;
1227 int rtn;
1228 unsigned int parity, bits, stb;
1229 struct eg20t_port *priv;
1230 unsigned long flags;
1231
1232 priv = container_of(port, struct eg20t_port, port);
1233 switch (termios->c_cflag & CSIZE) {
1234 case CS5:
1235 bits = PCH_UART_HAL_5BIT;
1236 break;
1237 case CS6:
1238 bits = PCH_UART_HAL_6BIT;
1239 break;
1240 case CS7:
1241 bits = PCH_UART_HAL_7BIT;
1242 break;
1243 default: /* CS8 */
1244 bits = PCH_UART_HAL_8BIT;
1245 break;
1246 }
1247 if (termios->c_cflag & CSTOPB)
1248 stb = PCH_UART_HAL_STB2;
1249 else
1250 stb = PCH_UART_HAL_STB1;
1251
1252 if (termios->c_cflag & PARENB) {
1253 if (!(termios->c_cflag & PARODD))
1254 parity = PCH_UART_HAL_PARITY_ODD;
1255 else
1256 parity = PCH_UART_HAL_PARITY_EVEN;
1257
1258 } else {
1259 parity = PCH_UART_HAL_PARITY_NONE;
1260 }
1261
1262 /* Only UART0 has auto hardware flow function */
1263 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1264 priv->mcr |= UART_MCR_AFE;
1265 else
1266 priv->mcr &= ~UART_MCR_AFE;
1267
1268 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1269
1270 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1271
1272 spin_lock_irqsave(&port->lock, flags);
1273
1274 uart_update_timeout(port, termios->c_cflag, baud);
1275 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1276 if (rtn)
1277 goto out;
1278
1279 /* Don't rewrite B0 */
1280 if (tty_termios_baud_rate(termios))
1281 tty_termios_encode_baud_rate(termios, baud, baud);
1282
1283 out:
1284 spin_unlock_irqrestore(&port->lock, flags);
1285 }
1286
1287 static const char *pch_uart_type(struct uart_port *port)
1288 {
1289 return KBUILD_MODNAME;
1290 }
1291
1292 static void pch_uart_release_port(struct uart_port *port)
1293 {
1294 struct eg20t_port *priv;
1295
1296 priv = container_of(port, struct eg20t_port, port);
1297 pci_iounmap(priv->pdev, priv->membase);
1298 pci_release_regions(priv->pdev);
1299 }
1300
1301 static int pch_uart_request_port(struct uart_port *port)
1302 {
1303 struct eg20t_port *priv;
1304 int ret;
1305 void __iomem *membase;
1306
1307 priv = container_of(port, struct eg20t_port, port);
1308 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1309 if (ret < 0)
1310 return -EBUSY;
1311
1312 membase = pci_iomap(priv->pdev, 1, 0);
1313 if (!membase) {
1314 pci_release_regions(priv->pdev);
1315 return -EBUSY;
1316 }
1317 priv->membase = port->membase = membase;
1318
1319 return 0;
1320 }
1321
1322 static void pch_uart_config_port(struct uart_port *port, int type)
1323 {
1324 struct eg20t_port *priv;
1325
1326 priv = container_of(port, struct eg20t_port, port);
1327 if (type & UART_CONFIG_TYPE) {
1328 port->type = priv->port_type;
1329 pch_uart_request_port(port);
1330 }
1331 }
1332
1333 static int pch_uart_verify_port(struct uart_port *port,
1334 struct serial_struct *serinfo)
1335 {
1336 struct eg20t_port *priv;
1337
1338 priv = container_of(port, struct eg20t_port, port);
1339 if (serinfo->flags & UPF_LOW_LATENCY) {
1340 dev_info(priv->port.dev,
1341 "PCH UART : Use PIO Mode (without DMA)\n");
1342 priv->use_dma = 0;
1343 serinfo->flags &= ~UPF_LOW_LATENCY;
1344 } else {
1345 #ifndef CONFIG_PCH_DMA
1346 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1347 __func__);
1348 return -EOPNOTSUPP;
1349 #endif
1350 priv->use_dma = 1;
1351 priv->use_dma_flag = 1;
1352 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1353 }
1354
1355 return 0;
1356 }
1357
1358 static struct uart_ops pch_uart_ops = {
1359 .tx_empty = pch_uart_tx_empty,
1360 .set_mctrl = pch_uart_set_mctrl,
1361 .get_mctrl = pch_uart_get_mctrl,
1362 .stop_tx = pch_uart_stop_tx,
1363 .start_tx = pch_uart_start_tx,
1364 .stop_rx = pch_uart_stop_rx,
1365 .enable_ms = pch_uart_enable_ms,
1366 .break_ctl = pch_uart_break_ctl,
1367 .startup = pch_uart_startup,
1368 .shutdown = pch_uart_shutdown,
1369 .set_termios = pch_uart_set_termios,
1370 /* .pm = pch_uart_pm, Not supported yet */
1371 /* .set_wake = pch_uart_set_wake, Not supported yet */
1372 .type = pch_uart_type,
1373 .release_port = pch_uart_release_port,
1374 .request_port = pch_uart_request_port,
1375 .config_port = pch_uart_config_port,
1376 .verify_port = pch_uart_verify_port
1377 };
1378
1379 static struct uart_driver pch_uart_driver = {
1380 .owner = THIS_MODULE,
1381 .driver_name = KBUILD_MODNAME,
1382 .dev_name = PCH_UART_DRIVER_DEVICE,
1383 .major = 0,
1384 .minor = 0,
1385 .nr = PCH_UART_NR,
1386 };
1387
1388 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1389 const struct pci_device_id *id)
1390 {
1391 struct eg20t_port *priv;
1392 int ret;
1393 unsigned int iobase;
1394 unsigned int mapbase;
1395 unsigned char *rxbuf;
1396 int fifosize, base_baud;
1397 int port_type;
1398 struct pch_uart_driver_data *board;
1399
1400 board = &drv_dat[id->driver_data];
1401 port_type = board->port_type;
1402
1403 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1404 if (priv == NULL)
1405 goto init_port_alloc_err;
1406
1407 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1408 if (!rxbuf)
1409 goto init_port_free_txbuf;
1410
1411 base_baud = 1843200; /* 1.8432MHz */
1412
1413 /* quirk for CM-iTC board */
1414 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
1415 base_baud = 192000000; /* 192.0MHz */
1416
1417 switch (port_type) {
1418 case PORT_UNKNOWN:
1419 fifosize = 256; /* EG20T/ML7213: UART0 */
1420 break;
1421 case PORT_8250:
1422 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1423 break;
1424 default:
1425 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1426 goto init_port_hal_free;
1427 }
1428
1429 pci_enable_msi(pdev);
1430
1431 iobase = pci_resource_start(pdev, 0);
1432 mapbase = pci_resource_start(pdev, 1);
1433 priv->mapbase = mapbase;
1434 priv->iobase = iobase;
1435 priv->pdev = pdev;
1436 priv->tx_empty = 1;
1437 priv->rxbuf.buf = rxbuf;
1438 priv->rxbuf.size = PAGE_SIZE;
1439
1440 priv->fifo_size = fifosize;
1441 priv->base_baud = base_baud;
1442 priv->port_type = PORT_MAX_8250 + port_type + 1;
1443 priv->port.dev = &pdev->dev;
1444 priv->port.iobase = iobase;
1445 priv->port.membase = NULL;
1446 priv->port.mapbase = mapbase;
1447 priv->port.irq = pdev->irq;
1448 priv->port.iotype = UPIO_PORT;
1449 priv->port.ops = &pch_uart_ops;
1450 priv->port.flags = UPF_BOOT_AUTOCONF;
1451 priv->port.fifosize = fifosize;
1452 priv->port.line = board->line_no;
1453 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1454
1455 spin_lock_init(&priv->port.lock);
1456
1457 pci_set_drvdata(pdev, priv);
1458 pch_uart_hal_request(pdev, fifosize, base_baud);
1459
1460 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1461 if (ret < 0)
1462 goto init_port_hal_free;
1463
1464 return priv;
1465
1466 init_port_hal_free:
1467 free_page((unsigned long)rxbuf);
1468 init_port_free_txbuf:
1469 kfree(priv);
1470 init_port_alloc_err:
1471
1472 return NULL;
1473 }
1474
1475 static void pch_uart_exit_port(struct eg20t_port *priv)
1476 {
1477 uart_remove_one_port(&pch_uart_driver, &priv->port);
1478 pci_set_drvdata(priv->pdev, NULL);
1479 free_page((unsigned long)priv->rxbuf.buf);
1480 }
1481
1482 static void pch_uart_pci_remove(struct pci_dev *pdev)
1483 {
1484 struct eg20t_port *priv;
1485
1486 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1487
1488 pci_disable_msi(pdev);
1489 pch_uart_exit_port(priv);
1490 pci_disable_device(pdev);
1491 kfree(priv);
1492 return;
1493 }
1494 #ifdef CONFIG_PM
1495 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1496 {
1497 struct eg20t_port *priv = pci_get_drvdata(pdev);
1498
1499 uart_suspend_port(&pch_uart_driver, &priv->port);
1500
1501 pci_save_state(pdev);
1502 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1503 return 0;
1504 }
1505
1506 static int pch_uart_pci_resume(struct pci_dev *pdev)
1507 {
1508 struct eg20t_port *priv = pci_get_drvdata(pdev);
1509 int ret;
1510
1511 pci_set_power_state(pdev, PCI_D0);
1512 pci_restore_state(pdev);
1513
1514 ret = pci_enable_device(pdev);
1515 if (ret) {
1516 dev_err(&pdev->dev,
1517 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1518 return ret;
1519 }
1520
1521 uart_resume_port(&pch_uart_driver, &priv->port);
1522
1523 return 0;
1524 }
1525 #else
1526 #define pch_uart_pci_suspend NULL
1527 #define pch_uart_pci_resume NULL
1528 #endif
1529
1530 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1531 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1532 .driver_data = pch_et20t_uart0},
1533 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1534 .driver_data = pch_et20t_uart1},
1535 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1536 .driver_data = pch_et20t_uart2},
1537 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1538 .driver_data = pch_et20t_uart3},
1539 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1540 .driver_data = pch_ml7213_uart0},
1541 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1542 .driver_data = pch_ml7213_uart1},
1543 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1544 .driver_data = pch_ml7213_uart2},
1545 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1546 .driver_data = pch_ml7223_uart0},
1547 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1548 .driver_data = pch_ml7223_uart1},
1549 {0,},
1550 };
1551
1552 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1553 const struct pci_device_id *id)
1554 {
1555 int ret;
1556 struct eg20t_port *priv;
1557
1558 ret = pci_enable_device(pdev);
1559 if (ret < 0)
1560 goto probe_error;
1561
1562 priv = pch_uart_init_port(pdev, id);
1563 if (!priv) {
1564 ret = -EBUSY;
1565 goto probe_disable_device;
1566 }
1567 pci_set_drvdata(pdev, priv);
1568
1569 return ret;
1570
1571 probe_disable_device:
1572 pci_disable_msi(pdev);
1573 pci_disable_device(pdev);
1574 probe_error:
1575 return ret;
1576 }
1577
1578 static struct pci_driver pch_uart_pci_driver = {
1579 .name = "pch_uart",
1580 .id_table = pch_uart_pci_id,
1581 .probe = pch_uart_pci_probe,
1582 .remove = __devexit_p(pch_uart_pci_remove),
1583 .suspend = pch_uart_pci_suspend,
1584 .resume = pch_uart_pci_resume,
1585 };
1586
1587 static int __init pch_uart_module_init(void)
1588 {
1589 int ret;
1590
1591 /* register as UART driver */
1592 ret = uart_register_driver(&pch_uart_driver);
1593 if (ret < 0)
1594 return ret;
1595
1596 /* register as PCI driver */
1597 ret = pci_register_driver(&pch_uart_pci_driver);
1598 if (ret < 0)
1599 uart_unregister_driver(&pch_uart_driver);
1600
1601 return ret;
1602 }
1603 module_init(pch_uart_module_init);
1604
1605 static void __exit pch_uart_module_exit(void)
1606 {
1607 pci_unregister_driver(&pch_uart_pci_driver);
1608 uart_unregister_driver(&pch_uart_driver);
1609 }
1610 module_exit(pch_uart_module_exit);
1611
1612 MODULE_LICENSE("GPL v2");
1613 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1614 module_param(default_baud, uint, S_IRUGO);
Linux kernel - Deliverables
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