2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
49 #include <mach/hardware.h>
52 #include <plat/regs-serial.h>
53 #include <plat/clock.h>
57 /* UART name and device definitions */
59 #define S3C24XX_SERIAL_NAME "ttySAC"
60 #define S3C24XX_SERIAL_MAJOR 204
61 #define S3C24XX_SERIAL_MINOR 64
63 /* macros to change one thing to another */
65 #define tx_enabled(port) ((port)->unused[0])
66 #define rx_enabled(port) ((port)->unused[1])
68 /* flag to ignore all characters coming in */
69 #define RXSTAT_DUMMY_READ (0x10000000)
71 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
73 return container_of(port
, struct s3c24xx_uart_port
, port
);
76 /* translate a port to the device name */
78 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
80 return to_platform_device(port
->dev
)->name
;
83 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
85 return (rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
);
89 * s3c64xx and later SoC's include the interrupt mask and status registers in
90 * the controller itself, unlike the s3c24xx SoC's which have these registers
91 * in the interrupt controller. Check if the port type is s3c64xx or higher.
93 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
95 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
98 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
101 unsigned int ucon
, ufcon
;
104 spin_lock_irqsave(&port
->lock
, flags
);
106 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
109 ufcon
= rd_regl(port
, S3C2410_UFCON
);
110 ufcon
|= S3C2410_UFCON_RESETRX
;
111 wr_regl(port
, S3C2410_UFCON
, ufcon
);
113 ucon
= rd_regl(port
, S3C2410_UCON
);
114 ucon
|= S3C2410_UCON_RXIRQMODE
;
115 wr_regl(port
, S3C2410_UCON
, ucon
);
117 rx_enabled(port
) = 1;
118 spin_unlock_irqrestore(&port
->lock
, flags
);
121 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
126 spin_lock_irqsave(&port
->lock
, flags
);
128 ucon
= rd_regl(port
, S3C2410_UCON
);
129 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
130 wr_regl(port
, S3C2410_UCON
, ucon
);
132 rx_enabled(port
) = 0;
133 spin_unlock_irqrestore(&port
->lock
, flags
);
136 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
138 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
140 if (tx_enabled(port
)) {
141 if (s3c24xx_serial_has_interrupt_mask(port
))
142 __set_bit(S3C64XX_UINTM_TXD
,
143 portaddrl(port
, S3C64XX_UINTM
));
145 disable_irq_nosync(ourport
->tx_irq
);
146 tx_enabled(port
) = 0;
147 if (port
->flags
& UPF_CONS_FLOW
)
148 s3c24xx_serial_rx_enable(port
);
152 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
154 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
156 if (!tx_enabled(port
)) {
157 if (port
->flags
& UPF_CONS_FLOW
)
158 s3c24xx_serial_rx_disable(port
);
160 if (s3c24xx_serial_has_interrupt_mask(port
))
161 __clear_bit(S3C64XX_UINTM_TXD
,
162 portaddrl(port
, S3C64XX_UINTM
));
164 enable_irq(ourport
->tx_irq
);
165 tx_enabled(port
) = 1;
169 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
171 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
173 if (rx_enabled(port
)) {
174 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
175 if (s3c24xx_serial_has_interrupt_mask(port
))
176 __set_bit(S3C64XX_UINTM_RXD
,
177 portaddrl(port
, S3C64XX_UINTM
));
179 disable_irq_nosync(ourport
->rx_irq
);
180 rx_enabled(port
) = 0;
184 static void s3c24xx_serial_enable_ms(struct uart_port
*port
)
188 static inline struct s3c24xx_uart_info
*s3c24xx_port_to_info(struct uart_port
*port
)
190 return to_ourport(port
)->info
;
193 static inline struct s3c2410_uartcfg
*s3c24xx_port_to_cfg(struct uart_port
*port
)
195 struct s3c24xx_uart_port
*ourport
;
197 if (port
->dev
== NULL
)
200 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
204 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
205 unsigned long ufstat
)
207 struct s3c24xx_uart_info
*info
= ourport
->info
;
209 if (ufstat
& info
->rx_fifofull
)
210 return ourport
->port
.fifosize
;
212 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
216 /* ? - where has parity gone?? */
217 #define S3C2410_UERSTAT_PARITY (0x1000)
220 s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
222 struct s3c24xx_uart_port
*ourport
= dev_id
;
223 struct uart_port
*port
= &ourport
->port
;
224 struct tty_struct
*tty
= port
->state
->port
.tty
;
225 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
228 while (max_count
-- > 0) {
229 ufcon
= rd_regl(port
, S3C2410_UFCON
);
230 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
232 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
235 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
236 ch
= rd_regb(port
, S3C2410_URXH
);
238 if (port
->flags
& UPF_CONS_FLOW
) {
239 int txe
= s3c24xx_serial_txempty_nofifo(port
);
241 if (rx_enabled(port
)) {
243 rx_enabled(port
) = 0;
248 ufcon
|= S3C2410_UFCON_RESETRX
;
249 wr_regl(port
, S3C2410_UFCON
, ufcon
);
250 rx_enabled(port
) = 1;
257 /* insert the character into the buffer */
262 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
263 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
266 /* check for break */
267 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
270 if (uart_handle_break(port
))
274 if (uerstat
& S3C2410_UERSTAT_FRAME
)
275 port
->icount
.frame
++;
276 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
277 port
->icount
.overrun
++;
279 uerstat
&= port
->read_status_mask
;
281 if (uerstat
& S3C2410_UERSTAT_BREAK
)
283 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
285 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
286 S3C2410_UERSTAT_OVERRUN
))
290 if (uart_handle_sysrq_char(port
, ch
))
293 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
299 tty_flip_buffer_push(tty
);
305 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
307 struct s3c24xx_uart_port
*ourport
= id
;
308 struct uart_port
*port
= &ourport
->port
;
309 struct circ_buf
*xmit
= &port
->state
->xmit
;
313 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
319 /* if there isn't anything more to transmit, or the uart is now
320 * stopped, disable the uart and exit
323 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
324 s3c24xx_serial_stop_tx(port
);
328 /* try and drain the buffer... */
330 while (!uart_circ_empty(xmit
) && count
-- > 0) {
331 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
334 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
335 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
339 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
340 uart_write_wakeup(port
);
342 if (uart_circ_empty(xmit
))
343 s3c24xx_serial_stop_tx(port
);
349 /* interrupt handler for s3c64xx and later SoC's.*/
350 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
352 struct s3c24xx_uart_port
*ourport
= id
;
353 struct uart_port
*port
= &ourport
->port
;
354 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
356 irqreturn_t ret
= IRQ_HANDLED
;
358 spin_lock_irqsave(&port
->lock
, flags
);
359 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
360 ret
= s3c24xx_serial_rx_chars(irq
, id
);
361 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
363 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
364 ret
= s3c24xx_serial_tx_chars(irq
, id
);
365 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
367 spin_unlock_irqrestore(&port
->lock
, flags
);
371 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
373 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
374 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
375 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
377 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
378 if ((ufstat
& info
->tx_fifomask
) != 0 ||
379 (ufstat
& info
->tx_fifofull
))
385 return s3c24xx_serial_txempty_nofifo(port
);
388 /* no modem control lines */
389 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
391 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
393 if (umstat
& S3C2410_UMSTAT_CTS
)
394 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
396 return TIOCM_CAR
| TIOCM_DSR
;
399 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
401 /* todo - possibly remove AFC and do manual CTS */
404 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
409 spin_lock_irqsave(&port
->lock
, flags
);
411 ucon
= rd_regl(port
, S3C2410_UCON
);
414 ucon
|= S3C2410_UCON_SBREAK
;
416 ucon
&= ~S3C2410_UCON_SBREAK
;
418 wr_regl(port
, S3C2410_UCON
, ucon
);
420 spin_unlock_irqrestore(&port
->lock
, flags
);
423 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
425 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
427 if (ourport
->tx_claimed
) {
428 if (!s3c24xx_serial_has_interrupt_mask(port
))
429 free_irq(ourport
->tx_irq
, ourport
);
430 tx_enabled(port
) = 0;
431 ourport
->tx_claimed
= 0;
434 if (ourport
->rx_claimed
) {
435 if (!s3c24xx_serial_has_interrupt_mask(port
))
436 free_irq(ourport
->rx_irq
, ourport
);
437 ourport
->rx_claimed
= 0;
438 rx_enabled(port
) = 0;
441 /* Clear pending interrupts and mask all interrupts */
442 if (s3c24xx_serial_has_interrupt_mask(port
)) {
443 wr_regl(port
, S3C64XX_UINTP
, 0xf);
444 wr_regl(port
, S3C64XX_UINTM
, 0xf);
448 static int s3c24xx_serial_startup(struct uart_port
*port
)
450 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
453 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
454 port
->mapbase
, port
->membase
);
456 rx_enabled(port
) = 1;
458 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
459 s3c24xx_serial_portname(port
), ourport
);
462 printk(KERN_ERR
"cannot get irq %d\n", ourport
->rx_irq
);
466 ourport
->rx_claimed
= 1;
468 dbg("requesting tx irq...\n");
470 tx_enabled(port
) = 1;
472 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
473 s3c24xx_serial_portname(port
), ourport
);
476 printk(KERN_ERR
"cannot get irq %d\n", ourport
->tx_irq
);
480 ourport
->tx_claimed
= 1;
482 dbg("s3c24xx_serial_startup ok\n");
484 /* the port reset code should have done the correct
485 * register setup for the port controls */
490 s3c24xx_serial_shutdown(port
);
494 static int s3c64xx_serial_startup(struct uart_port
*port
)
496 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
499 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
500 port
->mapbase
, port
->membase
);
502 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
503 s3c24xx_serial_portname(port
), ourport
);
505 printk(KERN_ERR
"cannot get irq %d\n", port
->irq
);
509 /* For compatibility with s3c24xx Soc's */
510 rx_enabled(port
) = 1;
511 ourport
->rx_claimed
= 1;
512 tx_enabled(port
) = 0;
513 ourport
->tx_claimed
= 1;
515 /* Enable Rx Interrupt */
516 __clear_bit(S3C64XX_UINTM_RXD
, portaddrl(port
, S3C64XX_UINTM
));
517 dbg("s3c64xx_serial_startup ok\n");
521 /* power power management control */
523 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
526 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
528 ourport
->pm_level
= level
;
532 if (!IS_ERR(ourport
->baudclk
))
533 clk_disable(ourport
->baudclk
);
535 clk_disable(ourport
->clk
);
539 clk_enable(ourport
->clk
);
541 if (!IS_ERR(ourport
->baudclk
))
542 clk_enable(ourport
->baudclk
);
546 printk(KERN_ERR
"s3c24xx_serial: unknown pm %d\n", level
);
550 /* baud rate calculation
552 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
553 * of different sources, including the peripheral clock ("pclk") and an
554 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
555 * with a programmable extra divisor.
557 * The following code goes through the clock sources, and calculates the
558 * baud clocks (and the resultant actual baud rates) and then tries to
559 * pick the closest one and select that.
563 #define MAX_CLK_NAME_LENGTH 15
565 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
567 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
570 if (info
->num_clks
== 1)
573 ucon
= rd_regl(port
, S3C2410_UCON
);
574 ucon
&= info
->clksel_mask
;
575 return ucon
>> info
->clksel_shift
;
578 static void s3c24xx_serial_setsource(struct uart_port
*port
,
579 unsigned int clk_sel
)
581 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
584 if (info
->num_clks
== 1)
587 ucon
= rd_regl(port
, S3C2410_UCON
);
588 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
591 ucon
&= ~info
->clksel_mask
;
592 ucon
|= clk_sel
<< info
->clksel_shift
;
593 wr_regl(port
, S3C2410_UCON
, ucon
);
596 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
597 unsigned int req_baud
, struct clk
**best_clk
,
598 unsigned int *clk_num
)
600 struct s3c24xx_uart_info
*info
= ourport
->info
;
603 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
604 char clkname
[MAX_CLK_NAME_LENGTH
];
605 int calc_deviation
, deviation
= (1 << 30) - 1;
607 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
608 ourport
->info
->def_clk_sel
;
609 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
610 if (!(clk_sel
& (1 << cnt
)))
613 sprintf(clkname
, "clk_uart_baud%d", cnt
);
614 clk
= clk_get(ourport
->port
.dev
, clkname
);
618 rate
= clk_get_rate(clk
);
622 if (ourport
->info
->has_divslot
) {
623 unsigned long div
= rate
/ req_baud
;
625 /* The UDIVSLOT register on the newer UARTs allows us to
626 * get a divisor adjustment of 1/16th on the baud clock.
628 * We don't keep the UDIVSLOT value (the 16ths we
629 * calculated by not multiplying the baud by 16) as it
630 * is easy enough to recalculate.
636 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
637 baud
= rate
/ (quot
* 16);
641 calc_deviation
= req_baud
- baud
;
642 if (calc_deviation
< 0)
643 calc_deviation
= -calc_deviation
;
645 if (calc_deviation
< deviation
) {
649 deviation
= calc_deviation
;
658 * This table takes the fractional value of the baud divisor and gives
659 * the recommended setting for the UDIVSLOT register.
661 static u16 udivslot_table
[16] = {
680 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
681 struct ktermios
*termios
,
682 struct ktermios
*old
)
684 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
685 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
686 struct clk
*clk
= ERR_PTR(-EINVAL
);
688 unsigned int baud
, quot
, clk_sel
= 0;
691 unsigned int udivslot
= 0;
694 * We don't support modem control lines.
696 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
697 termios
->c_cflag
|= CLOCAL
;
700 * Ask the core to calculate the divisor for us.
703 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
704 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
705 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
706 quot
= port
->custom_divisor
;
710 /* check to see if we need to change clock source */
712 if (ourport
->baudclk
!= clk
) {
713 s3c24xx_serial_setsource(port
, clk_sel
);
715 if (!IS_ERR(ourport
->baudclk
)) {
716 clk_disable(ourport
->baudclk
);
717 ourport
->baudclk
= ERR_PTR(-EINVAL
);
722 ourport
->baudclk
= clk
;
723 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
726 if (ourport
->info
->has_divslot
) {
727 unsigned int div
= ourport
->baudclk_rate
/ baud
;
729 if (cfg
->has_fracval
) {
730 udivslot
= (div
& 15);
731 dbg("fracval = %04x\n", udivslot
);
733 udivslot
= udivslot_table
[div
& 15];
734 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
738 switch (termios
->c_cflag
& CSIZE
) {
740 dbg("config: 5bits/char\n");
741 ulcon
= S3C2410_LCON_CS5
;
744 dbg("config: 6bits/char\n");
745 ulcon
= S3C2410_LCON_CS6
;
748 dbg("config: 7bits/char\n");
749 ulcon
= S3C2410_LCON_CS7
;
753 dbg("config: 8bits/char\n");
754 ulcon
= S3C2410_LCON_CS8
;
758 /* preserve original lcon IR settings */
759 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
761 if (termios
->c_cflag
& CSTOPB
)
762 ulcon
|= S3C2410_LCON_STOPB
;
764 umcon
= (termios
->c_cflag
& CRTSCTS
) ? S3C2410_UMCOM_AFC
: 0;
766 if (termios
->c_cflag
& PARENB
) {
767 if (termios
->c_cflag
& PARODD
)
768 ulcon
|= S3C2410_LCON_PODD
;
770 ulcon
|= S3C2410_LCON_PEVEN
;
772 ulcon
|= S3C2410_LCON_PNONE
;
775 spin_lock_irqsave(&port
->lock
, flags
);
777 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
778 ulcon
, quot
, udivslot
);
780 wr_regl(port
, S3C2410_ULCON
, ulcon
);
781 wr_regl(port
, S3C2410_UBRDIV
, quot
);
782 wr_regl(port
, S3C2410_UMCON
, umcon
);
784 if (ourport
->info
->has_divslot
)
785 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
787 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
788 rd_regl(port
, S3C2410_ULCON
),
789 rd_regl(port
, S3C2410_UCON
),
790 rd_regl(port
, S3C2410_UFCON
));
793 * Update the per-port timeout.
795 uart_update_timeout(port
, termios
->c_cflag
, baud
);
798 * Which character status flags are we interested in?
800 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
801 if (termios
->c_iflag
& INPCK
)
802 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
| S3C2410_UERSTAT_PARITY
;
805 * Which character status flags should we ignore?
807 port
->ignore_status_mask
= 0;
808 if (termios
->c_iflag
& IGNPAR
)
809 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
810 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
811 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
814 * Ignore all characters if CREAD is not set.
816 if ((termios
->c_cflag
& CREAD
) == 0)
817 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
819 spin_unlock_irqrestore(&port
->lock
, flags
);
822 static const char *s3c24xx_serial_type(struct uart_port
*port
)
824 switch (port
->type
) {
838 #define MAP_SIZE (0x100)
840 static void s3c24xx_serial_release_port(struct uart_port
*port
)
842 release_mem_region(port
->mapbase
, MAP_SIZE
);
845 static int s3c24xx_serial_request_port(struct uart_port
*port
)
847 const char *name
= s3c24xx_serial_portname(port
);
848 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
851 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
853 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
855 if (flags
& UART_CONFIG_TYPE
&&
856 s3c24xx_serial_request_port(port
) == 0)
857 port
->type
= info
->type
;
861 * verify the new serial_struct (for TIOCSSERIAL).
864 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
866 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
868 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
875 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
877 static struct console s3c24xx_serial_console
;
879 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
881 #define S3C24XX_SERIAL_CONSOLE NULL
884 static struct uart_ops s3c24xx_serial_ops
= {
885 .pm
= s3c24xx_serial_pm
,
886 .tx_empty
= s3c24xx_serial_tx_empty
,
887 .get_mctrl
= s3c24xx_serial_get_mctrl
,
888 .set_mctrl
= s3c24xx_serial_set_mctrl
,
889 .stop_tx
= s3c24xx_serial_stop_tx
,
890 .start_tx
= s3c24xx_serial_start_tx
,
891 .stop_rx
= s3c24xx_serial_stop_rx
,
892 .enable_ms
= s3c24xx_serial_enable_ms
,
893 .break_ctl
= s3c24xx_serial_break_ctl
,
894 .startup
= s3c24xx_serial_startup
,
895 .shutdown
= s3c24xx_serial_shutdown
,
896 .set_termios
= s3c24xx_serial_set_termios
,
897 .type
= s3c24xx_serial_type
,
898 .release_port
= s3c24xx_serial_release_port
,
899 .request_port
= s3c24xx_serial_request_port
,
900 .config_port
= s3c24xx_serial_config_port
,
901 .verify_port
= s3c24xx_serial_verify_port
,
904 static struct uart_driver s3c24xx_uart_drv
= {
905 .owner
= THIS_MODULE
,
906 .driver_name
= "s3c2410_serial",
907 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
908 .cons
= S3C24XX_SERIAL_CONSOLE
,
909 .dev_name
= S3C24XX_SERIAL_NAME
,
910 .major
= S3C24XX_SERIAL_MAJOR
,
911 .minor
= S3C24XX_SERIAL_MINOR
,
914 static struct s3c24xx_uart_port s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
917 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[0].port
.lock
),
921 .ops
= &s3c24xx_serial_ops
,
922 .flags
= UPF_BOOT_AUTOCONF
,
928 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[1].port
.lock
),
932 .ops
= &s3c24xx_serial_ops
,
933 .flags
= UPF_BOOT_AUTOCONF
,
937 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
941 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[2].port
.lock
),
945 .ops
= &s3c24xx_serial_ops
,
946 .flags
= UPF_BOOT_AUTOCONF
,
951 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
954 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[3].port
.lock
),
958 .ops
= &s3c24xx_serial_ops
,
959 .flags
= UPF_BOOT_AUTOCONF
,
966 /* s3c24xx_serial_resetport
968 * reset the fifos and other the settings.
971 static void s3c24xx_serial_resetport(struct uart_port
*port
,
972 struct s3c2410_uartcfg
*cfg
)
974 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
975 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
976 unsigned int ucon_mask
;
978 ucon_mask
= info
->clksel_mask
;
979 if (info
->type
== PORT_S3C2440
)
980 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
983 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
984 wr_regl(port
, S3C2410_ULCON
, cfg
->ulcon
);
986 /* reset both fifos */
987 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
988 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
990 /* some delay is required after fifo reset */
995 #ifdef CONFIG_CPU_FREQ
997 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
998 unsigned long val
, void *data
)
1000 struct s3c24xx_uart_port
*port
;
1001 struct uart_port
*uport
;
1003 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1004 uport
= &port
->port
;
1006 /* check to see if port is enabled */
1008 if (port
->pm_level
!= 0)
1011 /* try and work out if the baudrate is changing, we can detect
1012 * a change in rate, but we do not have support for detecting
1013 * a disturbance in the clock-rate over the change.
1016 if (IS_ERR(port
->baudclk
))
1019 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1022 if (val
== CPUFREQ_PRECHANGE
) {
1023 /* we should really shut the port down whilst the
1024 * frequency change is in progress. */
1026 } else if (val
== CPUFREQ_POSTCHANGE
) {
1027 struct ktermios
*termios
;
1028 struct tty_struct
*tty
;
1030 if (uport
->state
== NULL
)
1033 tty
= uport
->state
->port
.tty
;
1038 termios
= &tty
->termios
;
1040 if (termios
== NULL
) {
1041 printk(KERN_WARNING
"%s: no termios?\n", __func__
);
1045 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1052 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1054 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1056 return cpufreq_register_notifier(&port
->freq_transition
,
1057 CPUFREQ_TRANSITION_NOTIFIER
);
1060 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1062 cpufreq_unregister_notifier(&port
->freq_transition
,
1063 CPUFREQ_TRANSITION_NOTIFIER
);
1067 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1072 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1077 /* s3c24xx_serial_init_port
1079 * initialise a single serial port from the platform device given
1082 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1083 struct platform_device
*platdev
)
1085 struct uart_port
*port
= &ourport
->port
;
1086 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1087 struct resource
*res
;
1090 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1092 if (platdev
== NULL
)
1095 if (port
->mapbase
!= 0)
1098 /* setup info for port */
1099 port
->dev
= &platdev
->dev
;
1101 /* Startup sequence is different for s3c64xx and higher SoC's */
1102 if (s3c24xx_serial_has_interrupt_mask(port
))
1103 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1107 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1108 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1109 port
->flags
|= UPF_CONS_FLOW
;
1112 /* sort our the physical and virtual addresses for each UART */
1114 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1116 printk(KERN_ERR
"failed to find memory resource for uart\n");
1120 dbg("resource %p (%lx..%lx)\n", res
, res
->start
, res
->end
);
1122 port
->mapbase
= res
->start
;
1123 port
->membase
= S3C_VA_UART
+ (res
->start
& 0xfffff);
1124 ret
= platform_get_irq(platdev
, 0);
1129 ourport
->rx_irq
= ret
;
1130 ourport
->tx_irq
= ret
+ 1;
1133 ret
= platform_get_irq(platdev
, 1);
1135 ourport
->tx_irq
= ret
;
1137 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1139 /* Keep all interrupts masked and cleared */
1140 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1141 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1142 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1143 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1146 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1147 port
->mapbase
, port
->membase
, port
->irq
,
1148 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1150 /* reset the fifos (and setup the uart) */
1151 s3c24xx_serial_resetport(port
, cfg
);
1155 static ssize_t
s3c24xx_serial_show_clksrc(struct device
*dev
,
1156 struct device_attribute
*attr
,
1159 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1160 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1162 if (IS_ERR(ourport
->baudclk
))
1165 return snprintf(buf
, PAGE_SIZE
, "* %s\n",
1166 ourport
->baudclk
->name
?: "(null)");
1169 static DEVICE_ATTR(clock_source
, S_IRUGO
, s3c24xx_serial_show_clksrc
, NULL
);
1172 /* Device driver serial port probe */
1174 static const struct of_device_id s3c24xx_uart_dt_match
[];
1175 static int probe_index
;
1177 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1178 struct platform_device
*pdev
)
1181 if (pdev
->dev
.of_node
) {
1182 const struct of_device_id
*match
;
1183 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1184 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1187 return (struct s3c24xx_serial_drv_data
*)
1188 platform_get_device_id(pdev
)->driver_data
;
1191 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1193 struct s3c24xx_uart_port
*ourport
;
1196 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, probe_index
);
1198 ourport
= &s3c24xx_serial_ports
[probe_index
];
1200 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1201 if (!ourport
->drv_data
) {
1202 dev_err(&pdev
->dev
, "could not find driver data\n");
1206 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1207 ourport
->info
= ourport
->drv_data
->info
;
1208 ourport
->cfg
= (pdev
->dev
.platform_data
) ?
1209 (struct s3c2410_uartcfg
*)pdev
->dev
.platform_data
:
1210 ourport
->drv_data
->def_cfg
;
1212 ourport
->port
.fifosize
= (ourport
->info
->fifosize
) ?
1213 ourport
->info
->fifosize
:
1214 ourport
->drv_data
->fifosize
[probe_index
];
1218 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1220 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1224 dbg("%s: adding port\n", __func__
);
1225 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1226 platform_set_drvdata(pdev
, &ourport
->port
);
1228 ret
= device_create_file(&pdev
->dev
, &dev_attr_clock_source
);
1230 dev_err(&pdev
->dev
, "failed to add clock source attr.\n");
1232 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1234 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1242 static int __devexit
s3c24xx_serial_remove(struct platform_device
*dev
)
1244 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1247 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1248 device_remove_file(&dev
->dev
, &dev_attr_clock_source
);
1249 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1255 /* UART power management code */
1256 #ifdef CONFIG_PM_SLEEP
1257 static int s3c24xx_serial_suspend(struct device
*dev
)
1259 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1262 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1267 static int s3c24xx_serial_resume(struct device
*dev
)
1269 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1270 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1273 clk_enable(ourport
->clk
);
1274 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1275 clk_disable(ourport
->clk
);
1277 uart_resume_port(&s3c24xx_uart_drv
, port
);
1283 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1284 .suspend
= s3c24xx_serial_suspend
,
1285 .resume
= s3c24xx_serial_resume
,
1287 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1289 #else /* !CONFIG_PM_SLEEP */
1291 #define SERIAL_SAMSUNG_PM_OPS NULL
1292 #endif /* CONFIG_PM_SLEEP */
1296 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1298 static struct uart_port
*cons_uart
;
1301 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1303 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1304 unsigned long ufstat
, utrstat
;
1306 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
1307 /* fifo mode - check amount of data in fifo registers... */
1309 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1310 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
1313 /* in non-fifo mode, we go and use the tx buffer empty */
1315 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
1316 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
1320 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
1322 unsigned int ufcon
= rd_regl(cons_uart
, S3C2410_UFCON
);
1323 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1325 wr_regb(cons_uart
, S3C2410_UTXH
, ch
);
1329 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
1332 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
1336 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
1337 int *parity
, int *bits
)
1342 unsigned int ubrdiv
;
1344 unsigned int clk_sel
;
1345 char clk_name
[MAX_CLK_NAME_LENGTH
];
1347 ulcon
= rd_regl(port
, S3C2410_ULCON
);
1348 ucon
= rd_regl(port
, S3C2410_UCON
);
1349 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
1351 dbg("s3c24xx_serial_get_options: port=%p\n"
1352 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1353 port
, ulcon
, ucon
, ubrdiv
);
1355 if ((ucon
& 0xf) != 0) {
1356 /* consider the serial port configured if the tx/rx mode set */
1358 switch (ulcon
& S3C2410_LCON_CSMASK
) {
1359 case S3C2410_LCON_CS5
:
1362 case S3C2410_LCON_CS6
:
1365 case S3C2410_LCON_CS7
:
1369 case S3C2410_LCON_CS8
:
1374 switch (ulcon
& S3C2410_LCON_PMASK
) {
1375 case S3C2410_LCON_PEVEN
:
1379 case S3C2410_LCON_PODD
:
1383 case S3C2410_LCON_PNONE
:
1388 /* now calculate the baud rate */
1390 clk_sel
= s3c24xx_serial_getsource(port
);
1391 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
1393 clk
= clk_get(port
->dev
, clk_name
);
1395 rate
= clk_get_rate(clk
);
1399 *baud
= rate
/ (16 * (ubrdiv
+ 1));
1400 dbg("calculated baud %d\n", *baud
);
1406 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
1408 struct uart_port
*port
;
1414 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1415 co
, co
->index
, options
);
1417 /* is this a valid port */
1419 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
1422 port
= &s3c24xx_serial_ports
[co
->index
].port
;
1424 /* is the port configured? */
1426 if (port
->mapbase
== 0x0)
1431 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
1434 * Check whether an invalid uart number has been specified, and
1435 * if so, search for the first available port that does have
1439 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1441 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
1443 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
1445 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1448 static struct console s3c24xx_serial_console
= {
1449 .name
= S3C24XX_SERIAL_NAME
,
1450 .device
= uart_console_device
,
1451 .flags
= CON_PRINTBUFFER
,
1453 .write
= s3c24xx_serial_console_write
,
1454 .setup
= s3c24xx_serial_console_setup
,
1455 .data
= &s3c24xx_uart_drv
,
1457 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1459 #ifdef CONFIG_CPU_S3C2410
1460 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
1461 .info
= &(struct s3c24xx_uart_info
) {
1462 .name
= "Samsung S3C2410 UART",
1463 .type
= PORT_S3C2410
,
1465 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
1466 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
1467 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
1468 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
1469 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
1470 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
1471 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1473 .clksel_mask
= S3C2410_UCON_CLKMASK
,
1474 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
1476 .def_cfg
= &(struct s3c2410_uartcfg
) {
1477 .ucon
= S3C2410_UCON_DEFAULT
,
1478 .ufcon
= S3C2410_UFCON_DEFAULT
,
1481 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1483 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1486 #ifdef CONFIG_CPU_S3C2412
1487 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
1488 .info
= &(struct s3c24xx_uart_info
) {
1489 .name
= "Samsung S3C2412 UART",
1490 .type
= PORT_S3C2412
,
1493 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1494 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1495 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1496 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1497 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1498 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1499 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1501 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1502 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1504 .def_cfg
= &(struct s3c2410_uartcfg
) {
1505 .ucon
= S3C2410_UCON_DEFAULT
,
1506 .ufcon
= S3C2410_UFCON_DEFAULT
,
1509 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1511 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1514 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1515 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1516 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
1517 .info
= &(struct s3c24xx_uart_info
) {
1518 .name
= "Samsung S3C2440 UART",
1519 .type
= PORT_S3C2440
,
1522 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1523 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1524 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1525 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1526 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1527 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1528 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1530 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1531 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1533 .def_cfg
= &(struct s3c2410_uartcfg
) {
1534 .ucon
= S3C2410_UCON_DEFAULT
,
1535 .ufcon
= S3C2410_UFCON_DEFAULT
,
1538 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1540 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1543 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1544 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1545 defined(CONFIG_CPU_S5PC100)
1546 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
1547 .info
= &(struct s3c24xx_uart_info
) {
1548 .name
= "Samsung S3C6400 UART",
1549 .type
= PORT_S3C6400
,
1552 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1553 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1554 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1555 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1556 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1557 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1558 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1560 .clksel_mask
= S3C6400_UCON_CLKMASK
,
1561 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
1563 .def_cfg
= &(struct s3c2410_uartcfg
) {
1564 .ucon
= S3C2410_UCON_DEFAULT
,
1565 .ufcon
= S3C2410_UFCON_DEFAULT
,
1568 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1570 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1573 #ifdef CONFIG_CPU_S5PV210
1574 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
1575 .info
= &(struct s3c24xx_uart_info
) {
1576 .name
= "Samsung S5PV210 UART",
1577 .type
= PORT_S3C6400
,
1579 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1580 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1581 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1582 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1583 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1584 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1585 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1587 .clksel_mask
= S5PV210_UCON_CLKMASK
,
1588 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
1590 .def_cfg
= &(struct s3c2410_uartcfg
) {
1591 .ucon
= S5PV210_UCON_DEFAULT
,
1592 .ufcon
= S5PV210_UFCON_DEFAULT
,
1594 .fifosize
= { 256, 64, 16, 16 },
1596 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1598 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1601 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1602 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
1603 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data
= {
1604 .info
= &(struct s3c24xx_uart_info
) {
1605 .name
= "Samsung Exynos4 UART",
1606 .type
= PORT_S3C6400
,
1608 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1609 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1610 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1611 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1612 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1613 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1614 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1619 .def_cfg
= &(struct s3c2410_uartcfg
) {
1620 .ucon
= S5PV210_UCON_DEFAULT
,
1621 .ufcon
= S5PV210_UFCON_DEFAULT
,
1624 .fifosize
= { 256, 64, 16, 16 },
1626 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1628 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1631 static struct platform_device_id s3c24xx_serial_driver_ids
[] = {
1633 .name
= "s3c2410-uart",
1634 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
1636 .name
= "s3c2412-uart",
1637 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
1639 .name
= "s3c2440-uart",
1640 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
1642 .name
= "s3c6400-uart",
1643 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
1645 .name
= "s5pv210-uart",
1646 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
1648 .name
= "exynos4210-uart",
1649 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
1653 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
1656 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
1657 { .compatible
= "samsung,exynos4210-uart",
1658 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
1661 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
1663 #define s3c24xx_uart_dt_match NULL
1666 static struct platform_driver samsung_serial_driver
= {
1667 .probe
= s3c24xx_serial_probe
,
1668 .remove
= __devexit_p(s3c24xx_serial_remove
),
1669 .id_table
= s3c24xx_serial_driver_ids
,
1671 .name
= "samsung-uart",
1672 .owner
= THIS_MODULE
,
1673 .pm
= SERIAL_SAMSUNG_PM_OPS
,
1674 .of_match_table
= s3c24xx_uart_dt_match
,
1678 /* module initialisation code */
1680 static int __init
s3c24xx_serial_modinit(void)
1684 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1686 printk(KERN_ERR
"failed to register UART driver\n");
1690 return platform_driver_register(&samsung_serial_driver
);
1693 static void __exit
s3c24xx_serial_modexit(void)
1695 uart_unregister_driver(&s3c24xx_uart_drv
);
1698 module_init(s3c24xx_serial_modinit
);
1699 module_exit(s3c24xx_serial_modexit
);
1701 MODULE_ALIAS("platform:samsung-uart");
1702 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1703 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1704 MODULE_LICENSE("GPL v2");