2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
52 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
53 defined(CONFIG_DEBUG_LL) && \
56 extern void printascii(const char *);
59 static void dbg(const char *fmt
, ...)
65 vscnprintf(buff
, sizeof(buff
), fmt
, va
);
72 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75 /* UART name and device definitions */
77 #define S3C24XX_SERIAL_NAME "ttySAC"
78 #define S3C24XX_SERIAL_MAJOR 204
79 #define S3C24XX_SERIAL_MINOR 64
81 /* macros to change one thing to another */
83 #define tx_enabled(port) ((port)->unused[0])
84 #define rx_enabled(port) ((port)->unused[1])
86 /* flag to ignore all characters coming in */
87 #define RXSTAT_DUMMY_READ (0x10000000)
89 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
91 return container_of(port
, struct s3c24xx_uart_port
, port
);
94 /* translate a port to the device name */
96 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
98 return to_platform_device(port
->dev
)->name
;
101 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
103 return rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
;
107 * s3c64xx and later SoC's include the interrupt mask and status registers in
108 * the controller itself, unlike the s3c24xx SoC's which have these registers
109 * in the interrupt controller. Check if the port type is s3c64xx or higher.
111 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
113 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
116 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
119 unsigned int ucon
, ufcon
;
122 spin_lock_irqsave(&port
->lock
, flags
);
124 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
127 ufcon
= rd_regl(port
, S3C2410_UFCON
);
128 ufcon
|= S3C2410_UFCON_RESETRX
;
129 wr_regl(port
, S3C2410_UFCON
, ufcon
);
131 ucon
= rd_regl(port
, S3C2410_UCON
);
132 ucon
|= S3C2410_UCON_RXIRQMODE
;
133 wr_regl(port
, S3C2410_UCON
, ucon
);
135 rx_enabled(port
) = 1;
136 spin_unlock_irqrestore(&port
->lock
, flags
);
139 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
144 spin_lock_irqsave(&port
->lock
, flags
);
146 ucon
= rd_regl(port
, S3C2410_UCON
);
147 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
148 wr_regl(port
, S3C2410_UCON
, ucon
);
150 rx_enabled(port
) = 0;
151 spin_unlock_irqrestore(&port
->lock
, flags
);
154 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
156 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
158 if (tx_enabled(port
)) {
159 if (s3c24xx_serial_has_interrupt_mask(port
))
160 __set_bit(S3C64XX_UINTM_TXD
,
161 portaddrl(port
, S3C64XX_UINTM
));
163 disable_irq_nosync(ourport
->tx_irq
);
164 tx_enabled(port
) = 0;
165 if (port
->flags
& UPF_CONS_FLOW
)
166 s3c24xx_serial_rx_enable(port
);
170 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
172 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
174 if (!tx_enabled(port
)) {
175 if (port
->flags
& UPF_CONS_FLOW
)
176 s3c24xx_serial_rx_disable(port
);
178 if (s3c24xx_serial_has_interrupt_mask(port
))
179 __clear_bit(S3C64XX_UINTM_TXD
,
180 portaddrl(port
, S3C64XX_UINTM
));
182 enable_irq(ourport
->tx_irq
);
183 tx_enabled(port
) = 1;
187 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
189 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
191 if (rx_enabled(port
)) {
192 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
193 if (s3c24xx_serial_has_interrupt_mask(port
))
194 __set_bit(S3C64XX_UINTM_RXD
,
195 portaddrl(port
, S3C64XX_UINTM
));
197 disable_irq_nosync(ourport
->rx_irq
);
198 rx_enabled(port
) = 0;
202 static void s3c24xx_serial_enable_ms(struct uart_port
*port
)
206 static inline struct s3c24xx_uart_info
*s3c24xx_port_to_info(struct uart_port
*port
)
208 return to_ourport(port
)->info
;
211 static inline struct s3c2410_uartcfg
*s3c24xx_port_to_cfg(struct uart_port
*port
)
213 struct s3c24xx_uart_port
*ourport
;
215 if (port
->dev
== NULL
)
218 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
222 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
223 unsigned long ufstat
)
225 struct s3c24xx_uart_info
*info
= ourport
->info
;
227 if (ufstat
& info
->rx_fifofull
)
228 return ourport
->port
.fifosize
;
230 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
234 /* ? - where has parity gone?? */
235 #define S3C2410_UERSTAT_PARITY (0x1000)
238 s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
240 struct s3c24xx_uart_port
*ourport
= dev_id
;
241 struct uart_port
*port
= &ourport
->port
;
242 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
246 spin_lock_irqsave(&port
->lock
, flags
);
248 while (max_count
-- > 0) {
249 ufcon
= rd_regl(port
, S3C2410_UFCON
);
250 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
252 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
255 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
256 ch
= rd_regb(port
, S3C2410_URXH
);
258 if (port
->flags
& UPF_CONS_FLOW
) {
259 int txe
= s3c24xx_serial_txempty_nofifo(port
);
261 if (rx_enabled(port
)) {
263 rx_enabled(port
) = 0;
268 ufcon
|= S3C2410_UFCON_RESETRX
;
269 wr_regl(port
, S3C2410_UFCON
, ufcon
);
270 rx_enabled(port
) = 1;
271 spin_unlock_irqrestore(&port
->lock
,
279 /* insert the character into the buffer */
284 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
285 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
288 /* check for break */
289 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
292 if (uart_handle_break(port
))
296 if (uerstat
& S3C2410_UERSTAT_FRAME
)
297 port
->icount
.frame
++;
298 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
299 port
->icount
.overrun
++;
301 uerstat
&= port
->read_status_mask
;
303 if (uerstat
& S3C2410_UERSTAT_BREAK
)
305 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
307 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
308 S3C2410_UERSTAT_OVERRUN
))
312 if (uart_handle_sysrq_char(port
, ch
))
315 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
322 spin_unlock_irqrestore(&port
->lock
, flags
);
323 tty_flip_buffer_push(&port
->state
->port
);
329 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
331 struct s3c24xx_uart_port
*ourport
= id
;
332 struct uart_port
*port
= &ourport
->port
;
333 struct circ_buf
*xmit
= &port
->state
->xmit
;
337 spin_lock_irqsave(&port
->lock
, flags
);
340 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
346 /* if there isn't anything more to transmit, or the uart is now
347 * stopped, disable the uart and exit
350 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
351 s3c24xx_serial_stop_tx(port
);
355 /* try and drain the buffer... */
357 while (!uart_circ_empty(xmit
) && count
-- > 0) {
358 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
361 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
362 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
366 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
367 spin_unlock(&port
->lock
);
368 uart_write_wakeup(port
);
369 spin_lock(&port
->lock
);
372 if (uart_circ_empty(xmit
))
373 s3c24xx_serial_stop_tx(port
);
376 spin_unlock_irqrestore(&port
->lock
, flags
);
380 /* interrupt handler for s3c64xx and later SoC's.*/
381 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
383 struct s3c24xx_uart_port
*ourport
= id
;
384 struct uart_port
*port
= &ourport
->port
;
385 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
386 irqreturn_t ret
= IRQ_HANDLED
;
388 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
389 ret
= s3c24xx_serial_rx_chars(irq
, id
);
390 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
392 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
393 ret
= s3c24xx_serial_tx_chars(irq
, id
);
394 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
399 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
401 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
402 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
403 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
405 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
406 if ((ufstat
& info
->tx_fifomask
) != 0 ||
407 (ufstat
& info
->tx_fifofull
))
413 return s3c24xx_serial_txempty_nofifo(port
);
416 /* no modem control lines */
417 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
419 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
421 if (umstat
& S3C2410_UMSTAT_CTS
)
422 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
424 return TIOCM_CAR
| TIOCM_DSR
;
427 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
429 unsigned int umcon
= rd_regl(port
, S3C2410_UMCON
);
431 if (mctrl
& TIOCM_RTS
)
432 umcon
|= S3C2410_UMCOM_RTS_LOW
;
434 umcon
&= ~S3C2410_UMCOM_RTS_LOW
;
436 wr_regl(port
, S3C2410_UMCON
, umcon
);
439 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
444 spin_lock_irqsave(&port
->lock
, flags
);
446 ucon
= rd_regl(port
, S3C2410_UCON
);
449 ucon
|= S3C2410_UCON_SBREAK
;
451 ucon
&= ~S3C2410_UCON_SBREAK
;
453 wr_regl(port
, S3C2410_UCON
, ucon
);
455 spin_unlock_irqrestore(&port
->lock
, flags
);
458 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
460 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
462 if (ourport
->tx_claimed
) {
463 if (!s3c24xx_serial_has_interrupt_mask(port
))
464 free_irq(ourport
->tx_irq
, ourport
);
465 tx_enabled(port
) = 0;
466 ourport
->tx_claimed
= 0;
469 if (ourport
->rx_claimed
) {
470 if (!s3c24xx_serial_has_interrupt_mask(port
))
471 free_irq(ourport
->rx_irq
, ourport
);
472 ourport
->rx_claimed
= 0;
473 rx_enabled(port
) = 0;
476 /* Clear pending interrupts and mask all interrupts */
477 if (s3c24xx_serial_has_interrupt_mask(port
)) {
478 free_irq(port
->irq
, ourport
);
480 wr_regl(port
, S3C64XX_UINTP
, 0xf);
481 wr_regl(port
, S3C64XX_UINTM
, 0xf);
485 static int s3c24xx_serial_startup(struct uart_port
*port
)
487 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
490 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
491 port
, (unsigned long long)port
->mapbase
, port
->membase
);
493 rx_enabled(port
) = 1;
495 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
496 s3c24xx_serial_portname(port
), ourport
);
499 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->rx_irq
);
503 ourport
->rx_claimed
= 1;
505 dbg("requesting tx irq...\n");
507 tx_enabled(port
) = 1;
509 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
510 s3c24xx_serial_portname(port
), ourport
);
513 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->tx_irq
);
517 ourport
->tx_claimed
= 1;
519 dbg("s3c24xx_serial_startup ok\n");
521 /* the port reset code should have done the correct
522 * register setup for the port controls */
527 s3c24xx_serial_shutdown(port
);
531 static int s3c64xx_serial_startup(struct uart_port
*port
)
533 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
536 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
537 port
, (unsigned long long)port
->mapbase
, port
->membase
);
539 wr_regl(port
, S3C64XX_UINTM
, 0xf);
541 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
542 s3c24xx_serial_portname(port
), ourport
);
544 dev_err(port
->dev
, "cannot get irq %d\n", port
->irq
);
548 /* For compatibility with s3c24xx Soc's */
549 rx_enabled(port
) = 1;
550 ourport
->rx_claimed
= 1;
551 tx_enabled(port
) = 0;
552 ourport
->tx_claimed
= 1;
554 /* Enable Rx Interrupt */
555 __clear_bit(S3C64XX_UINTM_RXD
, portaddrl(port
, S3C64XX_UINTM
));
556 dbg("s3c64xx_serial_startup ok\n");
560 /* power power management control */
562 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
565 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
567 ourport
->pm_level
= level
;
571 if (!IS_ERR(ourport
->baudclk
))
572 clk_disable_unprepare(ourport
->baudclk
);
574 clk_disable_unprepare(ourport
->clk
);
578 clk_prepare_enable(ourport
->clk
);
580 if (!IS_ERR(ourport
->baudclk
))
581 clk_prepare_enable(ourport
->baudclk
);
585 dev_err(port
->dev
, "s3c24xx_serial: unknown pm %d\n", level
);
589 /* baud rate calculation
591 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
592 * of different sources, including the peripheral clock ("pclk") and an
593 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
594 * with a programmable extra divisor.
596 * The following code goes through the clock sources, and calculates the
597 * baud clocks (and the resultant actual baud rates) and then tries to
598 * pick the closest one and select that.
602 #define MAX_CLK_NAME_LENGTH 15
604 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
606 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
609 if (info
->num_clks
== 1)
612 ucon
= rd_regl(port
, S3C2410_UCON
);
613 ucon
&= info
->clksel_mask
;
614 return ucon
>> info
->clksel_shift
;
617 static void s3c24xx_serial_setsource(struct uart_port
*port
,
618 unsigned int clk_sel
)
620 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
623 if (info
->num_clks
== 1)
626 ucon
= rd_regl(port
, S3C2410_UCON
);
627 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
630 ucon
&= ~info
->clksel_mask
;
631 ucon
|= clk_sel
<< info
->clksel_shift
;
632 wr_regl(port
, S3C2410_UCON
, ucon
);
635 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
636 unsigned int req_baud
, struct clk
**best_clk
,
637 unsigned int *clk_num
)
639 struct s3c24xx_uart_info
*info
= ourport
->info
;
642 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
643 char clkname
[MAX_CLK_NAME_LENGTH
];
644 int calc_deviation
, deviation
= (1 << 30) - 1;
646 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
647 ourport
->info
->def_clk_sel
;
648 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
649 if (!(clk_sel
& (1 << cnt
)))
652 sprintf(clkname
, "clk_uart_baud%d", cnt
);
653 clk
= clk_get(ourport
->port
.dev
, clkname
);
657 rate
= clk_get_rate(clk
);
661 if (ourport
->info
->has_divslot
) {
662 unsigned long div
= rate
/ req_baud
;
664 /* The UDIVSLOT register on the newer UARTs allows us to
665 * get a divisor adjustment of 1/16th on the baud clock.
667 * We don't keep the UDIVSLOT value (the 16ths we
668 * calculated by not multiplying the baud by 16) as it
669 * is easy enough to recalculate.
675 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
676 baud
= rate
/ (quot
* 16);
680 calc_deviation
= req_baud
- baud
;
681 if (calc_deviation
< 0)
682 calc_deviation
= -calc_deviation
;
684 if (calc_deviation
< deviation
) {
688 deviation
= calc_deviation
;
697 * This table takes the fractional value of the baud divisor and gives
698 * the recommended setting for the UDIVSLOT register.
700 static u16 udivslot_table
[16] = {
719 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
720 struct ktermios
*termios
,
721 struct ktermios
*old
)
723 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
724 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
725 struct clk
*clk
= ERR_PTR(-EINVAL
);
727 unsigned int baud
, quot
, clk_sel
= 0;
730 unsigned int udivslot
= 0;
733 * We don't support modem control lines.
735 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
736 termios
->c_cflag
|= CLOCAL
;
739 * Ask the core to calculate the divisor for us.
742 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
743 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
744 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
745 quot
= port
->custom_divisor
;
749 /* check to see if we need to change clock source */
751 if (ourport
->baudclk
!= clk
) {
752 s3c24xx_serial_setsource(port
, clk_sel
);
754 if (!IS_ERR(ourport
->baudclk
)) {
755 clk_disable_unprepare(ourport
->baudclk
);
756 ourport
->baudclk
= ERR_PTR(-EINVAL
);
759 clk_prepare_enable(clk
);
761 ourport
->baudclk
= clk
;
762 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
765 if (ourport
->info
->has_divslot
) {
766 unsigned int div
= ourport
->baudclk_rate
/ baud
;
768 if (cfg
->has_fracval
) {
769 udivslot
= (div
& 15);
770 dbg("fracval = %04x\n", udivslot
);
772 udivslot
= udivslot_table
[div
& 15];
773 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
777 switch (termios
->c_cflag
& CSIZE
) {
779 dbg("config: 5bits/char\n");
780 ulcon
= S3C2410_LCON_CS5
;
783 dbg("config: 6bits/char\n");
784 ulcon
= S3C2410_LCON_CS6
;
787 dbg("config: 7bits/char\n");
788 ulcon
= S3C2410_LCON_CS7
;
792 dbg("config: 8bits/char\n");
793 ulcon
= S3C2410_LCON_CS8
;
797 /* preserve original lcon IR settings */
798 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
800 if (termios
->c_cflag
& CSTOPB
)
801 ulcon
|= S3C2410_LCON_STOPB
;
803 if (termios
->c_cflag
& PARENB
) {
804 if (termios
->c_cflag
& PARODD
)
805 ulcon
|= S3C2410_LCON_PODD
;
807 ulcon
|= S3C2410_LCON_PEVEN
;
809 ulcon
|= S3C2410_LCON_PNONE
;
812 spin_lock_irqsave(&port
->lock
, flags
);
814 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
815 ulcon
, quot
, udivslot
);
817 wr_regl(port
, S3C2410_ULCON
, ulcon
);
818 wr_regl(port
, S3C2410_UBRDIV
, quot
);
820 umcon
= rd_regl(port
, S3C2410_UMCON
);
821 if (termios
->c_cflag
& CRTSCTS
) {
822 umcon
|= S3C2410_UMCOM_AFC
;
823 /* Disable RTS when RX FIFO contains 63 bytes */
824 umcon
&= ~S3C2412_UMCON_AFC_8
;
826 umcon
&= ~S3C2410_UMCOM_AFC
;
828 wr_regl(port
, S3C2410_UMCON
, umcon
);
830 if (ourport
->info
->has_divslot
)
831 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
833 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
834 rd_regl(port
, S3C2410_ULCON
),
835 rd_regl(port
, S3C2410_UCON
),
836 rd_regl(port
, S3C2410_UFCON
));
839 * Update the per-port timeout.
841 uart_update_timeout(port
, termios
->c_cflag
, baud
);
844 * Which character status flags are we interested in?
846 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
847 if (termios
->c_iflag
& INPCK
)
848 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
| S3C2410_UERSTAT_PARITY
;
851 * Which character status flags should we ignore?
853 port
->ignore_status_mask
= 0;
854 if (termios
->c_iflag
& IGNPAR
)
855 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
856 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
857 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
860 * Ignore all characters if CREAD is not set.
862 if ((termios
->c_cflag
& CREAD
) == 0)
863 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
865 spin_unlock_irqrestore(&port
->lock
, flags
);
868 static const char *s3c24xx_serial_type(struct uart_port
*port
)
870 switch (port
->type
) {
884 #define MAP_SIZE (0x100)
886 static void s3c24xx_serial_release_port(struct uart_port
*port
)
888 release_mem_region(port
->mapbase
, MAP_SIZE
);
891 static int s3c24xx_serial_request_port(struct uart_port
*port
)
893 const char *name
= s3c24xx_serial_portname(port
);
894 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
897 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
899 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
901 if (flags
& UART_CONFIG_TYPE
&&
902 s3c24xx_serial_request_port(port
) == 0)
903 port
->type
= info
->type
;
907 * verify the new serial_struct (for TIOCSSERIAL).
910 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
912 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
914 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
921 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
923 static struct console s3c24xx_serial_console
;
925 static int __init
s3c24xx_serial_console_init(void)
927 register_console(&s3c24xx_serial_console
);
930 console_initcall(s3c24xx_serial_console_init
);
932 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
934 #define S3C24XX_SERIAL_CONSOLE NULL
937 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
938 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
);
939 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
943 static struct uart_ops s3c24xx_serial_ops
= {
944 .pm
= s3c24xx_serial_pm
,
945 .tx_empty
= s3c24xx_serial_tx_empty
,
946 .get_mctrl
= s3c24xx_serial_get_mctrl
,
947 .set_mctrl
= s3c24xx_serial_set_mctrl
,
948 .stop_tx
= s3c24xx_serial_stop_tx
,
949 .start_tx
= s3c24xx_serial_start_tx
,
950 .stop_rx
= s3c24xx_serial_stop_rx
,
951 .enable_ms
= s3c24xx_serial_enable_ms
,
952 .break_ctl
= s3c24xx_serial_break_ctl
,
953 .startup
= s3c24xx_serial_startup
,
954 .shutdown
= s3c24xx_serial_shutdown
,
955 .set_termios
= s3c24xx_serial_set_termios
,
956 .type
= s3c24xx_serial_type
,
957 .release_port
= s3c24xx_serial_release_port
,
958 .request_port
= s3c24xx_serial_request_port
,
959 .config_port
= s3c24xx_serial_config_port
,
960 .verify_port
= s3c24xx_serial_verify_port
,
961 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
962 .poll_get_char
= s3c24xx_serial_get_poll_char
,
963 .poll_put_char
= s3c24xx_serial_put_poll_char
,
967 static struct uart_driver s3c24xx_uart_drv
= {
968 .owner
= THIS_MODULE
,
969 .driver_name
= "s3c2410_serial",
970 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
971 .cons
= S3C24XX_SERIAL_CONSOLE
,
972 .dev_name
= S3C24XX_SERIAL_NAME
,
973 .major
= S3C24XX_SERIAL_MAJOR
,
974 .minor
= S3C24XX_SERIAL_MINOR
,
977 static struct s3c24xx_uart_port s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
980 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[0].port
.lock
),
984 .ops
= &s3c24xx_serial_ops
,
985 .flags
= UPF_BOOT_AUTOCONF
,
991 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[1].port
.lock
),
995 .ops
= &s3c24xx_serial_ops
,
996 .flags
= UPF_BOOT_AUTOCONF
,
1000 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1004 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[2].port
.lock
),
1008 .ops
= &s3c24xx_serial_ops
,
1009 .flags
= UPF_BOOT_AUTOCONF
,
1014 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1017 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[3].port
.lock
),
1021 .ops
= &s3c24xx_serial_ops
,
1022 .flags
= UPF_BOOT_AUTOCONF
,
1029 /* s3c24xx_serial_resetport
1031 * reset the fifos and other the settings.
1034 static void s3c24xx_serial_resetport(struct uart_port
*port
,
1035 struct s3c2410_uartcfg
*cfg
)
1037 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1038 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
1039 unsigned int ucon_mask
;
1041 ucon_mask
= info
->clksel_mask
;
1042 if (info
->type
== PORT_S3C2440
)
1043 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
1046 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
1048 /* reset both fifos */
1049 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
1050 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
1052 /* some delay is required after fifo reset */
1057 #ifdef CONFIG_CPU_FREQ
1059 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
1060 unsigned long val
, void *data
)
1062 struct s3c24xx_uart_port
*port
;
1063 struct uart_port
*uport
;
1065 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1066 uport
= &port
->port
;
1068 /* check to see if port is enabled */
1070 if (port
->pm_level
!= 0)
1073 /* try and work out if the baudrate is changing, we can detect
1074 * a change in rate, but we do not have support for detecting
1075 * a disturbance in the clock-rate over the change.
1078 if (IS_ERR(port
->baudclk
))
1081 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1084 if (val
== CPUFREQ_PRECHANGE
) {
1085 /* we should really shut the port down whilst the
1086 * frequency change is in progress. */
1088 } else if (val
== CPUFREQ_POSTCHANGE
) {
1089 struct ktermios
*termios
;
1090 struct tty_struct
*tty
;
1092 if (uport
->state
== NULL
)
1095 tty
= uport
->state
->port
.tty
;
1100 termios
= &tty
->termios
;
1102 if (termios
== NULL
) {
1103 dev_warn(uport
->dev
, "%s: no termios?\n", __func__
);
1107 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1114 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1116 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1118 return cpufreq_register_notifier(&port
->freq_transition
,
1119 CPUFREQ_TRANSITION_NOTIFIER
);
1122 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1124 cpufreq_unregister_notifier(&port
->freq_transition
,
1125 CPUFREQ_TRANSITION_NOTIFIER
);
1129 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1134 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1139 /* s3c24xx_serial_init_port
1141 * initialise a single serial port from the platform device given
1144 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1145 struct platform_device
*platdev
)
1147 struct uart_port
*port
= &ourport
->port
;
1148 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1149 struct resource
*res
;
1152 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1154 if (platdev
== NULL
)
1157 if (port
->mapbase
!= 0)
1160 /* setup info for port */
1161 port
->dev
= &platdev
->dev
;
1163 /* Startup sequence is different for s3c64xx and higher SoC's */
1164 if (s3c24xx_serial_has_interrupt_mask(port
))
1165 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1169 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1170 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1171 port
->flags
|= UPF_CONS_FLOW
;
1174 /* sort our the physical and virtual addresses for each UART */
1176 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1178 dev_err(port
->dev
, "failed to find memory resource for uart\n");
1182 dbg("resource %pR)\n", res
);
1184 port
->membase
= devm_ioremap(port
->dev
, res
->start
, resource_size(res
));
1185 if (!port
->membase
) {
1186 dev_err(port
->dev
, "failed to remap controller address\n");
1190 port
->mapbase
= res
->start
;
1191 ret
= platform_get_irq(platdev
, 0);
1196 ourport
->rx_irq
= ret
;
1197 ourport
->tx_irq
= ret
+ 1;
1200 ret
= platform_get_irq(platdev
, 1);
1202 ourport
->tx_irq
= ret
;
1204 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1205 if (IS_ERR(ourport
->clk
)) {
1206 pr_err("%s: Controller clock not found\n",
1207 dev_name(&platdev
->dev
));
1208 return PTR_ERR(ourport
->clk
);
1211 ret
= clk_prepare_enable(ourport
->clk
);
1213 pr_err("uart: clock failed to prepare+enable: %d\n", ret
);
1214 clk_put(ourport
->clk
);
1218 /* Keep all interrupts masked and cleared */
1219 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1220 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1221 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1222 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1225 dbg("port: map=%08x, mem=%p, irq=%d (%d,%d), clock=%u\n",
1226 port
->mapbase
, port
->membase
, port
->irq
,
1227 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1229 /* reset the fifos (and setup the uart) */
1230 s3c24xx_serial_resetport(port
, cfg
);
1234 #ifdef CONFIG_SAMSUNG_CLOCK
1235 static ssize_t
s3c24xx_serial_show_clksrc(struct device
*dev
,
1236 struct device_attribute
*attr
,
1239 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1240 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1242 if (IS_ERR(ourport
->baudclk
))
1245 return snprintf(buf
, PAGE_SIZE
, "* %s\n",
1246 ourport
->baudclk
->name
?: "(null)");
1249 static DEVICE_ATTR(clock_source
, S_IRUGO
, s3c24xx_serial_show_clksrc
, NULL
);
1252 /* Device driver serial port probe */
1254 static const struct of_device_id s3c24xx_uart_dt_match
[];
1255 static int probe_index
;
1257 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1258 struct platform_device
*pdev
)
1261 if (pdev
->dev
.of_node
) {
1262 const struct of_device_id
*match
;
1263 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1264 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1267 return (struct s3c24xx_serial_drv_data
*)
1268 platform_get_device_id(pdev
)->driver_data
;
1271 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1273 struct s3c24xx_uart_port
*ourport
;
1276 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, probe_index
);
1278 ourport
= &s3c24xx_serial_ports
[probe_index
];
1280 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1281 if (!ourport
->drv_data
) {
1282 dev_err(&pdev
->dev
, "could not find driver data\n");
1286 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1287 ourport
->info
= ourport
->drv_data
->info
;
1288 ourport
->cfg
= (dev_get_platdata(&pdev
->dev
)) ?
1289 dev_get_platdata(&pdev
->dev
) :
1290 ourport
->drv_data
->def_cfg
;
1292 ourport
->port
.fifosize
= (ourport
->info
->fifosize
) ?
1293 ourport
->info
->fifosize
:
1294 ourport
->drv_data
->fifosize
[probe_index
];
1298 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1300 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1304 if (!s3c24xx_uart_drv
.state
) {
1305 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1307 pr_err("Failed to register Samsung UART driver\n");
1312 dbg("%s: adding port\n", __func__
);
1313 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1314 platform_set_drvdata(pdev
, &ourport
->port
);
1317 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1318 * so that a potential re-enablement through the pm-callback overlaps
1319 * and keeps the clock enabled in this case.
1321 clk_disable_unprepare(ourport
->clk
);
1323 #ifdef CONFIG_SAMSUNG_CLOCK
1324 ret
= device_create_file(&pdev
->dev
, &dev_attr_clock_source
);
1326 dev_err(&pdev
->dev
, "failed to add clock source attr.\n");
1329 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1331 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1339 static int s3c24xx_serial_remove(struct platform_device
*dev
)
1341 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1344 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1345 #ifdef CONFIG_SAMSUNG_CLOCK
1346 device_remove_file(&dev
->dev
, &dev_attr_clock_source
);
1348 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1351 uart_unregister_driver(&s3c24xx_uart_drv
);
1356 /* UART power management code */
1357 #ifdef CONFIG_PM_SLEEP
1358 static int s3c24xx_serial_suspend(struct device
*dev
)
1360 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1363 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1368 static int s3c24xx_serial_resume(struct device
*dev
)
1370 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1371 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1374 clk_prepare_enable(ourport
->clk
);
1375 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1376 clk_disable_unprepare(ourport
->clk
);
1378 uart_resume_port(&s3c24xx_uart_drv
, port
);
1384 static int s3c24xx_serial_resume_noirq(struct device
*dev
)
1386 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1389 /* restore IRQ mask */
1390 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1391 unsigned int uintm
= 0xf;
1392 if (tx_enabled(port
))
1393 uintm
&= ~S3C64XX_UINTM_TXD_MSK
;
1394 if (rx_enabled(port
))
1395 uintm
&= ~S3C64XX_UINTM_RXD_MSK
;
1396 wr_regl(port
, S3C64XX_UINTM
, uintm
);
1403 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1404 .suspend
= s3c24xx_serial_suspend
,
1405 .resume
= s3c24xx_serial_resume
,
1406 .resume_noirq
= s3c24xx_serial_resume_noirq
,
1408 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1410 #else /* !CONFIG_PM_SLEEP */
1412 #define SERIAL_SAMSUNG_PM_OPS NULL
1413 #endif /* CONFIG_PM_SLEEP */
1417 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1419 static struct uart_port
*cons_uart
;
1422 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1424 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1425 unsigned long ufstat
, utrstat
;
1427 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
1428 /* fifo mode - check amount of data in fifo registers... */
1430 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1431 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
1434 /* in non-fifo mode, we go and use the tx buffer empty */
1436 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
1437 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
1441 s3c24xx_port_configured(unsigned int ucon
)
1443 /* consider the serial port configured if the tx/rx mode set */
1444 return (ucon
& 0xf) != 0;
1447 #ifdef CONFIG_CONSOLE_POLL
1449 * Console polling routines for writing and reading from the uart while
1450 * in an interrupt or debug context.
1453 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
)
1455 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1456 unsigned int ufstat
;
1458 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1459 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
1460 return NO_POLL_CHAR
;
1462 return rd_regb(port
, S3C2410_URXH
);
1465 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
1468 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
1469 unsigned int ucon
= rd_regl(port
, S3C2410_UCON
);
1471 /* not possible to xmit on unconfigured port */
1472 if (!s3c24xx_port_configured(ucon
))
1475 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1477 wr_regb(port
, S3C2410_UTXH
, c
);
1480 #endif /* CONFIG_CONSOLE_POLL */
1483 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
1485 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
1487 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1489 wr_regb(port
, S3C2410_UTXH
, ch
);
1493 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
1496 unsigned int ucon
= rd_regl(cons_uart
, S3C2410_UCON
);
1498 /* not possible to xmit on unconfigured port */
1499 if (!s3c24xx_port_configured(ucon
))
1502 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
1506 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
1507 int *parity
, int *bits
)
1512 unsigned int ubrdiv
;
1514 unsigned int clk_sel
;
1515 char clk_name
[MAX_CLK_NAME_LENGTH
];
1517 ulcon
= rd_regl(port
, S3C2410_ULCON
);
1518 ucon
= rd_regl(port
, S3C2410_UCON
);
1519 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
1521 dbg("s3c24xx_serial_get_options: port=%p\n"
1522 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1523 port
, ulcon
, ucon
, ubrdiv
);
1525 if (s3c24xx_port_configured(ucon
)) {
1526 switch (ulcon
& S3C2410_LCON_CSMASK
) {
1527 case S3C2410_LCON_CS5
:
1530 case S3C2410_LCON_CS6
:
1533 case S3C2410_LCON_CS7
:
1537 case S3C2410_LCON_CS8
:
1542 switch (ulcon
& S3C2410_LCON_PMASK
) {
1543 case S3C2410_LCON_PEVEN
:
1547 case S3C2410_LCON_PODD
:
1551 case S3C2410_LCON_PNONE
:
1556 /* now calculate the baud rate */
1558 clk_sel
= s3c24xx_serial_getsource(port
);
1559 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
1561 clk
= clk_get(port
->dev
, clk_name
);
1563 rate
= clk_get_rate(clk
);
1567 *baud
= rate
/ (16 * (ubrdiv
+ 1));
1568 dbg("calculated baud %d\n", *baud
);
1574 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
1576 struct uart_port
*port
;
1582 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1583 co
, co
->index
, options
);
1585 /* is this a valid port */
1587 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
1590 port
= &s3c24xx_serial_ports
[co
->index
].port
;
1592 /* is the port configured? */
1594 if (port
->mapbase
== 0x0)
1599 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
1602 * Check whether an invalid uart number has been specified, and
1603 * if so, search for the first available port that does have
1607 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1609 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
1611 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
1613 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1616 static struct console s3c24xx_serial_console
= {
1617 .name
= S3C24XX_SERIAL_NAME
,
1618 .device
= uart_console_device
,
1619 .flags
= CON_PRINTBUFFER
,
1621 .write
= s3c24xx_serial_console_write
,
1622 .setup
= s3c24xx_serial_console_setup
,
1623 .data
= &s3c24xx_uart_drv
,
1625 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1627 #ifdef CONFIG_CPU_S3C2410
1628 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
1629 .info
= &(struct s3c24xx_uart_info
) {
1630 .name
= "Samsung S3C2410 UART",
1631 .type
= PORT_S3C2410
,
1633 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
1634 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
1635 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
1636 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
1637 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
1638 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
1639 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1641 .clksel_mask
= S3C2410_UCON_CLKMASK
,
1642 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
1644 .def_cfg
= &(struct s3c2410_uartcfg
) {
1645 .ucon
= S3C2410_UCON_DEFAULT
,
1646 .ufcon
= S3C2410_UFCON_DEFAULT
,
1649 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1651 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1654 #ifdef CONFIG_CPU_S3C2412
1655 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
1656 .info
= &(struct s3c24xx_uart_info
) {
1657 .name
= "Samsung S3C2412 UART",
1658 .type
= PORT_S3C2412
,
1661 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1662 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1663 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1664 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1665 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1666 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1667 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1669 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1670 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1672 .def_cfg
= &(struct s3c2410_uartcfg
) {
1673 .ucon
= S3C2410_UCON_DEFAULT
,
1674 .ufcon
= S3C2410_UFCON_DEFAULT
,
1677 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1679 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1682 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1683 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1684 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
1685 .info
= &(struct s3c24xx_uart_info
) {
1686 .name
= "Samsung S3C2440 UART",
1687 .type
= PORT_S3C2440
,
1690 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1691 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1692 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1693 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1694 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1695 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1696 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1698 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1699 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1701 .def_cfg
= &(struct s3c2410_uartcfg
) {
1702 .ucon
= S3C2410_UCON_DEFAULT
,
1703 .ufcon
= S3C2410_UFCON_DEFAULT
,
1706 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1708 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1711 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1712 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1713 defined(CONFIG_CPU_S5PC100)
1714 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
1715 .info
= &(struct s3c24xx_uart_info
) {
1716 .name
= "Samsung S3C6400 UART",
1717 .type
= PORT_S3C6400
,
1720 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1721 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1722 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1723 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1724 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1725 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1726 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1728 .clksel_mask
= S3C6400_UCON_CLKMASK
,
1729 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
1731 .def_cfg
= &(struct s3c2410_uartcfg
) {
1732 .ucon
= S3C2410_UCON_DEFAULT
,
1733 .ufcon
= S3C2410_UFCON_DEFAULT
,
1736 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1738 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1741 #ifdef CONFIG_CPU_S5PV210
1742 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
1743 .info
= &(struct s3c24xx_uart_info
) {
1744 .name
= "Samsung S5PV210 UART",
1745 .type
= PORT_S3C6400
,
1747 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1748 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1749 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1750 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1751 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1752 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1753 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1755 .clksel_mask
= S5PV210_UCON_CLKMASK
,
1756 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
1758 .def_cfg
= &(struct s3c2410_uartcfg
) {
1759 .ucon
= S5PV210_UCON_DEFAULT
,
1760 .ufcon
= S5PV210_UFCON_DEFAULT
,
1762 .fifosize
= { 256, 64, 16, 16 },
1764 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1766 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1769 #if defined(CONFIG_ARCH_EXYNOS)
1770 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data
= {
1771 .info
= &(struct s3c24xx_uart_info
) {
1772 .name
= "Samsung Exynos4 UART",
1773 .type
= PORT_S3C6400
,
1775 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1776 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1777 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1778 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1779 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1780 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1781 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1786 .def_cfg
= &(struct s3c2410_uartcfg
) {
1787 .ucon
= S5PV210_UCON_DEFAULT
,
1788 .ufcon
= S5PV210_UFCON_DEFAULT
,
1791 .fifosize
= { 256, 64, 16, 16 },
1793 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1795 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1798 static struct platform_device_id s3c24xx_serial_driver_ids
[] = {
1800 .name
= "s3c2410-uart",
1801 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
1803 .name
= "s3c2412-uart",
1804 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
1806 .name
= "s3c2440-uart",
1807 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
1809 .name
= "s3c6400-uart",
1810 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
1812 .name
= "s5pv210-uart",
1813 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
1815 .name
= "exynos4210-uart",
1816 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
1820 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
1823 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
1824 { .compatible
= "samsung,s3c2410-uart",
1825 .data
= (void *)S3C2410_SERIAL_DRV_DATA
},
1826 { .compatible
= "samsung,s3c2412-uart",
1827 .data
= (void *)S3C2412_SERIAL_DRV_DATA
},
1828 { .compatible
= "samsung,s3c2440-uart",
1829 .data
= (void *)S3C2440_SERIAL_DRV_DATA
},
1830 { .compatible
= "samsung,s3c6400-uart",
1831 .data
= (void *)S3C6400_SERIAL_DRV_DATA
},
1832 { .compatible
= "samsung,s5pv210-uart",
1833 .data
= (void *)S5PV210_SERIAL_DRV_DATA
},
1834 { .compatible
= "samsung,exynos4210-uart",
1835 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
1838 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
1841 static struct platform_driver samsung_serial_driver
= {
1842 .probe
= s3c24xx_serial_probe
,
1843 .remove
= s3c24xx_serial_remove
,
1844 .id_table
= s3c24xx_serial_driver_ids
,
1846 .name
= "samsung-uart",
1847 .owner
= THIS_MODULE
,
1848 .pm
= SERIAL_SAMSUNG_PM_OPS
,
1849 .of_match_table
= of_match_ptr(s3c24xx_uart_dt_match
),
1853 module_platform_driver(samsung_serial_driver
);
1855 MODULE_ALIAS("platform:samsung-uart");
1856 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1857 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1858 MODULE_LICENSE("GPL v2");