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Merge tag 'power-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[deliverable/linux.git] / drivers / tty / serial / samsung.c
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46 #include <linux/of.h>
47
48 #include <asm/irq.h>
49
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
52 #endif
53
54 #include "samsung.h"
55
56 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
57 defined(CONFIG_DEBUG_LL) && \
58 !defined(MODULE)
59
60 extern void printascii(const char *);
61
62 __printf(1, 2)
63 static void dbg(const char *fmt, ...)
64 {
65 va_list va;
66 char buff[256];
67
68 va_start(va, fmt);
69 vscnprintf(buff, sizeof(buff), fmt, va);
70 va_end(va);
71
72 printascii(buff);
73 }
74
75 #else
76 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
77 #endif
78
79 /* UART name and device definitions */
80
81 #define S3C24XX_SERIAL_NAME "ttySAC"
82 #define S3C24XX_SERIAL_MAJOR 204
83 #define S3C24XX_SERIAL_MINOR 64
84
85 /* macros to change one thing to another */
86
87 #define tx_enabled(port) ((port)->unused[0])
88 #define rx_enabled(port) ((port)->unused[1])
89
90 /* flag to ignore all characters coming in */
91 #define RXSTAT_DUMMY_READ (0x10000000)
92
93 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
94 {
95 return container_of(port, struct s3c24xx_uart_port, port);
96 }
97
98 /* translate a port to the device name */
99
100 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
101 {
102 return to_platform_device(port->dev)->name;
103 }
104
105 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
106 {
107 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
108 }
109
110 /*
111 * s3c64xx and later SoC's include the interrupt mask and status registers in
112 * the controller itself, unlike the s3c24xx SoC's which have these registers
113 * in the interrupt controller. Check if the port type is s3c64xx or higher.
114 */
115 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
116 {
117 return to_ourport(port)->info->type == PORT_S3C6400;
118 }
119
120 static void s3c24xx_serial_rx_enable(struct uart_port *port)
121 {
122 unsigned long flags;
123 unsigned int ucon, ufcon;
124 int count = 10000;
125
126 spin_lock_irqsave(&port->lock, flags);
127
128 while (--count && !s3c24xx_serial_txempty_nofifo(port))
129 udelay(100);
130
131 ufcon = rd_regl(port, S3C2410_UFCON);
132 ufcon |= S3C2410_UFCON_RESETRX;
133 wr_regl(port, S3C2410_UFCON, ufcon);
134
135 ucon = rd_regl(port, S3C2410_UCON);
136 ucon |= S3C2410_UCON_RXIRQMODE;
137 wr_regl(port, S3C2410_UCON, ucon);
138
139 rx_enabled(port) = 1;
140 spin_unlock_irqrestore(&port->lock, flags);
141 }
142
143 static void s3c24xx_serial_rx_disable(struct uart_port *port)
144 {
145 unsigned long flags;
146 unsigned int ucon;
147
148 spin_lock_irqsave(&port->lock, flags);
149
150 ucon = rd_regl(port, S3C2410_UCON);
151 ucon &= ~S3C2410_UCON_RXIRQMODE;
152 wr_regl(port, S3C2410_UCON, ucon);
153
154 rx_enabled(port) = 0;
155 spin_unlock_irqrestore(&port->lock, flags);
156 }
157
158 static void s3c24xx_serial_stop_tx(struct uart_port *port)
159 {
160 struct s3c24xx_uart_port *ourport = to_ourport(port);
161
162 if (tx_enabled(port)) {
163 if (s3c24xx_serial_has_interrupt_mask(port))
164 __set_bit(S3C64XX_UINTM_TXD,
165 portaddrl(port, S3C64XX_UINTM));
166 else
167 disable_irq_nosync(ourport->tx_irq);
168 tx_enabled(port) = 0;
169 if (port->flags & UPF_CONS_FLOW)
170 s3c24xx_serial_rx_enable(port);
171 }
172 }
173
174 static void s3c24xx_serial_start_tx(struct uart_port *port)
175 {
176 struct s3c24xx_uart_port *ourport = to_ourport(port);
177
178 if (!tx_enabled(port)) {
179 if (port->flags & UPF_CONS_FLOW)
180 s3c24xx_serial_rx_disable(port);
181
182 if (s3c24xx_serial_has_interrupt_mask(port))
183 __clear_bit(S3C64XX_UINTM_TXD,
184 portaddrl(port, S3C64XX_UINTM));
185 else
186 enable_irq(ourport->tx_irq);
187 tx_enabled(port) = 1;
188 }
189 }
190
191 static void s3c24xx_serial_stop_rx(struct uart_port *port)
192 {
193 struct s3c24xx_uart_port *ourport = to_ourport(port);
194
195 if (rx_enabled(port)) {
196 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
197 if (s3c24xx_serial_has_interrupt_mask(port))
198 __set_bit(S3C64XX_UINTM_RXD,
199 portaddrl(port, S3C64XX_UINTM));
200 else
201 disable_irq_nosync(ourport->rx_irq);
202 rx_enabled(port) = 0;
203 }
204 }
205
206 static void s3c24xx_serial_enable_ms(struct uart_port *port)
207 {
208 }
209
210 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
211 {
212 return to_ourport(port)->info;
213 }
214
215 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
216 {
217 struct s3c24xx_uart_port *ourport;
218
219 if (port->dev == NULL)
220 return NULL;
221
222 ourport = container_of(port, struct s3c24xx_uart_port, port);
223 return ourport->cfg;
224 }
225
226 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
227 unsigned long ufstat)
228 {
229 struct s3c24xx_uart_info *info = ourport->info;
230
231 if (ufstat & info->rx_fifofull)
232 return ourport->port.fifosize;
233
234 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
235 }
236
237
238 /* ? - where has parity gone?? */
239 #define S3C2410_UERSTAT_PARITY (0x1000)
240
241 static irqreturn_t
242 s3c24xx_serial_rx_chars(int irq, void *dev_id)
243 {
244 struct s3c24xx_uart_port *ourport = dev_id;
245 struct uart_port *port = &ourport->port;
246 unsigned int ufcon, ch, flag, ufstat, uerstat;
247 unsigned long flags;
248 int max_count = 64;
249
250 spin_lock_irqsave(&port->lock, flags);
251
252 while (max_count-- > 0) {
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufstat = rd_regl(port, S3C2410_UFSTAT);
255
256 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
257 break;
258
259 uerstat = rd_regl(port, S3C2410_UERSTAT);
260 ch = rd_regb(port, S3C2410_URXH);
261
262 if (port->flags & UPF_CONS_FLOW) {
263 int txe = s3c24xx_serial_txempty_nofifo(port);
264
265 if (rx_enabled(port)) {
266 if (!txe) {
267 rx_enabled(port) = 0;
268 continue;
269 }
270 } else {
271 if (txe) {
272 ufcon |= S3C2410_UFCON_RESETRX;
273 wr_regl(port, S3C2410_UFCON, ufcon);
274 rx_enabled(port) = 1;
275 spin_unlock_irqrestore(&port->lock,
276 flags);
277 goto out;
278 }
279 continue;
280 }
281 }
282
283 /* insert the character into the buffer */
284
285 flag = TTY_NORMAL;
286 port->icount.rx++;
287
288 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
289 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
290 ch, uerstat);
291
292 /* check for break */
293 if (uerstat & S3C2410_UERSTAT_BREAK) {
294 dbg("break!\n");
295 port->icount.brk++;
296 if (uart_handle_break(port))
297 goto ignore_char;
298 }
299
300 if (uerstat & S3C2410_UERSTAT_FRAME)
301 port->icount.frame++;
302 if (uerstat & S3C2410_UERSTAT_OVERRUN)
303 port->icount.overrun++;
304
305 uerstat &= port->read_status_mask;
306
307 if (uerstat & S3C2410_UERSTAT_BREAK)
308 flag = TTY_BREAK;
309 else if (uerstat & S3C2410_UERSTAT_PARITY)
310 flag = TTY_PARITY;
311 else if (uerstat & (S3C2410_UERSTAT_FRAME |
312 S3C2410_UERSTAT_OVERRUN))
313 flag = TTY_FRAME;
314 }
315
316 if (uart_handle_sysrq_char(port, ch))
317 goto ignore_char;
318
319 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
320 ch, flag);
321
322 ignore_char:
323 continue;
324 }
325
326 spin_unlock_irqrestore(&port->lock, flags);
327 tty_flip_buffer_push(&port->state->port);
328
329 out:
330 return IRQ_HANDLED;
331 }
332
333 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
334 {
335 struct s3c24xx_uart_port *ourport = id;
336 struct uart_port *port = &ourport->port;
337 struct circ_buf *xmit = &port->state->xmit;
338 unsigned long flags;
339 int count = 256;
340
341 spin_lock_irqsave(&port->lock, flags);
342
343 if (port->x_char) {
344 wr_regb(port, S3C2410_UTXH, port->x_char);
345 port->icount.tx++;
346 port->x_char = 0;
347 goto out;
348 }
349
350 /* if there isn't anything more to transmit, or the uart is now
351 * stopped, disable the uart and exit
352 */
353
354 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
355 s3c24xx_serial_stop_tx(port);
356 goto out;
357 }
358
359 /* try and drain the buffer... */
360
361 while (!uart_circ_empty(xmit) && count-- > 0) {
362 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
363 break;
364
365 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
366 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
367 port->icount.tx++;
368 }
369
370 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
371 spin_unlock(&port->lock);
372 uart_write_wakeup(port);
373 spin_lock(&port->lock);
374 }
375
376 if (uart_circ_empty(xmit))
377 s3c24xx_serial_stop_tx(port);
378
379 out:
380 spin_unlock_irqrestore(&port->lock, flags);
381 return IRQ_HANDLED;
382 }
383
384 /* interrupt handler for s3c64xx and later SoC's.*/
385 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
386 {
387 struct s3c24xx_uart_port *ourport = id;
388 struct uart_port *port = &ourport->port;
389 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
390 irqreturn_t ret = IRQ_HANDLED;
391
392 if (pend & S3C64XX_UINTM_RXD_MSK) {
393 ret = s3c24xx_serial_rx_chars(irq, id);
394 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
395 }
396 if (pend & S3C64XX_UINTM_TXD_MSK) {
397 ret = s3c24xx_serial_tx_chars(irq, id);
398 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
399 }
400 return ret;
401 }
402
403 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
404 {
405 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
406 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
407 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
408
409 if (ufcon & S3C2410_UFCON_FIFOMODE) {
410 if ((ufstat & info->tx_fifomask) != 0 ||
411 (ufstat & info->tx_fifofull))
412 return 0;
413
414 return 1;
415 }
416
417 return s3c24xx_serial_txempty_nofifo(port);
418 }
419
420 /* no modem control lines */
421 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
422 {
423 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
424
425 if (umstat & S3C2410_UMSTAT_CTS)
426 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
427 else
428 return TIOCM_CAR | TIOCM_DSR;
429 }
430
431 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
432 {
433 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
434
435 if (mctrl & TIOCM_RTS)
436 umcon |= S3C2410_UMCOM_RTS_LOW;
437 else
438 umcon &= ~S3C2410_UMCOM_RTS_LOW;
439
440 wr_regl(port, S3C2410_UMCON, umcon);
441 }
442
443 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
444 {
445 unsigned long flags;
446 unsigned int ucon;
447
448 spin_lock_irqsave(&port->lock, flags);
449
450 ucon = rd_regl(port, S3C2410_UCON);
451
452 if (break_state)
453 ucon |= S3C2410_UCON_SBREAK;
454 else
455 ucon &= ~S3C2410_UCON_SBREAK;
456
457 wr_regl(port, S3C2410_UCON, ucon);
458
459 spin_unlock_irqrestore(&port->lock, flags);
460 }
461
462 static void s3c24xx_serial_shutdown(struct uart_port *port)
463 {
464 struct s3c24xx_uart_port *ourport = to_ourport(port);
465
466 if (ourport->tx_claimed) {
467 if (!s3c24xx_serial_has_interrupt_mask(port))
468 free_irq(ourport->tx_irq, ourport);
469 tx_enabled(port) = 0;
470 ourport->tx_claimed = 0;
471 }
472
473 if (ourport->rx_claimed) {
474 if (!s3c24xx_serial_has_interrupt_mask(port))
475 free_irq(ourport->rx_irq, ourport);
476 ourport->rx_claimed = 0;
477 rx_enabled(port) = 0;
478 }
479
480 /* Clear pending interrupts and mask all interrupts */
481 if (s3c24xx_serial_has_interrupt_mask(port)) {
482 free_irq(port->irq, ourport);
483
484 wr_regl(port, S3C64XX_UINTP, 0xf);
485 wr_regl(port, S3C64XX_UINTM, 0xf);
486 }
487 }
488
489 static int s3c24xx_serial_startup(struct uart_port *port)
490 {
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
492 int ret;
493
494 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
495 port, (unsigned long long)port->mapbase, port->membase);
496
497 rx_enabled(port) = 1;
498
499 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
500 s3c24xx_serial_portname(port), ourport);
501
502 if (ret != 0) {
503 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
504 return ret;
505 }
506
507 ourport->rx_claimed = 1;
508
509 dbg("requesting tx irq...\n");
510
511 tx_enabled(port) = 1;
512
513 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
514 s3c24xx_serial_portname(port), ourport);
515
516 if (ret) {
517 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
518 goto err;
519 }
520
521 ourport->tx_claimed = 1;
522
523 dbg("s3c24xx_serial_startup ok\n");
524
525 /* the port reset code should have done the correct
526 * register setup for the port controls */
527
528 return ret;
529
530 err:
531 s3c24xx_serial_shutdown(port);
532 return ret;
533 }
534
535 static int s3c64xx_serial_startup(struct uart_port *port)
536 {
537 struct s3c24xx_uart_port *ourport = to_ourport(port);
538 int ret;
539
540 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
541 port, (unsigned long long)port->mapbase, port->membase);
542
543 wr_regl(port, S3C64XX_UINTM, 0xf);
544
545 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
546 s3c24xx_serial_portname(port), ourport);
547 if (ret) {
548 dev_err(port->dev, "cannot get irq %d\n", port->irq);
549 return ret;
550 }
551
552 /* For compatibility with s3c24xx Soc's */
553 rx_enabled(port) = 1;
554 ourport->rx_claimed = 1;
555 tx_enabled(port) = 0;
556 ourport->tx_claimed = 1;
557
558 /* Enable Rx Interrupt */
559 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
560 dbg("s3c64xx_serial_startup ok\n");
561 return ret;
562 }
563
564 /* power power management control */
565
566 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
567 unsigned int old)
568 {
569 struct s3c24xx_uart_port *ourport = to_ourport(port);
570
571 ourport->pm_level = level;
572
573 switch (level) {
574 case 3:
575 if (!IS_ERR(ourport->baudclk))
576 clk_disable_unprepare(ourport->baudclk);
577
578 clk_disable_unprepare(ourport->clk);
579 break;
580
581 case 0:
582 clk_prepare_enable(ourport->clk);
583
584 if (!IS_ERR(ourport->baudclk))
585 clk_prepare_enable(ourport->baudclk);
586
587 break;
588 default:
589 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
590 }
591 }
592
593 /* baud rate calculation
594 *
595 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
596 * of different sources, including the peripheral clock ("pclk") and an
597 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
598 * with a programmable extra divisor.
599 *
600 * The following code goes through the clock sources, and calculates the
601 * baud clocks (and the resultant actual baud rates) and then tries to
602 * pick the closest one and select that.
603 *
604 */
605
606 #define MAX_CLK_NAME_LENGTH 15
607
608 static inline int s3c24xx_serial_getsource(struct uart_port *port)
609 {
610 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
611 unsigned int ucon;
612
613 if (info->num_clks == 1)
614 return 0;
615
616 ucon = rd_regl(port, S3C2410_UCON);
617 ucon &= info->clksel_mask;
618 return ucon >> info->clksel_shift;
619 }
620
621 static void s3c24xx_serial_setsource(struct uart_port *port,
622 unsigned int clk_sel)
623 {
624 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
625 unsigned int ucon;
626
627 if (info->num_clks == 1)
628 return;
629
630 ucon = rd_regl(port, S3C2410_UCON);
631 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
632 return;
633
634 ucon &= ~info->clksel_mask;
635 ucon |= clk_sel << info->clksel_shift;
636 wr_regl(port, S3C2410_UCON, ucon);
637 }
638
639 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
640 unsigned int req_baud, struct clk **best_clk,
641 unsigned int *clk_num)
642 {
643 struct s3c24xx_uart_info *info = ourport->info;
644 struct clk *clk;
645 unsigned long rate;
646 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
647 char clkname[MAX_CLK_NAME_LENGTH];
648 int calc_deviation, deviation = (1 << 30) - 1;
649
650 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
651 ourport->info->def_clk_sel;
652 for (cnt = 0; cnt < info->num_clks; cnt++) {
653 if (!(clk_sel & (1 << cnt)))
654 continue;
655
656 sprintf(clkname, "clk_uart_baud%d", cnt);
657 clk = clk_get(ourport->port.dev, clkname);
658 if (IS_ERR(clk))
659 continue;
660
661 rate = clk_get_rate(clk);
662 if (!rate)
663 continue;
664
665 if (ourport->info->has_divslot) {
666 unsigned long div = rate / req_baud;
667
668 /* The UDIVSLOT register on the newer UARTs allows us to
669 * get a divisor adjustment of 1/16th on the baud clock.
670 *
671 * We don't keep the UDIVSLOT value (the 16ths we
672 * calculated by not multiplying the baud by 16) as it
673 * is easy enough to recalculate.
674 */
675
676 quot = div / 16;
677 baud = rate / div;
678 } else {
679 quot = (rate + (8 * req_baud)) / (16 * req_baud);
680 baud = rate / (quot * 16);
681 }
682 quot--;
683
684 calc_deviation = req_baud - baud;
685 if (calc_deviation < 0)
686 calc_deviation = -calc_deviation;
687
688 if (calc_deviation < deviation) {
689 *best_clk = clk;
690 best_quot = quot;
691 *clk_num = cnt;
692 deviation = calc_deviation;
693 }
694 }
695
696 return best_quot;
697 }
698
699 /* udivslot_table[]
700 *
701 * This table takes the fractional value of the baud divisor and gives
702 * the recommended setting for the UDIVSLOT register.
703 */
704 static u16 udivslot_table[16] = {
705 [0] = 0x0000,
706 [1] = 0x0080,
707 [2] = 0x0808,
708 [3] = 0x0888,
709 [4] = 0x2222,
710 [5] = 0x4924,
711 [6] = 0x4A52,
712 [7] = 0x54AA,
713 [8] = 0x5555,
714 [9] = 0xD555,
715 [10] = 0xD5D5,
716 [11] = 0xDDD5,
717 [12] = 0xDDDD,
718 [13] = 0xDFDD,
719 [14] = 0xDFDF,
720 [15] = 0xFFDF,
721 };
722
723 static void s3c24xx_serial_set_termios(struct uart_port *port,
724 struct ktermios *termios,
725 struct ktermios *old)
726 {
727 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
728 struct s3c24xx_uart_port *ourport = to_ourport(port);
729 struct clk *clk = ERR_PTR(-EINVAL);
730 unsigned long flags;
731 unsigned int baud, quot, clk_sel = 0;
732 unsigned int ulcon;
733 unsigned int umcon;
734 unsigned int udivslot = 0;
735
736 /*
737 * We don't support modem control lines.
738 */
739 termios->c_cflag &= ~(HUPCL | CMSPAR);
740 termios->c_cflag |= CLOCAL;
741
742 /*
743 * Ask the core to calculate the divisor for us.
744 */
745
746 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
747 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
748 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
749 quot = port->custom_divisor;
750 if (IS_ERR(clk))
751 return;
752
753 /* check to see if we need to change clock source */
754
755 if (ourport->baudclk != clk) {
756 s3c24xx_serial_setsource(port, clk_sel);
757
758 if (!IS_ERR(ourport->baudclk)) {
759 clk_disable_unprepare(ourport->baudclk);
760 ourport->baudclk = ERR_PTR(-EINVAL);
761 }
762
763 clk_prepare_enable(clk);
764
765 ourport->baudclk = clk;
766 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
767 }
768
769 if (ourport->info->has_divslot) {
770 unsigned int div = ourport->baudclk_rate / baud;
771
772 if (cfg->has_fracval) {
773 udivslot = (div & 15);
774 dbg("fracval = %04x\n", udivslot);
775 } else {
776 udivslot = udivslot_table[div & 15];
777 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
778 }
779 }
780
781 switch (termios->c_cflag & CSIZE) {
782 case CS5:
783 dbg("config: 5bits/char\n");
784 ulcon = S3C2410_LCON_CS5;
785 break;
786 case CS6:
787 dbg("config: 6bits/char\n");
788 ulcon = S3C2410_LCON_CS6;
789 break;
790 case CS7:
791 dbg("config: 7bits/char\n");
792 ulcon = S3C2410_LCON_CS7;
793 break;
794 case CS8:
795 default:
796 dbg("config: 8bits/char\n");
797 ulcon = S3C2410_LCON_CS8;
798 break;
799 }
800
801 /* preserve original lcon IR settings */
802 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
803
804 if (termios->c_cflag & CSTOPB)
805 ulcon |= S3C2410_LCON_STOPB;
806
807 if (termios->c_cflag & PARENB) {
808 if (termios->c_cflag & PARODD)
809 ulcon |= S3C2410_LCON_PODD;
810 else
811 ulcon |= S3C2410_LCON_PEVEN;
812 } else {
813 ulcon |= S3C2410_LCON_PNONE;
814 }
815
816 spin_lock_irqsave(&port->lock, flags);
817
818 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
819 ulcon, quot, udivslot);
820
821 wr_regl(port, S3C2410_ULCON, ulcon);
822 wr_regl(port, S3C2410_UBRDIV, quot);
823
824 umcon = rd_regl(port, S3C2410_UMCON);
825 if (termios->c_cflag & CRTSCTS) {
826 umcon |= S3C2410_UMCOM_AFC;
827 /* Disable RTS when RX FIFO contains 63 bytes */
828 umcon &= ~S3C2412_UMCON_AFC_8;
829 } else {
830 umcon &= ~S3C2410_UMCOM_AFC;
831 }
832 wr_regl(port, S3C2410_UMCON, umcon);
833
834 if (ourport->info->has_divslot)
835 wr_regl(port, S3C2443_DIVSLOT, udivslot);
836
837 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
838 rd_regl(port, S3C2410_ULCON),
839 rd_regl(port, S3C2410_UCON),
840 rd_regl(port, S3C2410_UFCON));
841
842 /*
843 * Update the per-port timeout.
844 */
845 uart_update_timeout(port, termios->c_cflag, baud);
846
847 /*
848 * Which character status flags are we interested in?
849 */
850 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
851 if (termios->c_iflag & INPCK)
852 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
853
854 /*
855 * Which character status flags should we ignore?
856 */
857 port->ignore_status_mask = 0;
858 if (termios->c_iflag & IGNPAR)
859 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
860 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
861 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
862
863 /*
864 * Ignore all characters if CREAD is not set.
865 */
866 if ((termios->c_cflag & CREAD) == 0)
867 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
868
869 spin_unlock_irqrestore(&port->lock, flags);
870 }
871
872 static const char *s3c24xx_serial_type(struct uart_port *port)
873 {
874 switch (port->type) {
875 case PORT_S3C2410:
876 return "S3C2410";
877 case PORT_S3C2440:
878 return "S3C2440";
879 case PORT_S3C2412:
880 return "S3C2412";
881 case PORT_S3C6400:
882 return "S3C6400/10";
883 default:
884 return NULL;
885 }
886 }
887
888 #define MAP_SIZE (0x100)
889
890 static void s3c24xx_serial_release_port(struct uart_port *port)
891 {
892 release_mem_region(port->mapbase, MAP_SIZE);
893 }
894
895 static int s3c24xx_serial_request_port(struct uart_port *port)
896 {
897 const char *name = s3c24xx_serial_portname(port);
898 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
899 }
900
901 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
902 {
903 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
904
905 if (flags & UART_CONFIG_TYPE &&
906 s3c24xx_serial_request_port(port) == 0)
907 port->type = info->type;
908 }
909
910 /*
911 * verify the new serial_struct (for TIOCSSERIAL).
912 */
913 static int
914 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
915 {
916 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
917
918 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
919 return -EINVAL;
920
921 return 0;
922 }
923
924
925 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
926
927 static struct console s3c24xx_serial_console;
928
929 static int __init s3c24xx_serial_console_init(void)
930 {
931 register_console(&s3c24xx_serial_console);
932 return 0;
933 }
934 console_initcall(s3c24xx_serial_console_init);
935
936 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
937 #else
938 #define S3C24XX_SERIAL_CONSOLE NULL
939 #endif
940
941 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
942 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
943 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
944 unsigned char c);
945 #endif
946
947 static struct uart_ops s3c24xx_serial_ops = {
948 .pm = s3c24xx_serial_pm,
949 .tx_empty = s3c24xx_serial_tx_empty,
950 .get_mctrl = s3c24xx_serial_get_mctrl,
951 .set_mctrl = s3c24xx_serial_set_mctrl,
952 .stop_tx = s3c24xx_serial_stop_tx,
953 .start_tx = s3c24xx_serial_start_tx,
954 .stop_rx = s3c24xx_serial_stop_rx,
955 .enable_ms = s3c24xx_serial_enable_ms,
956 .break_ctl = s3c24xx_serial_break_ctl,
957 .startup = s3c24xx_serial_startup,
958 .shutdown = s3c24xx_serial_shutdown,
959 .set_termios = s3c24xx_serial_set_termios,
960 .type = s3c24xx_serial_type,
961 .release_port = s3c24xx_serial_release_port,
962 .request_port = s3c24xx_serial_request_port,
963 .config_port = s3c24xx_serial_config_port,
964 .verify_port = s3c24xx_serial_verify_port,
965 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
966 .poll_get_char = s3c24xx_serial_get_poll_char,
967 .poll_put_char = s3c24xx_serial_put_poll_char,
968 #endif
969 };
970
971 static struct uart_driver s3c24xx_uart_drv = {
972 .owner = THIS_MODULE,
973 .driver_name = "s3c2410_serial",
974 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
975 .cons = S3C24XX_SERIAL_CONSOLE,
976 .dev_name = S3C24XX_SERIAL_NAME,
977 .major = S3C24XX_SERIAL_MAJOR,
978 .minor = S3C24XX_SERIAL_MINOR,
979 };
980
981 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
982 [0] = {
983 .port = {
984 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
985 .iotype = UPIO_MEM,
986 .uartclk = 0,
987 .fifosize = 16,
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
990 .line = 0,
991 }
992 },
993 [1] = {
994 .port = {
995 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
996 .iotype = UPIO_MEM,
997 .uartclk = 0,
998 .fifosize = 16,
999 .ops = &s3c24xx_serial_ops,
1000 .flags = UPF_BOOT_AUTOCONF,
1001 .line = 1,
1002 }
1003 },
1004 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1005
1006 [2] = {
1007 .port = {
1008 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1009 .iotype = UPIO_MEM,
1010 .uartclk = 0,
1011 .fifosize = 16,
1012 .ops = &s3c24xx_serial_ops,
1013 .flags = UPF_BOOT_AUTOCONF,
1014 .line = 2,
1015 }
1016 },
1017 #endif
1018 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1019 [3] = {
1020 .port = {
1021 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1022 .iotype = UPIO_MEM,
1023 .uartclk = 0,
1024 .fifosize = 16,
1025 .ops = &s3c24xx_serial_ops,
1026 .flags = UPF_BOOT_AUTOCONF,
1027 .line = 3,
1028 }
1029 }
1030 #endif
1031 };
1032
1033 /* s3c24xx_serial_resetport
1034 *
1035 * reset the fifos and other the settings.
1036 */
1037
1038 static void s3c24xx_serial_resetport(struct uart_port *port,
1039 struct s3c2410_uartcfg *cfg)
1040 {
1041 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1042 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1043 unsigned int ucon_mask;
1044
1045 ucon_mask = info->clksel_mask;
1046 if (info->type == PORT_S3C2440)
1047 ucon_mask |= S3C2440_UCON0_DIVMASK;
1048
1049 ucon &= ucon_mask;
1050 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1051
1052 /* reset both fifos */
1053 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1054 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1055
1056 /* some delay is required after fifo reset */
1057 udelay(1);
1058 }
1059
1060
1061 #ifdef CONFIG_CPU_FREQ
1062
1063 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1064 unsigned long val, void *data)
1065 {
1066 struct s3c24xx_uart_port *port;
1067 struct uart_port *uport;
1068
1069 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1070 uport = &port->port;
1071
1072 /* check to see if port is enabled */
1073
1074 if (port->pm_level != 0)
1075 return 0;
1076
1077 /* try and work out if the baudrate is changing, we can detect
1078 * a change in rate, but we do not have support for detecting
1079 * a disturbance in the clock-rate over the change.
1080 */
1081
1082 if (IS_ERR(port->baudclk))
1083 goto exit;
1084
1085 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1086 goto exit;
1087
1088 if (val == CPUFREQ_PRECHANGE) {
1089 /* we should really shut the port down whilst the
1090 * frequency change is in progress. */
1091
1092 } else if (val == CPUFREQ_POSTCHANGE) {
1093 struct ktermios *termios;
1094 struct tty_struct *tty;
1095
1096 if (uport->state == NULL)
1097 goto exit;
1098
1099 tty = uport->state->port.tty;
1100
1101 if (tty == NULL)
1102 goto exit;
1103
1104 termios = &tty->termios;
1105
1106 if (termios == NULL) {
1107 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1108 goto exit;
1109 }
1110
1111 s3c24xx_serial_set_termios(uport, termios, NULL);
1112 }
1113
1114 exit:
1115 return 0;
1116 }
1117
1118 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1119 {
1120 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1121
1122 return cpufreq_register_notifier(&port->freq_transition,
1123 CPUFREQ_TRANSITION_NOTIFIER);
1124 }
1125
1126 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1127 {
1128 cpufreq_unregister_notifier(&port->freq_transition,
1129 CPUFREQ_TRANSITION_NOTIFIER);
1130 }
1131
1132 #else
1133 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1134 {
1135 return 0;
1136 }
1137
1138 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1139 {
1140 }
1141 #endif
1142
1143 /* s3c24xx_serial_init_port
1144 *
1145 * initialise a single serial port from the platform device given
1146 */
1147
1148 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1149 struct platform_device *platdev)
1150 {
1151 struct uart_port *port = &ourport->port;
1152 struct s3c2410_uartcfg *cfg = ourport->cfg;
1153 struct resource *res;
1154 int ret;
1155
1156 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1157
1158 if (platdev == NULL)
1159 return -ENODEV;
1160
1161 if (port->mapbase != 0)
1162 return 0;
1163
1164 /* setup info for port */
1165 port->dev = &platdev->dev;
1166
1167 /* Startup sequence is different for s3c64xx and higher SoC's */
1168 if (s3c24xx_serial_has_interrupt_mask(port))
1169 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1170
1171 port->uartclk = 1;
1172
1173 if (cfg->uart_flags & UPF_CONS_FLOW) {
1174 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1175 port->flags |= UPF_CONS_FLOW;
1176 }
1177
1178 /* sort our the physical and virtual addresses for each UART */
1179
1180 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1181 if (res == NULL) {
1182 dev_err(port->dev, "failed to find memory resource for uart\n");
1183 return -EINVAL;
1184 }
1185
1186 dbg("resource %pR)\n", res);
1187
1188 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1189 if (!port->membase) {
1190 dev_err(port->dev, "failed to remap controller address\n");
1191 return -EBUSY;
1192 }
1193
1194 port->mapbase = res->start;
1195 ret = platform_get_irq(platdev, 0);
1196 if (ret < 0)
1197 port->irq = 0;
1198 else {
1199 port->irq = ret;
1200 ourport->rx_irq = ret;
1201 ourport->tx_irq = ret + 1;
1202 }
1203
1204 ret = platform_get_irq(platdev, 1);
1205 if (ret > 0)
1206 ourport->tx_irq = ret;
1207
1208 ourport->clk = clk_get(&platdev->dev, "uart");
1209 if (IS_ERR(ourport->clk)) {
1210 pr_err("%s: Controller clock not found\n",
1211 dev_name(&platdev->dev));
1212 return PTR_ERR(ourport->clk);
1213 }
1214
1215 ret = clk_prepare_enable(ourport->clk);
1216 if (ret) {
1217 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1218 clk_put(ourport->clk);
1219 return ret;
1220 }
1221
1222 /* Keep all interrupts masked and cleared */
1223 if (s3c24xx_serial_has_interrupt_mask(port)) {
1224 wr_regl(port, S3C64XX_UINTM, 0xf);
1225 wr_regl(port, S3C64XX_UINTP, 0xf);
1226 wr_regl(port, S3C64XX_UINTSP, 0xf);
1227 }
1228
1229 dbg("port: map=%08x, mem=%p, irq=%d (%d,%d), clock=%u\n",
1230 port->mapbase, port->membase, port->irq,
1231 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1232
1233 /* reset the fifos (and setup the uart) */
1234 s3c24xx_serial_resetport(port, cfg);
1235 return 0;
1236 }
1237
1238 #ifdef CONFIG_SAMSUNG_CLOCK
1239 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1240 struct device_attribute *attr,
1241 char *buf)
1242 {
1243 struct uart_port *port = s3c24xx_dev_to_port(dev);
1244 struct s3c24xx_uart_port *ourport = to_ourport(port);
1245
1246 if (IS_ERR(ourport->baudclk))
1247 return -EINVAL;
1248
1249 return snprintf(buf, PAGE_SIZE, "* %s\n",
1250 ourport->baudclk->name ?: "(null)");
1251 }
1252
1253 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1254 #endif
1255
1256 /* Device driver serial port probe */
1257
1258 static const struct of_device_id s3c24xx_uart_dt_match[];
1259 static int probe_index;
1260
1261 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1262 struct platform_device *pdev)
1263 {
1264 #ifdef CONFIG_OF
1265 if (pdev->dev.of_node) {
1266 const struct of_device_id *match;
1267 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1268 return (struct s3c24xx_serial_drv_data *)match->data;
1269 }
1270 #endif
1271 return (struct s3c24xx_serial_drv_data *)
1272 platform_get_device_id(pdev)->driver_data;
1273 }
1274
1275 static int s3c24xx_serial_probe(struct platform_device *pdev)
1276 {
1277 struct s3c24xx_uart_port *ourport;
1278 int ret;
1279
1280 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1281
1282 ourport = &s3c24xx_serial_ports[probe_index];
1283
1284 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1285 if (!ourport->drv_data) {
1286 dev_err(&pdev->dev, "could not find driver data\n");
1287 return -ENODEV;
1288 }
1289
1290 ourport->baudclk = ERR_PTR(-EINVAL);
1291 ourport->info = ourport->drv_data->info;
1292 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1293 dev_get_platdata(&pdev->dev) :
1294 ourport->drv_data->def_cfg;
1295
1296 ourport->port.fifosize = (ourport->info->fifosize) ?
1297 ourport->info->fifosize :
1298 ourport->drv_data->fifosize[probe_index];
1299
1300 probe_index++;
1301
1302 dbg("%s: initialising port %p...\n", __func__, ourport);
1303
1304 ret = s3c24xx_serial_init_port(ourport, pdev);
1305 if (ret < 0)
1306 goto probe_err;
1307
1308 if (!s3c24xx_uart_drv.state) {
1309 ret = uart_register_driver(&s3c24xx_uart_drv);
1310 if (ret < 0) {
1311 pr_err("Failed to register Samsung UART driver\n");
1312 return ret;
1313 }
1314 }
1315
1316 dbg("%s: adding port\n", __func__);
1317 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1318 platform_set_drvdata(pdev, &ourport->port);
1319
1320 /*
1321 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1322 * so that a potential re-enablement through the pm-callback overlaps
1323 * and keeps the clock enabled in this case.
1324 */
1325 clk_disable_unprepare(ourport->clk);
1326
1327 #ifdef CONFIG_SAMSUNG_CLOCK
1328 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1329 if (ret < 0)
1330 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1331 #endif
1332
1333 ret = s3c24xx_serial_cpufreq_register(ourport);
1334 if (ret < 0)
1335 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1336
1337 return 0;
1338
1339 probe_err:
1340 return ret;
1341 }
1342
1343 static int s3c24xx_serial_remove(struct platform_device *dev)
1344 {
1345 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1346
1347 if (port) {
1348 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1349 #ifdef CONFIG_SAMSUNG_CLOCK
1350 device_remove_file(&dev->dev, &dev_attr_clock_source);
1351 #endif
1352 uart_remove_one_port(&s3c24xx_uart_drv, port);
1353 }
1354
1355 uart_unregister_driver(&s3c24xx_uart_drv);
1356
1357 return 0;
1358 }
1359
1360 /* UART power management code */
1361 #ifdef CONFIG_PM_SLEEP
1362 static int s3c24xx_serial_suspend(struct device *dev)
1363 {
1364 struct uart_port *port = s3c24xx_dev_to_port(dev);
1365
1366 if (port)
1367 uart_suspend_port(&s3c24xx_uart_drv, port);
1368
1369 return 0;
1370 }
1371
1372 static int s3c24xx_serial_resume(struct device *dev)
1373 {
1374 struct uart_port *port = s3c24xx_dev_to_port(dev);
1375 struct s3c24xx_uart_port *ourport = to_ourport(port);
1376
1377 if (port) {
1378 clk_prepare_enable(ourport->clk);
1379 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1380 clk_disable_unprepare(ourport->clk);
1381
1382 uart_resume_port(&s3c24xx_uart_drv, port);
1383 }
1384
1385 return 0;
1386 }
1387
1388 static int s3c24xx_serial_resume_noirq(struct device *dev)
1389 {
1390 struct uart_port *port = s3c24xx_dev_to_port(dev);
1391
1392 if (port) {
1393 /* restore IRQ mask */
1394 if (s3c24xx_serial_has_interrupt_mask(port)) {
1395 unsigned int uintm = 0xf;
1396 if (tx_enabled(port))
1397 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1398 if (rx_enabled(port))
1399 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1400 wr_regl(port, S3C64XX_UINTM, uintm);
1401 }
1402 }
1403
1404 return 0;
1405 }
1406
1407 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1408 .suspend = s3c24xx_serial_suspend,
1409 .resume = s3c24xx_serial_resume,
1410 .resume_noirq = s3c24xx_serial_resume_noirq,
1411 };
1412 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1413
1414 #else /* !CONFIG_PM_SLEEP */
1415
1416 #define SERIAL_SAMSUNG_PM_OPS NULL
1417 #endif /* CONFIG_PM_SLEEP */
1418
1419 /* Console code */
1420
1421 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1422
1423 static struct uart_port *cons_uart;
1424
1425 static int
1426 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1427 {
1428 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1429 unsigned long ufstat, utrstat;
1430
1431 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1432 /* fifo mode - check amount of data in fifo registers... */
1433
1434 ufstat = rd_regl(port, S3C2410_UFSTAT);
1435 return (ufstat & info->tx_fifofull) ? 0 : 1;
1436 }
1437
1438 /* in non-fifo mode, we go and use the tx buffer empty */
1439
1440 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1441 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1442 }
1443
1444 static bool
1445 s3c24xx_port_configured(unsigned int ucon)
1446 {
1447 /* consider the serial port configured if the tx/rx mode set */
1448 return (ucon & 0xf) != 0;
1449 }
1450
1451 #ifdef CONFIG_CONSOLE_POLL
1452 /*
1453 * Console polling routines for writing and reading from the uart while
1454 * in an interrupt or debug context.
1455 */
1456
1457 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1458 {
1459 struct s3c24xx_uart_port *ourport = to_ourport(port);
1460 unsigned int ufstat;
1461
1462 ufstat = rd_regl(port, S3C2410_UFSTAT);
1463 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1464 return NO_POLL_CHAR;
1465
1466 return rd_regb(port, S3C2410_URXH);
1467 }
1468
1469 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1470 unsigned char c)
1471 {
1472 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1473 unsigned int ucon = rd_regl(port, S3C2410_UCON);
1474
1475 /* not possible to xmit on unconfigured port */
1476 if (!s3c24xx_port_configured(ucon))
1477 return;
1478
1479 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1480 cpu_relax();
1481 wr_regb(port, S3C2410_UTXH, c);
1482 }
1483
1484 #endif /* CONFIG_CONSOLE_POLL */
1485
1486 static void
1487 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1488 {
1489 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1490
1491 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1492 cpu_relax();
1493 wr_regb(port, S3C2410_UTXH, ch);
1494 }
1495
1496 static void
1497 s3c24xx_serial_console_write(struct console *co, const char *s,
1498 unsigned int count)
1499 {
1500 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1501
1502 /* not possible to xmit on unconfigured port */
1503 if (!s3c24xx_port_configured(ucon))
1504 return;
1505
1506 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1507 }
1508
1509 static void __init
1510 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1511 int *parity, int *bits)
1512 {
1513 struct clk *clk;
1514 unsigned int ulcon;
1515 unsigned int ucon;
1516 unsigned int ubrdiv;
1517 unsigned long rate;
1518 unsigned int clk_sel;
1519 char clk_name[MAX_CLK_NAME_LENGTH];
1520
1521 ulcon = rd_regl(port, S3C2410_ULCON);
1522 ucon = rd_regl(port, S3C2410_UCON);
1523 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1524
1525 dbg("s3c24xx_serial_get_options: port=%p\n"
1526 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1527 port, ulcon, ucon, ubrdiv);
1528
1529 if (s3c24xx_port_configured(ucon)) {
1530 switch (ulcon & S3C2410_LCON_CSMASK) {
1531 case S3C2410_LCON_CS5:
1532 *bits = 5;
1533 break;
1534 case S3C2410_LCON_CS6:
1535 *bits = 6;
1536 break;
1537 case S3C2410_LCON_CS7:
1538 *bits = 7;
1539 break;
1540 default:
1541 case S3C2410_LCON_CS8:
1542 *bits = 8;
1543 break;
1544 }
1545
1546 switch (ulcon & S3C2410_LCON_PMASK) {
1547 case S3C2410_LCON_PEVEN:
1548 *parity = 'e';
1549 break;
1550
1551 case S3C2410_LCON_PODD:
1552 *parity = 'o';
1553 break;
1554
1555 case S3C2410_LCON_PNONE:
1556 default:
1557 *parity = 'n';
1558 }
1559
1560 /* now calculate the baud rate */
1561
1562 clk_sel = s3c24xx_serial_getsource(port);
1563 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1564
1565 clk = clk_get(port->dev, clk_name);
1566 if (!IS_ERR(clk))
1567 rate = clk_get_rate(clk);
1568 else
1569 rate = 1;
1570
1571 *baud = rate / (16 * (ubrdiv + 1));
1572 dbg("calculated baud %d\n", *baud);
1573 }
1574
1575 }
1576
1577 static int __init
1578 s3c24xx_serial_console_setup(struct console *co, char *options)
1579 {
1580 struct uart_port *port;
1581 int baud = 9600;
1582 int bits = 8;
1583 int parity = 'n';
1584 int flow = 'n';
1585
1586 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1587 co, co->index, options);
1588
1589 /* is this a valid port */
1590
1591 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1592 co->index = 0;
1593
1594 port = &s3c24xx_serial_ports[co->index].port;
1595
1596 /* is the port configured? */
1597
1598 if (port->mapbase == 0x0)
1599 return -ENODEV;
1600
1601 cons_uart = port;
1602
1603 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1604
1605 /*
1606 * Check whether an invalid uart number has been specified, and
1607 * if so, search for the first available port that does have
1608 * console support.
1609 */
1610 if (options)
1611 uart_parse_options(options, &baud, &parity, &bits, &flow);
1612 else
1613 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1614
1615 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1616
1617 return uart_set_options(port, co, baud, parity, bits, flow);
1618 }
1619
1620 static struct console s3c24xx_serial_console = {
1621 .name = S3C24XX_SERIAL_NAME,
1622 .device = uart_console_device,
1623 .flags = CON_PRINTBUFFER,
1624 .index = -1,
1625 .write = s3c24xx_serial_console_write,
1626 .setup = s3c24xx_serial_console_setup,
1627 .data = &s3c24xx_uart_drv,
1628 };
1629 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1630
1631 #ifdef CONFIG_CPU_S3C2410
1632 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1633 .info = &(struct s3c24xx_uart_info) {
1634 .name = "Samsung S3C2410 UART",
1635 .type = PORT_S3C2410,
1636 .fifosize = 16,
1637 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1638 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1639 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1640 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1641 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1642 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1643 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1644 .num_clks = 2,
1645 .clksel_mask = S3C2410_UCON_CLKMASK,
1646 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1647 },
1648 .def_cfg = &(struct s3c2410_uartcfg) {
1649 .ucon = S3C2410_UCON_DEFAULT,
1650 .ufcon = S3C2410_UFCON_DEFAULT,
1651 },
1652 };
1653 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1654 #else
1655 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1656 #endif
1657
1658 #ifdef CONFIG_CPU_S3C2412
1659 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1660 .info = &(struct s3c24xx_uart_info) {
1661 .name = "Samsung S3C2412 UART",
1662 .type = PORT_S3C2412,
1663 .fifosize = 64,
1664 .has_divslot = 1,
1665 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1666 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1667 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1668 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1669 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1670 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1671 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1672 .num_clks = 4,
1673 .clksel_mask = S3C2412_UCON_CLKMASK,
1674 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1675 },
1676 .def_cfg = &(struct s3c2410_uartcfg) {
1677 .ucon = S3C2410_UCON_DEFAULT,
1678 .ufcon = S3C2410_UFCON_DEFAULT,
1679 },
1680 };
1681 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1682 #else
1683 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1684 #endif
1685
1686 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1687 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1688 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1689 .info = &(struct s3c24xx_uart_info) {
1690 .name = "Samsung S3C2440 UART",
1691 .type = PORT_S3C2440,
1692 .fifosize = 64,
1693 .has_divslot = 1,
1694 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1695 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1696 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1697 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1698 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1699 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1700 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1701 .num_clks = 4,
1702 .clksel_mask = S3C2412_UCON_CLKMASK,
1703 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1704 },
1705 .def_cfg = &(struct s3c2410_uartcfg) {
1706 .ucon = S3C2410_UCON_DEFAULT,
1707 .ufcon = S3C2410_UFCON_DEFAULT,
1708 },
1709 };
1710 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1711 #else
1712 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1713 #endif
1714
1715 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1716 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1717 defined(CONFIG_CPU_S5PC100)
1718 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1719 .info = &(struct s3c24xx_uart_info) {
1720 .name = "Samsung S3C6400 UART",
1721 .type = PORT_S3C6400,
1722 .fifosize = 64,
1723 .has_divslot = 1,
1724 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1725 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1726 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1727 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1728 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1729 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1730 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1731 .num_clks = 4,
1732 .clksel_mask = S3C6400_UCON_CLKMASK,
1733 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1734 },
1735 .def_cfg = &(struct s3c2410_uartcfg) {
1736 .ucon = S3C2410_UCON_DEFAULT,
1737 .ufcon = S3C2410_UFCON_DEFAULT,
1738 },
1739 };
1740 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1741 #else
1742 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1743 #endif
1744
1745 #ifdef CONFIG_CPU_S5PV210
1746 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1747 .info = &(struct s3c24xx_uart_info) {
1748 .name = "Samsung S5PV210 UART",
1749 .type = PORT_S3C6400,
1750 .has_divslot = 1,
1751 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1752 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1753 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1754 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1755 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1756 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1757 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1758 .num_clks = 2,
1759 .clksel_mask = S5PV210_UCON_CLKMASK,
1760 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1761 },
1762 .def_cfg = &(struct s3c2410_uartcfg) {
1763 .ucon = S5PV210_UCON_DEFAULT,
1764 .ufcon = S5PV210_UFCON_DEFAULT,
1765 },
1766 .fifosize = { 256, 64, 16, 16 },
1767 };
1768 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1769 #else
1770 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1771 #endif
1772
1773 #if defined(CONFIG_ARCH_EXYNOS)
1774 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1775 .info = &(struct s3c24xx_uart_info) {
1776 .name = "Samsung Exynos4 UART",
1777 .type = PORT_S3C6400,
1778 .has_divslot = 1,
1779 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1780 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1781 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1782 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1783 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1784 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1785 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1786 .num_clks = 1,
1787 .clksel_mask = 0,
1788 .clksel_shift = 0,
1789 },
1790 .def_cfg = &(struct s3c2410_uartcfg) {
1791 .ucon = S5PV210_UCON_DEFAULT,
1792 .ufcon = S5PV210_UFCON_DEFAULT,
1793 .has_fracval = 1,
1794 },
1795 .fifosize = { 256, 64, 16, 16 },
1796 };
1797 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1798 #else
1799 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1800 #endif
1801
1802 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1803 {
1804 .name = "s3c2410-uart",
1805 .driver_data = S3C2410_SERIAL_DRV_DATA,
1806 }, {
1807 .name = "s3c2412-uart",
1808 .driver_data = S3C2412_SERIAL_DRV_DATA,
1809 }, {
1810 .name = "s3c2440-uart",
1811 .driver_data = S3C2440_SERIAL_DRV_DATA,
1812 }, {
1813 .name = "s3c6400-uart",
1814 .driver_data = S3C6400_SERIAL_DRV_DATA,
1815 }, {
1816 .name = "s5pv210-uart",
1817 .driver_data = S5PV210_SERIAL_DRV_DATA,
1818 }, {
1819 .name = "exynos4210-uart",
1820 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1821 },
1822 { },
1823 };
1824 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1825
1826 #ifdef CONFIG_OF
1827 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1828 { .compatible = "samsung,s3c2410-uart",
1829 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1830 { .compatible = "samsung,s3c2412-uart",
1831 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1832 { .compatible = "samsung,s3c2440-uart",
1833 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1834 { .compatible = "samsung,s3c6400-uart",
1835 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1836 { .compatible = "samsung,s5pv210-uart",
1837 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1838 { .compatible = "samsung,exynos4210-uart",
1839 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1840 {},
1841 };
1842 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1843 #endif
1844
1845 static struct platform_driver samsung_serial_driver = {
1846 .probe = s3c24xx_serial_probe,
1847 .remove = s3c24xx_serial_remove,
1848 .id_table = s3c24xx_serial_driver_ids,
1849 .driver = {
1850 .name = "samsung-uart",
1851 .owner = THIS_MODULE,
1852 .pm = SERIAL_SAMSUNG_PM_OPS,
1853 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1854 },
1855 };
1856
1857 module_platform_driver(samsung_serial_driver);
1858
1859 MODULE_ALIAS("platform:samsung-uart");
1860 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1861 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1862 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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