2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/regmap.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/spi/spi.h>
31 #include <linux/uaccess.h>
33 #define SC16IS7XX_NAME "sc16is7xx"
34 #define SC16IS7XX_MAX_DEVS 8
36 /* SC16IS7XX register definitions */
37 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
38 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
39 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
40 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
41 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
42 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
43 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
44 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
45 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
46 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
47 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
48 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
49 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
52 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
55 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
58 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
61 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
63 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
64 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
65 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
67 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
68 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
69 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
71 /* Enhanced Register set: Only if (LCR == 0xBF) */
72 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
73 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
74 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
75 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
76 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
78 /* IER register bits */
79 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
80 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
82 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
84 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
87 /* IER register bits - write only if (EFR[4] == 1) */
88 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
89 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
90 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
91 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
93 /* FCR register bits */
94 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
95 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
96 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
97 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
98 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
100 /* FCR register bits - write only if (EFR[4] == 1) */
101 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
102 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
104 /* IIR register bits */
105 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
106 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
107 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
108 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
109 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
110 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
111 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
114 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
117 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
118 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
122 /* LCR register bits */
123 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
124 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
126 * Word length bits table:
132 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
134 * STOP length bit table:
136 * 1 -> 1-1.5 stop bits if
138 * 2 stop bits otherwise
140 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
141 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
142 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
143 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
144 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
145 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
146 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
147 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
148 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
149 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
151 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
154 /* MCR register bits */
155 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
158 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
159 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
160 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
161 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
165 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
169 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
174 /* LSR register bits */
175 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
176 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
177 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
178 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
179 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
180 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
181 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
182 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
183 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
185 /* MSR register bits */
186 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
187 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
191 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
195 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
199 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
200 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
203 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
206 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
209 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
213 * TCR trigger levels are available from 0 to 60 characters with a granularity
215 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
216 * no built-in hardware check to make sure this condition is met. Also, the TCR
217 * must be programmed with this condition before auto RTS or software flow
218 * control is enabled to avoid spurious operation of the device.
220 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
221 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
225 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
226 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
227 * trigger levels. Trigger levels from 4 characters to 60 characters are
228 * available with a granularity of four.
230 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
231 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
232 * the trigger level defined in FCR is discarded. This applies to both transmit
233 * FIFO and receive FIFO trigger level setting.
235 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
236 * default state, that is, '00'.
238 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
239 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
241 /* IOControl register bits (Only 750/760) */
242 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
243 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
244 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
246 /* EFCR register bits */
247 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
249 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
250 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
251 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
252 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
253 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
254 * 0 = rate upto 115.2 kbit/s
256 * 1 = rate upto 1.152 Mbit/s
260 /* EFR register bits */
261 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
262 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
263 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
264 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
265 * and writing to IER[7:4],
268 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
269 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
271 * SWFLOW bits 3 & 2 table:
272 * 00 -> no transmitter flow
274 * 01 -> transmitter generates
276 * 10 -> transmitter generates
278 * 11 -> transmitter generates
279 * XON1, XON2, XOFF1 and
282 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
283 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
285 * SWFLOW bits 3 & 2 table:
286 * 00 -> no received flow
288 * 01 -> receiver compares
290 * 10 -> receiver compares
292 * 11 -> receiver compares
293 * XON1, XON2, XOFF1 and
297 /* Misc definitions */
298 #define SC16IS7XX_FIFO_SIZE (64)
299 #define SC16IS7XX_REG_SHIFT 2
301 struct sc16is7xx_devtype
{
307 #define SC16IS7XX_RECONF_MD (1 << 0)
308 #define SC16IS7XX_RECONF_IER (1 << 1)
309 #define SC16IS7XX_RECONF_RS485 (1 << 2)
311 struct sc16is7xx_one_config
{
316 struct sc16is7xx_one
{
317 struct uart_port port
;
319 struct kthread_work tx_work
;
320 struct kthread_work reg_work
;
321 struct sc16is7xx_one_config config
;
324 struct sc16is7xx_port
{
325 const struct sc16is7xx_devtype
*devtype
;
326 struct regmap
*regmap
;
328 #ifdef CONFIG_GPIOLIB
329 struct gpio_chip gpio
;
331 unsigned char buf
[SC16IS7XX_FIFO_SIZE
];
332 struct kthread_worker kworker
;
333 struct task_struct
*kworker_task
;
334 struct kthread_work irq_work
;
335 struct sc16is7xx_one p
[0];
338 static unsigned long sc16is7xx_lines
;
340 static struct uart_driver sc16is7xx_uart
= {
341 .owner
= THIS_MODULE
,
343 .nr
= SC16IS7XX_MAX_DEVS
,
346 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
347 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
349 static int sc16is7xx_line(struct uart_port
*port
)
351 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
356 static u8
sc16is7xx_port_read(struct uart_port
*port
, u8 reg
)
358 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
359 unsigned int val
= 0;
360 const u8 line
= sc16is7xx_line(port
);
362 regmap_read(s
->regmap
, (reg
<< SC16IS7XX_REG_SHIFT
) | line
, &val
);
367 static void sc16is7xx_port_write(struct uart_port
*port
, u8 reg
, u8 val
)
369 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
370 const u8 line
= sc16is7xx_line(port
);
372 regmap_write(s
->regmap
, (reg
<< SC16IS7XX_REG_SHIFT
) | line
, val
);
375 static void sc16is7xx_fifo_read(struct uart_port
*port
, unsigned int rxlen
)
377 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
378 const u8 line
= sc16is7xx_line(port
);
379 u8 addr
= (SC16IS7XX_RHR_REG
<< SC16IS7XX_REG_SHIFT
) | line
;
381 regcache_cache_bypass(s
->regmap
, true);
382 regmap_raw_read(s
->regmap
, addr
, s
->buf
, rxlen
);
383 regcache_cache_bypass(s
->regmap
, false);
386 static void sc16is7xx_fifo_write(struct uart_port
*port
, u8 to_send
)
388 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
389 const u8 line
= sc16is7xx_line(port
);
390 u8 addr
= (SC16IS7XX_THR_REG
<< SC16IS7XX_REG_SHIFT
) | line
;
393 * Don't send zero-length data, at least on SPI it confuses the chip
394 * delivering wrong TXLVL data.
396 if (unlikely(!to_send
))
399 regcache_cache_bypass(s
->regmap
, true);
400 regmap_raw_write(s
->regmap
, addr
, s
->buf
, to_send
);
401 regcache_cache_bypass(s
->regmap
, false);
404 static void sc16is7xx_port_update(struct uart_port
*port
, u8 reg
,
407 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
408 const u8 line
= sc16is7xx_line(port
);
410 regmap_update_bits(s
->regmap
, (reg
<< SC16IS7XX_REG_SHIFT
) | line
,
414 static int sc16is7xx_alloc_line(void)
418 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS
> BITS_PER_LONG
);
420 for (i
= 0; i
< SC16IS7XX_MAX_DEVS
; i
++)
421 if (!test_and_set_bit(i
, &sc16is7xx_lines
))
427 static void sc16is7xx_power(struct uart_port
*port
, int on
)
429 sc16is7xx_port_update(port
, SC16IS7XX_IER_REG
,
430 SC16IS7XX_IER_SLEEP_BIT
,
431 on
? 0 : SC16IS7XX_IER_SLEEP_BIT
);
434 static const struct sc16is7xx_devtype sc16is74x_devtype
= {
440 static const struct sc16is7xx_devtype sc16is750_devtype
= {
446 static const struct sc16is7xx_devtype sc16is752_devtype
= {
452 static const struct sc16is7xx_devtype sc16is760_devtype
= {
458 static const struct sc16is7xx_devtype sc16is762_devtype
= {
464 static bool sc16is7xx_regmap_volatile(struct device
*dev
, unsigned int reg
)
466 switch (reg
>> SC16IS7XX_REG_SHIFT
) {
467 case SC16IS7XX_RHR_REG
:
468 case SC16IS7XX_IIR_REG
:
469 case SC16IS7XX_LSR_REG
:
470 case SC16IS7XX_MSR_REG
:
471 case SC16IS7XX_TXLVL_REG
:
472 case SC16IS7XX_RXLVL_REG
:
473 case SC16IS7XX_IOSTATE_REG
:
482 static bool sc16is7xx_regmap_precious(struct device
*dev
, unsigned int reg
)
484 switch (reg
>> SC16IS7XX_REG_SHIFT
) {
485 case SC16IS7XX_RHR_REG
:
494 static int sc16is7xx_set_baud(struct uart_port
*port
, int baud
)
496 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
499 unsigned long clk
= port
->uartclk
, div
= clk
/ 16 / baud
;
502 prescaler
= SC16IS7XX_MCR_CLKSEL_BIT
;
506 lcr
= sc16is7xx_port_read(port
, SC16IS7XX_LCR_REG
);
508 /* Open the LCR divisors for configuration */
509 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
510 SC16IS7XX_LCR_CONF_MODE_B
);
512 /* Enable enhanced features */
513 regcache_cache_bypass(s
->regmap
, true);
514 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
,
515 SC16IS7XX_EFR_ENABLE_BIT
);
516 regcache_cache_bypass(s
->regmap
, false);
518 /* Put LCR back to the normal mode */
519 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
521 sc16is7xx_port_update(port
, SC16IS7XX_MCR_REG
,
522 SC16IS7XX_MCR_CLKSEL_BIT
,
525 /* Open the LCR divisors for configuration */
526 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
527 SC16IS7XX_LCR_CONF_MODE_A
);
529 /* Write the new divisor */
530 regcache_cache_bypass(s
->regmap
, true);
531 sc16is7xx_port_write(port
, SC16IS7XX_DLH_REG
, div
/ 256);
532 sc16is7xx_port_write(port
, SC16IS7XX_DLL_REG
, div
% 256);
533 regcache_cache_bypass(s
->regmap
, false);
535 /* Put LCR back to the normal mode */
536 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
538 return DIV_ROUND_CLOSEST(clk
/ 16, div
);
541 static void sc16is7xx_handle_rx(struct uart_port
*port
, unsigned int rxlen
,
544 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
545 unsigned int lsr
= 0, ch
, flag
, bytes_read
, i
;
546 bool read_lsr
= (iir
== SC16IS7XX_IIR_RLSE_SRC
) ? true : false;
548 if (unlikely(rxlen
>= sizeof(s
->buf
))) {
549 dev_warn_ratelimited(port
->dev
,
550 "ttySC%i: Possible RX FIFO overrun: %d\n",
552 port
->icount
.buf_overrun
++;
553 /* Ensure sanity of RX level */
554 rxlen
= sizeof(s
->buf
);
558 /* Only read lsr if there are possible errors in FIFO */
560 lsr
= sc16is7xx_port_read(port
, SC16IS7XX_LSR_REG
);
561 if (!(lsr
& SC16IS7XX_LSR_FIFOE_BIT
))
562 read_lsr
= false; /* No errors left in FIFO */
567 s
->buf
[0] = sc16is7xx_port_read(port
, SC16IS7XX_RHR_REG
);
570 sc16is7xx_fifo_read(port
, rxlen
);
574 lsr
&= SC16IS7XX_LSR_BRK_ERROR_MASK
;
580 if (lsr
& SC16IS7XX_LSR_BI_BIT
) {
582 if (uart_handle_break(port
))
584 } else if (lsr
& SC16IS7XX_LSR_PE_BIT
)
585 port
->icount
.parity
++;
586 else if (lsr
& SC16IS7XX_LSR_FE_BIT
)
587 port
->icount
.frame
++;
588 else if (lsr
& SC16IS7XX_LSR_OE_BIT
)
589 port
->icount
.overrun
++;
591 lsr
&= port
->read_status_mask
;
592 if (lsr
& SC16IS7XX_LSR_BI_BIT
)
594 else if (lsr
& SC16IS7XX_LSR_PE_BIT
)
596 else if (lsr
& SC16IS7XX_LSR_FE_BIT
)
598 else if (lsr
& SC16IS7XX_LSR_OE_BIT
)
602 for (i
= 0; i
< bytes_read
; ++i
) {
604 if (uart_handle_sysrq_char(port
, ch
))
607 if (lsr
& port
->ignore_status_mask
)
610 uart_insert_char(port
, lsr
, SC16IS7XX_LSR_OE_BIT
, ch
,
616 tty_flip_buffer_push(&port
->state
->port
);
619 static void sc16is7xx_handle_tx(struct uart_port
*port
)
621 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
622 struct circ_buf
*xmit
= &port
->state
->xmit
;
623 unsigned int txlen
, to_send
, i
;
625 if (unlikely(port
->x_char
)) {
626 sc16is7xx_port_write(port
, SC16IS7XX_THR_REG
, port
->x_char
);
632 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
))
635 /* Get length of data pending in circular buffer */
636 to_send
= uart_circ_chars_pending(xmit
);
637 if (likely(to_send
)) {
638 /* Limit to size of TX FIFO */
639 txlen
= sc16is7xx_port_read(port
, SC16IS7XX_TXLVL_REG
);
640 if (txlen
> SC16IS7XX_FIFO_SIZE
) {
641 dev_err_ratelimited(port
->dev
,
642 "chip reports %d free bytes in TX fifo, but it only has %d",
643 txlen
, SC16IS7XX_FIFO_SIZE
);
646 to_send
= (to_send
> txlen
) ? txlen
: to_send
;
648 /* Add data to send */
649 port
->icount
.tx
+= to_send
;
651 /* Convert to linear buffer */
652 for (i
= 0; i
< to_send
; ++i
) {
653 s
->buf
[i
] = xmit
->buf
[xmit
->tail
];
654 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
657 sc16is7xx_fifo_write(port
, to_send
);
660 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
661 uart_write_wakeup(port
);
664 static void sc16is7xx_port_irq(struct sc16is7xx_port
*s
, int portno
)
666 struct uart_port
*port
= &s
->p
[portno
].port
;
669 unsigned int iir
, msr
, rxlen
;
671 iir
= sc16is7xx_port_read(port
, SC16IS7XX_IIR_REG
);
672 if (iir
& SC16IS7XX_IIR_NO_INT_BIT
)
675 iir
&= SC16IS7XX_IIR_ID_MASK
;
678 case SC16IS7XX_IIR_RDI_SRC
:
679 case SC16IS7XX_IIR_RLSE_SRC
:
680 case SC16IS7XX_IIR_RTOI_SRC
:
681 case SC16IS7XX_IIR_XOFFI_SRC
:
682 rxlen
= sc16is7xx_port_read(port
, SC16IS7XX_RXLVL_REG
);
684 sc16is7xx_handle_rx(port
, rxlen
, iir
);
687 case SC16IS7XX_IIR_CTSRTS_SRC
:
688 msr
= sc16is7xx_port_read(port
, SC16IS7XX_MSR_REG
);
689 uart_handle_cts_change(port
,
690 !!(msr
& SC16IS7XX_MSR_DCTS_BIT
));
692 case SC16IS7XX_IIR_THRI_SRC
:
693 sc16is7xx_handle_tx(port
);
696 dev_err_ratelimited(port
->dev
,
697 "ttySC%i: Unexpected interrupt: %x",
704 static void sc16is7xx_ist(struct kthread_work
*ws
)
706 struct sc16is7xx_port
*s
= to_sc16is7xx_port(ws
, irq_work
);
709 for (i
= 0; i
< s
->devtype
->nr_uart
; ++i
)
710 sc16is7xx_port_irq(s
, i
);
713 static irqreturn_t
sc16is7xx_irq(int irq
, void *dev_id
)
715 struct sc16is7xx_port
*s
= (struct sc16is7xx_port
*)dev_id
;
717 queue_kthread_work(&s
->kworker
, &s
->irq_work
);
722 static void sc16is7xx_tx_proc(struct kthread_work
*ws
)
724 struct uart_port
*port
= &(to_sc16is7xx_one(ws
, tx_work
)->port
);
726 if ((port
->rs485
.flags
& SER_RS485_ENABLED
) &&
727 (port
->rs485
.delay_rts_before_send
> 0))
728 msleep(port
->rs485
.delay_rts_before_send
);
730 sc16is7xx_handle_tx(port
);
733 static void sc16is7xx_reconf_rs485(struct uart_port
*port
)
735 const u32 mask
= SC16IS7XX_EFCR_AUTO_RS485_BIT
|
736 SC16IS7XX_EFCR_RTS_INVERT_BIT
;
738 struct serial_rs485
*rs485
= &port
->rs485
;
739 unsigned long irqflags
;
741 spin_lock_irqsave(&port
->lock
, irqflags
);
742 if (rs485
->flags
& SER_RS485_ENABLED
) {
743 efcr
|= SC16IS7XX_EFCR_AUTO_RS485_BIT
;
745 if (rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
746 efcr
|= SC16IS7XX_EFCR_RTS_INVERT_BIT
;
748 spin_unlock_irqrestore(&port
->lock
, irqflags
);
750 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
, mask
, efcr
);
753 static void sc16is7xx_reg_proc(struct kthread_work
*ws
)
755 struct sc16is7xx_one
*one
= to_sc16is7xx_one(ws
, reg_work
);
756 struct sc16is7xx_one_config config
;
757 unsigned long irqflags
;
759 spin_lock_irqsave(&one
->port
.lock
, irqflags
);
760 config
= one
->config
;
761 memset(&one
->config
, 0, sizeof(one
->config
));
762 spin_unlock_irqrestore(&one
->port
.lock
, irqflags
);
764 if (config
.flags
& SC16IS7XX_RECONF_MD
) {
765 sc16is7xx_port_update(&one
->port
, SC16IS7XX_MCR_REG
,
766 SC16IS7XX_MCR_LOOP_BIT
,
767 (one
->port
.mctrl
& TIOCM_LOOP
) ?
768 SC16IS7XX_MCR_LOOP_BIT
: 0);
769 sc16is7xx_port_update(&one
->port
, SC16IS7XX_MCR_REG
,
770 SC16IS7XX_MCR_RTS_BIT
,
771 (one
->port
.mctrl
& TIOCM_RTS
) ?
772 SC16IS7XX_MCR_RTS_BIT
: 0);
773 sc16is7xx_port_update(&one
->port
, SC16IS7XX_MCR_REG
,
774 SC16IS7XX_MCR_DTR_BIT
,
775 (one
->port
.mctrl
& TIOCM_DTR
) ?
776 SC16IS7XX_MCR_DTR_BIT
: 0);
778 if (config
.flags
& SC16IS7XX_RECONF_IER
)
779 sc16is7xx_port_update(&one
->port
, SC16IS7XX_IER_REG
,
780 config
.ier_clear
, 0);
782 if (config
.flags
& SC16IS7XX_RECONF_RS485
)
783 sc16is7xx_reconf_rs485(&one
->port
);
786 static void sc16is7xx_ier_clear(struct uart_port
*port
, u8 bit
)
788 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
789 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
791 one
->config
.flags
|= SC16IS7XX_RECONF_IER
;
792 one
->config
.ier_clear
|= bit
;
793 queue_kthread_work(&s
->kworker
, &one
->reg_work
);
796 static void sc16is7xx_stop_tx(struct uart_port
*port
)
798 sc16is7xx_ier_clear(port
, SC16IS7XX_IER_THRI_BIT
);
801 static void sc16is7xx_stop_rx(struct uart_port
*port
)
803 sc16is7xx_ier_clear(port
, SC16IS7XX_IER_RDI_BIT
);
806 static void sc16is7xx_start_tx(struct uart_port
*port
)
808 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
809 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
811 queue_kthread_work(&s
->kworker
, &one
->tx_work
);
814 static unsigned int sc16is7xx_tx_empty(struct uart_port
*port
)
818 lsr
= sc16is7xx_port_read(port
, SC16IS7XX_LSR_REG
);
820 return (lsr
& SC16IS7XX_LSR_TEMT_BIT
) ? TIOCSER_TEMT
: 0;
823 static unsigned int sc16is7xx_get_mctrl(struct uart_port
*port
)
826 unsigned int ret
= 0;
828 msr
= sc16is7xx_port_read(port
, SC16IS7XX_MSR_REG
);
830 ret
|= (msr
& SC16IS7XX_MSR_CTS_BIT
) ? TIOCM_CTS
: 0;
831 ret
|= (msr
& SC16IS7XX_MSR_DSR_BIT
) ? TIOCM_DSR
: 0;
832 ret
|= (msr
& SC16IS7XX_MSR_RI_BIT
) ? TIOCM_RNG
: 0;
833 ret
|= (msr
& SC16IS7XX_MSR_CD_BIT
) ? TIOCM_CAR
: 0;
837 static void sc16is7xx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
839 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
840 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
842 one
->config
.flags
|= SC16IS7XX_RECONF_MD
;
843 queue_kthread_work(&s
->kworker
, &one
->reg_work
);
846 static void sc16is7xx_break_ctl(struct uart_port
*port
, int break_state
)
848 sc16is7xx_port_update(port
, SC16IS7XX_LCR_REG
,
849 SC16IS7XX_LCR_TXBREAK_BIT
,
850 break_state
? SC16IS7XX_LCR_TXBREAK_BIT
: 0);
853 static void sc16is7xx_set_termios(struct uart_port
*port
,
854 struct ktermios
*termios
,
855 struct ktermios
*old
)
857 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
858 unsigned int lcr
, flow
= 0;
861 /* Mask termios capabilities we don't support */
862 termios
->c_cflag
&= ~CMSPAR
;
865 switch (termios
->c_cflag
& CSIZE
) {
867 lcr
= SC16IS7XX_LCR_WORD_LEN_5
;
870 lcr
= SC16IS7XX_LCR_WORD_LEN_6
;
873 lcr
= SC16IS7XX_LCR_WORD_LEN_7
;
876 lcr
= SC16IS7XX_LCR_WORD_LEN_8
;
879 lcr
= SC16IS7XX_LCR_WORD_LEN_8
;
880 termios
->c_cflag
&= ~CSIZE
;
881 termios
->c_cflag
|= CS8
;
886 if (termios
->c_cflag
& PARENB
) {
887 lcr
|= SC16IS7XX_LCR_PARITY_BIT
;
888 if (!(termios
->c_cflag
& PARODD
))
889 lcr
|= SC16IS7XX_LCR_EVENPARITY_BIT
;
893 if (termios
->c_cflag
& CSTOPB
)
894 lcr
|= SC16IS7XX_LCR_STOPLEN_BIT
; /* 2 stops */
896 /* Set read status mask */
897 port
->read_status_mask
= SC16IS7XX_LSR_OE_BIT
;
898 if (termios
->c_iflag
& INPCK
)
899 port
->read_status_mask
|= SC16IS7XX_LSR_PE_BIT
|
900 SC16IS7XX_LSR_FE_BIT
;
901 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
902 port
->read_status_mask
|= SC16IS7XX_LSR_BI_BIT
;
904 /* Set status ignore mask */
905 port
->ignore_status_mask
= 0;
906 if (termios
->c_iflag
& IGNBRK
)
907 port
->ignore_status_mask
|= SC16IS7XX_LSR_BI_BIT
;
908 if (!(termios
->c_cflag
& CREAD
))
909 port
->ignore_status_mask
|= SC16IS7XX_LSR_BRK_ERROR_MASK
;
911 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
912 SC16IS7XX_LCR_CONF_MODE_B
);
914 /* Configure flow control */
915 regcache_cache_bypass(s
->regmap
, true);
916 sc16is7xx_port_write(port
, SC16IS7XX_XON1_REG
, termios
->c_cc
[VSTART
]);
917 sc16is7xx_port_write(port
, SC16IS7XX_XOFF1_REG
, termios
->c_cc
[VSTOP
]);
918 if (termios
->c_cflag
& CRTSCTS
)
919 flow
|= SC16IS7XX_EFR_AUTOCTS_BIT
|
920 SC16IS7XX_EFR_AUTORTS_BIT
;
921 if (termios
->c_iflag
& IXON
)
922 flow
|= SC16IS7XX_EFR_SWFLOW3_BIT
;
923 if (termios
->c_iflag
& IXOFF
)
924 flow
|= SC16IS7XX_EFR_SWFLOW1_BIT
;
926 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
, flow
);
927 regcache_cache_bypass(s
->regmap
, false);
929 /* Update LCR register */
930 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
932 /* Get baud rate generator configuration */
933 baud
= uart_get_baud_rate(port
, termios
, old
,
934 port
->uartclk
/ 16 / 4 / 0xffff,
937 /* Setup baudrate generator */
938 baud
= sc16is7xx_set_baud(port
, baud
);
940 /* Update timeout according to new baud rate */
941 uart_update_timeout(port
, termios
->c_cflag
, baud
);
944 static int sc16is7xx_config_rs485(struct uart_port
*port
,
945 struct serial_rs485
*rs485
)
947 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
948 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
950 if (rs485
->flags
& SER_RS485_ENABLED
) {
951 bool rts_during_rx
, rts_during_tx
;
953 rts_during_rx
= rs485
->flags
& SER_RS485_RTS_AFTER_SEND
;
954 rts_during_tx
= rs485
->flags
& SER_RS485_RTS_ON_SEND
;
956 if (rts_during_rx
== rts_during_tx
)
958 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
959 rts_during_tx
, rts_during_rx
);
962 * RTS signal is handled by HW, it's timing can't be influenced.
963 * However, it's sometimes useful to delay TX even without RTS
964 * control therefore we try to handle .delay_rts_before_send.
966 if (rs485
->delay_rts_after_send
)
970 port
->rs485
= *rs485
;
971 one
->config
.flags
|= SC16IS7XX_RECONF_RS485
;
972 queue_kthread_work(&s
->kworker
, &one
->reg_work
);
977 static int sc16is7xx_startup(struct uart_port
*port
)
979 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
982 sc16is7xx_power(port
, 1);
985 val
= SC16IS7XX_FCR_RXRESET_BIT
| SC16IS7XX_FCR_TXRESET_BIT
;
986 sc16is7xx_port_write(port
, SC16IS7XX_FCR_REG
, val
);
988 sc16is7xx_port_write(port
, SC16IS7XX_FCR_REG
,
989 SC16IS7XX_FCR_FIFO_BIT
);
992 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
993 SC16IS7XX_LCR_CONF_MODE_B
);
995 regcache_cache_bypass(s
->regmap
, true);
997 /* Enable write access to enhanced features and internal clock div */
998 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
,
999 SC16IS7XX_EFR_ENABLE_BIT
);
1001 /* Enable TCR/TLR */
1002 sc16is7xx_port_update(port
, SC16IS7XX_MCR_REG
,
1003 SC16IS7XX_MCR_TCRTLR_BIT
,
1004 SC16IS7XX_MCR_TCRTLR_BIT
);
1006 /* Configure flow control levels */
1007 /* Flow control halt level 48, resume level 24 */
1008 sc16is7xx_port_write(port
, SC16IS7XX_TCR_REG
,
1009 SC16IS7XX_TCR_RX_RESUME(24) |
1010 SC16IS7XX_TCR_RX_HALT(48));
1012 regcache_cache_bypass(s
->regmap
, false);
1014 /* Now, initialize the UART */
1015 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, SC16IS7XX_LCR_WORD_LEN_8
);
1017 /* Enable the Rx and Tx FIFO */
1018 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
,
1019 SC16IS7XX_EFCR_RXDISABLE_BIT
|
1020 SC16IS7XX_EFCR_TXDISABLE_BIT
,
1023 /* Enable RX, TX, CTS change interrupts */
1024 val
= SC16IS7XX_IER_RDI_BIT
| SC16IS7XX_IER_THRI_BIT
|
1025 SC16IS7XX_IER_CTSI_BIT
;
1026 sc16is7xx_port_write(port
, SC16IS7XX_IER_REG
, val
);
1031 static void sc16is7xx_shutdown(struct uart_port
*port
)
1033 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
1035 /* Disable all interrupts */
1036 sc16is7xx_port_write(port
, SC16IS7XX_IER_REG
, 0);
1038 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
,
1039 SC16IS7XX_EFCR_RXDISABLE_BIT
|
1040 SC16IS7XX_EFCR_TXDISABLE_BIT
,
1041 SC16IS7XX_EFCR_RXDISABLE_BIT
|
1042 SC16IS7XX_EFCR_TXDISABLE_BIT
);
1044 sc16is7xx_power(port
, 0);
1046 flush_kthread_worker(&s
->kworker
);
1049 static const char *sc16is7xx_type(struct uart_port
*port
)
1051 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
1053 return (port
->type
== PORT_SC16IS7XX
) ? s
->devtype
->name
: NULL
;
1056 static int sc16is7xx_request_port(struct uart_port
*port
)
1062 static void sc16is7xx_config_port(struct uart_port
*port
, int flags
)
1064 if (flags
& UART_CONFIG_TYPE
)
1065 port
->type
= PORT_SC16IS7XX
;
1068 static int sc16is7xx_verify_port(struct uart_port
*port
,
1069 struct serial_struct
*s
)
1071 if ((s
->type
!= PORT_UNKNOWN
) && (s
->type
!= PORT_SC16IS7XX
))
1073 if (s
->irq
!= port
->irq
)
1079 static void sc16is7xx_pm(struct uart_port
*port
, unsigned int state
,
1080 unsigned int oldstate
)
1082 sc16is7xx_power(port
, (state
== UART_PM_STATE_ON
) ? 1 : 0);
1085 static void sc16is7xx_null_void(struct uart_port
*port
)
1090 static const struct uart_ops sc16is7xx_ops
= {
1091 .tx_empty
= sc16is7xx_tx_empty
,
1092 .set_mctrl
= sc16is7xx_set_mctrl
,
1093 .get_mctrl
= sc16is7xx_get_mctrl
,
1094 .stop_tx
= sc16is7xx_stop_tx
,
1095 .start_tx
= sc16is7xx_start_tx
,
1096 .stop_rx
= sc16is7xx_stop_rx
,
1097 .break_ctl
= sc16is7xx_break_ctl
,
1098 .startup
= sc16is7xx_startup
,
1099 .shutdown
= sc16is7xx_shutdown
,
1100 .set_termios
= sc16is7xx_set_termios
,
1101 .type
= sc16is7xx_type
,
1102 .request_port
= sc16is7xx_request_port
,
1103 .release_port
= sc16is7xx_null_void
,
1104 .config_port
= sc16is7xx_config_port
,
1105 .verify_port
= sc16is7xx_verify_port
,
1109 #ifdef CONFIG_GPIOLIB
1110 static int sc16is7xx_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1113 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1115 struct uart_port
*port
= &s
->p
[0].port
;
1117 val
= sc16is7xx_port_read(port
, SC16IS7XX_IOSTATE_REG
);
1119 return !!(val
& BIT(offset
));
1122 static void sc16is7xx_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
1124 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1126 struct uart_port
*port
= &s
->p
[0].port
;
1128 sc16is7xx_port_update(port
, SC16IS7XX_IOSTATE_REG
, BIT(offset
),
1129 val
? BIT(offset
) : 0);
1132 static int sc16is7xx_gpio_direction_input(struct gpio_chip
*chip
,
1135 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1137 struct uart_port
*port
= &s
->p
[0].port
;
1139 sc16is7xx_port_update(port
, SC16IS7XX_IODIR_REG
, BIT(offset
), 0);
1144 static int sc16is7xx_gpio_direction_output(struct gpio_chip
*chip
,
1145 unsigned offset
, int val
)
1147 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1149 struct uart_port
*port
= &s
->p
[0].port
;
1151 sc16is7xx_port_update(port
, SC16IS7XX_IOSTATE_REG
, BIT(offset
),
1152 val
? BIT(offset
) : 0);
1153 sc16is7xx_port_update(port
, SC16IS7XX_IODIR_REG
, BIT(offset
),
1160 static int sc16is7xx_probe(struct device
*dev
,
1161 const struct sc16is7xx_devtype
*devtype
,
1162 struct regmap
*regmap
, int irq
, unsigned long flags
)
1164 struct sched_param sched_param
= { .sched_priority
= MAX_RT_PRIO
/ 2 };
1165 unsigned long freq
, *pfreq
= dev_get_platdata(dev
);
1167 struct sc16is7xx_port
*s
;
1170 return PTR_ERR(regmap
);
1172 /* Alloc port structure */
1173 s
= devm_kzalloc(dev
, sizeof(*s
) +
1174 sizeof(struct sc16is7xx_one
) * devtype
->nr_uart
,
1177 dev_err(dev
, "Error allocating port structure\n");
1181 s
->clk
= devm_clk_get(dev
, NULL
);
1182 if (IS_ERR(s
->clk
)) {
1186 return PTR_ERR(s
->clk
);
1188 clk_prepare_enable(s
->clk
);
1189 freq
= clk_get_rate(s
->clk
);
1193 s
->devtype
= devtype
;
1194 dev_set_drvdata(dev
, s
);
1196 init_kthread_worker(&s
->kworker
);
1197 init_kthread_work(&s
->irq_work
, sc16is7xx_ist
);
1198 s
->kworker_task
= kthread_run(kthread_worker_fn
, &s
->kworker
,
1200 if (IS_ERR(s
->kworker_task
)) {
1201 ret
= PTR_ERR(s
->kworker_task
);
1204 sched_setscheduler(s
->kworker_task
, SCHED_FIFO
, &sched_param
);
1206 #ifdef CONFIG_GPIOLIB
1207 if (devtype
->nr_gpio
) {
1208 /* Setup GPIO cotroller */
1209 s
->gpio
.owner
= THIS_MODULE
;
1210 s
->gpio
.parent
= dev
;
1211 s
->gpio
.label
= dev_name(dev
);
1212 s
->gpio
.direction_input
= sc16is7xx_gpio_direction_input
;
1213 s
->gpio
.get
= sc16is7xx_gpio_get
;
1214 s
->gpio
.direction_output
= sc16is7xx_gpio_direction_output
;
1215 s
->gpio
.set
= sc16is7xx_gpio_set
;
1217 s
->gpio
.ngpio
= devtype
->nr_gpio
;
1218 s
->gpio
.can_sleep
= 1;
1219 ret
= gpiochip_add(&s
->gpio
);
1225 for (i
= 0; i
< devtype
->nr_uart
; ++i
) {
1227 /* Initialize port data */
1228 s
->p
[i
].port
.dev
= dev
;
1229 s
->p
[i
].port
.irq
= irq
;
1230 s
->p
[i
].port
.type
= PORT_SC16IS7XX
;
1231 s
->p
[i
].port
.fifosize
= SC16IS7XX_FIFO_SIZE
;
1232 s
->p
[i
].port
.flags
= UPF_FIXED_TYPE
| UPF_LOW_LATENCY
;
1233 s
->p
[i
].port
.iotype
= UPIO_PORT
;
1234 s
->p
[i
].port
.uartclk
= freq
;
1235 s
->p
[i
].port
.rs485_config
= sc16is7xx_config_rs485
;
1236 s
->p
[i
].port
.ops
= &sc16is7xx_ops
;
1237 s
->p
[i
].port
.line
= sc16is7xx_alloc_line();
1238 if (s
->p
[i
].port
.line
>= SC16IS7XX_MAX_DEVS
) {
1243 /* Disable all interrupts */
1244 sc16is7xx_port_write(&s
->p
[i
].port
, SC16IS7XX_IER_REG
, 0);
1246 sc16is7xx_port_write(&s
->p
[i
].port
, SC16IS7XX_EFCR_REG
,
1247 SC16IS7XX_EFCR_RXDISABLE_BIT
|
1248 SC16IS7XX_EFCR_TXDISABLE_BIT
);
1249 /* Initialize kthread work structs */
1250 init_kthread_work(&s
->p
[i
].tx_work
, sc16is7xx_tx_proc
);
1251 init_kthread_work(&s
->p
[i
].reg_work
, sc16is7xx_reg_proc
);
1253 uart_add_one_port(&sc16is7xx_uart
, &s
->p
[i
].port
);
1254 /* Go to suspend mode */
1255 sc16is7xx_power(&s
->p
[i
].port
, 0);
1258 /* Setup interrupt */
1259 ret
= devm_request_irq(dev
, irq
, sc16is7xx_irq
,
1260 IRQF_ONESHOT
| flags
, dev_name(dev
), s
);
1265 for (i
--; i
>= 0; i
--) {
1266 uart_remove_one_port(&sc16is7xx_uart
, &s
->p
[i
].port
);
1267 clear_bit(s
->p
[i
].port
.line
, &sc16is7xx_lines
);
1270 #ifdef CONFIG_GPIOLIB
1271 if (devtype
->nr_gpio
)
1272 gpiochip_remove(&s
->gpio
);
1276 kthread_stop(s
->kworker_task
);
1279 if (!IS_ERR(s
->clk
))
1280 clk_disable_unprepare(s
->clk
);
1285 static int sc16is7xx_remove(struct device
*dev
)
1287 struct sc16is7xx_port
*s
= dev_get_drvdata(dev
);
1290 #ifdef CONFIG_GPIOLIB
1291 if (s
->devtype
->nr_gpio
)
1292 gpiochip_remove(&s
->gpio
);
1295 for (i
= 0; i
< s
->devtype
->nr_uart
; i
++) {
1296 uart_remove_one_port(&sc16is7xx_uart
, &s
->p
[i
].port
);
1297 clear_bit(s
->p
[i
].port
.line
, &sc16is7xx_lines
);
1298 sc16is7xx_power(&s
->p
[i
].port
, 0);
1301 flush_kthread_worker(&s
->kworker
);
1302 kthread_stop(s
->kworker_task
);
1304 if (!IS_ERR(s
->clk
))
1305 clk_disable_unprepare(s
->clk
);
1310 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids
[] = {
1311 { .compatible
= "nxp,sc16is740", .data
= &sc16is74x_devtype
, },
1312 { .compatible
= "nxp,sc16is741", .data
= &sc16is74x_devtype
, },
1313 { .compatible
= "nxp,sc16is750", .data
= &sc16is750_devtype
, },
1314 { .compatible
= "nxp,sc16is752", .data
= &sc16is752_devtype
, },
1315 { .compatible
= "nxp,sc16is760", .data
= &sc16is760_devtype
, },
1316 { .compatible
= "nxp,sc16is762", .data
= &sc16is762_devtype
, },
1319 MODULE_DEVICE_TABLE(of
, sc16is7xx_dt_ids
);
1321 static struct regmap_config regcfg
= {
1325 .cache_type
= REGCACHE_RBTREE
,
1326 .volatile_reg
= sc16is7xx_regmap_volatile
,
1327 .precious_reg
= sc16is7xx_regmap_precious
,
1330 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1331 static int sc16is7xx_spi_probe(struct spi_device
*spi
)
1333 const struct sc16is7xx_devtype
*devtype
;
1334 unsigned long flags
= 0;
1335 struct regmap
*regmap
;
1339 spi
->bits_per_word
= 8;
1340 /* only supports mode 0 on SC16IS762 */
1341 spi
->mode
= spi
->mode
? : SPI_MODE_0
;
1342 spi
->max_speed_hz
= spi
->max_speed_hz
? : 15000000;
1343 ret
= spi_setup(spi
);
1347 if (spi
->dev
.of_node
) {
1348 const struct of_device_id
*of_id
=
1349 of_match_device(sc16is7xx_dt_ids
, &spi
->dev
);
1354 devtype
= (struct sc16is7xx_devtype
*)of_id
->data
;
1356 const struct spi_device_id
*id_entry
= spi_get_device_id(spi
);
1358 devtype
= (struct sc16is7xx_devtype
*)id_entry
->driver_data
;
1359 flags
= IRQF_TRIGGER_FALLING
;
1362 regcfg
.max_register
= (0xf << SC16IS7XX_REG_SHIFT
) |
1363 (devtype
->nr_uart
- 1);
1364 regmap
= devm_regmap_init_spi(spi
, ®cfg
);
1366 return sc16is7xx_probe(&spi
->dev
, devtype
, regmap
, spi
->irq
, flags
);
1369 static int sc16is7xx_spi_remove(struct spi_device
*spi
)
1371 return sc16is7xx_remove(&spi
->dev
);
1374 static const struct spi_device_id sc16is7xx_spi_id_table
[] = {
1375 { "sc16is74x", (kernel_ulong_t
)&sc16is74x_devtype
, },
1376 { "sc16is740", (kernel_ulong_t
)&sc16is74x_devtype
, },
1377 { "sc16is741", (kernel_ulong_t
)&sc16is74x_devtype
, },
1378 { "sc16is750", (kernel_ulong_t
)&sc16is750_devtype
, },
1379 { "sc16is752", (kernel_ulong_t
)&sc16is752_devtype
, },
1380 { "sc16is760", (kernel_ulong_t
)&sc16is760_devtype
, },
1381 { "sc16is762", (kernel_ulong_t
)&sc16is762_devtype
, },
1385 MODULE_DEVICE_TABLE(spi
, sc16is7xx_spi_id_table
);
1387 static struct spi_driver sc16is7xx_spi_uart_driver
= {
1389 .name
= SC16IS7XX_NAME
,
1390 .of_match_table
= of_match_ptr(sc16is7xx_dt_ids
),
1392 .probe
= sc16is7xx_spi_probe
,
1393 .remove
= sc16is7xx_spi_remove
,
1394 .id_table
= sc16is7xx_spi_id_table
,
1397 MODULE_ALIAS("spi:sc16is7xx");
1400 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1401 static int sc16is7xx_i2c_probe(struct i2c_client
*i2c
,
1402 const struct i2c_device_id
*id
)
1404 const struct sc16is7xx_devtype
*devtype
;
1405 unsigned long flags
= 0;
1406 struct regmap
*regmap
;
1408 if (i2c
->dev
.of_node
) {
1409 const struct of_device_id
*of_id
=
1410 of_match_device(sc16is7xx_dt_ids
, &i2c
->dev
);
1415 devtype
= (struct sc16is7xx_devtype
*)of_id
->data
;
1417 devtype
= (struct sc16is7xx_devtype
*)id
->driver_data
;
1418 flags
= IRQF_TRIGGER_FALLING
;
1421 regcfg
.max_register
= (0xf << SC16IS7XX_REG_SHIFT
) |
1422 (devtype
->nr_uart
- 1);
1423 regmap
= devm_regmap_init_i2c(i2c
, ®cfg
);
1425 return sc16is7xx_probe(&i2c
->dev
, devtype
, regmap
, i2c
->irq
, flags
);
1428 static int sc16is7xx_i2c_remove(struct i2c_client
*client
)
1430 return sc16is7xx_remove(&client
->dev
);
1433 static const struct i2c_device_id sc16is7xx_i2c_id_table
[] = {
1434 { "sc16is74x", (kernel_ulong_t
)&sc16is74x_devtype
, },
1435 { "sc16is740", (kernel_ulong_t
)&sc16is74x_devtype
, },
1436 { "sc16is741", (kernel_ulong_t
)&sc16is74x_devtype
, },
1437 { "sc16is750", (kernel_ulong_t
)&sc16is750_devtype
, },
1438 { "sc16is752", (kernel_ulong_t
)&sc16is752_devtype
, },
1439 { "sc16is760", (kernel_ulong_t
)&sc16is760_devtype
, },
1440 { "sc16is762", (kernel_ulong_t
)&sc16is762_devtype
, },
1443 MODULE_DEVICE_TABLE(i2c
, sc16is7xx_i2c_id_table
);
1445 static struct i2c_driver sc16is7xx_i2c_uart_driver
= {
1447 .name
= SC16IS7XX_NAME
,
1448 .of_match_table
= of_match_ptr(sc16is7xx_dt_ids
),
1450 .probe
= sc16is7xx_i2c_probe
,
1451 .remove
= sc16is7xx_i2c_remove
,
1452 .id_table
= sc16is7xx_i2c_id_table
,
1457 static int __init
sc16is7xx_init(void)
1461 ret
= uart_register_driver(&sc16is7xx_uart
);
1463 pr_err("Registering UART driver failed\n");
1467 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1468 ret
= i2c_add_driver(&sc16is7xx_i2c_uart_driver
);
1470 pr_err("failed to init sc16is7xx i2c --> %d\n", ret
);
1475 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1476 ret
= spi_register_driver(&sc16is7xx_spi_uart_driver
);
1478 pr_err("failed to init sc16is7xx spi --> %d\n", ret
);
1484 module_init(sc16is7xx_init
);
1486 static void __exit
sc16is7xx_exit(void)
1488 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1489 i2c_del_driver(&sc16is7xx_i2c_uart_driver
);
1492 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1493 spi_unregister_driver(&sc16is7xx_spi_uart_driver
);
1495 uart_unregister_driver(&sc16is7xx_uart
);
1497 module_exit(sc16is7xx_exit
);
1499 MODULE_LICENSE("GPL");
1500 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1501 MODULE_DESCRIPTION("SC16IS7XX serial driver");