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tty: remove use of __devexit
[deliverable/linux.git] / drivers / tty / serial / sccnxp.c
1 /*
2 * NXP (Philips) SCC+++(SCN+++) serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #define SUPPORT_SYSRQ
16 #endif
17
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/io.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/platform_device.h>
27 #include <linux/platform_data/sccnxp.h>
28
29 #define SCCNXP_NAME "uart-sccnxp"
30 #define SCCNXP_MAJOR 204
31 #define SCCNXP_MINOR 205
32
33 #define SCCNXP_MR_REG (0x00)
34 # define MR0_BAUD_NORMAL (0 << 0)
35 # define MR0_BAUD_EXT1 (1 << 0)
36 # define MR0_BAUD_EXT2 (5 << 0)
37 # define MR0_FIFO (1 << 3)
38 # define MR0_TXLVL (1 << 4)
39 # define MR1_BITS_5 (0 << 0)
40 # define MR1_BITS_6 (1 << 0)
41 # define MR1_BITS_7 (2 << 0)
42 # define MR1_BITS_8 (3 << 0)
43 # define MR1_PAR_EVN (0 << 2)
44 # define MR1_PAR_ODD (1 << 2)
45 # define MR1_PAR_NO (4 << 2)
46 # define MR2_STOP1 (7 << 0)
47 # define MR2_STOP2 (0xf << 0)
48 #define SCCNXP_SR_REG (0x01)
49 #define SCCNXP_CSR_REG SCCNXP_SR_REG
50 # define SR_RXRDY (1 << 0)
51 # define SR_FULL (1 << 1)
52 # define SR_TXRDY (1 << 2)
53 # define SR_TXEMT (1 << 3)
54 # define SR_OVR (1 << 4)
55 # define SR_PE (1 << 5)
56 # define SR_FE (1 << 6)
57 # define SR_BRK (1 << 7)
58 #define SCCNXP_CR_REG (0x02)
59 # define CR_RX_ENABLE (1 << 0)
60 # define CR_RX_DISABLE (1 << 1)
61 # define CR_TX_ENABLE (1 << 2)
62 # define CR_TX_DISABLE (1 << 3)
63 # define CR_CMD_MRPTR1 (0x01 << 4)
64 # define CR_CMD_RX_RESET (0x02 << 4)
65 # define CR_CMD_TX_RESET (0x03 << 4)
66 # define CR_CMD_STATUS_RESET (0x04 << 4)
67 # define CR_CMD_BREAK_RESET (0x05 << 4)
68 # define CR_CMD_START_BREAK (0x06 << 4)
69 # define CR_CMD_STOP_BREAK (0x07 << 4)
70 # define CR_CMD_MRPTR0 (0x0b << 4)
71 #define SCCNXP_RHR_REG (0x03)
72 #define SCCNXP_THR_REG SCCNXP_RHR_REG
73 #define SCCNXP_IPCR_REG (0x04)
74 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
75 # define ACR_BAUD0 (0 << 7)
76 # define ACR_BAUD1 (1 << 7)
77 # define ACR_TIMER_MODE (6 << 4)
78 #define SCCNXP_ISR_REG (0x05)
79 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
80 # define IMR_TXRDY (1 << 0)
81 # define IMR_RXRDY (1 << 1)
82 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
83 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
84 #define SCCNXP_IPR_REG (0x0d)
85 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
86 #define SCCNXP_SOP_REG (0x0e)
87 #define SCCNXP_ROP_REG (0x0f)
88
89 /* Route helpers */
90 #define MCTRL_MASK(sig) (0xf << (sig))
91 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
92 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
93
94 /* Supported chip types */
95 enum {
96 SCCNXP_TYPE_SC2681 = 2681,
97 SCCNXP_TYPE_SC2691 = 2691,
98 SCCNXP_TYPE_SC2692 = 2692,
99 SCCNXP_TYPE_SC2891 = 2891,
100 SCCNXP_TYPE_SC2892 = 2892,
101 SCCNXP_TYPE_SC28202 = 28202,
102 SCCNXP_TYPE_SC68681 = 68681,
103 SCCNXP_TYPE_SC68692 = 68692,
104 };
105
106 struct sccnxp_port {
107 struct uart_driver uart;
108 struct uart_port port[SCCNXP_MAX_UARTS];
109
110 const char *name;
111 int irq;
112
113 u8 imr;
114 u8 addr_mask;
115 int freq_std;
116
117 int flags;
118 #define SCCNXP_HAVE_IO 0x00000001
119 #define SCCNXP_HAVE_MR0 0x00000002
120
121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
122 struct console console;
123 #endif
124
125 struct mutex sccnxp_mutex;
126
127 struct sccnxp_pdata pdata;
128 };
129
130 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
131 {
132 return readb(base + (reg << shift));
133 }
134
135 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
136 {
137 writeb(v, base + (reg << shift));
138 }
139
140 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
141 {
142 struct sccnxp_port *s = dev_get_drvdata(port->dev);
143
144 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
145 port->regshift);
146 }
147
148 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
149 {
150 struct sccnxp_port *s = dev_get_drvdata(port->dev);
151
152 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
153 }
154
155 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
156 {
157 return sccnxp_read(port, (port->line << 3) + reg);
158 }
159
160 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
161 {
162 sccnxp_write(port, (port->line << 3) + reg, v);
163 }
164
165 static int sccnxp_update_best_err(int a, int b, int *besterr)
166 {
167 int err = abs(a - b);
168
169 if ((*besterr < 0) || (*besterr > err)) {
170 *besterr = err;
171 return 0;
172 }
173
174 return 1;
175 }
176
177 struct baud_table {
178 u8 csr;
179 u8 acr;
180 u8 mr0;
181 int baud;
182 };
183
184 const struct baud_table baud_std[] = {
185 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
186 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
187 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
188 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
189 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
190 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
191 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
192 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
193 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
194 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
195 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
196 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
197 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
198 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
199 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
200 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
201 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
202 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
203 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
204 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
205 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
206 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
207 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
208 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
209 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
210 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
211 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
212 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
213 { 0, 0, 0, 0 }
214 };
215
216 static int sccnxp_set_baud(struct uart_port *port, int baud)
217 {
218 struct sccnxp_port *s = dev_get_drvdata(port->dev);
219 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
220 u8 i, acr = 0, csr = 0, mr0 = 0;
221
222 /* Find best baud from table */
223 for (i = 0; baud_std[i].baud && besterr; i++) {
224 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
225 continue;
226 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
227 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
228 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
229 acr = baud_std[i].acr;
230 csr = baud_std[i].csr;
231 mr0 = baud_std[i].mr0;
232 bestbaud = tmp_baud;
233 }
234 }
235
236 if (s->flags & SCCNXP_HAVE_MR0) {
237 /* Enable FIFO, set half level for TX */
238 mr0 |= MR0_FIFO | MR0_TXLVL;
239 /* Update MR0 */
240 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
241 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
242 }
243
244 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
245 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
246
247 if (baud != bestbaud)
248 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
249 baud, bestbaud);
250
251 return bestbaud;
252 }
253
254 static void sccnxp_enable_irq(struct uart_port *port, int mask)
255 {
256 struct sccnxp_port *s = dev_get_drvdata(port->dev);
257
258 s->imr |= mask << (port->line * 4);
259 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
260 }
261
262 static void sccnxp_disable_irq(struct uart_port *port, int mask)
263 {
264 struct sccnxp_port *s = dev_get_drvdata(port->dev);
265
266 s->imr &= ~(mask << (port->line * 4));
267 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
268 }
269
270 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
271 {
272 u8 bitmask;
273 struct sccnxp_port *s = dev_get_drvdata(port->dev);
274
275 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
276 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
277 if (state)
278 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
279 else
280 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
281 }
282 }
283
284 static void sccnxp_handle_rx(struct uart_port *port)
285 {
286 u8 sr;
287 unsigned int ch, flag;
288 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
289
290 if (!tty)
291 return;
292
293 for (;;) {
294 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
295 if (!(sr & SR_RXRDY))
296 break;
297 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
298
299 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
300
301 port->icount.rx++;
302 flag = TTY_NORMAL;
303
304 if (unlikely(sr)) {
305 if (sr & SR_BRK) {
306 port->icount.brk++;
307 if (uart_handle_break(port))
308 continue;
309 } else if (sr & SR_PE)
310 port->icount.parity++;
311 else if (sr & SR_FE)
312 port->icount.frame++;
313 else if (sr & SR_OVR)
314 port->icount.overrun++;
315
316 sr &= port->read_status_mask;
317 if (sr & SR_BRK)
318 flag = TTY_BREAK;
319 else if (sr & SR_PE)
320 flag = TTY_PARITY;
321 else if (sr & SR_FE)
322 flag = TTY_FRAME;
323 else if (sr & SR_OVR)
324 flag = TTY_OVERRUN;
325 }
326
327 if (uart_handle_sysrq_char(port, ch))
328 continue;
329
330 if (sr & port->ignore_status_mask)
331 continue;
332
333 uart_insert_char(port, sr, SR_OVR, ch, flag);
334 }
335
336 tty_flip_buffer_push(tty);
337
338 tty_kref_put(tty);
339 }
340
341 static void sccnxp_handle_tx(struct uart_port *port)
342 {
343 u8 sr;
344 struct circ_buf *xmit = &port->state->xmit;
345 struct sccnxp_port *s = dev_get_drvdata(port->dev);
346
347 if (unlikely(port->x_char)) {
348 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
349 port->icount.tx++;
350 port->x_char = 0;
351 return;
352 }
353
354 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
355 /* Disable TX if FIFO is empty */
356 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
357 sccnxp_disable_irq(port, IMR_TXRDY);
358
359 /* Set direction to input */
360 if (s->flags & SCCNXP_HAVE_IO)
361 sccnxp_set_bit(port, DIR_OP, 0);
362 }
363 return;
364 }
365
366 while (!uart_circ_empty(xmit)) {
367 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
368 if (!(sr & SR_TXRDY))
369 break;
370
371 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
373 port->icount.tx++;
374 }
375
376 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
377 uart_write_wakeup(port);
378 }
379
380 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
381 {
382 int i;
383 u8 isr;
384 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
385
386 mutex_lock(&s->sccnxp_mutex);
387
388 for (;;) {
389 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
390 isr &= s->imr;
391 if (!isr)
392 break;
393
394 dev_dbg(s->port[0].dev, "IRQ status: 0x%02x\n", isr);
395
396 for (i = 0; i < s->uart.nr; i++) {
397 if (isr & ISR_RXRDY(i))
398 sccnxp_handle_rx(&s->port[i]);
399 if (isr & ISR_TXRDY(i))
400 sccnxp_handle_tx(&s->port[i]);
401 }
402 }
403
404 mutex_unlock(&s->sccnxp_mutex);
405
406 return IRQ_HANDLED;
407 }
408
409 static void sccnxp_start_tx(struct uart_port *port)
410 {
411 struct sccnxp_port *s = dev_get_drvdata(port->dev);
412
413 mutex_lock(&s->sccnxp_mutex);
414
415 /* Set direction to output */
416 if (s->flags & SCCNXP_HAVE_IO)
417 sccnxp_set_bit(port, DIR_OP, 1);
418
419 sccnxp_enable_irq(port, IMR_TXRDY);
420
421 mutex_unlock(&s->sccnxp_mutex);
422 }
423
424 static void sccnxp_stop_tx(struct uart_port *port)
425 {
426 /* Do nothing */
427 }
428
429 static void sccnxp_stop_rx(struct uart_port *port)
430 {
431 struct sccnxp_port *s = dev_get_drvdata(port->dev);
432
433 mutex_lock(&s->sccnxp_mutex);
434 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
435 mutex_unlock(&s->sccnxp_mutex);
436 }
437
438 static unsigned int sccnxp_tx_empty(struct uart_port *port)
439 {
440 u8 val;
441 struct sccnxp_port *s = dev_get_drvdata(port->dev);
442
443 mutex_lock(&s->sccnxp_mutex);
444 val = sccnxp_port_read(port, SCCNXP_SR_REG);
445 mutex_unlock(&s->sccnxp_mutex);
446
447 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
448 }
449
450 static void sccnxp_enable_ms(struct uart_port *port)
451 {
452 /* Do nothing */
453 }
454
455 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
456 {
457 struct sccnxp_port *s = dev_get_drvdata(port->dev);
458
459 if (!(s->flags & SCCNXP_HAVE_IO))
460 return;
461
462 mutex_lock(&s->sccnxp_mutex);
463
464 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
465 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
466
467 mutex_unlock(&s->sccnxp_mutex);
468 }
469
470 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
471 {
472 u8 bitmask, ipr;
473 struct sccnxp_port *s = dev_get_drvdata(port->dev);
474 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
475
476 if (!(s->flags & SCCNXP_HAVE_IO))
477 return mctrl;
478
479 mutex_lock(&s->sccnxp_mutex);
480
481 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
482
483 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
484 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
485 DSR_IP);
486 mctrl &= ~TIOCM_DSR;
487 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
488 }
489 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
490 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
491 CTS_IP);
492 mctrl &= ~TIOCM_CTS;
493 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
494 }
495 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
496 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
497 DCD_IP);
498 mctrl &= ~TIOCM_CAR;
499 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
500 }
501 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
502 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
503 RNG_IP);
504 mctrl &= ~TIOCM_RNG;
505 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
506 }
507
508 mutex_unlock(&s->sccnxp_mutex);
509
510 return mctrl;
511 }
512
513 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
514 {
515 struct sccnxp_port *s = dev_get_drvdata(port->dev);
516
517 mutex_lock(&s->sccnxp_mutex);
518 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
519 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
520 mutex_unlock(&s->sccnxp_mutex);
521 }
522
523 static void sccnxp_set_termios(struct uart_port *port,
524 struct ktermios *termios, struct ktermios *old)
525 {
526 struct sccnxp_port *s = dev_get_drvdata(port->dev);
527 u8 mr1, mr2;
528 int baud;
529
530 mutex_lock(&s->sccnxp_mutex);
531
532 /* Mask termios capabilities we don't support */
533 termios->c_cflag &= ~CMSPAR;
534
535 /* Disable RX & TX, reset break condition, status and FIFOs */
536 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
537 CR_RX_DISABLE | CR_TX_DISABLE);
538 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
539 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
540 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
541
542 /* Word size */
543 switch (termios->c_cflag & CSIZE) {
544 case CS5:
545 mr1 = MR1_BITS_5;
546 break;
547 case CS6:
548 mr1 = MR1_BITS_6;
549 break;
550 case CS7:
551 mr1 = MR1_BITS_7;
552 break;
553 case CS8:
554 default:
555 mr1 = MR1_BITS_8;
556 break;
557 }
558
559 /* Parity */
560 if (termios->c_cflag & PARENB) {
561 if (termios->c_cflag & PARODD)
562 mr1 |= MR1_PAR_ODD;
563 } else
564 mr1 |= MR1_PAR_NO;
565
566 /* Stop bits */
567 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
568
569 /* Update desired format */
570 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
571 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
572 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
573
574 /* Set read status mask */
575 port->read_status_mask = SR_OVR;
576 if (termios->c_iflag & INPCK)
577 port->read_status_mask |= SR_PE | SR_FE;
578 if (termios->c_iflag & (BRKINT | PARMRK))
579 port->read_status_mask |= SR_BRK;
580
581 /* Set status ignore mask */
582 port->ignore_status_mask = 0;
583 if (termios->c_iflag & IGNBRK)
584 port->ignore_status_mask |= SR_BRK;
585 if (!(termios->c_cflag & CREAD))
586 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
587
588 /* Setup baudrate */
589 baud = uart_get_baud_rate(port, termios, old, 50,
590 (s->flags & SCCNXP_HAVE_MR0) ?
591 230400 : 38400);
592 baud = sccnxp_set_baud(port, baud);
593
594 /* Update timeout according to new baud rate */
595 uart_update_timeout(port, termios->c_cflag, baud);
596
597 if (tty_termios_baud_rate(termios))
598 tty_termios_encode_baud_rate(termios, baud, baud);
599
600 /* Enable RX & TX */
601 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
602
603 mutex_unlock(&s->sccnxp_mutex);
604 }
605
606 static int sccnxp_startup(struct uart_port *port)
607 {
608 struct sccnxp_port *s = dev_get_drvdata(port->dev);
609
610 mutex_lock(&s->sccnxp_mutex);
611
612 if (s->flags & SCCNXP_HAVE_IO) {
613 /* Outputs are controlled manually */
614 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
615 }
616
617 /* Reset break condition, status and FIFOs */
618 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
619 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
620 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
622
623 /* Enable RX & TX */
624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
625
626 /* Enable RX interrupt */
627 sccnxp_enable_irq(port, IMR_RXRDY);
628
629 mutex_unlock(&s->sccnxp_mutex);
630
631 return 0;
632 }
633
634 static void sccnxp_shutdown(struct uart_port *port)
635 {
636 struct sccnxp_port *s = dev_get_drvdata(port->dev);
637
638 mutex_lock(&s->sccnxp_mutex);
639
640 /* Disable interrupts */
641 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
642
643 /* Disable TX & RX */
644 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
645
646 /* Leave direction to input */
647 if (s->flags & SCCNXP_HAVE_IO)
648 sccnxp_set_bit(port, DIR_OP, 0);
649
650 mutex_unlock(&s->sccnxp_mutex);
651 }
652
653 static const char *sccnxp_type(struct uart_port *port)
654 {
655 struct sccnxp_port *s = dev_get_drvdata(port->dev);
656
657 return (port->type == PORT_SC26XX) ? s->name : NULL;
658 }
659
660 static void sccnxp_release_port(struct uart_port *port)
661 {
662 /* Do nothing */
663 }
664
665 static int sccnxp_request_port(struct uart_port *port)
666 {
667 /* Do nothing */
668 return 0;
669 }
670
671 static void sccnxp_config_port(struct uart_port *port, int flags)
672 {
673 if (flags & UART_CONFIG_TYPE)
674 port->type = PORT_SC26XX;
675 }
676
677 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
678 {
679 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
680 return 0;
681 if (s->irq == port->irq)
682 return 0;
683
684 return -EINVAL;
685 }
686
687 static const struct uart_ops sccnxp_ops = {
688 .tx_empty = sccnxp_tx_empty,
689 .set_mctrl = sccnxp_set_mctrl,
690 .get_mctrl = sccnxp_get_mctrl,
691 .stop_tx = sccnxp_stop_tx,
692 .start_tx = sccnxp_start_tx,
693 .stop_rx = sccnxp_stop_rx,
694 .enable_ms = sccnxp_enable_ms,
695 .break_ctl = sccnxp_break_ctl,
696 .startup = sccnxp_startup,
697 .shutdown = sccnxp_shutdown,
698 .set_termios = sccnxp_set_termios,
699 .type = sccnxp_type,
700 .release_port = sccnxp_release_port,
701 .request_port = sccnxp_request_port,
702 .config_port = sccnxp_config_port,
703 .verify_port = sccnxp_verify_port,
704 };
705
706 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
707 static void sccnxp_console_putchar(struct uart_port *port, int c)
708 {
709 int tryes = 100000;
710
711 while (tryes--) {
712 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
713 sccnxp_port_write(port, SCCNXP_THR_REG, c);
714 break;
715 }
716 barrier();
717 }
718 }
719
720 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
721 {
722 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
723 struct uart_port *port = &s->port[co->index];
724
725 mutex_lock(&s->sccnxp_mutex);
726 uart_console_write(port, c, n, sccnxp_console_putchar);
727 mutex_unlock(&s->sccnxp_mutex);
728 }
729
730 static int sccnxp_console_setup(struct console *co, char *options)
731 {
732 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
733 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
734 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
735
736 if (options)
737 uart_parse_options(options, &baud, &parity, &bits, &flow);
738
739 return uart_set_options(port, co, baud, parity, bits, flow);
740 }
741 #endif
742
743 static int sccnxp_probe(struct platform_device *pdev)
744 {
745 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
746 int chiptype = pdev->id_entry->driver_data;
747 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
748 int i, ret, fifosize, freq_min, freq_max;
749 struct sccnxp_port *s;
750 void __iomem *membase;
751
752 if (!res) {
753 dev_err(&pdev->dev, "Missing memory resource data\n");
754 return -EADDRNOTAVAIL;
755 }
756
757 dev_set_name(&pdev->dev, SCCNXP_NAME);
758
759 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
760 if (!s) {
761 dev_err(&pdev->dev, "Error allocating port structure\n");
762 return -ENOMEM;
763 }
764 platform_set_drvdata(pdev, s);
765
766 mutex_init(&s->sccnxp_mutex);
767
768 /* Individual chip settings */
769 switch (chiptype) {
770 case SCCNXP_TYPE_SC2681:
771 s->name = "SC2681";
772 s->uart.nr = 2;
773 s->freq_std = 3686400;
774 s->addr_mask = 0x0f;
775 s->flags = SCCNXP_HAVE_IO;
776 fifosize = 3;
777 freq_min = 1000000;
778 freq_max = 4000000;
779 break;
780 case SCCNXP_TYPE_SC2691:
781 s->name = "SC2691";
782 s->uart.nr = 1;
783 s->freq_std = 3686400;
784 s->addr_mask = 0x07;
785 s->flags = 0;
786 fifosize = 3;
787 freq_min = 1000000;
788 freq_max = 4000000;
789 break;
790 case SCCNXP_TYPE_SC2692:
791 s->name = "SC2692";
792 s->uart.nr = 2;
793 s->freq_std = 3686400;
794 s->addr_mask = 0x0f;
795 s->flags = SCCNXP_HAVE_IO;
796 fifosize = 3;
797 freq_min = 1000000;
798 freq_max = 4000000;
799 break;
800 case SCCNXP_TYPE_SC2891:
801 s->name = "SC2891";
802 s->uart.nr = 1;
803 s->freq_std = 3686400;
804 s->addr_mask = 0x0f;
805 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
806 fifosize = 16;
807 freq_min = 100000;
808 freq_max = 8000000;
809 break;
810 case SCCNXP_TYPE_SC2892:
811 s->name = "SC2892";
812 s->uart.nr = 2;
813 s->freq_std = 3686400;
814 s->addr_mask = 0x0f;
815 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
816 fifosize = 16;
817 freq_min = 100000;
818 freq_max = 8000000;
819 break;
820 case SCCNXP_TYPE_SC28202:
821 s->name = "SC28202";
822 s->uart.nr = 2;
823 s->freq_std = 14745600;
824 s->addr_mask = 0x7f;
825 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
826 fifosize = 256;
827 freq_min = 1000000;
828 freq_max = 50000000;
829 break;
830 case SCCNXP_TYPE_SC68681:
831 s->name = "SC68681";
832 s->uart.nr = 2;
833 s->freq_std = 3686400;
834 s->addr_mask = 0x0f;
835 s->flags = SCCNXP_HAVE_IO;
836 fifosize = 3;
837 freq_min = 1000000;
838 freq_max = 4000000;
839 break;
840 case SCCNXP_TYPE_SC68692:
841 s->name = "SC68692";
842 s->uart.nr = 2;
843 s->freq_std = 3686400;
844 s->addr_mask = 0x0f;
845 s->flags = SCCNXP_HAVE_IO;
846 fifosize = 3;
847 freq_min = 1000000;
848 freq_max = 4000000;
849 break;
850 default:
851 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
852 ret = -ENOTSUPP;
853 goto err_out;
854 }
855
856 if (!pdata) {
857 dev_warn(&pdev->dev,
858 "No platform data supplied, using defaults\n");
859 s->pdata.frequency = s->freq_std;
860 } else
861 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
862
863 s->irq = platform_get_irq(pdev, 0);
864 if (s->irq <= 0) {
865 dev_err(&pdev->dev, "Missing irq resource data\n");
866 ret = -ENXIO;
867 goto err_out;
868 }
869
870 /* Check input frequency */
871 if ((s->pdata.frequency < freq_min) ||
872 (s->pdata.frequency > freq_max)) {
873 dev_err(&pdev->dev, "Frequency out of bounds\n");
874 ret = -EINVAL;
875 goto err_out;
876 }
877
878 membase = devm_request_and_ioremap(&pdev->dev, res);
879 if (!membase) {
880 dev_err(&pdev->dev, "Failed to ioremap\n");
881 ret = -EIO;
882 goto err_out;
883 }
884
885 s->uart.owner = THIS_MODULE;
886 s->uart.dev_name = "ttySC";
887 s->uart.major = SCCNXP_MAJOR;
888 s->uart.minor = SCCNXP_MINOR;
889 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
890 s->uart.cons = &s->console;
891 s->uart.cons->device = uart_console_device;
892 s->uart.cons->write = sccnxp_console_write;
893 s->uart.cons->setup = sccnxp_console_setup;
894 s->uart.cons->flags = CON_PRINTBUFFER;
895 s->uart.cons->index = -1;
896 s->uart.cons->data = s;
897 strcpy(s->uart.cons->name, "ttySC");
898 #endif
899 ret = uart_register_driver(&s->uart);
900 if (ret) {
901 dev_err(&pdev->dev, "Registering UART driver failed\n");
902 goto err_out;
903 }
904
905 for (i = 0; i < s->uart.nr; i++) {
906 s->port[i].line = i;
907 s->port[i].dev = &pdev->dev;
908 s->port[i].irq = s->irq;
909 s->port[i].type = PORT_SC26XX;
910 s->port[i].fifosize = fifosize;
911 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
912 s->port[i].iotype = UPIO_MEM;
913 s->port[i].mapbase = res->start;
914 s->port[i].membase = membase;
915 s->port[i].regshift = s->pdata.reg_shift;
916 s->port[i].uartclk = s->pdata.frequency;
917 s->port[i].ops = &sccnxp_ops;
918 uart_add_one_port(&s->uart, &s->port[i]);
919 /* Set direction to input */
920 if (s->flags & SCCNXP_HAVE_IO)
921 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
922 }
923
924 /* Disable interrupts */
925 s->imr = 0;
926 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
927
928 /* Board specific configure */
929 if (s->pdata.init)
930 s->pdata.init();
931
932 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, sccnxp_ist,
933 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
934 dev_name(&pdev->dev), s);
935 if (!ret)
936 return 0;
937
938 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
939
940 err_out:
941 platform_set_drvdata(pdev, NULL);
942
943 return ret;
944 }
945
946 static int sccnxp_remove(struct platform_device *pdev)
947 {
948 int i;
949 struct sccnxp_port *s = platform_get_drvdata(pdev);
950
951 devm_free_irq(&pdev->dev, s->irq, s);
952
953 for (i = 0; i < s->uart.nr; i++)
954 uart_remove_one_port(&s->uart, &s->port[i]);
955
956 uart_unregister_driver(&s->uart);
957 platform_set_drvdata(pdev, NULL);
958
959 if (s->pdata.exit)
960 s->pdata.exit();
961
962 return 0;
963 }
964
965 static const struct platform_device_id sccnxp_id_table[] = {
966 { "sc2681", SCCNXP_TYPE_SC2681 },
967 { "sc2691", SCCNXP_TYPE_SC2691 },
968 { "sc2692", SCCNXP_TYPE_SC2692 },
969 { "sc2891", SCCNXP_TYPE_SC2891 },
970 { "sc2892", SCCNXP_TYPE_SC2892 },
971 { "sc28202", SCCNXP_TYPE_SC28202 },
972 { "sc68681", SCCNXP_TYPE_SC68681 },
973 { "sc68692", SCCNXP_TYPE_SC68692 },
974 { },
975 };
976 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
977
978 static struct platform_driver sccnxp_uart_driver = {
979 .driver = {
980 .name = SCCNXP_NAME,
981 .owner = THIS_MODULE,
982 },
983 .probe = sccnxp_probe,
984 .remove = sccnxp_remove,
985 .id_table = sccnxp_id_table,
986 };
987 module_platform_driver(sccnxp_uart_driver);
988
989 MODULE_LICENSE("GPL v2");
990 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
991 MODULE_DESCRIPTION("SCCNXP serial driver");
Linux kernel - Deliverables
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