projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
misc: mic: depend on X86 for both host and card drivers.
[deliverable/linux.git] / drivers / tty / serial / serial-tegra.c
1 /*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/serial_core.h>
40 #include <linux/serial_reg.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/termios.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46
47 #include <linux/clk/tegra.h>
48
49 #define TEGRA_UART_TYPE "TEGRA_UART"
50 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
51 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
52
53 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
54 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
55 #define TEGRA_UART_IER_EORD 0x20
56 #define TEGRA_UART_MCR_RTS_EN 0x40
57 #define TEGRA_UART_MCR_CTS_EN 0x20
58 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
59 UART_LSR_PE | UART_LSR_FE)
60 #define TEGRA_UART_IRDA_CSR 0x08
61 #define TEGRA_UART_SIR_ENABLED 0x80
62
63 #define TEGRA_UART_TX_PIO 1
64 #define TEGRA_UART_TX_DMA 2
65 #define TEGRA_UART_MIN_DMA 16
66 #define TEGRA_UART_FIFO_SIZE 32
67
68 /*
69 * Tx fifo trigger level setting in tegra uart is in
70 * reverse way then conventional uart.
71 */
72 #define TEGRA_UART_TX_TRIG_16B 0x00
73 #define TEGRA_UART_TX_TRIG_8B 0x10
74 #define TEGRA_UART_TX_TRIG_4B 0x20
75 #define TEGRA_UART_TX_TRIG_1B 0x30
76
77 #define TEGRA_UART_MAXIMUM 5
78
79 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
80 #define TEGRA_UART_DEFAULT_BAUD 115200
81 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
82
83 /* Tx transfer mode */
84 #define TEGRA_TX_PIO 1
85 #define TEGRA_TX_DMA 2
86
87 /**
88 * tegra_uart_chip_data: SOC specific data.
89 *
90 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
91 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
92 * Tegra30 does not allow this.
93 * @support_clk_src_div: Clock source support the clock divider.
94 */
95 struct tegra_uart_chip_data {
96 bool tx_fifo_full_status;
97 bool allow_txfifo_reset_fifo_mode;
98 bool support_clk_src_div;
99 };
100
101 struct tegra_uart_port {
102 struct uart_port uport;
103 const struct tegra_uart_chip_data *cdata;
104
105 struct clk *uart_clk;
106 unsigned int current_baud;
107
108 /* Register shadow */
109 unsigned long fcr_shadow;
110 unsigned long mcr_shadow;
111 unsigned long lcr_shadow;
112 unsigned long ier_shadow;
113 bool rts_active;
114
115 int tx_in_progress;
116 unsigned int tx_bytes;
117
118 bool enable_modem_interrupt;
119
120 bool rx_timeout;
121 int rx_in_progress;
122 int symb_bit;
123 int dma_req_sel;
124
125 struct dma_chan *rx_dma_chan;
126 struct dma_chan *tx_dma_chan;
127 dma_addr_t rx_dma_buf_phys;
128 dma_addr_t tx_dma_buf_phys;
129 unsigned char *rx_dma_buf_virt;
130 unsigned char *tx_dma_buf_virt;
131 struct dma_async_tx_descriptor *tx_dma_desc;
132 struct dma_async_tx_descriptor *rx_dma_desc;
133 dma_cookie_t tx_cookie;
134 dma_cookie_t rx_cookie;
135 int tx_bytes_requested;
136 int rx_bytes_requested;
137 };
138
139 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
140 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141
142 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
143 unsigned long reg)
144 {
145 return readl(tup->uport.membase + (reg << tup->uport.regshift));
146 }
147
148 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
149 unsigned long reg)
150 {
151 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
152 }
153
154 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
155 {
156 return container_of(u, struct tegra_uart_port, uport);
157 }
158
159 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
160 {
161 struct tegra_uart_port *tup = to_tegra_uport(u);
162
163 /*
164 * RI - Ring detector is active
165 * CD/DCD/CAR - Carrier detect is always active. For some reason
166 * linux has different names for carrier detect.
167 * DSR - Data Set ready is active as the hardware doesn't support it.
168 * Don't know if the linux support this yet?
169 * CTS - Clear to send. Always set to active, as the hardware handles
170 * CTS automatically.
171 */
172 if (tup->enable_modem_interrupt)
173 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
174 return TIOCM_CTS;
175 }
176
177 static void set_rts(struct tegra_uart_port *tup, bool active)
178 {
179 unsigned long mcr;
180
181 mcr = tup->mcr_shadow;
182 if (active)
183 mcr |= TEGRA_UART_MCR_RTS_EN;
184 else
185 mcr &= ~TEGRA_UART_MCR_RTS_EN;
186 if (mcr != tup->mcr_shadow) {
187 tegra_uart_write(tup, mcr, UART_MCR);
188 tup->mcr_shadow = mcr;
189 }
190 return;
191 }
192
193 static void set_dtr(struct tegra_uart_port *tup, bool active)
194 {
195 unsigned long mcr;
196
197 mcr = tup->mcr_shadow;
198 if (active)
199 mcr |= UART_MCR_DTR;
200 else
201 mcr &= ~UART_MCR_DTR;
202 if (mcr != tup->mcr_shadow) {
203 tegra_uart_write(tup, mcr, UART_MCR);
204 tup->mcr_shadow = mcr;
205 }
206 return;
207 }
208
209 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
210 {
211 struct tegra_uart_port *tup = to_tegra_uport(u);
212 unsigned long mcr;
213 int dtr_enable;
214
215 mcr = tup->mcr_shadow;
216 tup->rts_active = !!(mctrl & TIOCM_RTS);
217 set_rts(tup, tup->rts_active);
218
219 dtr_enable = !!(mctrl & TIOCM_DTR);
220 set_dtr(tup, dtr_enable);
221 return;
222 }
223
224 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
225 {
226 struct tegra_uart_port *tup = to_tegra_uport(u);
227 unsigned long lcr;
228
229 lcr = tup->lcr_shadow;
230 if (break_ctl)
231 lcr |= UART_LCR_SBC;
232 else
233 lcr &= ~UART_LCR_SBC;
234 tegra_uart_write(tup, lcr, UART_LCR);
235 tup->lcr_shadow = lcr;
236 }
237
238 /* Wait for a symbol-time. */
239 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
240 unsigned int syms)
241 {
242 if (tup->current_baud)
243 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
244 tup->current_baud));
245 }
246
247 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
248 {
249 unsigned long fcr = tup->fcr_shadow;
250
251 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
252 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
253 tegra_uart_write(tup, fcr, UART_FCR);
254 } else {
255 fcr &= ~UART_FCR_ENABLE_FIFO;
256 tegra_uart_write(tup, fcr, UART_FCR);
257 udelay(60);
258 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
259 tegra_uart_write(tup, fcr, UART_FCR);
260 fcr |= UART_FCR_ENABLE_FIFO;
261 tegra_uart_write(tup, fcr, UART_FCR);
262 }
263
264 /* Dummy read to ensure the write is posted */
265 tegra_uart_read(tup, UART_SCR);
266
267 /* Wait for the flush to propagate. */
268 tegra_uart_wait_sym_time(tup, 1);
269 }
270
271 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
272 {
273 unsigned long rate;
274 unsigned int divisor;
275 unsigned long lcr;
276 int ret;
277
278 if (tup->current_baud == baud)
279 return 0;
280
281 if (tup->cdata->support_clk_src_div) {
282 rate = baud * 16;
283 ret = clk_set_rate(tup->uart_clk, rate);
284 if (ret < 0) {
285 dev_err(tup->uport.dev,
286 "clk_set_rate() failed for rate %lu\n", rate);
287 return ret;
288 }
289 divisor = 1;
290 } else {
291 rate = clk_get_rate(tup->uart_clk);
292 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
293 }
294
295 lcr = tup->lcr_shadow;
296 lcr |= UART_LCR_DLAB;
297 tegra_uart_write(tup, lcr, UART_LCR);
298
299 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
300 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
301
302 lcr &= ~UART_LCR_DLAB;
303 tegra_uart_write(tup, lcr, UART_LCR);
304
305 /* Dummy read to ensure the write is posted */
306 tegra_uart_read(tup, UART_SCR);
307
308 tup->current_baud = baud;
309
310 /* wait two character intervals at new rate */
311 tegra_uart_wait_sym_time(tup, 2);
312 return 0;
313 }
314
315 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
316 unsigned long lsr)
317 {
318 char flag = TTY_NORMAL;
319
320 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
321 if (lsr & UART_LSR_OE) {
322 /* Overrrun error */
323 flag |= TTY_OVERRUN;
324 tup->uport.icount.overrun++;
325 dev_err(tup->uport.dev, "Got overrun errors\n");
326 } else if (lsr & UART_LSR_PE) {
327 /* Parity error */
328 flag |= TTY_PARITY;
329 tup->uport.icount.parity++;
330 dev_err(tup->uport.dev, "Got Parity errors\n");
331 } else if (lsr & UART_LSR_FE) {
332 flag |= TTY_FRAME;
333 tup->uport.icount.frame++;
334 dev_err(tup->uport.dev, "Got frame errors\n");
335 } else if (lsr & UART_LSR_BI) {
336 dev_err(tup->uport.dev, "Got Break\n");
337 tup->uport.icount.brk++;
338 /* If FIFO read error without any data, reset Rx FIFO */
339 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
340 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
341 }
342 }
343 return flag;
344 }
345
346 static int tegra_uart_request_port(struct uart_port *u)
347 {
348 return 0;
349 }
350
351 static void tegra_uart_release_port(struct uart_port *u)
352 {
353 /* Nothing to do here */
354 }
355
356 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
357 {
358 struct circ_buf *xmit = &tup->uport.state->xmit;
359 int i;
360
361 for (i = 0; i < max_bytes; i++) {
362 BUG_ON(uart_circ_empty(xmit));
363 if (tup->cdata->tx_fifo_full_status) {
364 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
365 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
366 break;
367 }
368 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
369 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
370 tup->uport.icount.tx++;
371 }
372 }
373
374 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
375 unsigned int bytes)
376 {
377 if (bytes > TEGRA_UART_MIN_DMA)
378 bytes = TEGRA_UART_MIN_DMA;
379
380 tup->tx_in_progress = TEGRA_UART_TX_PIO;
381 tup->tx_bytes = bytes;
382 tup->ier_shadow |= UART_IER_THRI;
383 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
384 }
385
386 static void tegra_uart_tx_dma_complete(void *args)
387 {
388 struct tegra_uart_port *tup = args;
389 struct circ_buf *xmit = &tup->uport.state->xmit;
390 struct dma_tx_state state;
391 unsigned long flags;
392 int count;
393
394 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
395 count = tup->tx_bytes_requested - state.residue;
396 async_tx_ack(tup->tx_dma_desc);
397 spin_lock_irqsave(&tup->uport.lock, flags);
398 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
399 tup->tx_in_progress = 0;
400 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
401 uart_write_wakeup(&tup->uport);
402 tegra_uart_start_next_tx(tup);
403 spin_unlock_irqrestore(&tup->uport.lock, flags);
404 }
405
406 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
407 unsigned long count)
408 {
409 struct circ_buf *xmit = &tup->uport.state->xmit;
410 dma_addr_t tx_phys_addr;
411
412 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
413 UART_XMIT_SIZE, DMA_TO_DEVICE);
414
415 tup->tx_bytes = count & ~(0xF);
416 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
417 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
418 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
419 DMA_PREP_INTERRUPT);
420 if (!tup->tx_dma_desc) {
421 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
422 return -EIO;
423 }
424
425 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
426 tup->tx_dma_desc->callback_param = tup;
427 tup->tx_in_progress = TEGRA_UART_TX_DMA;
428 tup->tx_bytes_requested = tup->tx_bytes;
429 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
430 dma_async_issue_pending(tup->tx_dma_chan);
431 return 0;
432 }
433
434 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
435 {
436 unsigned long tail;
437 unsigned long count;
438 struct circ_buf *xmit = &tup->uport.state->xmit;
439
440 tail = (unsigned long)&xmit->buf[xmit->tail];
441 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
442 if (!count)
443 return;
444
445 if (count < TEGRA_UART_MIN_DMA)
446 tegra_uart_start_pio_tx(tup, count);
447 else if (BYTES_TO_ALIGN(tail) > 0)
448 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
449 else
450 tegra_uart_start_tx_dma(tup, count);
451 }
452
453 /* Called by serial core driver with u->lock taken. */
454 static void tegra_uart_start_tx(struct uart_port *u)
455 {
456 struct tegra_uart_port *tup = to_tegra_uport(u);
457 struct circ_buf *xmit = &u->state->xmit;
458
459 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
460 tegra_uart_start_next_tx(tup);
461 }
462
463 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
464 {
465 struct tegra_uart_port *tup = to_tegra_uport(u);
466 unsigned int ret = 0;
467 unsigned long flags;
468
469 spin_lock_irqsave(&u->lock, flags);
470 if (!tup->tx_in_progress) {
471 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
472 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
473 ret = TIOCSER_TEMT;
474 }
475 spin_unlock_irqrestore(&u->lock, flags);
476 return ret;
477 }
478
479 static void tegra_uart_stop_tx(struct uart_port *u)
480 {
481 struct tegra_uart_port *tup = to_tegra_uport(u);
482 struct circ_buf *xmit = &tup->uport.state->xmit;
483 struct dma_tx_state state;
484 int count;
485
486 dmaengine_terminate_all(tup->tx_dma_chan);
487 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
488 count = tup->tx_bytes_requested - state.residue;
489 async_tx_ack(tup->tx_dma_desc);
490 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
491 tup->tx_in_progress = 0;
492 return;
493 }
494
495 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
496 {
497 struct circ_buf *xmit = &tup->uport.state->xmit;
498
499 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
500 tup->tx_in_progress = 0;
501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
502 uart_write_wakeup(&tup->uport);
503 tegra_uart_start_next_tx(tup);
504 return;
505 }
506
507 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
508 struct tty_port *tty)
509 {
510 do {
511 char flag = TTY_NORMAL;
512 unsigned long lsr = 0;
513 unsigned char ch;
514
515 lsr = tegra_uart_read(tup, UART_LSR);
516 if (!(lsr & UART_LSR_DR))
517 break;
518
519 flag = tegra_uart_decode_rx_error(tup, lsr);
520 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
521 tup->uport.icount.rx++;
522
523 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
524 tty_insert_flip_char(tty, ch, flag);
525 } while (1);
526
527 return;
528 }
529
530 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
531 struct tty_port *tty, int count)
532 {
533 int copied;
534
535 tup->uport.icount.rx += count;
536 if (!tty) {
537 dev_err(tup->uport.dev, "No tty port\n");
538 return;
539 }
540 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
541 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
542 copied = tty_insert_flip_string(tty,
543 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
544 if (copied != count) {
545 WARN_ON(1);
546 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
547 }
548 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
549 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
550 }
551
552 static void tegra_uart_rx_dma_complete(void *args)
553 {
554 struct tegra_uart_port *tup = args;
555 struct uart_port *u = &tup->uport;
556 int count = tup->rx_bytes_requested;
557 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
558 struct tty_port *port = &u->state->port;
559 unsigned long flags;
560
561 async_tx_ack(tup->rx_dma_desc);
562 spin_lock_irqsave(&u->lock, flags);
563
564 /* Deactivate flow control to stop sender */
565 if (tup->rts_active)
566 set_rts(tup, false);
567
568 /* If we are here, DMA is stopped */
569 if (count)
570 tegra_uart_copy_rx_to_tty(tup, port, count);
571
572 tegra_uart_handle_rx_pio(tup, port);
573 if (tty) {
574 spin_unlock_irqrestore(&u->lock, flags);
575 tty_flip_buffer_push(port);
576 spin_lock_irqsave(&u->lock, flags);
577 tty_kref_put(tty);
578 }
579 tegra_uart_start_rx_dma(tup);
580
581 /* Activate flow control to start transfer */
582 if (tup->rts_active)
583 set_rts(tup, true);
584
585 spin_unlock_irqrestore(&u->lock, flags);
586 }
587
588 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup,
589 unsigned long *flags)
590 {
591 struct dma_tx_state state;
592 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
593 struct tty_port *port = &tup->uport.state->port;
594 struct uart_port *u = &tup->uport;
595 int count;
596
597 /* Deactivate flow control to stop sender */
598 if (tup->rts_active)
599 set_rts(tup, false);
600
601 dmaengine_terminate_all(tup->rx_dma_chan);
602 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
603 count = tup->rx_bytes_requested - state.residue;
604
605 /* If we are here, DMA is stopped */
606 if (count)
607 tegra_uart_copy_rx_to_tty(tup, port, count);
608
609 tegra_uart_handle_rx_pio(tup, port);
610 if (tty) {
611 spin_unlock_irqrestore(&u->lock, *flags);
612 tty_flip_buffer_push(port);
613 spin_lock_irqsave(&u->lock, *flags);
614 tty_kref_put(tty);
615 }
616 tegra_uart_start_rx_dma(tup);
617
618 if (tup->rts_active)
619 set_rts(tup, true);
620 }
621
622 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
623 {
624 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
625
626 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
627 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
628 DMA_PREP_INTERRUPT);
629 if (!tup->rx_dma_desc) {
630 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
631 return -EIO;
632 }
633
634 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
635 tup->rx_dma_desc->callback_param = tup;
636 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
637 count, DMA_TO_DEVICE);
638 tup->rx_bytes_requested = count;
639 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
640 dma_async_issue_pending(tup->rx_dma_chan);
641 return 0;
642 }
643
644 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
645 {
646 struct tegra_uart_port *tup = to_tegra_uport(u);
647 unsigned long msr;
648
649 msr = tegra_uart_read(tup, UART_MSR);
650 if (!(msr & UART_MSR_ANY_DELTA))
651 return;
652
653 if (msr & UART_MSR_TERI)
654 tup->uport.icount.rng++;
655 if (msr & UART_MSR_DDSR)
656 tup->uport.icount.dsr++;
657 /* We may only get DDCD when HW init and reset */
658 if (msr & UART_MSR_DDCD)
659 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
660 /* Will start/stop_tx accordingly */
661 if (msr & UART_MSR_DCTS)
662 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
663 return;
664 }
665
666 static irqreturn_t tegra_uart_isr(int irq, void *data)
667 {
668 struct tegra_uart_port *tup = data;
669 struct uart_port *u = &tup->uport;
670 unsigned long iir;
671 unsigned long ier;
672 bool is_rx_int = false;
673 unsigned long flags;
674
675 spin_lock_irqsave(&u->lock, flags);
676 while (1) {
677 iir = tegra_uart_read(tup, UART_IIR);
678 if (iir & UART_IIR_NO_INT) {
679 if (is_rx_int) {
680 tegra_uart_handle_rx_dma(tup, &flags);
681 if (tup->rx_in_progress) {
682 ier = tup->ier_shadow;
683 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
684 TEGRA_UART_IER_EORD);
685 tup->ier_shadow = ier;
686 tegra_uart_write(tup, ier, UART_IER);
687 }
688 }
689 spin_unlock_irqrestore(&u->lock, flags);
690 return IRQ_HANDLED;
691 }
692
693 switch ((iir >> 1) & 0x7) {
694 case 0: /* Modem signal change interrupt */
695 tegra_uart_handle_modem_signal_change(u);
696 break;
697
698 case 1: /* Transmit interrupt only triggered when using PIO */
699 tup->ier_shadow &= ~UART_IER_THRI;
700 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
701 tegra_uart_handle_tx_pio(tup);
702 break;
703
704 case 4: /* End of data */
705 case 6: /* Rx timeout */
706 case 2: /* Receive */
707 if (!is_rx_int) {
708 is_rx_int = true;
709 /* Disable Rx interrupts */
710 ier = tup->ier_shadow;
711 ier |= UART_IER_RDI;
712 tegra_uart_write(tup, ier, UART_IER);
713 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
714 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
715 tup->ier_shadow = ier;
716 tegra_uart_write(tup, ier, UART_IER);
717 }
718 break;
719
720 case 3: /* Receive error */
721 tegra_uart_decode_rx_error(tup,
722 tegra_uart_read(tup, UART_LSR));
723 break;
724
725 case 5: /* break nothing to handle */
726 case 7: /* break nothing to handle */
727 break;
728 }
729 }
730 }
731
732 static void tegra_uart_stop_rx(struct uart_port *u)
733 {
734 struct tegra_uart_port *tup = to_tegra_uport(u);
735 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
736 struct tty_port *port = &u->state->port;
737 struct dma_tx_state state;
738 unsigned long ier;
739 int count;
740
741 if (tup->rts_active)
742 set_rts(tup, false);
743
744 if (!tup->rx_in_progress)
745 return;
746
747 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
748
749 ier = tup->ier_shadow;
750 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
751 TEGRA_UART_IER_EORD);
752 tup->ier_shadow = ier;
753 tegra_uart_write(tup, ier, UART_IER);
754 tup->rx_in_progress = 0;
755 if (tup->rx_dma_chan) {
756 dmaengine_terminate_all(tup->rx_dma_chan);
757 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
758 async_tx_ack(tup->rx_dma_desc);
759 count = tup->rx_bytes_requested - state.residue;
760 tegra_uart_copy_rx_to_tty(tup, port, count);
761 tegra_uart_handle_rx_pio(tup, port);
762 } else {
763 tegra_uart_handle_rx_pio(tup, port);
764 }
765 if (tty) {
766 tty_flip_buffer_push(port);
767 tty_kref_put(tty);
768 }
769 return;
770 }
771
772 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
773 {
774 unsigned long flags;
775 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
776 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
777 unsigned long wait_time;
778 unsigned long lsr;
779 unsigned long msr;
780 unsigned long mcr;
781
782 /* Disable interrupts */
783 tegra_uart_write(tup, 0, UART_IER);
784
785 lsr = tegra_uart_read(tup, UART_LSR);
786 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
787 msr = tegra_uart_read(tup, UART_MSR);
788 mcr = tegra_uart_read(tup, UART_MCR);
789 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
790 dev_err(tup->uport.dev,
791 "Tx Fifo not empty, CTS disabled, waiting\n");
792
793 /* Wait for Tx fifo to be empty */
794 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
795 wait_time = min(fifo_empty_time, 100lu);
796 udelay(wait_time);
797 fifo_empty_time -= wait_time;
798 if (!fifo_empty_time) {
799 msr = tegra_uart_read(tup, UART_MSR);
800 mcr = tegra_uart_read(tup, UART_MCR);
801 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
802 (msr & UART_MSR_CTS))
803 dev_err(tup->uport.dev,
804 "Slave not ready\n");
805 break;
806 }
807 lsr = tegra_uart_read(tup, UART_LSR);
808 }
809 }
810
811 spin_lock_irqsave(&tup->uport.lock, flags);
812 /* Reset the Rx and Tx FIFOs */
813 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
814 tup->current_baud = 0;
815 spin_unlock_irqrestore(&tup->uport.lock, flags);
816
817 clk_disable_unprepare(tup->uart_clk);
818 }
819
820 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
821 {
822 int ret;
823
824 tup->fcr_shadow = 0;
825 tup->mcr_shadow = 0;
826 tup->lcr_shadow = 0;
827 tup->ier_shadow = 0;
828 tup->current_baud = 0;
829
830 clk_prepare_enable(tup->uart_clk);
831
832 /* Reset the UART controller to clear all previous status.*/
833 tegra_periph_reset_assert(tup->uart_clk);
834 udelay(10);
835 tegra_periph_reset_deassert(tup->uart_clk);
836
837 tup->rx_in_progress = 0;
838 tup->tx_in_progress = 0;
839
840 /*
841 * Set the trigger level
842 *
843 * For PIO mode:
844 *
845 * For receive, this will interrupt the CPU after that many number of
846 * bytes are received, for the remaining bytes the receive timeout
847 * interrupt is received. Rx high watermark is set to 4.
848 *
849 * For transmit, if the trasnmit interrupt is enabled, this will
850 * interrupt the CPU when the number of entries in the FIFO reaches the
851 * low watermark. Tx low watermark is set to 16 bytes.
852 *
853 * For DMA mode:
854 *
855 * Set the Tx trigger to 16. This should match the DMA burst size that
856 * programmed in the DMA registers.
857 */
858 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
859 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
860 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
861 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
862
863 /*
864 * Initialize the UART with default configuration
865 * (115200, N, 8, 1) so that the receive DMA buffer may be
866 * enqueued
867 */
868 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
869 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
870 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
871 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
872
873 ret = tegra_uart_start_rx_dma(tup);
874 if (ret < 0) {
875 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
876 return ret;
877 }
878 tup->rx_in_progress = 1;
879
880 /*
881 * Enable IE_RXS for the receive status interrupts like line errros.
882 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
883 *
884 * If using DMA mode, enable EORD instead of receive interrupt which
885 * will interrupt after the UART is done with the receive instead of
886 * the interrupt when the FIFO "threshold" is reached.
887 *
888 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
889 * the DATA is sitting in the FIFO and couldn't be transferred to the
890 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
891 * triggered when there is a pause of the incomming data stream for 4
892 * characters long.
893 *
894 * For pauses in the data which is not aligned to 4 bytes, we get
895 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
896 * then the EORD.
897 */
898 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
899 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
900 return 0;
901 }
902
903 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
904 bool dma_to_memory)
905 {
906 struct dma_chan *dma_chan;
907 unsigned char *dma_buf;
908 dma_addr_t dma_phys;
909 int ret;
910 struct dma_slave_config dma_sconfig;
911 dma_cap_mask_t mask;
912
913 dma_cap_zero(mask);
914 dma_cap_set(DMA_SLAVE, mask);
915 dma_chan = dma_request_channel(mask, NULL, NULL);
916 if (!dma_chan) {
917 dev_err(tup->uport.dev,
918 "Dma channel is not available, will try later\n");
919 return -EPROBE_DEFER;
920 }
921
922 if (dma_to_memory) {
923 dma_buf = dma_alloc_coherent(tup->uport.dev,
924 TEGRA_UART_RX_DMA_BUFFER_SIZE,
925 &dma_phys, GFP_KERNEL);
926 if (!dma_buf) {
927 dev_err(tup->uport.dev,
928 "Not able to allocate the dma buffer\n");
929 dma_release_channel(dma_chan);
930 return -ENOMEM;
931 }
932 } else {
933 dma_phys = dma_map_single(tup->uport.dev,
934 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
935 DMA_TO_DEVICE);
936 dma_buf = tup->uport.state->xmit.buf;
937 }
938
939 dma_sconfig.slave_id = tup->dma_req_sel;
940 if (dma_to_memory) {
941 dma_sconfig.src_addr = tup->uport.mapbase;
942 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
943 dma_sconfig.src_maxburst = 4;
944 } else {
945 dma_sconfig.dst_addr = tup->uport.mapbase;
946 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
947 dma_sconfig.dst_maxburst = 16;
948 }
949
950 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
951 if (ret < 0) {
952 dev_err(tup->uport.dev,
953 "Dma slave config failed, err = %d\n", ret);
954 goto scrub;
955 }
956
957 if (dma_to_memory) {
958 tup->rx_dma_chan = dma_chan;
959 tup->rx_dma_buf_virt = dma_buf;
960 tup->rx_dma_buf_phys = dma_phys;
961 } else {
962 tup->tx_dma_chan = dma_chan;
963 tup->tx_dma_buf_virt = dma_buf;
964 tup->tx_dma_buf_phys = dma_phys;
965 }
966 return 0;
967
968 scrub:
969 dma_release_channel(dma_chan);
970 return ret;
971 }
972
973 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
974 bool dma_to_memory)
975 {
976 struct dma_chan *dma_chan;
977
978 if (dma_to_memory) {
979 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
980 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
981 dma_chan = tup->rx_dma_chan;
982 tup->rx_dma_chan = NULL;
983 tup->rx_dma_buf_phys = 0;
984 tup->rx_dma_buf_virt = NULL;
985 } else {
986 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
987 UART_XMIT_SIZE, DMA_TO_DEVICE);
988 dma_chan = tup->tx_dma_chan;
989 tup->tx_dma_chan = NULL;
990 tup->tx_dma_buf_phys = 0;
991 tup->tx_dma_buf_virt = NULL;
992 }
993 dma_release_channel(dma_chan);
994 }
995
996 static int tegra_uart_startup(struct uart_port *u)
997 {
998 struct tegra_uart_port *tup = to_tegra_uport(u);
999 int ret;
1000
1001 ret = tegra_uart_dma_channel_allocate(tup, false);
1002 if (ret < 0) {
1003 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1004 return ret;
1005 }
1006
1007 ret = tegra_uart_dma_channel_allocate(tup, true);
1008 if (ret < 0) {
1009 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1010 goto fail_rx_dma;
1011 }
1012
1013 ret = tegra_uart_hw_init(tup);
1014 if (ret < 0) {
1015 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1016 goto fail_hw_init;
1017 }
1018
1019 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
1020 dev_name(u->dev), tup);
1021 if (ret < 0) {
1022 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1023 goto fail_hw_init;
1024 }
1025 return 0;
1026
1027 fail_hw_init:
1028 tegra_uart_dma_channel_free(tup, true);
1029 fail_rx_dma:
1030 tegra_uart_dma_channel_free(tup, false);
1031 return ret;
1032 }
1033
1034 static void tegra_uart_shutdown(struct uart_port *u)
1035 {
1036 struct tegra_uart_port *tup = to_tegra_uport(u);
1037
1038 tegra_uart_hw_deinit(tup);
1039
1040 tup->rx_in_progress = 0;
1041 tup->tx_in_progress = 0;
1042
1043 tegra_uart_dma_channel_free(tup, true);
1044 tegra_uart_dma_channel_free(tup, false);
1045 free_irq(u->irq, tup);
1046 }
1047
1048 static void tegra_uart_enable_ms(struct uart_port *u)
1049 {
1050 struct tegra_uart_port *tup = to_tegra_uport(u);
1051
1052 if (tup->enable_modem_interrupt) {
1053 tup->ier_shadow |= UART_IER_MSI;
1054 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1055 }
1056 }
1057
1058 static void tegra_uart_set_termios(struct uart_port *u,
1059 struct ktermios *termios, struct ktermios *oldtermios)
1060 {
1061 struct tegra_uart_port *tup = to_tegra_uport(u);
1062 unsigned int baud;
1063 unsigned long flags;
1064 unsigned int lcr;
1065 int symb_bit = 1;
1066 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1067 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1068 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1069
1070 max_divider *= 16;
1071 spin_lock_irqsave(&u->lock, flags);
1072
1073 /* Changing configuration, it is safe to stop any rx now */
1074 if (tup->rts_active)
1075 set_rts(tup, false);
1076
1077 /* Clear all interrupts as configuration is going to be change */
1078 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1079 tegra_uart_read(tup, UART_IER);
1080 tegra_uart_write(tup, 0, UART_IER);
1081 tegra_uart_read(tup, UART_IER);
1082
1083 /* Parity */
1084 lcr = tup->lcr_shadow;
1085 lcr &= ~UART_LCR_PARITY;
1086
1087 /* CMSPAR isn't supported by this driver */
1088 termios->c_cflag &= ~CMSPAR;
1089
1090 if ((termios->c_cflag & PARENB) == PARENB) {
1091 symb_bit++;
1092 if (termios->c_cflag & PARODD) {
1093 lcr |= UART_LCR_PARITY;
1094 lcr &= ~UART_LCR_EPAR;
1095 lcr &= ~UART_LCR_SPAR;
1096 } else {
1097 lcr |= UART_LCR_PARITY;
1098 lcr |= UART_LCR_EPAR;
1099 lcr &= ~UART_LCR_SPAR;
1100 }
1101 }
1102
1103 lcr &= ~UART_LCR_WLEN8;
1104 switch (termios->c_cflag & CSIZE) {
1105 case CS5:
1106 lcr |= UART_LCR_WLEN5;
1107 symb_bit += 5;
1108 break;
1109 case CS6:
1110 lcr |= UART_LCR_WLEN6;
1111 symb_bit += 6;
1112 break;
1113 case CS7:
1114 lcr |= UART_LCR_WLEN7;
1115 symb_bit += 7;
1116 break;
1117 default:
1118 lcr |= UART_LCR_WLEN8;
1119 symb_bit += 8;
1120 break;
1121 }
1122
1123 /* Stop bits */
1124 if (termios->c_cflag & CSTOPB) {
1125 lcr |= UART_LCR_STOP;
1126 symb_bit += 2;
1127 } else {
1128 lcr &= ~UART_LCR_STOP;
1129 symb_bit++;
1130 }
1131
1132 tegra_uart_write(tup, lcr, UART_LCR);
1133 tup->lcr_shadow = lcr;
1134 tup->symb_bit = symb_bit;
1135
1136 /* Baud rate. */
1137 baud = uart_get_baud_rate(u, termios, oldtermios,
1138 parent_clk_rate/max_divider,
1139 parent_clk_rate/16);
1140 spin_unlock_irqrestore(&u->lock, flags);
1141 tegra_set_baudrate(tup, baud);
1142 if (tty_termios_baud_rate(termios))
1143 tty_termios_encode_baud_rate(termios, baud, baud);
1144 spin_lock_irqsave(&u->lock, flags);
1145
1146 /* Flow control */
1147 if (termios->c_cflag & CRTSCTS) {
1148 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1149 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1150 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1151 /* if top layer has asked to set rts active then do so here */
1152 if (tup->rts_active)
1153 set_rts(tup, true);
1154 } else {
1155 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1156 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1157 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1158 }
1159
1160 /* update the port timeout based on new settings */
1161 uart_update_timeout(u, termios->c_cflag, baud);
1162
1163 /* Make sure all write has completed */
1164 tegra_uart_read(tup, UART_IER);
1165
1166 /* Reenable interrupt */
1167 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1168 tegra_uart_read(tup, UART_IER);
1169
1170 spin_unlock_irqrestore(&u->lock, flags);
1171 return;
1172 }
1173
1174 /*
1175 * Flush any TX data submitted for DMA and PIO. Called when the
1176 * TX circular buffer is reset.
1177 */
1178 static void tegra_uart_flush_buffer(struct uart_port *u)
1179 {
1180 struct tegra_uart_port *tup = to_tegra_uport(u);
1181
1182 tup->tx_bytes = 0;
1183 if (tup->tx_dma_chan)
1184 dmaengine_terminate_all(tup->tx_dma_chan);
1185 return;
1186 }
1187
1188 static const char *tegra_uart_type(struct uart_port *u)
1189 {
1190 return TEGRA_UART_TYPE;
1191 }
1192
1193 static struct uart_ops tegra_uart_ops = {
1194 .tx_empty = tegra_uart_tx_empty,
1195 .set_mctrl = tegra_uart_set_mctrl,
1196 .get_mctrl = tegra_uart_get_mctrl,
1197 .stop_tx = tegra_uart_stop_tx,
1198 .start_tx = tegra_uart_start_tx,
1199 .stop_rx = tegra_uart_stop_rx,
1200 .flush_buffer = tegra_uart_flush_buffer,
1201 .enable_ms = tegra_uart_enable_ms,
1202 .break_ctl = tegra_uart_break_ctl,
1203 .startup = tegra_uart_startup,
1204 .shutdown = tegra_uart_shutdown,
1205 .set_termios = tegra_uart_set_termios,
1206 .type = tegra_uart_type,
1207 .request_port = tegra_uart_request_port,
1208 .release_port = tegra_uart_release_port,
1209 };
1210
1211 static struct uart_driver tegra_uart_driver = {
1212 .owner = THIS_MODULE,
1213 .driver_name = "tegra_hsuart",
1214 .dev_name = "ttyTHS",
1215 .cons = NULL,
1216 .nr = TEGRA_UART_MAXIMUM,
1217 };
1218
1219 static int tegra_uart_parse_dt(struct platform_device *pdev,
1220 struct tegra_uart_port *tup)
1221 {
1222 struct device_node *np = pdev->dev.of_node;
1223 u32 of_dma[2];
1224 int port;
1225
1226 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1227 of_dma, 2) >= 0) {
1228 tup->dma_req_sel = of_dma[1];
1229 } else {
1230 dev_err(&pdev->dev, "missing dma requestor in device tree\n");
1231 return -EINVAL;
1232 }
1233
1234 port = of_alias_get_id(np, "serial");
1235 if (port < 0) {
1236 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1237 return port;
1238 }
1239 tup->uport.line = port;
1240
1241 tup->enable_modem_interrupt = of_property_read_bool(np,
1242 "nvidia,enable-modem-interrupt");
1243 return 0;
1244 }
1245
1246 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1247 .tx_fifo_full_status = false,
1248 .allow_txfifo_reset_fifo_mode = true,
1249 .support_clk_src_div = false,
1250 };
1251
1252 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1253 .tx_fifo_full_status = true,
1254 .allow_txfifo_reset_fifo_mode = false,
1255 .support_clk_src_div = true,
1256 };
1257
1258 static struct of_device_id tegra_uart_of_match[] = {
1259 {
1260 .compatible = "nvidia,tegra30-hsuart",
1261 .data = &tegra30_uart_chip_data,
1262 }, {
1263 .compatible = "nvidia,tegra20-hsuart",
1264 .data = &tegra20_uart_chip_data,
1265 }, {
1266 },
1267 };
1268 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1269
1270 static int tegra_uart_probe(struct platform_device *pdev)
1271 {
1272 struct tegra_uart_port *tup;
1273 struct uart_port *u;
1274 struct resource *resource;
1275 int ret;
1276 const struct tegra_uart_chip_data *cdata;
1277 const struct of_device_id *match;
1278
1279 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1280 if (!match) {
1281 dev_err(&pdev->dev, "Error: No device match found\n");
1282 return -ENODEV;
1283 }
1284 cdata = match->data;
1285
1286 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1287 if (!tup) {
1288 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1289 return -ENOMEM;
1290 }
1291
1292 ret = tegra_uart_parse_dt(pdev, tup);
1293 if (ret < 0)
1294 return ret;
1295
1296 u = &tup->uport;
1297 u->dev = &pdev->dev;
1298 u->ops = &tegra_uart_ops;
1299 u->type = PORT_TEGRA;
1300 u->fifosize = 32;
1301 tup->cdata = cdata;
1302
1303 platform_set_drvdata(pdev, tup);
1304 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305 if (!resource) {
1306 dev_err(&pdev->dev, "No IO memory resource\n");
1307 return -ENODEV;
1308 }
1309
1310 u->mapbase = resource->start;
1311 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1312 if (IS_ERR(u->membase))
1313 return PTR_ERR(u->membase);
1314
1315 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1316 if (IS_ERR(tup->uart_clk)) {
1317 dev_err(&pdev->dev, "Couldn't get the clock\n");
1318 return PTR_ERR(tup->uart_clk);
1319 }
1320
1321 u->iotype = UPIO_MEM32;
1322 u->irq = platform_get_irq(pdev, 0);
1323 u->regshift = 2;
1324 ret = uart_add_one_port(&tegra_uart_driver, u);
1325 if (ret < 0) {
1326 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1327 return ret;
1328 }
1329 return ret;
1330 }
1331
1332 static int tegra_uart_remove(struct platform_device *pdev)
1333 {
1334 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1335 struct uart_port *u = &tup->uport;
1336
1337 uart_remove_one_port(&tegra_uart_driver, u);
1338 return 0;
1339 }
1340
1341 #ifdef CONFIG_PM_SLEEP
1342 static int tegra_uart_suspend(struct device *dev)
1343 {
1344 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1345 struct uart_port *u = &tup->uport;
1346
1347 return uart_suspend_port(&tegra_uart_driver, u);
1348 }
1349
1350 static int tegra_uart_resume(struct device *dev)
1351 {
1352 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1353 struct uart_port *u = &tup->uport;
1354
1355 return uart_resume_port(&tegra_uart_driver, u);
1356 }
1357 #endif
1358
1359 static const struct dev_pm_ops tegra_uart_pm_ops = {
1360 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1361 };
1362
1363 static struct platform_driver tegra_uart_platform_driver = {
1364 .probe = tegra_uart_probe,
1365 .remove = tegra_uart_remove,
1366 .driver = {
1367 .name = "serial-tegra",
1368 .of_match_table = tegra_uart_of_match,
1369 .pm = &tegra_uart_pm_ops,
1370 },
1371 };
1372
1373 static int __init tegra_uart_init(void)
1374 {
1375 int ret;
1376
1377 ret = uart_register_driver(&tegra_uart_driver);
1378 if (ret < 0) {
1379 pr_err("Could not register %s driver\n",
1380 tegra_uart_driver.driver_name);
1381 return ret;
1382 }
1383
1384 ret = platform_driver_register(&tegra_uart_platform_driver);
1385 if (ret < 0) {
1386 pr_err("Uart platform driver register failed, e = %d\n", ret);
1387 uart_unregister_driver(&tegra_uart_driver);
1388 return ret;
1389 }
1390 return 0;
1391 }
1392
1393 static void __exit tegra_uart_exit(void)
1394 {
1395 pr_info("Unloading tegra uart driver\n");
1396 platform_driver_unregister(&tegra_uart_platform_driver);
1397 uart_unregister_driver(&tegra_uart_driver);
1398 }
1399
1400 module_init(tegra_uart_init);
1401 module_exit(tegra_uart_exit);
1402
1403 MODULE_ALIAS("platform:serial-tegra");
1404 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1405 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1406 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.061522 seconds and 5 git commands to generate.