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serial: sh-sci: Stop acknowledging DMA transmit completions
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
90
91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
94
95 /* Interface clock */
96 struct clk *iclk;
97 /* Function clock */
98 struct clk *fclk;
99
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
102
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
105
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 struct dma_async_tx_descriptor *desc_rx[2];
108 dma_cookie_t cookie_tx;
109 dma_cookie_t cookie_rx[2];
110 dma_cookie_t active_rx;
111 dma_addr_t tx_dma_addr;
112 unsigned int tx_dma_len;
113 struct scatterlist sg_rx[2];
114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
120 unsigned int rx_timeout;
121 #endif
122
123 struct notifier_block freq_transition;
124 };
125
126 /* Function prototypes */
127 static void sci_start_tx(struct uart_port *port);
128 static void sci_stop_tx(struct uart_port *port);
129 static void sci_start_rx(struct uart_port *port);
130
131 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
132
133 static struct sci_port sci_ports[SCI_NPORTS];
134 static struct uart_driver sci_uart_driver;
135
136 static inline struct sci_port *
137 to_sci_port(struct uart_port *uart)
138 {
139 return container_of(uart, struct sci_port, port);
140 }
141
142 struct plat_sci_reg {
143 u8 offset, size;
144 };
145
146 /* Helper for invalidating specific entries of an inherited map. */
147 #define sci_reg_invalid { .offset = 0, .size = 0 }
148
149 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
150 [SCIx_PROBE_REGTYPE] = {
151 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
152 },
153
154 /*
155 * Common SCI definitions, dependent on the port's regshift
156 * value.
157 */
158 [SCIx_SCI_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = sci_reg_invalid,
166 [SCFDR] = sci_reg_invalid,
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 [HSSRR] = sci_reg_invalid,
172 [SCPCR] = sci_reg_invalid,
173 [SCPDR] = sci_reg_invalid,
174 },
175
176 /*
177 * Common definitions for legacy IrDA ports, dependent on
178 * regshift value.
179 */
180 [SCIx_IRDA_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 [SCFCR] = { 0x06, 8 },
188 [SCFDR] = { 0x07, 16 },
189 [SCTFDR] = sci_reg_invalid,
190 [SCRFDR] = sci_reg_invalid,
191 [SCSPTR] = sci_reg_invalid,
192 [SCLSR] = sci_reg_invalid,
193 [HSSRR] = sci_reg_invalid,
194 [SCPCR] = sci_reg_invalid,
195 [SCPDR] = sci_reg_invalid,
196 },
197
198 /*
199 * Common SCIFA definitions.
200 */
201 [SCIx_SCIFA_REGTYPE] = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x20, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x24, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCFDR] = { 0x1c, 16 },
210 [SCTFDR] = sci_reg_invalid,
211 [SCRFDR] = sci_reg_invalid,
212 [SCSPTR] = sci_reg_invalid,
213 [SCLSR] = sci_reg_invalid,
214 [HSSRR] = sci_reg_invalid,
215 [SCPCR] = { 0x30, 16 },
216 [SCPDR] = { 0x34, 16 },
217 },
218
219 /*
220 * Common SCIFB definitions.
221 */
222 [SCIx_SCIFB_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x40, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x60, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = sci_reg_invalid,
231 [SCTFDR] = { 0x38, 16 },
232 [SCRFDR] = { 0x3c, 16 },
233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
235 [HSSRR] = sci_reg_invalid,
236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
238 },
239
240 /*
241 * Common SH-2(A) SCIF definitions for ports with FIFO data
242 * count registers.
243 */
244 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
245 [SCSMR] = { 0x00, 16 },
246 [SCBRR] = { 0x04, 8 },
247 [SCSCR] = { 0x08, 16 },
248 [SCxTDR] = { 0x0c, 8 },
249 [SCxSR] = { 0x10, 16 },
250 [SCxRDR] = { 0x14, 8 },
251 [SCFCR] = { 0x18, 16 },
252 [SCFDR] = { 0x1c, 16 },
253 [SCTFDR] = sci_reg_invalid,
254 [SCRFDR] = sci_reg_invalid,
255 [SCSPTR] = { 0x20, 16 },
256 [SCLSR] = { 0x24, 16 },
257 [HSSRR] = sci_reg_invalid,
258 [SCPCR] = sci_reg_invalid,
259 [SCPDR] = sci_reg_invalid,
260 },
261
262 /*
263 * Common SH-3 SCIF definitions.
264 */
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
278 [HSSRR] = sci_reg_invalid,
279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
281 },
282
283 /*
284 * Common SH-4(A) SCIF(B) definitions.
285 */
286 [SCIx_SH4_SCIF_REGTYPE] = {
287 [SCSMR] = { 0x00, 16 },
288 [SCBRR] = { 0x04, 8 },
289 [SCSCR] = { 0x08, 16 },
290 [SCxTDR] = { 0x0c, 8 },
291 [SCxSR] = { 0x10, 16 },
292 [SCxRDR] = { 0x14, 8 },
293 [SCFCR] = { 0x18, 16 },
294 [SCFDR] = { 0x1c, 16 },
295 [SCTFDR] = sci_reg_invalid,
296 [SCRFDR] = sci_reg_invalid,
297 [SCSPTR] = { 0x20, 16 },
298 [SCLSR] = { 0x24, 16 },
299 [HSSRR] = sci_reg_invalid,
300 [SCPCR] = sci_reg_invalid,
301 [SCPDR] = sci_reg_invalid,
302 },
303
304 /*
305 * Common HSCIF definitions.
306 */
307 [SCIx_HSCIF_REGTYPE] = {
308 [SCSMR] = { 0x00, 16 },
309 [SCBRR] = { 0x04, 8 },
310 [SCSCR] = { 0x08, 16 },
311 [SCxTDR] = { 0x0c, 8 },
312 [SCxSR] = { 0x10, 16 },
313 [SCxRDR] = { 0x14, 8 },
314 [SCFCR] = { 0x18, 16 },
315 [SCFDR] = { 0x1c, 16 },
316 [SCTFDR] = sci_reg_invalid,
317 [SCRFDR] = sci_reg_invalid,
318 [SCSPTR] = { 0x20, 16 },
319 [SCLSR] = { 0x24, 16 },
320 [HSSRR] = { 0x40, 16 },
321 [SCPCR] = sci_reg_invalid,
322 [SCPDR] = sci_reg_invalid,
323 },
324
325 /*
326 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
327 * register.
328 */
329 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
330 [SCSMR] = { 0x00, 16 },
331 [SCBRR] = { 0x04, 8 },
332 [SCSCR] = { 0x08, 16 },
333 [SCxTDR] = { 0x0c, 8 },
334 [SCxSR] = { 0x10, 16 },
335 [SCxRDR] = { 0x14, 8 },
336 [SCFCR] = { 0x18, 16 },
337 [SCFDR] = { 0x1c, 16 },
338 [SCTFDR] = sci_reg_invalid,
339 [SCRFDR] = sci_reg_invalid,
340 [SCSPTR] = sci_reg_invalid,
341 [SCLSR] = { 0x24, 16 },
342 [HSSRR] = sci_reg_invalid,
343 [SCPCR] = sci_reg_invalid,
344 [SCPDR] = sci_reg_invalid,
345 },
346
347 /*
348 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
349 * count registers.
350 */
351 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x0c, 8 },
356 [SCxSR] = { 0x10, 16 },
357 [SCxRDR] = { 0x14, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
361 [SCRFDR] = { 0x20, 16 },
362 [SCSPTR] = { 0x24, 16 },
363 [SCLSR] = { 0x28, 16 },
364 [HSSRR] = sci_reg_invalid,
365 [SCPCR] = sci_reg_invalid,
366 [SCPDR] = sci_reg_invalid,
367 },
368
369 /*
370 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
371 * registers.
372 */
373 [SCIx_SH7705_SCIF_REGTYPE] = {
374 [SCSMR] = { 0x00, 16 },
375 [SCBRR] = { 0x04, 8 },
376 [SCSCR] = { 0x08, 16 },
377 [SCxTDR] = { 0x20, 8 },
378 [SCxSR] = { 0x14, 16 },
379 [SCxRDR] = { 0x24, 8 },
380 [SCFCR] = { 0x18, 16 },
381 [SCFDR] = { 0x1c, 16 },
382 [SCTFDR] = sci_reg_invalid,
383 [SCRFDR] = sci_reg_invalid,
384 [SCSPTR] = sci_reg_invalid,
385 [SCLSR] = sci_reg_invalid,
386 [HSSRR] = sci_reg_invalid,
387 [SCPCR] = sci_reg_invalid,
388 [SCPDR] = sci_reg_invalid,
389 },
390 };
391
392 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
393
394 /*
395 * The "offset" here is rather misleading, in that it refers to an enum
396 * value relative to the port mapping rather than the fixed offset
397 * itself, which needs to be manually retrieved from the platform's
398 * register map for the given port.
399 */
400 static unsigned int sci_serial_in(struct uart_port *p, int offset)
401 {
402 const struct plat_sci_reg *reg = sci_getreg(p, offset);
403
404 if (reg->size == 8)
405 return ioread8(p->membase + (reg->offset << p->regshift));
406 else if (reg->size == 16)
407 return ioread16(p->membase + (reg->offset << p->regshift));
408 else
409 WARN(1, "Invalid register access\n");
410
411 return 0;
412 }
413
414 static void sci_serial_out(struct uart_port *p, int offset, int value)
415 {
416 const struct plat_sci_reg *reg = sci_getreg(p, offset);
417
418 if (reg->size == 8)
419 iowrite8(value, p->membase + (reg->offset << p->regshift));
420 else if (reg->size == 16)
421 iowrite16(value, p->membase + (reg->offset << p->regshift));
422 else
423 WARN(1, "Invalid register access\n");
424 }
425
426 static int sci_probe_regmap(struct plat_sci_port *cfg)
427 {
428 switch (cfg->type) {
429 case PORT_SCI:
430 cfg->regtype = SCIx_SCI_REGTYPE;
431 break;
432 case PORT_IRDA:
433 cfg->regtype = SCIx_IRDA_REGTYPE;
434 break;
435 case PORT_SCIFA:
436 cfg->regtype = SCIx_SCIFA_REGTYPE;
437 break;
438 case PORT_SCIFB:
439 cfg->regtype = SCIx_SCIFB_REGTYPE;
440 break;
441 case PORT_SCIF:
442 /*
443 * The SH-4 is a bit of a misnomer here, although that's
444 * where this particular port layout originated. This
445 * configuration (or some slight variation thereof)
446 * remains the dominant model for all SCIFs.
447 */
448 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
449 break;
450 case PORT_HSCIF:
451 cfg->regtype = SCIx_HSCIF_REGTYPE;
452 break;
453 default:
454 pr_err("Can't probe register map for given port\n");
455 return -EINVAL;
456 }
457
458 return 0;
459 }
460
461 static void sci_port_enable(struct sci_port *sci_port)
462 {
463 if (!sci_port->port.dev)
464 return;
465
466 pm_runtime_get_sync(sci_port->port.dev);
467
468 clk_prepare_enable(sci_port->iclk);
469 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
470 clk_prepare_enable(sci_port->fclk);
471 }
472
473 static void sci_port_disable(struct sci_port *sci_port)
474 {
475 if (!sci_port->port.dev)
476 return;
477
478 /* Cancel the break timer to ensure that the timer handler will not try
479 * to access the hardware with clocks and power disabled. Reset the
480 * break flag to make the break debouncing state machine ready for the
481 * next break.
482 */
483 del_timer_sync(&sci_port->break_timer);
484 sci_port->break_flag = 0;
485
486 clk_disable_unprepare(sci_port->fclk);
487 clk_disable_unprepare(sci_port->iclk);
488
489 pm_runtime_put_sync(sci_port->port.dev);
490 }
491
492 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
493 {
494 if (port->type == PORT_SCI) {
495 /* Just store the mask */
496 serial_port_out(port, SCxSR, mask);
497 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
498 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
499 /* Only clear the status bits we want to clear */
500 serial_port_out(port, SCxSR,
501 serial_port_in(port, SCxSR) & mask);
502 } else {
503 /* Store the mask, clear parity/framing errors */
504 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
505 }
506 }
507
508 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
509
510 #ifdef CONFIG_CONSOLE_POLL
511 static int sci_poll_get_char(struct uart_port *port)
512 {
513 unsigned short status;
514 int c;
515
516 do {
517 status = serial_port_in(port, SCxSR);
518 if (status & SCxSR_ERRORS(port)) {
519 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
520 continue;
521 }
522 break;
523 } while (1);
524
525 if (!(status & SCxSR_RDxF(port)))
526 return NO_POLL_CHAR;
527
528 c = serial_port_in(port, SCxRDR);
529
530 /* Dummy read */
531 serial_port_in(port, SCxSR);
532 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
533
534 return c;
535 }
536 #endif
537
538 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
539 {
540 unsigned short status;
541
542 do {
543 status = serial_port_in(port, SCxSR);
544 } while (!(status & SCxSR_TDxE(port)));
545
546 serial_port_out(port, SCxTDR, c);
547 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
548 }
549 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
550
551 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
552 {
553 struct sci_port *s = to_sci_port(port);
554 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
555
556 /*
557 * Use port-specific handler if provided.
558 */
559 if (s->cfg->ops && s->cfg->ops->init_pins) {
560 s->cfg->ops->init_pins(port, cflag);
561 return;
562 }
563
564 /*
565 * For the generic path SCSPTR is necessary. Bail out if that's
566 * unavailable, too.
567 */
568 if (!reg->size)
569 return;
570
571 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
572 ((!(cflag & CRTSCTS)))) {
573 unsigned short status;
574
575 status = serial_port_in(port, SCSPTR);
576 status &= ~SCSPTR_CTSIO;
577 status |= SCSPTR_RTSIO;
578 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
579 }
580 }
581
582 static int sci_txfill(struct uart_port *port)
583 {
584 const struct plat_sci_reg *reg;
585
586 reg = sci_getreg(port, SCTFDR);
587 if (reg->size)
588 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
589
590 reg = sci_getreg(port, SCFDR);
591 if (reg->size)
592 return serial_port_in(port, SCFDR) >> 8;
593
594 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
595 }
596
597 static int sci_txroom(struct uart_port *port)
598 {
599 return port->fifosize - sci_txfill(port);
600 }
601
602 static int sci_rxfill(struct uart_port *port)
603 {
604 const struct plat_sci_reg *reg;
605
606 reg = sci_getreg(port, SCRFDR);
607 if (reg->size)
608 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
609
610 reg = sci_getreg(port, SCFDR);
611 if (reg->size)
612 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
613
614 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
615 }
616
617 /*
618 * SCI helper for checking the state of the muxed port/RXD pins.
619 */
620 static inline int sci_rxd_in(struct uart_port *port)
621 {
622 struct sci_port *s = to_sci_port(port);
623
624 if (s->cfg->port_reg <= 0)
625 return 1;
626
627 /* Cast for ARM damage */
628 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
629 }
630
631 /* ********************************************************************** *
632 * the interrupt related routines *
633 * ********************************************************************** */
634
635 static void sci_transmit_chars(struct uart_port *port)
636 {
637 struct circ_buf *xmit = &port->state->xmit;
638 unsigned int stopped = uart_tx_stopped(port);
639 unsigned short status;
640 unsigned short ctrl;
641 int count;
642
643 status = serial_port_in(port, SCxSR);
644 if (!(status & SCxSR_TDxE(port))) {
645 ctrl = serial_port_in(port, SCSCR);
646 if (uart_circ_empty(xmit))
647 ctrl &= ~SCSCR_TIE;
648 else
649 ctrl |= SCSCR_TIE;
650 serial_port_out(port, SCSCR, ctrl);
651 return;
652 }
653
654 count = sci_txroom(port);
655
656 do {
657 unsigned char c;
658
659 if (port->x_char) {
660 c = port->x_char;
661 port->x_char = 0;
662 } else if (!uart_circ_empty(xmit) && !stopped) {
663 c = xmit->buf[xmit->tail];
664 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
665 } else {
666 break;
667 }
668
669 serial_port_out(port, SCxTDR, c);
670
671 port->icount.tx++;
672 } while (--count > 0);
673
674 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
675
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(port);
678 if (uart_circ_empty(xmit)) {
679 sci_stop_tx(port);
680 } else {
681 ctrl = serial_port_in(port, SCSCR);
682
683 if (port->type != PORT_SCI) {
684 serial_port_in(port, SCxSR); /* Dummy read */
685 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
686 }
687
688 ctrl |= SCSCR_TIE;
689 serial_port_out(port, SCSCR, ctrl);
690 }
691 }
692
693 /* On SH3, SCIF may read end-of-break as a space->mark char */
694 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
695
696 static void sci_receive_chars(struct uart_port *port)
697 {
698 struct sci_port *sci_port = to_sci_port(port);
699 struct tty_port *tport = &port->state->port;
700 int i, count, copied = 0;
701 unsigned short status;
702 unsigned char flag;
703
704 status = serial_port_in(port, SCxSR);
705 if (!(status & SCxSR_RDxF(port)))
706 return;
707
708 while (1) {
709 /* Don't copy more bytes than there is room for in the buffer */
710 count = tty_buffer_request_room(tport, sci_rxfill(port));
711
712 /* If for any reason we can't copy more data, we're done! */
713 if (count == 0)
714 break;
715
716 if (port->type == PORT_SCI) {
717 char c = serial_port_in(port, SCxRDR);
718 if (uart_handle_sysrq_char(port, c) ||
719 sci_port->break_flag)
720 count = 0;
721 else
722 tty_insert_flip_char(tport, c, TTY_NORMAL);
723 } else {
724 for (i = 0; i < count; i++) {
725 char c = serial_port_in(port, SCxRDR);
726
727 status = serial_port_in(port, SCxSR);
728 #if defined(CONFIG_CPU_SH3)
729 /* Skip "chars" during break */
730 if (sci_port->break_flag) {
731 if ((c == 0) &&
732 (status & SCxSR_FER(port))) {
733 count--; i--;
734 continue;
735 }
736
737 /* Nonzero => end-of-break */
738 dev_dbg(port->dev, "debounce<%02x>\n", c);
739 sci_port->break_flag = 0;
740
741 if (STEPFN(c)) {
742 count--; i--;
743 continue;
744 }
745 }
746 #endif /* CONFIG_CPU_SH3 */
747 if (uart_handle_sysrq_char(port, c)) {
748 count--; i--;
749 continue;
750 }
751
752 /* Store data and status */
753 if (status & SCxSR_FER(port)) {
754 flag = TTY_FRAME;
755 port->icount.frame++;
756 dev_notice(port->dev, "frame error\n");
757 } else if (status & SCxSR_PER(port)) {
758 flag = TTY_PARITY;
759 port->icount.parity++;
760 dev_notice(port->dev, "parity error\n");
761 } else
762 flag = TTY_NORMAL;
763
764 tty_insert_flip_char(tport, c, flag);
765 }
766 }
767
768 serial_port_in(port, SCxSR); /* dummy read */
769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
770
771 copied += count;
772 port->icount.rx += count;
773 }
774
775 if (copied) {
776 /* Tell the rest of the system the news. New characters! */
777 tty_flip_buffer_push(tport);
778 } else {
779 serial_port_in(port, SCxSR); /* dummy read */
780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
781 }
782 }
783
784 #define SCI_BREAK_JIFFIES (HZ/20)
785
786 /*
787 * The sci generates interrupts during the break,
788 * 1 per millisecond or so during the break period, for 9600 baud.
789 * So dont bother disabling interrupts.
790 * But dont want more than 1 break event.
791 * Use a kernel timer to periodically poll the rx line until
792 * the break is finished.
793 */
794 static inline void sci_schedule_break_timer(struct sci_port *port)
795 {
796 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
797 }
798
799 /* Ensure that two consecutive samples find the break over. */
800 static void sci_break_timer(unsigned long data)
801 {
802 struct sci_port *port = (struct sci_port *)data;
803
804 if (sci_rxd_in(&port->port) == 0) {
805 port->break_flag = 1;
806 sci_schedule_break_timer(port);
807 } else if (port->break_flag == 1) {
808 /* break is over. */
809 port->break_flag = 2;
810 sci_schedule_break_timer(port);
811 } else
812 port->break_flag = 0;
813 }
814
815 static int sci_handle_errors(struct uart_port *port)
816 {
817 int copied = 0;
818 unsigned short status = serial_port_in(port, SCxSR);
819 struct tty_port *tport = &port->state->port;
820 struct sci_port *s = to_sci_port(port);
821
822 /* Handle overruns */
823 if (status & s->overrun_mask) {
824 port->icount.overrun++;
825
826 /* overrun error */
827 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
828 copied++;
829
830 dev_notice(port->dev, "overrun error\n");
831 }
832
833 if (status & SCxSR_FER(port)) {
834 if (sci_rxd_in(port) == 0) {
835 /* Notify of BREAK */
836 struct sci_port *sci_port = to_sci_port(port);
837
838 if (!sci_port->break_flag) {
839 port->icount.brk++;
840
841 sci_port->break_flag = 1;
842 sci_schedule_break_timer(sci_port);
843
844 /* Do sysrq handling. */
845 if (uart_handle_break(port))
846 return 0;
847
848 dev_dbg(port->dev, "BREAK detected\n");
849
850 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
851 copied++;
852 }
853
854 } else {
855 /* frame error */
856 port->icount.frame++;
857
858 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
859 copied++;
860
861 dev_notice(port->dev, "frame error\n");
862 }
863 }
864
865 if (status & SCxSR_PER(port)) {
866 /* parity error */
867 port->icount.parity++;
868
869 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
870 copied++;
871
872 dev_notice(port->dev, "parity error\n");
873 }
874
875 if (copied)
876 tty_flip_buffer_push(tport);
877
878 return copied;
879 }
880
881 static int sci_handle_fifo_overrun(struct uart_port *port)
882 {
883 struct tty_port *tport = &port->state->port;
884 struct sci_port *s = to_sci_port(port);
885 const struct plat_sci_reg *reg;
886 int copied = 0;
887 u16 status;
888
889 reg = sci_getreg(port, s->overrun_reg);
890 if (!reg->size)
891 return 0;
892
893 status = serial_port_in(port, s->overrun_reg);
894 if (status & s->overrun_mask) {
895 status &= ~s->overrun_mask;
896 serial_port_out(port, s->overrun_reg, status);
897
898 port->icount.overrun++;
899
900 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
901 tty_flip_buffer_push(tport);
902
903 dev_dbg(port->dev, "overrun error\n");
904 copied++;
905 }
906
907 return copied;
908 }
909
910 static int sci_handle_breaks(struct uart_port *port)
911 {
912 int copied = 0;
913 unsigned short status = serial_port_in(port, SCxSR);
914 struct tty_port *tport = &port->state->port;
915 struct sci_port *s = to_sci_port(port);
916
917 if (uart_handle_break(port))
918 return 0;
919
920 if (!s->break_flag && status & SCxSR_BRK(port)) {
921 #if defined(CONFIG_CPU_SH3)
922 /* Debounce break */
923 s->break_flag = 1;
924 #endif
925
926 port->icount.brk++;
927
928 /* Notify of BREAK */
929 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
930 copied++;
931
932 dev_dbg(port->dev, "BREAK detected\n");
933 }
934
935 if (copied)
936 tty_flip_buffer_push(tport);
937
938 copied += sci_handle_fifo_overrun(port);
939
940 return copied;
941 }
942
943 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
944 {
945 #ifdef CONFIG_SERIAL_SH_SCI_DMA
946 struct uart_port *port = ptr;
947 struct sci_port *s = to_sci_port(port);
948
949 if (s->chan_rx) {
950 u16 scr = serial_port_in(port, SCSCR);
951 u16 ssr = serial_port_in(port, SCxSR);
952
953 /* Disable future Rx interrupts */
954 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
955 disable_irq_nosync(irq);
956 scr |= SCSCR_RDRQE;
957 } else {
958 scr &= ~SCSCR_RIE;
959 }
960 serial_port_out(port, SCSCR, scr);
961 /* Clear current interrupt */
962 serial_port_out(port, SCxSR,
963 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
964 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
965 jiffies, s->rx_timeout);
966 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
967
968 return IRQ_HANDLED;
969 }
970 #endif
971
972 /* I think sci_receive_chars has to be called irrespective
973 * of whether the I_IXOFF is set, otherwise, how is the interrupt
974 * to be disabled?
975 */
976 sci_receive_chars(ptr);
977
978 return IRQ_HANDLED;
979 }
980
981 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
982 {
983 struct uart_port *port = ptr;
984 unsigned long flags;
985
986 spin_lock_irqsave(&port->lock, flags);
987 sci_transmit_chars(port);
988 spin_unlock_irqrestore(&port->lock, flags);
989
990 return IRQ_HANDLED;
991 }
992
993 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
994 {
995 struct uart_port *port = ptr;
996
997 /* Handle errors */
998 if (port->type == PORT_SCI) {
999 if (sci_handle_errors(port)) {
1000 /* discard character in rx buffer */
1001 serial_port_in(port, SCxSR);
1002 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1003 }
1004 } else {
1005 sci_handle_fifo_overrun(port);
1006 sci_rx_interrupt(irq, ptr);
1007 }
1008
1009 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1010
1011 /* Kick the transmission */
1012 sci_tx_interrupt(irq, ptr);
1013
1014 return IRQ_HANDLED;
1015 }
1016
1017 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1018 {
1019 struct uart_port *port = ptr;
1020
1021 /* Handle BREAKs */
1022 sci_handle_breaks(port);
1023 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1024
1025 return IRQ_HANDLED;
1026 }
1027
1028 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1029 {
1030 /*
1031 * Not all ports (such as SCIFA) will support REIE. Rather than
1032 * special-casing the port type, we check the port initialization
1033 * IRQ enable mask to see whether the IRQ is desired at all. If
1034 * it's unset, it's logically inferred that there's no point in
1035 * testing for it.
1036 */
1037 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1038 }
1039
1040 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1041 {
1042 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1043 struct uart_port *port = ptr;
1044 struct sci_port *s = to_sci_port(port);
1045 irqreturn_t ret = IRQ_NONE;
1046
1047 ssr_status = serial_port_in(port, SCxSR);
1048 scr_status = serial_port_in(port, SCSCR);
1049 if (s->overrun_reg == SCxSR)
1050 orer_status = ssr_status;
1051 else {
1052 if (sci_getreg(port, s->overrun_reg)->size)
1053 orer_status = serial_port_in(port, s->overrun_reg);
1054 }
1055
1056 err_enabled = scr_status & port_rx_irq_mask(port);
1057
1058 /* Tx Interrupt */
1059 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1060 !s->chan_tx)
1061 ret = sci_tx_interrupt(irq, ptr);
1062
1063 /*
1064 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1065 * DR flags
1066 */
1067 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1068 (scr_status & SCSCR_RIE))
1069 ret = sci_rx_interrupt(irq, ptr);
1070
1071 /* Error Interrupt */
1072 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1073 ret = sci_er_interrupt(irq, ptr);
1074
1075 /* Break Interrupt */
1076 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1077 ret = sci_br_interrupt(irq, ptr);
1078
1079 /* Overrun Interrupt */
1080 if (orer_status & s->overrun_mask) {
1081 sci_handle_fifo_overrun(port);
1082 ret = IRQ_HANDLED;
1083 }
1084
1085 return ret;
1086 }
1087
1088 /*
1089 * Here we define a transition notifier so that we can update all of our
1090 * ports' baud rate when the peripheral clock changes.
1091 */
1092 static int sci_notifier(struct notifier_block *self,
1093 unsigned long phase, void *p)
1094 {
1095 struct sci_port *sci_port;
1096 unsigned long flags;
1097
1098 sci_port = container_of(self, struct sci_port, freq_transition);
1099
1100 if (phase == CPUFREQ_POSTCHANGE) {
1101 struct uart_port *port = &sci_port->port;
1102
1103 spin_lock_irqsave(&port->lock, flags);
1104 port->uartclk = clk_get_rate(sci_port->iclk);
1105 spin_unlock_irqrestore(&port->lock, flags);
1106 }
1107
1108 return NOTIFY_OK;
1109 }
1110
1111 static const struct sci_irq_desc {
1112 const char *desc;
1113 irq_handler_t handler;
1114 } sci_irq_desc[] = {
1115 /*
1116 * Split out handlers, the default case.
1117 */
1118 [SCIx_ERI_IRQ] = {
1119 .desc = "rx err",
1120 .handler = sci_er_interrupt,
1121 },
1122
1123 [SCIx_RXI_IRQ] = {
1124 .desc = "rx full",
1125 .handler = sci_rx_interrupt,
1126 },
1127
1128 [SCIx_TXI_IRQ] = {
1129 .desc = "tx empty",
1130 .handler = sci_tx_interrupt,
1131 },
1132
1133 [SCIx_BRI_IRQ] = {
1134 .desc = "break",
1135 .handler = sci_br_interrupt,
1136 },
1137
1138 /*
1139 * Special muxed handler.
1140 */
1141 [SCIx_MUX_IRQ] = {
1142 .desc = "mux",
1143 .handler = sci_mpxed_interrupt,
1144 },
1145 };
1146
1147 static int sci_request_irq(struct sci_port *port)
1148 {
1149 struct uart_port *up = &port->port;
1150 int i, j, ret = 0;
1151
1152 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1153 const struct sci_irq_desc *desc;
1154 int irq;
1155
1156 if (SCIx_IRQ_IS_MUXED(port)) {
1157 i = SCIx_MUX_IRQ;
1158 irq = up->irq;
1159 } else {
1160 irq = port->irqs[i];
1161
1162 /*
1163 * Certain port types won't support all of the
1164 * available interrupt sources.
1165 */
1166 if (unlikely(irq < 0))
1167 continue;
1168 }
1169
1170 desc = sci_irq_desc + i;
1171 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1172 dev_name(up->dev), desc->desc);
1173 if (!port->irqstr[j])
1174 goto out_nomem;
1175
1176 ret = request_irq(irq, desc->handler, up->irqflags,
1177 port->irqstr[j], port);
1178 if (unlikely(ret)) {
1179 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1180 goto out_noirq;
1181 }
1182 }
1183
1184 return 0;
1185
1186 out_noirq:
1187 while (--i >= 0)
1188 free_irq(port->irqs[i], port);
1189
1190 out_nomem:
1191 while (--j >= 0)
1192 kfree(port->irqstr[j]);
1193
1194 return ret;
1195 }
1196
1197 static void sci_free_irq(struct sci_port *port)
1198 {
1199 int i;
1200
1201 /*
1202 * Intentionally in reverse order so we iterate over the muxed
1203 * IRQ first.
1204 */
1205 for (i = 0; i < SCIx_NR_IRQS; i++) {
1206 int irq = port->irqs[i];
1207
1208 /*
1209 * Certain port types won't support all of the available
1210 * interrupt sources.
1211 */
1212 if (unlikely(irq < 0))
1213 continue;
1214
1215 free_irq(port->irqs[i], port);
1216 kfree(port->irqstr[i]);
1217
1218 if (SCIx_IRQ_IS_MUXED(port)) {
1219 /* If there's only one IRQ, we're done. */
1220 return;
1221 }
1222 }
1223 }
1224
1225 static unsigned int sci_tx_empty(struct uart_port *port)
1226 {
1227 unsigned short status = serial_port_in(port, SCxSR);
1228 unsigned short in_tx_fifo = sci_txfill(port);
1229
1230 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1231 }
1232
1233 /*
1234 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1235 * CTS/RTS is supported in hardware by at least one port and controlled
1236 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1237 * handled via the ->init_pins() op, which is a bit of a one-way street,
1238 * lacking any ability to defer pin control -- this will later be
1239 * converted over to the GPIO framework).
1240 *
1241 * Other modes (such as loopback) are supported generically on certain
1242 * port types, but not others. For these it's sufficient to test for the
1243 * existence of the support register and simply ignore the port type.
1244 */
1245 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1246 {
1247 if (mctrl & TIOCM_LOOP) {
1248 const struct plat_sci_reg *reg;
1249
1250 /*
1251 * Standard loopback mode for SCFCR ports.
1252 */
1253 reg = sci_getreg(port, SCFCR);
1254 if (reg->size)
1255 serial_port_out(port, SCFCR,
1256 serial_port_in(port, SCFCR) |
1257 SCFCR_LOOP);
1258 }
1259 }
1260
1261 static unsigned int sci_get_mctrl(struct uart_port *port)
1262 {
1263 /*
1264 * CTS/RTS is handled in hardware when supported, while nothing
1265 * else is wired up. Keep it simple and simply assert DSR/CAR.
1266 */
1267 return TIOCM_DSR | TIOCM_CAR;
1268 }
1269
1270 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1271 static void sci_dma_tx_complete(void *arg)
1272 {
1273 struct sci_port *s = arg;
1274 struct uart_port *port = &s->port;
1275 struct circ_buf *xmit = &port->state->xmit;
1276 unsigned long flags;
1277
1278 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1279
1280 spin_lock_irqsave(&port->lock, flags);
1281
1282 xmit->tail += s->tx_dma_len;
1283 xmit->tail &= UART_XMIT_SIZE - 1;
1284
1285 port->icount.tx += s->tx_dma_len;
1286
1287 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1288 uart_write_wakeup(port);
1289
1290 if (!uart_circ_empty(xmit)) {
1291 s->cookie_tx = 0;
1292 schedule_work(&s->work_tx);
1293 } else {
1294 s->cookie_tx = -EINVAL;
1295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1296 u16 ctrl = serial_port_in(port, SCSCR);
1297 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1298 }
1299 }
1300
1301 spin_unlock_irqrestore(&port->lock, flags);
1302 }
1303
1304 /* Locking: called with port lock held */
1305 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1306 {
1307 struct uart_port *port = &s->port;
1308 struct tty_port *tport = &port->state->port;
1309 int i, active, room;
1310
1311 room = tty_buffer_request_room(tport, count);
1312
1313 if (s->active_rx == s->cookie_rx[0]) {
1314 active = 0;
1315 } else if (s->active_rx == s->cookie_rx[1]) {
1316 active = 1;
1317 } else {
1318 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1319 s->active_rx);
1320 return 0;
1321 }
1322
1323 if (room < count)
1324 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1325 count - room);
1326 if (!room)
1327 return room;
1328
1329 for (i = 0; i < room; i++)
1330 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1331 TTY_NORMAL);
1332
1333 port->icount.rx += room;
1334
1335 return room;
1336 }
1337
1338 static void sci_dma_rx_complete(void *arg)
1339 {
1340 struct sci_port *s = arg;
1341 struct uart_port *port = &s->port;
1342 unsigned long flags;
1343 int count;
1344
1345 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1346 s->active_rx);
1347
1348 spin_lock_irqsave(&port->lock, flags);
1349
1350 count = sci_dma_rx_push(s, s->buf_len_rx);
1351
1352 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1353
1354 spin_unlock_irqrestore(&port->lock, flags);
1355
1356 if (count)
1357 tty_flip_buffer_push(&port->state->port);
1358
1359 schedule_work(&s->work_rx);
1360 }
1361
1362 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1363 {
1364 struct dma_chan *chan = s->chan_rx;
1365 struct uart_port *port = &s->port;
1366
1367 s->chan_rx = NULL;
1368 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1369 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2,
1370 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1371 dma_release_channel(chan);
1372 if (enable_pio)
1373 sci_start_rx(port);
1374 }
1375
1376 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1377 {
1378 struct dma_chan *chan = s->chan_tx;
1379 struct uart_port *port = &s->port;
1380
1381 s->chan_tx = NULL;
1382 s->cookie_tx = -EINVAL;
1383 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1384 DMA_TO_DEVICE);
1385 dma_release_channel(chan);
1386 if (enable_pio)
1387 sci_start_tx(port);
1388 }
1389
1390 static void sci_submit_rx(struct sci_port *s)
1391 {
1392 struct dma_chan *chan = s->chan_rx;
1393 int i;
1394
1395 for (i = 0; i < 2; i++) {
1396 struct scatterlist *sg = &s->sg_rx[i];
1397 struct dma_async_tx_descriptor *desc;
1398
1399 desc = dmaengine_prep_slave_sg(chan,
1400 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1401
1402 if (desc) {
1403 s->desc_rx[i] = desc;
1404 desc->callback = sci_dma_rx_complete;
1405 desc->callback_param = s;
1406 s->cookie_rx[i] = dmaengine_submit(desc);
1407 }
1408
1409 if (!desc || dma_submit_error(s->cookie_rx[i])) {
1410 if (i) {
1411 async_tx_ack(s->desc_rx[0]);
1412 s->cookie_rx[0] = -EINVAL;
1413 }
1414 if (desc) {
1415 async_tx_ack(desc);
1416 s->cookie_rx[i] = -EINVAL;
1417 }
1418 dev_warn(s->port.dev,
1419 "Failed to re-start Rx DMA, using PIO\n");
1420 sci_rx_dma_release(s, true);
1421 return;
1422 }
1423 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1424 s->cookie_rx[i], i);
1425 }
1426
1427 s->active_rx = s->cookie_rx[0];
1428
1429 dma_async_issue_pending(chan);
1430 }
1431
1432 static void work_fn_rx(struct work_struct *work)
1433 {
1434 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1435 struct uart_port *port = &s->port;
1436 struct dma_async_tx_descriptor *desc;
1437 struct dma_tx_state state;
1438 enum dma_status status;
1439 int new;
1440
1441 if (s->active_rx == s->cookie_rx[0]) {
1442 new = 0;
1443 } else if (s->active_rx == s->cookie_rx[1]) {
1444 new = 1;
1445 } else {
1446 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1447 s->active_rx);
1448 return;
1449 }
1450 desc = s->desc_rx[new];
1451
1452 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1453 if (status != DMA_COMPLETE) {
1454 /* Handle incomplete DMA receive */
1455 struct dma_chan *chan = s->chan_rx;
1456 unsigned long flags;
1457 unsigned int read;
1458 int count;
1459
1460 dmaengine_terminate_all(chan);
1461 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1462 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1463 s->active_rx);
1464
1465 spin_lock_irqsave(&port->lock, flags);
1466 count = sci_dma_rx_push(s, read);
1467 spin_unlock_irqrestore(&port->lock, flags);
1468
1469 if (count)
1470 tty_flip_buffer_push(&port->state->port);
1471
1472 sci_submit_rx(s);
1473
1474 return;
1475 }
1476
1477 s->cookie_rx[new] = dmaengine_submit(desc);
1478 if (dma_submit_error(s->cookie_rx[new])) {
1479 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1480 sci_rx_dma_release(s, true);
1481 return;
1482 }
1483
1484 s->active_rx = s->cookie_rx[!new];
1485
1486 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1487 __func__, s->cookie_rx[new], new, s->active_rx);
1488 }
1489
1490 static void work_fn_tx(struct work_struct *work)
1491 {
1492 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1493 struct dma_async_tx_descriptor *desc;
1494 struct dma_chan *chan = s->chan_tx;
1495 struct uart_port *port = &s->port;
1496 struct circ_buf *xmit = &port->state->xmit;
1497 dma_addr_t buf;
1498
1499 /*
1500 * DMA is idle now.
1501 * Port xmit buffer is already mapped, and it is one page... Just adjust
1502 * offsets and lengths. Since it is a circular buffer, we have to
1503 * transmit till the end, and then the rest. Take the port lock to get a
1504 * consistent xmit buffer state.
1505 */
1506 spin_lock_irq(&port->lock);
1507 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1508 s->tx_dma_len = min_t(unsigned int,
1509 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1510 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1511 spin_unlock_irq(&port->lock);
1512
1513 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1514 DMA_MEM_TO_DEV,
1515 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1516 if (!desc) {
1517 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1518 /* switch to PIO */
1519 sci_tx_dma_release(s, true);
1520 return;
1521 }
1522
1523 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1524 DMA_TO_DEVICE);
1525
1526 spin_lock_irq(&port->lock);
1527 desc->callback = sci_dma_tx_complete;
1528 desc->callback_param = s;
1529 spin_unlock_irq(&port->lock);
1530 s->cookie_tx = dmaengine_submit(desc);
1531 if (dma_submit_error(s->cookie_tx)) {
1532 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1533 /* switch to PIO */
1534 sci_tx_dma_release(s, true);
1535 return;
1536 }
1537
1538 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1539 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1540
1541 dma_async_issue_pending(chan);
1542 }
1543 #endif
1544
1545 static void sci_start_tx(struct uart_port *port)
1546 {
1547 struct sci_port *s = to_sci_port(port);
1548 unsigned short ctrl;
1549
1550 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1551 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1552 u16 new, scr = serial_port_in(port, SCSCR);
1553 if (s->chan_tx)
1554 new = scr | SCSCR_TDRQE;
1555 else
1556 new = scr & ~SCSCR_TDRQE;
1557 if (new != scr)
1558 serial_port_out(port, SCSCR, new);
1559 }
1560
1561 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1562 dma_submit_error(s->cookie_tx)) {
1563 s->cookie_tx = 0;
1564 schedule_work(&s->work_tx);
1565 }
1566 #endif
1567
1568 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1569 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1570 ctrl = serial_port_in(port, SCSCR);
1571 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1572 }
1573 }
1574
1575 static void sci_stop_tx(struct uart_port *port)
1576 {
1577 unsigned short ctrl;
1578
1579 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1580 ctrl = serial_port_in(port, SCSCR);
1581
1582 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1583 ctrl &= ~SCSCR_TDRQE;
1584
1585 ctrl &= ~SCSCR_TIE;
1586
1587 serial_port_out(port, SCSCR, ctrl);
1588 }
1589
1590 static void sci_start_rx(struct uart_port *port)
1591 {
1592 unsigned short ctrl;
1593
1594 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1595
1596 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1597 ctrl &= ~SCSCR_RDRQE;
1598
1599 serial_port_out(port, SCSCR, ctrl);
1600 }
1601
1602 static void sci_stop_rx(struct uart_port *port)
1603 {
1604 unsigned short ctrl;
1605
1606 ctrl = serial_port_in(port, SCSCR);
1607
1608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1609 ctrl &= ~SCSCR_RDRQE;
1610
1611 ctrl &= ~port_rx_irq_mask(port);
1612
1613 serial_port_out(port, SCSCR, ctrl);
1614 }
1615
1616 static void sci_break_ctl(struct uart_port *port, int break_state)
1617 {
1618 struct sci_port *s = to_sci_port(port);
1619 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1620 unsigned short scscr, scsptr;
1621
1622 /* check wheter the port has SCSPTR */
1623 if (!reg->size) {
1624 /*
1625 * Not supported by hardware. Most parts couple break and rx
1626 * interrupts together, with break detection always enabled.
1627 */
1628 return;
1629 }
1630
1631 scsptr = serial_port_in(port, SCSPTR);
1632 scscr = serial_port_in(port, SCSCR);
1633
1634 if (break_state == -1) {
1635 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1636 scscr &= ~SCSCR_TE;
1637 } else {
1638 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1639 scscr |= SCSCR_TE;
1640 }
1641
1642 serial_port_out(port, SCSPTR, scsptr);
1643 serial_port_out(port, SCSCR, scscr);
1644 }
1645
1646 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1647 static bool filter(struct dma_chan *chan, void *slave)
1648 {
1649 struct sh_dmae_slave *param = slave;
1650
1651 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1652 __func__, param->shdma_slave.slave_id);
1653
1654 chan->private = &param->shdma_slave;
1655 return true;
1656 }
1657
1658 static void rx_timer_fn(unsigned long arg)
1659 {
1660 struct sci_port *s = (struct sci_port *)arg;
1661 struct uart_port *port = &s->port;
1662 u16 scr = serial_port_in(port, SCSCR);
1663
1664 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1665 scr &= ~SCSCR_RDRQE;
1666 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1667 }
1668 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1669 dev_dbg(port->dev, "DMA Rx timed out\n");
1670 schedule_work(&s->work_rx);
1671 }
1672
1673 static void sci_request_dma(struct uart_port *port)
1674 {
1675 struct sci_port *s = to_sci_port(port);
1676 struct sh_dmae_slave *param;
1677 struct dma_chan *chan;
1678 dma_cap_mask_t mask;
1679
1680 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1681
1682 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1683 return;
1684
1685 dma_cap_zero(mask);
1686 dma_cap_set(DMA_SLAVE, mask);
1687
1688 param = &s->param_tx;
1689
1690 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1691 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1692
1693 s->cookie_tx = -EINVAL;
1694 chan = dma_request_channel(mask, filter, param);
1695 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1696 if (chan) {
1697 s->chan_tx = chan;
1698 /* UART circular tx buffer is an aligned page. */
1699 s->tx_dma_addr = dma_map_single(chan->device->dev,
1700 port->state->xmit.buf,
1701 UART_XMIT_SIZE,
1702 DMA_TO_DEVICE);
1703 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1704 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1705 dma_release_channel(chan);
1706 s->chan_tx = NULL;
1707 } else {
1708 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1709 __func__, UART_XMIT_SIZE,
1710 port->state->xmit.buf, &s->tx_dma_addr);
1711 }
1712
1713 INIT_WORK(&s->work_tx, work_fn_tx);
1714 }
1715
1716 param = &s->param_rx;
1717
1718 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1719 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1720
1721 chan = dma_request_channel(mask, filter, param);
1722 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1723 if (chan) {
1724 dma_addr_t dma[2];
1725 void *buf[2];
1726 int i;
1727
1728 s->chan_rx = chan;
1729
1730 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1731 buf[0] = dma_alloc_coherent(chan->device->dev,
1732 s->buf_len_rx * 2, &dma[0],
1733 GFP_KERNEL);
1734
1735 if (!buf[0]) {
1736 dev_warn(port->dev,
1737 "Failed to allocate Rx dma buffer, using PIO\n");
1738 dma_release_channel(chan);
1739 s->chan_rx = NULL;
1740 sci_start_rx(port);
1741 return;
1742 }
1743
1744 buf[1] = buf[0] + s->buf_len_rx;
1745 dma[1] = dma[0] + s->buf_len_rx;
1746
1747 for (i = 0; i < 2; i++) {
1748 struct scatterlist *sg = &s->sg_rx[i];
1749
1750 sg_init_table(sg, 1);
1751 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1752 (uintptr_t)buf[i] & ~PAGE_MASK);
1753 sg_dma_address(sg) = dma[i];
1754 }
1755
1756 INIT_WORK(&s->work_rx, work_fn_rx);
1757 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1758
1759 sci_submit_rx(s);
1760 }
1761 }
1762
1763 static void sci_free_dma(struct uart_port *port)
1764 {
1765 struct sci_port *s = to_sci_port(port);
1766
1767 if (s->chan_tx)
1768 sci_tx_dma_release(s, false);
1769 if (s->chan_rx)
1770 sci_rx_dma_release(s, false);
1771 }
1772 #else
1773 static inline void sci_request_dma(struct uart_port *port)
1774 {
1775 }
1776
1777 static inline void sci_free_dma(struct uart_port *port)
1778 {
1779 }
1780 #endif
1781
1782 static int sci_startup(struct uart_port *port)
1783 {
1784 struct sci_port *s = to_sci_port(port);
1785 unsigned long flags;
1786 int ret;
1787
1788 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1789
1790 ret = sci_request_irq(s);
1791 if (unlikely(ret < 0))
1792 return ret;
1793
1794 sci_request_dma(port);
1795
1796 spin_lock_irqsave(&port->lock, flags);
1797 sci_start_tx(port);
1798 sci_start_rx(port);
1799 spin_unlock_irqrestore(&port->lock, flags);
1800
1801 return 0;
1802 }
1803
1804 static void sci_shutdown(struct uart_port *port)
1805 {
1806 struct sci_port *s = to_sci_port(port);
1807 unsigned long flags;
1808
1809 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1810
1811 spin_lock_irqsave(&port->lock, flags);
1812 sci_stop_rx(port);
1813 sci_stop_tx(port);
1814 spin_unlock_irqrestore(&port->lock, flags);
1815
1816 sci_free_dma(port);
1817 sci_free_irq(s);
1818 }
1819
1820 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1821 unsigned long freq)
1822 {
1823 if (s->sampling_rate)
1824 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1825
1826 /* Warn, but use a safe default */
1827 WARN_ON(1);
1828
1829 return ((freq + 16 * bps) / (32 * bps) - 1);
1830 }
1831
1832 /* calculate frame length from SMR */
1833 static int sci_baud_calc_frame_len(unsigned int smr_val)
1834 {
1835 int len = 10;
1836
1837 if (smr_val & SCSMR_CHR)
1838 len--;
1839 if (smr_val & SCSMR_PE)
1840 len++;
1841 if (smr_val & SCSMR_STOP)
1842 len++;
1843
1844 return len;
1845 }
1846
1847
1848 /* calculate sample rate, BRR, and clock select for HSCIF */
1849 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1850 int *brr, unsigned int *srr,
1851 unsigned int *cks, int frame_len)
1852 {
1853 int sr, c, br, err, recv_margin;
1854 int min_err = 1000; /* 100% */
1855 int recv_max_margin = 0;
1856
1857 /* Find the combination of sample rate and clock select with the
1858 smallest deviation from the desired baud rate. */
1859 for (sr = 8; sr <= 32; sr++) {
1860 for (c = 0; c <= 3; c++) {
1861 /* integerized formulas from HSCIF documentation */
1862 br = DIV_ROUND_CLOSEST(freq, (sr *
1863 (1 << (2 * c + 1)) * bps)) - 1;
1864 br = clamp(br, 0, 255);
1865 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1866 (1 << (2 * c + 1)) / 1000)) -
1867 1000;
1868 /* Calc recv margin
1869 * M: Receive margin (%)
1870 * N: Ratio of bit rate to clock (N = sampling rate)
1871 * D: Clock duty (D = 0 to 1.0)
1872 * L: Frame length (L = 9 to 12)
1873 * F: Absolute value of clock frequency deviation
1874 *
1875 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1876 * (|D - 0.5| / N * (1 + F))|
1877 * NOTE: Usually, treat D for 0.5, F is 0 by this
1878 * calculation.
1879 */
1880 recv_margin = abs((500 -
1881 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1882 if (abs(min_err) > abs(err)) {
1883 min_err = err;
1884 recv_max_margin = recv_margin;
1885 } else if ((min_err == err) &&
1886 (recv_margin > recv_max_margin))
1887 recv_max_margin = recv_margin;
1888 else
1889 continue;
1890
1891 *brr = br;
1892 *srr = sr - 1;
1893 *cks = c;
1894 }
1895 }
1896
1897 if (min_err == 1000) {
1898 WARN_ON(1);
1899 /* use defaults */
1900 *brr = 255;
1901 *srr = 15;
1902 *cks = 0;
1903 }
1904 }
1905
1906 static void sci_reset(struct uart_port *port)
1907 {
1908 const struct plat_sci_reg *reg;
1909 unsigned int status;
1910
1911 do {
1912 status = serial_port_in(port, SCxSR);
1913 } while (!(status & SCxSR_TEND(port)));
1914
1915 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1916
1917 reg = sci_getreg(port, SCFCR);
1918 if (reg->size)
1919 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1920 }
1921
1922 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1923 struct ktermios *old)
1924 {
1925 struct sci_port *s = to_sci_port(port);
1926 const struct plat_sci_reg *reg;
1927 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1928 int t = -1;
1929 unsigned int srr = 15;
1930
1931 if ((termios->c_cflag & CSIZE) == CS7)
1932 smr_val |= SCSMR_CHR;
1933 if (termios->c_cflag & PARENB)
1934 smr_val |= SCSMR_PE;
1935 if (termios->c_cflag & PARODD)
1936 smr_val |= SCSMR_PE | SCSMR_ODD;
1937 if (termios->c_cflag & CSTOPB)
1938 smr_val |= SCSMR_STOP;
1939
1940 /*
1941 * earlyprintk comes here early on with port->uartclk set to zero.
1942 * the clock framework is not up and running at this point so here
1943 * we assume that 115200 is the maximum baud rate. please note that
1944 * the baud rate is not programmed during earlyprintk - it is assumed
1945 * that the previous boot loader has enabled required clocks and
1946 * setup the baud rate generator hardware for us already.
1947 */
1948 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1949
1950 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1951 if (likely(baud && port->uartclk)) {
1952 if (s->cfg->type == PORT_HSCIF) {
1953 int frame_len = sci_baud_calc_frame_len(smr_val);
1954 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1955 &cks, frame_len);
1956 } else {
1957 t = sci_scbrr_calc(s, baud, port->uartclk);
1958 for (cks = 0; t >= 256 && cks <= 3; cks++)
1959 t >>= 2;
1960 }
1961 }
1962
1963 sci_port_enable(s);
1964
1965 sci_reset(port);
1966
1967 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1968
1969 uart_update_timeout(port, termios->c_cflag, baud);
1970
1971 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1972 __func__, smr_val, cks, t, s->cfg->scscr);
1973
1974 if (t >= 0) {
1975 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1976 serial_port_out(port, SCBRR, t);
1977 reg = sci_getreg(port, HSSRR);
1978 if (reg->size)
1979 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1980 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1981 } else
1982 serial_port_out(port, SCSMR, smr_val);
1983
1984 sci_init_pins(port, termios->c_cflag);
1985
1986 reg = sci_getreg(port, SCFCR);
1987 if (reg->size) {
1988 unsigned short ctrl = serial_port_in(port, SCFCR);
1989
1990 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1991 if (termios->c_cflag & CRTSCTS)
1992 ctrl |= SCFCR_MCE;
1993 else
1994 ctrl &= ~SCFCR_MCE;
1995 }
1996
1997 /*
1998 * As we've done a sci_reset() above, ensure we don't
1999 * interfere with the FIFOs while toggling MCE. As the
2000 * reset values could still be set, simply mask them out.
2001 */
2002 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2003
2004 serial_port_out(port, SCFCR, ctrl);
2005 }
2006
2007 serial_port_out(port, SCSCR, s->cfg->scscr);
2008
2009 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2010 /*
2011 * Calculate delay for 2 DMA buffers (4 FIFO).
2012 * See serial_core.c::uart_update_timeout().
2013 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2014 * function calculates 1 jiffie for the data plus 5 jiffies for the
2015 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2016 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2017 * value obtained by this formula is too small. Therefore, if the value
2018 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2019 */
2020 if (s->chan_rx) {
2021 unsigned int bits;
2022
2023 /* byte size and parity */
2024 switch (termios->c_cflag & CSIZE) {
2025 case CS5:
2026 bits = 7;
2027 break;
2028 case CS6:
2029 bits = 8;
2030 break;
2031 case CS7:
2032 bits = 9;
2033 break;
2034 default:
2035 bits = 10;
2036 break;
2037 }
2038
2039 if (termios->c_cflag & CSTOPB)
2040 bits++;
2041 if (termios->c_cflag & PARENB)
2042 bits++;
2043 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2044 (baud / 10), 10);
2045 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2046 s->rx_timeout * 1000 / HZ, port->timeout);
2047 if (s->rx_timeout < msecs_to_jiffies(20))
2048 s->rx_timeout = msecs_to_jiffies(20);
2049 }
2050 #endif
2051
2052 if ((termios->c_cflag & CREAD) != 0)
2053 sci_start_rx(port);
2054
2055 sci_port_disable(s);
2056 }
2057
2058 static void sci_pm(struct uart_port *port, unsigned int state,
2059 unsigned int oldstate)
2060 {
2061 struct sci_port *sci_port = to_sci_port(port);
2062
2063 switch (state) {
2064 case UART_PM_STATE_OFF:
2065 sci_port_disable(sci_port);
2066 break;
2067 default:
2068 sci_port_enable(sci_port);
2069 break;
2070 }
2071 }
2072
2073 static const char *sci_type(struct uart_port *port)
2074 {
2075 switch (port->type) {
2076 case PORT_IRDA:
2077 return "irda";
2078 case PORT_SCI:
2079 return "sci";
2080 case PORT_SCIF:
2081 return "scif";
2082 case PORT_SCIFA:
2083 return "scifa";
2084 case PORT_SCIFB:
2085 return "scifb";
2086 case PORT_HSCIF:
2087 return "hscif";
2088 }
2089
2090 return NULL;
2091 }
2092
2093 static int sci_remap_port(struct uart_port *port)
2094 {
2095 struct sci_port *sport = to_sci_port(port);
2096
2097 /*
2098 * Nothing to do if there's already an established membase.
2099 */
2100 if (port->membase)
2101 return 0;
2102
2103 if (port->flags & UPF_IOREMAP) {
2104 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2105 if (unlikely(!port->membase)) {
2106 dev_err(port->dev, "can't remap port#%d\n", port->line);
2107 return -ENXIO;
2108 }
2109 } else {
2110 /*
2111 * For the simple (and majority of) cases where we don't
2112 * need to do any remapping, just cast the cookie
2113 * directly.
2114 */
2115 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2116 }
2117
2118 return 0;
2119 }
2120
2121 static void sci_release_port(struct uart_port *port)
2122 {
2123 struct sci_port *sport = to_sci_port(port);
2124
2125 if (port->flags & UPF_IOREMAP) {
2126 iounmap(port->membase);
2127 port->membase = NULL;
2128 }
2129
2130 release_mem_region(port->mapbase, sport->reg_size);
2131 }
2132
2133 static int sci_request_port(struct uart_port *port)
2134 {
2135 struct resource *res;
2136 struct sci_port *sport = to_sci_port(port);
2137 int ret;
2138
2139 res = request_mem_region(port->mapbase, sport->reg_size,
2140 dev_name(port->dev));
2141 if (unlikely(res == NULL)) {
2142 dev_err(port->dev, "request_mem_region failed.");
2143 return -EBUSY;
2144 }
2145
2146 ret = sci_remap_port(port);
2147 if (unlikely(ret != 0)) {
2148 release_resource(res);
2149 return ret;
2150 }
2151
2152 return 0;
2153 }
2154
2155 static void sci_config_port(struct uart_port *port, int flags)
2156 {
2157 if (flags & UART_CONFIG_TYPE) {
2158 struct sci_port *sport = to_sci_port(port);
2159
2160 port->type = sport->cfg->type;
2161 sci_request_port(port);
2162 }
2163 }
2164
2165 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2166 {
2167 if (ser->baud_base < 2400)
2168 /* No paper tape reader for Mitch.. */
2169 return -EINVAL;
2170
2171 return 0;
2172 }
2173
2174 static struct uart_ops sci_uart_ops = {
2175 .tx_empty = sci_tx_empty,
2176 .set_mctrl = sci_set_mctrl,
2177 .get_mctrl = sci_get_mctrl,
2178 .start_tx = sci_start_tx,
2179 .stop_tx = sci_stop_tx,
2180 .stop_rx = sci_stop_rx,
2181 .break_ctl = sci_break_ctl,
2182 .startup = sci_startup,
2183 .shutdown = sci_shutdown,
2184 .set_termios = sci_set_termios,
2185 .pm = sci_pm,
2186 .type = sci_type,
2187 .release_port = sci_release_port,
2188 .request_port = sci_request_port,
2189 .config_port = sci_config_port,
2190 .verify_port = sci_verify_port,
2191 #ifdef CONFIG_CONSOLE_POLL
2192 .poll_get_char = sci_poll_get_char,
2193 .poll_put_char = sci_poll_put_char,
2194 #endif
2195 };
2196
2197 static int sci_init_single(struct platform_device *dev,
2198 struct sci_port *sci_port, unsigned int index,
2199 struct plat_sci_port *p, bool early)
2200 {
2201 struct uart_port *port = &sci_port->port;
2202 const struct resource *res;
2203 unsigned int i;
2204 int ret;
2205
2206 sci_port->cfg = p;
2207
2208 port->ops = &sci_uart_ops;
2209 port->iotype = UPIO_MEM;
2210 port->line = index;
2211
2212 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2213 if (res == NULL)
2214 return -ENOMEM;
2215
2216 port->mapbase = res->start;
2217 sci_port->reg_size = resource_size(res);
2218
2219 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2220 sci_port->irqs[i] = platform_get_irq(dev, i);
2221
2222 /* The SCI generates several interrupts. They can be muxed together or
2223 * connected to different interrupt lines. In the muxed case only one
2224 * interrupt resource is specified. In the non-muxed case three or four
2225 * interrupt resources are specified, as the BRI interrupt is optional.
2226 */
2227 if (sci_port->irqs[0] < 0)
2228 return -ENXIO;
2229
2230 if (sci_port->irqs[1] < 0) {
2231 sci_port->irqs[1] = sci_port->irqs[0];
2232 sci_port->irqs[2] = sci_port->irqs[0];
2233 sci_port->irqs[3] = sci_port->irqs[0];
2234 }
2235
2236 if (p->regtype == SCIx_PROBE_REGTYPE) {
2237 ret = sci_probe_regmap(p);
2238 if (unlikely(ret))
2239 return ret;
2240 }
2241
2242 switch (p->type) {
2243 case PORT_SCIFB:
2244 port->fifosize = 256;
2245 sci_port->overrun_reg = SCxSR;
2246 sci_port->overrun_mask = SCIFA_ORER;
2247 sci_port->sampling_rate = 16;
2248 break;
2249 case PORT_HSCIF:
2250 port->fifosize = 128;
2251 sci_port->overrun_reg = SCLSR;
2252 sci_port->overrun_mask = SCLSR_ORER;
2253 sci_port->sampling_rate = 0;
2254 break;
2255 case PORT_SCIFA:
2256 port->fifosize = 64;
2257 sci_port->overrun_reg = SCxSR;
2258 sci_port->overrun_mask = SCIFA_ORER;
2259 sci_port->sampling_rate = 16;
2260 break;
2261 case PORT_SCIF:
2262 port->fifosize = 16;
2263 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2264 sci_port->overrun_reg = SCxSR;
2265 sci_port->overrun_mask = SCIFA_ORER;
2266 sci_port->sampling_rate = 16;
2267 } else {
2268 sci_port->overrun_reg = SCLSR;
2269 sci_port->overrun_mask = SCLSR_ORER;
2270 sci_port->sampling_rate = 32;
2271 }
2272 break;
2273 default:
2274 port->fifosize = 1;
2275 sci_port->overrun_reg = SCxSR;
2276 sci_port->overrun_mask = SCI_ORER;
2277 sci_port->sampling_rate = 32;
2278 break;
2279 }
2280
2281 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2282 * match the SoC datasheet, this should be investigated. Let platform
2283 * data override the sampling rate for now.
2284 */
2285 if (p->sampling_rate)
2286 sci_port->sampling_rate = p->sampling_rate;
2287
2288 if (!early) {
2289 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2290 if (IS_ERR(sci_port->iclk)) {
2291 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2292 if (IS_ERR(sci_port->iclk)) {
2293 dev_err(&dev->dev, "can't get iclk\n");
2294 return PTR_ERR(sci_port->iclk);
2295 }
2296 }
2297
2298 /*
2299 * The function clock is optional, ignore it if we can't
2300 * find it.
2301 */
2302 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2303 if (IS_ERR(sci_port->fclk))
2304 sci_port->fclk = NULL;
2305
2306 port->dev = &dev->dev;
2307
2308 pm_runtime_enable(&dev->dev);
2309 }
2310
2311 sci_port->break_timer.data = (unsigned long)sci_port;
2312 sci_port->break_timer.function = sci_break_timer;
2313 init_timer(&sci_port->break_timer);
2314
2315 /*
2316 * Establish some sensible defaults for the error detection.
2317 */
2318 if (p->type == PORT_SCI) {
2319 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2320 sci_port->error_clear = SCI_ERROR_CLEAR;
2321 } else {
2322 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2323 sci_port->error_clear = SCIF_ERROR_CLEAR;
2324 }
2325
2326 /*
2327 * Make the error mask inclusive of overrun detection, if
2328 * supported.
2329 */
2330 if (sci_port->overrun_reg == SCxSR) {
2331 sci_port->error_mask |= sci_port->overrun_mask;
2332 sci_port->error_clear &= ~sci_port->overrun_mask;
2333 }
2334
2335 port->type = p->type;
2336 port->flags = UPF_FIXED_PORT | p->flags;
2337 port->regshift = p->regshift;
2338
2339 /*
2340 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2341 * for the multi-IRQ ports, which is where we are primarily
2342 * concerned with the shutdown path synchronization.
2343 *
2344 * For the muxed case there's nothing more to do.
2345 */
2346 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2347 port->irqflags = 0;
2348
2349 port->serial_in = sci_serial_in;
2350 port->serial_out = sci_serial_out;
2351
2352 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2353 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2354 p->dma_slave_tx, p->dma_slave_rx);
2355
2356 return 0;
2357 }
2358
2359 static void sci_cleanup_single(struct sci_port *port)
2360 {
2361 clk_put(port->iclk);
2362 clk_put(port->fclk);
2363
2364 pm_runtime_disable(port->port.dev);
2365 }
2366
2367 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2368 static void serial_console_putchar(struct uart_port *port, int ch)
2369 {
2370 sci_poll_put_char(port, ch);
2371 }
2372
2373 /*
2374 * Print a string to the serial port trying not to disturb
2375 * any possible real use of the port...
2376 */
2377 static void serial_console_write(struct console *co, const char *s,
2378 unsigned count)
2379 {
2380 struct sci_port *sci_port = &sci_ports[co->index];
2381 struct uart_port *port = &sci_port->port;
2382 unsigned short bits, ctrl;
2383 unsigned long flags;
2384 int locked = 1;
2385
2386 local_irq_save(flags);
2387 if (port->sysrq)
2388 locked = 0;
2389 else if (oops_in_progress)
2390 locked = spin_trylock(&port->lock);
2391 else
2392 spin_lock(&port->lock);
2393
2394 /* first save the SCSCR then disable the interrupts */
2395 ctrl = serial_port_in(port, SCSCR);
2396 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2397
2398 uart_console_write(port, s, count, serial_console_putchar);
2399
2400 /* wait until fifo is empty and last bit has been transmitted */
2401 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2402 while ((serial_port_in(port, SCxSR) & bits) != bits)
2403 cpu_relax();
2404
2405 /* restore the SCSCR */
2406 serial_port_out(port, SCSCR, ctrl);
2407
2408 if (locked)
2409 spin_unlock(&port->lock);
2410 local_irq_restore(flags);
2411 }
2412
2413 static int serial_console_setup(struct console *co, char *options)
2414 {
2415 struct sci_port *sci_port;
2416 struct uart_port *port;
2417 int baud = 115200;
2418 int bits = 8;
2419 int parity = 'n';
2420 int flow = 'n';
2421 int ret;
2422
2423 /*
2424 * Refuse to handle any bogus ports.
2425 */
2426 if (co->index < 0 || co->index >= SCI_NPORTS)
2427 return -ENODEV;
2428
2429 sci_port = &sci_ports[co->index];
2430 port = &sci_port->port;
2431
2432 /*
2433 * Refuse to handle uninitialized ports.
2434 */
2435 if (!port->ops)
2436 return -ENODEV;
2437
2438 ret = sci_remap_port(port);
2439 if (unlikely(ret != 0))
2440 return ret;
2441
2442 if (options)
2443 uart_parse_options(options, &baud, &parity, &bits, &flow);
2444
2445 return uart_set_options(port, co, baud, parity, bits, flow);
2446 }
2447
2448 static struct console serial_console = {
2449 .name = "ttySC",
2450 .device = uart_console_device,
2451 .write = serial_console_write,
2452 .setup = serial_console_setup,
2453 .flags = CON_PRINTBUFFER,
2454 .index = -1,
2455 .data = &sci_uart_driver,
2456 };
2457
2458 static struct console early_serial_console = {
2459 .name = "early_ttySC",
2460 .write = serial_console_write,
2461 .flags = CON_PRINTBUFFER,
2462 .index = -1,
2463 };
2464
2465 static char early_serial_buf[32];
2466
2467 static int sci_probe_earlyprintk(struct platform_device *pdev)
2468 {
2469 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2470
2471 if (early_serial_console.data)
2472 return -EEXIST;
2473
2474 early_serial_console.index = pdev->id;
2475
2476 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2477
2478 serial_console_setup(&early_serial_console, early_serial_buf);
2479
2480 if (!strstr(early_serial_buf, "keep"))
2481 early_serial_console.flags |= CON_BOOT;
2482
2483 register_console(&early_serial_console);
2484 return 0;
2485 }
2486
2487 #define SCI_CONSOLE (&serial_console)
2488
2489 #else
2490 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2491 {
2492 return -EINVAL;
2493 }
2494
2495 #define SCI_CONSOLE NULL
2496
2497 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2498
2499 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2500
2501 static struct uart_driver sci_uart_driver = {
2502 .owner = THIS_MODULE,
2503 .driver_name = "sci",
2504 .dev_name = "ttySC",
2505 .major = SCI_MAJOR,
2506 .minor = SCI_MINOR_START,
2507 .nr = SCI_NPORTS,
2508 .cons = SCI_CONSOLE,
2509 };
2510
2511 static int sci_remove(struct platform_device *dev)
2512 {
2513 struct sci_port *port = platform_get_drvdata(dev);
2514
2515 cpufreq_unregister_notifier(&port->freq_transition,
2516 CPUFREQ_TRANSITION_NOTIFIER);
2517
2518 uart_remove_one_port(&sci_uart_driver, &port->port);
2519
2520 sci_cleanup_single(port);
2521
2522 return 0;
2523 }
2524
2525 struct sci_port_info {
2526 unsigned int type;
2527 unsigned int regtype;
2528 };
2529
2530 static const struct of_device_id of_sci_match[] = {
2531 {
2532 .compatible = "renesas,scif",
2533 .data = &(const struct sci_port_info) {
2534 .type = PORT_SCIF,
2535 .regtype = SCIx_SH4_SCIF_REGTYPE,
2536 },
2537 }, {
2538 .compatible = "renesas,scifa",
2539 .data = &(const struct sci_port_info) {
2540 .type = PORT_SCIFA,
2541 .regtype = SCIx_SCIFA_REGTYPE,
2542 },
2543 }, {
2544 .compatible = "renesas,scifb",
2545 .data = &(const struct sci_port_info) {
2546 .type = PORT_SCIFB,
2547 .regtype = SCIx_SCIFB_REGTYPE,
2548 },
2549 }, {
2550 .compatible = "renesas,hscif",
2551 .data = &(const struct sci_port_info) {
2552 .type = PORT_HSCIF,
2553 .regtype = SCIx_HSCIF_REGTYPE,
2554 },
2555 }, {
2556 .compatible = "renesas,sci",
2557 .data = &(const struct sci_port_info) {
2558 .type = PORT_SCI,
2559 .regtype = SCIx_SCI_REGTYPE,
2560 },
2561 }, {
2562 /* Terminator */
2563 },
2564 };
2565 MODULE_DEVICE_TABLE(of, of_sci_match);
2566
2567 static struct plat_sci_port *
2568 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2569 {
2570 struct device_node *np = pdev->dev.of_node;
2571 const struct of_device_id *match;
2572 const struct sci_port_info *info;
2573 struct plat_sci_port *p;
2574 int id;
2575
2576 if (!IS_ENABLED(CONFIG_OF) || !np)
2577 return NULL;
2578
2579 match = of_match_node(of_sci_match, pdev->dev.of_node);
2580 if (!match)
2581 return NULL;
2582
2583 info = match->data;
2584
2585 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2586 if (!p)
2587 return NULL;
2588
2589 /* Get the line number for the aliases node. */
2590 id = of_alias_get_id(np, "serial");
2591 if (id < 0) {
2592 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2593 return NULL;
2594 }
2595
2596 *dev_id = id;
2597
2598 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2599 p->type = info->type;
2600 p->regtype = info->regtype;
2601 p->scscr = SCSCR_RE | SCSCR_TE;
2602
2603 return p;
2604 }
2605
2606 static int sci_probe_single(struct platform_device *dev,
2607 unsigned int index,
2608 struct plat_sci_port *p,
2609 struct sci_port *sciport)
2610 {
2611 int ret;
2612
2613 /* Sanity check */
2614 if (unlikely(index >= SCI_NPORTS)) {
2615 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2616 index+1, SCI_NPORTS);
2617 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2618 return -EINVAL;
2619 }
2620
2621 ret = sci_init_single(dev, sciport, index, p, false);
2622 if (ret)
2623 return ret;
2624
2625 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2626 if (ret) {
2627 sci_cleanup_single(sciport);
2628 return ret;
2629 }
2630
2631 return 0;
2632 }
2633
2634 static int sci_probe(struct platform_device *dev)
2635 {
2636 struct plat_sci_port *p;
2637 struct sci_port *sp;
2638 unsigned int dev_id;
2639 int ret;
2640
2641 /*
2642 * If we've come here via earlyprintk initialization, head off to
2643 * the special early probe. We don't have sufficient device state
2644 * to make it beyond this yet.
2645 */
2646 if (is_early_platform_device(dev))
2647 return sci_probe_earlyprintk(dev);
2648
2649 if (dev->dev.of_node) {
2650 p = sci_parse_dt(dev, &dev_id);
2651 if (p == NULL)
2652 return -EINVAL;
2653 } else {
2654 p = dev->dev.platform_data;
2655 if (p == NULL) {
2656 dev_err(&dev->dev, "no platform data supplied\n");
2657 return -EINVAL;
2658 }
2659
2660 dev_id = dev->id;
2661 }
2662
2663 sp = &sci_ports[dev_id];
2664 platform_set_drvdata(dev, sp);
2665
2666 ret = sci_probe_single(dev, dev_id, p, sp);
2667 if (ret)
2668 return ret;
2669
2670 sp->freq_transition.notifier_call = sci_notifier;
2671
2672 ret = cpufreq_register_notifier(&sp->freq_transition,
2673 CPUFREQ_TRANSITION_NOTIFIER);
2674 if (unlikely(ret < 0)) {
2675 uart_remove_one_port(&sci_uart_driver, &sp->port);
2676 sci_cleanup_single(sp);
2677 return ret;
2678 }
2679
2680 #ifdef CONFIG_SH_STANDARD_BIOS
2681 sh_bios_gdb_detach();
2682 #endif
2683
2684 return 0;
2685 }
2686
2687 static __maybe_unused int sci_suspend(struct device *dev)
2688 {
2689 struct sci_port *sport = dev_get_drvdata(dev);
2690
2691 if (sport)
2692 uart_suspend_port(&sci_uart_driver, &sport->port);
2693
2694 return 0;
2695 }
2696
2697 static __maybe_unused int sci_resume(struct device *dev)
2698 {
2699 struct sci_port *sport = dev_get_drvdata(dev);
2700
2701 if (sport)
2702 uart_resume_port(&sci_uart_driver, &sport->port);
2703
2704 return 0;
2705 }
2706
2707 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2708
2709 static struct platform_driver sci_driver = {
2710 .probe = sci_probe,
2711 .remove = sci_remove,
2712 .driver = {
2713 .name = "sh-sci",
2714 .pm = &sci_dev_pm_ops,
2715 .of_match_table = of_match_ptr(of_sci_match),
2716 },
2717 };
2718
2719 static int __init sci_init(void)
2720 {
2721 int ret;
2722
2723 pr_info("%s\n", banner);
2724
2725 ret = uart_register_driver(&sci_uart_driver);
2726 if (likely(ret == 0)) {
2727 ret = platform_driver_register(&sci_driver);
2728 if (unlikely(ret))
2729 uart_unregister_driver(&sci_uart_driver);
2730 }
2731
2732 return ret;
2733 }
2734
2735 static void __exit sci_exit(void)
2736 {
2737 platform_driver_unregister(&sci_driver);
2738 uart_unregister_driver(&sci_uart_driver);
2739 }
2740
2741 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2742 early_platform_init_buffer("earlyprintk", &sci_driver,
2743 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2744 #endif
2745 module_init(sci_init);
2746 module_exit(sci_exit);
2747
2748 MODULE_LICENSE("GPL");
2749 MODULE_ALIAS("platform:sh-sci");
2750 MODULE_AUTHOR("Paul Mundt");
2751 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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