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serial: sh-sci: Add SCIFA/B SCPCR register definitions
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 int overrun_bit;
85 unsigned int error_mask;
86 unsigned int sampling_rate;
87
88
89 /* Break timer */
90 struct timer_list break_timer;
91 int break_flag;
92
93 /* Interface clock */
94 struct clk *iclk;
95 /* Function clock */
96 struct clk *fclk;
97
98 int irqs[SCIx_NR_IRQS];
99 char *irqstr[SCIx_NR_IRQS];
100
101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
103
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 struct dma_async_tx_descriptor *desc_tx;
106 struct dma_async_tx_descriptor *desc_rx[2];
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 struct scatterlist sg_tx;
111 unsigned int sg_len_tx;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
120 #endif
121
122 struct notifier_block freq_transition;
123 };
124
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
137 {
138 return container_of(uart, struct sci_port, port);
139 }
140
141 struct plat_sci_reg {
142 u8 offset, size;
143 };
144
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147
148 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
171 [SCPCR] = sci_reg_invalid,
172 [SCPDR] = sci_reg_invalid,
173 },
174
175 /*
176 * Common definitions for legacy IrDA ports, dependent on
177 * regshift value.
178 */
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 [HSSRR] = sci_reg_invalid,
193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
195 },
196
197 /*
198 * Common SCIFA definitions.
199 */
200 [SCIx_SCIFA_REGTYPE] = {
201 [SCSMR] = { 0x00, 16 },
202 [SCBRR] = { 0x04, 8 },
203 [SCSCR] = { 0x08, 16 },
204 [SCxTDR] = { 0x20, 8 },
205 [SCxSR] = { 0x14, 16 },
206 [SCxRDR] = { 0x24, 8 },
207 [SCFCR] = { 0x18, 16 },
208 [SCFDR] = { 0x1c, 16 },
209 [SCTFDR] = sci_reg_invalid,
210 [SCRFDR] = sci_reg_invalid,
211 [SCSPTR] = sci_reg_invalid,
212 [SCLSR] = sci_reg_invalid,
213 [HSSRR] = sci_reg_invalid,
214 [SCPCR] = { 0x30, 16 },
215 [SCPDR] = { 0x34, 16 },
216 },
217
218 /*
219 * Common SCIFB definitions.
220 */
221 [SCIx_SCIFB_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x40, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x60, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = sci_reg_invalid,
230 [SCTFDR] = { 0x38, 16 },
231 [SCRFDR] = { 0x3c, 16 },
232 [SCSPTR] = sci_reg_invalid,
233 [SCLSR] = sci_reg_invalid,
234 [HSSRR] = sci_reg_invalid,
235 [SCPCR] = { 0x30, 16 },
236 [SCPDR] = { 0x34, 16 },
237 },
238
239 /*
240 * Common SH-2(A) SCIF definitions for ports with FIFO data
241 * count registers.
242 */
243 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x0c, 8 },
248 [SCxSR] = { 0x10, 16 },
249 [SCxRDR] = { 0x14, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = { 0x1c, 16 },
252 [SCTFDR] = sci_reg_invalid,
253 [SCRFDR] = sci_reg_invalid,
254 [SCSPTR] = { 0x20, 16 },
255 [SCLSR] = { 0x24, 16 },
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = sci_reg_invalid,
258 [SCPDR] = sci_reg_invalid,
259 },
260
261 /*
262 * Common SH-3 SCIF definitions.
263 */
264 [SCIx_SH3_SCIF_REGTYPE] = {
265 [SCSMR] = { 0x00, 8 },
266 [SCBRR] = { 0x02, 8 },
267 [SCSCR] = { 0x04, 8 },
268 [SCxTDR] = { 0x06, 8 },
269 [SCxSR] = { 0x08, 16 },
270 [SCxRDR] = { 0x0a, 8 },
271 [SCFCR] = { 0x0c, 8 },
272 [SCFDR] = { 0x0e, 16 },
273 [SCTFDR] = sci_reg_invalid,
274 [SCRFDR] = sci_reg_invalid,
275 [SCSPTR] = sci_reg_invalid,
276 [SCLSR] = sci_reg_invalid,
277 [HSSRR] = sci_reg_invalid,
278 [SCPCR] = sci_reg_invalid,
279 [SCPDR] = sci_reg_invalid,
280 },
281
282 /*
283 * Common SH-4(A) SCIF(B) definitions.
284 */
285 [SCIx_SH4_SCIF_REGTYPE] = {
286 [SCSMR] = { 0x00, 16 },
287 [SCBRR] = { 0x04, 8 },
288 [SCSCR] = { 0x08, 16 },
289 [SCxTDR] = { 0x0c, 8 },
290 [SCxSR] = { 0x10, 16 },
291 [SCxRDR] = { 0x14, 8 },
292 [SCFCR] = { 0x18, 16 },
293 [SCFDR] = { 0x1c, 16 },
294 [SCTFDR] = sci_reg_invalid,
295 [SCRFDR] = sci_reg_invalid,
296 [SCSPTR] = { 0x20, 16 },
297 [SCLSR] = { 0x24, 16 },
298 [HSSRR] = sci_reg_invalid,
299 [SCPCR] = sci_reg_invalid,
300 [SCPDR] = sci_reg_invalid,
301 },
302
303 /*
304 * Common HSCIF definitions.
305 */
306 [SCIx_HSCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x0c, 8 },
311 [SCxSR] = { 0x10, 16 },
312 [SCxRDR] = { 0x14, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = { 0x20, 16 },
318 [SCLSR] = { 0x24, 16 },
319 [HSSRR] = { 0x40, 16 },
320 [SCPCR] = sci_reg_invalid,
321 [SCPDR] = sci_reg_invalid,
322 },
323
324 /*
325 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
326 * register.
327 */
328 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
329 [SCSMR] = { 0x00, 16 },
330 [SCBRR] = { 0x04, 8 },
331 [SCSCR] = { 0x08, 16 },
332 [SCxTDR] = { 0x0c, 8 },
333 [SCxSR] = { 0x10, 16 },
334 [SCxRDR] = { 0x14, 8 },
335 [SCFCR] = { 0x18, 16 },
336 [SCFDR] = { 0x1c, 16 },
337 [SCTFDR] = sci_reg_invalid,
338 [SCRFDR] = sci_reg_invalid,
339 [SCSPTR] = sci_reg_invalid,
340 [SCLSR] = { 0x24, 16 },
341 [HSSRR] = sci_reg_invalid,
342 [SCPCR] = sci_reg_invalid,
343 [SCPDR] = sci_reg_invalid,
344 },
345
346 /*
347 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
348 * count registers.
349 */
350 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
351 [SCSMR] = { 0x00, 16 },
352 [SCBRR] = { 0x04, 8 },
353 [SCSCR] = { 0x08, 16 },
354 [SCxTDR] = { 0x0c, 8 },
355 [SCxSR] = { 0x10, 16 },
356 [SCxRDR] = { 0x14, 8 },
357 [SCFCR] = { 0x18, 16 },
358 [SCFDR] = { 0x1c, 16 },
359 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
360 [SCRFDR] = { 0x20, 16 },
361 [SCSPTR] = { 0x24, 16 },
362 [SCLSR] = { 0x28, 16 },
363 [HSSRR] = sci_reg_invalid,
364 [SCPCR] = sci_reg_invalid,
365 [SCPDR] = sci_reg_invalid,
366 },
367
368 /*
369 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
370 * registers.
371 */
372 [SCIx_SH7705_SCIF_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x20, 8 },
377 [SCxSR] = { 0x14, 16 },
378 [SCxRDR] = { 0x24, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCTFDR] = sci_reg_invalid,
382 [SCRFDR] = sci_reg_invalid,
383 [SCSPTR] = sci_reg_invalid,
384 [SCLSR] = sci_reg_invalid,
385 [HSSRR] = sci_reg_invalid,
386 [SCPCR] = sci_reg_invalid,
387 [SCPDR] = sci_reg_invalid,
388 },
389 };
390
391 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
392
393 /*
394 * The "offset" here is rather misleading, in that it refers to an enum
395 * value relative to the port mapping rather than the fixed offset
396 * itself, which needs to be manually retrieved from the platform's
397 * register map for the given port.
398 */
399 static unsigned int sci_serial_in(struct uart_port *p, int offset)
400 {
401 struct plat_sci_reg *reg = sci_getreg(p, offset);
402
403 if (reg->size == 8)
404 return ioread8(p->membase + (reg->offset << p->regshift));
405 else if (reg->size == 16)
406 return ioread16(p->membase + (reg->offset << p->regshift));
407 else
408 WARN(1, "Invalid register access\n");
409
410 return 0;
411 }
412
413 static void sci_serial_out(struct uart_port *p, int offset, int value)
414 {
415 struct plat_sci_reg *reg = sci_getreg(p, offset);
416
417 if (reg->size == 8)
418 iowrite8(value, p->membase + (reg->offset << p->regshift));
419 else if (reg->size == 16)
420 iowrite16(value, p->membase + (reg->offset << p->regshift));
421 else
422 WARN(1, "Invalid register access\n");
423 }
424
425 static int sci_probe_regmap(struct plat_sci_port *cfg)
426 {
427 switch (cfg->type) {
428 case PORT_SCI:
429 cfg->regtype = SCIx_SCI_REGTYPE;
430 break;
431 case PORT_IRDA:
432 cfg->regtype = SCIx_IRDA_REGTYPE;
433 break;
434 case PORT_SCIFA:
435 cfg->regtype = SCIx_SCIFA_REGTYPE;
436 break;
437 case PORT_SCIFB:
438 cfg->regtype = SCIx_SCIFB_REGTYPE;
439 break;
440 case PORT_SCIF:
441 /*
442 * The SH-4 is a bit of a misnomer here, although that's
443 * where this particular port layout originated. This
444 * configuration (or some slight variation thereof)
445 * remains the dominant model for all SCIFs.
446 */
447 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
448 break;
449 case PORT_HSCIF:
450 cfg->regtype = SCIx_HSCIF_REGTYPE;
451 break;
452 default:
453 pr_err("Can't probe register map for given port\n");
454 return -EINVAL;
455 }
456
457 return 0;
458 }
459
460 static void sci_port_enable(struct sci_port *sci_port)
461 {
462 if (!sci_port->port.dev)
463 return;
464
465 pm_runtime_get_sync(sci_port->port.dev);
466
467 clk_prepare_enable(sci_port->iclk);
468 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
469 clk_prepare_enable(sci_port->fclk);
470 }
471
472 static void sci_port_disable(struct sci_port *sci_port)
473 {
474 if (!sci_port->port.dev)
475 return;
476
477 /* Cancel the break timer to ensure that the timer handler will not try
478 * to access the hardware with clocks and power disabled. Reset the
479 * break flag to make the break debouncing state machine ready for the
480 * next break.
481 */
482 del_timer_sync(&sci_port->break_timer);
483 sci_port->break_flag = 0;
484
485 clk_disable_unprepare(sci_port->fclk);
486 clk_disable_unprepare(sci_port->iclk);
487
488 pm_runtime_put_sync(sci_port->port.dev);
489 }
490
491 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
492
493 #ifdef CONFIG_CONSOLE_POLL
494 static int sci_poll_get_char(struct uart_port *port)
495 {
496 unsigned short status;
497 int c;
498
499 do {
500 status = serial_port_in(port, SCxSR);
501 if (status & SCxSR_ERRORS(port)) {
502 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
503 continue;
504 }
505 break;
506 } while (1);
507
508 if (!(status & SCxSR_RDxF(port)))
509 return NO_POLL_CHAR;
510
511 c = serial_port_in(port, SCxRDR);
512
513 /* Dummy read */
514 serial_port_in(port, SCxSR);
515 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
516
517 return c;
518 }
519 #endif
520
521 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
522 {
523 unsigned short status;
524
525 do {
526 status = serial_port_in(port, SCxSR);
527 } while (!(status & SCxSR_TDxE(port)));
528
529 serial_port_out(port, SCxTDR, c);
530 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
531 }
532 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
533
534 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
535 {
536 struct sci_port *s = to_sci_port(port);
537 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
538
539 /*
540 * Use port-specific handler if provided.
541 */
542 if (s->cfg->ops && s->cfg->ops->init_pins) {
543 s->cfg->ops->init_pins(port, cflag);
544 return;
545 }
546
547 /*
548 * For the generic path SCSPTR is necessary. Bail out if that's
549 * unavailable, too.
550 */
551 if (!reg->size)
552 return;
553
554 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
555 ((!(cflag & CRTSCTS)))) {
556 unsigned short status;
557
558 status = serial_port_in(port, SCSPTR);
559 status &= ~SCSPTR_CTSIO;
560 status |= SCSPTR_RTSIO;
561 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
562 }
563 }
564
565 static int sci_txfill(struct uart_port *port)
566 {
567 struct plat_sci_reg *reg;
568
569 reg = sci_getreg(port, SCTFDR);
570 if (reg->size)
571 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
572
573 reg = sci_getreg(port, SCFDR);
574 if (reg->size)
575 return serial_port_in(port, SCFDR) >> 8;
576
577 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
578 }
579
580 static int sci_txroom(struct uart_port *port)
581 {
582 return port->fifosize - sci_txfill(port);
583 }
584
585 static int sci_rxfill(struct uart_port *port)
586 {
587 struct plat_sci_reg *reg;
588
589 reg = sci_getreg(port, SCRFDR);
590 if (reg->size)
591 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
592
593 reg = sci_getreg(port, SCFDR);
594 if (reg->size)
595 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
596
597 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
598 }
599
600 /*
601 * SCI helper for checking the state of the muxed port/RXD pins.
602 */
603 static inline int sci_rxd_in(struct uart_port *port)
604 {
605 struct sci_port *s = to_sci_port(port);
606
607 if (s->cfg->port_reg <= 0)
608 return 1;
609
610 /* Cast for ARM damage */
611 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
612 }
613
614 /* ********************************************************************** *
615 * the interrupt related routines *
616 * ********************************************************************** */
617
618 static void sci_transmit_chars(struct uart_port *port)
619 {
620 struct circ_buf *xmit = &port->state->xmit;
621 unsigned int stopped = uart_tx_stopped(port);
622 unsigned short status;
623 unsigned short ctrl;
624 int count;
625
626 status = serial_port_in(port, SCxSR);
627 if (!(status & SCxSR_TDxE(port))) {
628 ctrl = serial_port_in(port, SCSCR);
629 if (uart_circ_empty(xmit))
630 ctrl &= ~SCSCR_TIE;
631 else
632 ctrl |= SCSCR_TIE;
633 serial_port_out(port, SCSCR, ctrl);
634 return;
635 }
636
637 count = sci_txroom(port);
638
639 do {
640 unsigned char c;
641
642 if (port->x_char) {
643 c = port->x_char;
644 port->x_char = 0;
645 } else if (!uart_circ_empty(xmit) && !stopped) {
646 c = xmit->buf[xmit->tail];
647 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
648 } else {
649 break;
650 }
651
652 serial_port_out(port, SCxTDR, c);
653
654 port->icount.tx++;
655 } while (--count > 0);
656
657 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
658
659 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
660 uart_write_wakeup(port);
661 if (uart_circ_empty(xmit)) {
662 sci_stop_tx(port);
663 } else {
664 ctrl = serial_port_in(port, SCSCR);
665
666 if (port->type != PORT_SCI) {
667 serial_port_in(port, SCxSR); /* Dummy read */
668 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
669 }
670
671 ctrl |= SCSCR_TIE;
672 serial_port_out(port, SCSCR, ctrl);
673 }
674 }
675
676 /* On SH3, SCIF may read end-of-break as a space->mark char */
677 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
678
679 static void sci_receive_chars(struct uart_port *port)
680 {
681 struct sci_port *sci_port = to_sci_port(port);
682 struct tty_port *tport = &port->state->port;
683 int i, count, copied = 0;
684 unsigned short status;
685 unsigned char flag;
686
687 status = serial_port_in(port, SCxSR);
688 if (!(status & SCxSR_RDxF(port)))
689 return;
690
691 while (1) {
692 /* Don't copy more bytes than there is room for in the buffer */
693 count = tty_buffer_request_room(tport, sci_rxfill(port));
694
695 /* If for any reason we can't copy more data, we're done! */
696 if (count == 0)
697 break;
698
699 if (port->type == PORT_SCI) {
700 char c = serial_port_in(port, SCxRDR);
701 if (uart_handle_sysrq_char(port, c) ||
702 sci_port->break_flag)
703 count = 0;
704 else
705 tty_insert_flip_char(tport, c, TTY_NORMAL);
706 } else {
707 for (i = 0; i < count; i++) {
708 char c = serial_port_in(port, SCxRDR);
709
710 status = serial_port_in(port, SCxSR);
711 #if defined(CONFIG_CPU_SH3)
712 /* Skip "chars" during break */
713 if (sci_port->break_flag) {
714 if ((c == 0) &&
715 (status & SCxSR_FER(port))) {
716 count--; i--;
717 continue;
718 }
719
720 /* Nonzero => end-of-break */
721 dev_dbg(port->dev, "debounce<%02x>\n", c);
722 sci_port->break_flag = 0;
723
724 if (STEPFN(c)) {
725 count--; i--;
726 continue;
727 }
728 }
729 #endif /* CONFIG_CPU_SH3 */
730 if (uart_handle_sysrq_char(port, c)) {
731 count--; i--;
732 continue;
733 }
734
735 /* Store data and status */
736 if (status & SCxSR_FER(port)) {
737 flag = TTY_FRAME;
738 port->icount.frame++;
739 dev_notice(port->dev, "frame error\n");
740 } else if (status & SCxSR_PER(port)) {
741 flag = TTY_PARITY;
742 port->icount.parity++;
743 dev_notice(port->dev, "parity error\n");
744 } else
745 flag = TTY_NORMAL;
746
747 tty_insert_flip_char(tport, c, flag);
748 }
749 }
750
751 serial_port_in(port, SCxSR); /* dummy read */
752 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
753
754 copied += count;
755 port->icount.rx += count;
756 }
757
758 if (copied) {
759 /* Tell the rest of the system the news. New characters! */
760 tty_flip_buffer_push(tport);
761 } else {
762 serial_port_in(port, SCxSR); /* dummy read */
763 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
764 }
765 }
766
767 #define SCI_BREAK_JIFFIES (HZ/20)
768
769 /*
770 * The sci generates interrupts during the break,
771 * 1 per millisecond or so during the break period, for 9600 baud.
772 * So dont bother disabling interrupts.
773 * But dont want more than 1 break event.
774 * Use a kernel timer to periodically poll the rx line until
775 * the break is finished.
776 */
777 static inline void sci_schedule_break_timer(struct sci_port *port)
778 {
779 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
780 }
781
782 /* Ensure that two consecutive samples find the break over. */
783 static void sci_break_timer(unsigned long data)
784 {
785 struct sci_port *port = (struct sci_port *)data;
786
787 if (sci_rxd_in(&port->port) == 0) {
788 port->break_flag = 1;
789 sci_schedule_break_timer(port);
790 } else if (port->break_flag == 1) {
791 /* break is over. */
792 port->break_flag = 2;
793 sci_schedule_break_timer(port);
794 } else
795 port->break_flag = 0;
796 }
797
798 static int sci_handle_errors(struct uart_port *port)
799 {
800 int copied = 0;
801 unsigned short status = serial_port_in(port, SCxSR);
802 struct tty_port *tport = &port->state->port;
803 struct sci_port *s = to_sci_port(port);
804
805 /* Handle overruns */
806 if (status & (1 << s->overrun_bit)) {
807 port->icount.overrun++;
808
809 /* overrun error */
810 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
811 copied++;
812
813 dev_notice(port->dev, "overrun error\n");
814 }
815
816 if (status & SCxSR_FER(port)) {
817 if (sci_rxd_in(port) == 0) {
818 /* Notify of BREAK */
819 struct sci_port *sci_port = to_sci_port(port);
820
821 if (!sci_port->break_flag) {
822 port->icount.brk++;
823
824 sci_port->break_flag = 1;
825 sci_schedule_break_timer(sci_port);
826
827 /* Do sysrq handling. */
828 if (uart_handle_break(port))
829 return 0;
830
831 dev_dbg(port->dev, "BREAK detected\n");
832
833 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
834 copied++;
835 }
836
837 } else {
838 /* frame error */
839 port->icount.frame++;
840
841 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
842 copied++;
843
844 dev_notice(port->dev, "frame error\n");
845 }
846 }
847
848 if (status & SCxSR_PER(port)) {
849 /* parity error */
850 port->icount.parity++;
851
852 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
853 copied++;
854
855 dev_notice(port->dev, "parity error\n");
856 }
857
858 if (copied)
859 tty_flip_buffer_push(tport);
860
861 return copied;
862 }
863
864 static int sci_handle_fifo_overrun(struct uart_port *port)
865 {
866 struct tty_port *tport = &port->state->port;
867 struct sci_port *s = to_sci_port(port);
868 struct plat_sci_reg *reg;
869 int copied = 0, offset;
870 u16 status, bit;
871
872 switch (port->type) {
873 case PORT_SCIF:
874 case PORT_HSCIF:
875 offset = SCLSR;
876 break;
877 case PORT_SCIFA:
878 case PORT_SCIFB:
879 offset = SCxSR;
880 break;
881 default:
882 return 0;
883 }
884
885 reg = sci_getreg(port, offset);
886 if (!reg->size)
887 return 0;
888
889 status = serial_port_in(port, offset);
890 bit = 1 << s->overrun_bit;
891
892 if (status & bit) {
893 status &= ~bit;
894 serial_port_out(port, offset, status);
895
896 port->icount.overrun++;
897
898 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
899 tty_flip_buffer_push(tport);
900
901 dev_dbg(port->dev, "overrun error\n");
902 copied++;
903 }
904
905 return copied;
906 }
907
908 static int sci_handle_breaks(struct uart_port *port)
909 {
910 int copied = 0;
911 unsigned short status = serial_port_in(port, SCxSR);
912 struct tty_port *tport = &port->state->port;
913 struct sci_port *s = to_sci_port(port);
914
915 if (uart_handle_break(port))
916 return 0;
917
918 if (!s->break_flag && status & SCxSR_BRK(port)) {
919 #if defined(CONFIG_CPU_SH3)
920 /* Debounce break */
921 s->break_flag = 1;
922 #endif
923
924 port->icount.brk++;
925
926 /* Notify of BREAK */
927 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
928 copied++;
929
930 dev_dbg(port->dev, "BREAK detected\n");
931 }
932
933 if (copied)
934 tty_flip_buffer_push(tport);
935
936 copied += sci_handle_fifo_overrun(port);
937
938 return copied;
939 }
940
941 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
942 {
943 #ifdef CONFIG_SERIAL_SH_SCI_DMA
944 struct uart_port *port = ptr;
945 struct sci_port *s = to_sci_port(port);
946
947 if (s->chan_rx) {
948 u16 scr = serial_port_in(port, SCSCR);
949 u16 ssr = serial_port_in(port, SCxSR);
950
951 /* Disable future Rx interrupts */
952 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
953 disable_irq_nosync(irq);
954 scr |= SCSCR_RDRQE;
955 } else {
956 scr &= ~SCSCR_RIE;
957 }
958 serial_port_out(port, SCSCR, scr);
959 /* Clear current interrupt */
960 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
961 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
962 jiffies, s->rx_timeout);
963 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
964
965 return IRQ_HANDLED;
966 }
967 #endif
968
969 /* I think sci_receive_chars has to be called irrespective
970 * of whether the I_IXOFF is set, otherwise, how is the interrupt
971 * to be disabled?
972 */
973 sci_receive_chars(ptr);
974
975 return IRQ_HANDLED;
976 }
977
978 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
979 {
980 struct uart_port *port = ptr;
981 unsigned long flags;
982
983 spin_lock_irqsave(&port->lock, flags);
984 sci_transmit_chars(port);
985 spin_unlock_irqrestore(&port->lock, flags);
986
987 return IRQ_HANDLED;
988 }
989
990 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
991 {
992 struct uart_port *port = ptr;
993
994 /* Handle errors */
995 if (port->type == PORT_SCI) {
996 if (sci_handle_errors(port)) {
997 /* discard character in rx buffer */
998 serial_port_in(port, SCxSR);
999 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1000 }
1001 } else {
1002 sci_handle_fifo_overrun(port);
1003 sci_rx_interrupt(irq, ptr);
1004 }
1005
1006 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1007
1008 /* Kick the transmission */
1009 sci_tx_interrupt(irq, ptr);
1010
1011 return IRQ_HANDLED;
1012 }
1013
1014 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1015 {
1016 struct uart_port *port = ptr;
1017
1018 /* Handle BREAKs */
1019 sci_handle_breaks(port);
1020 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1021
1022 return IRQ_HANDLED;
1023 }
1024
1025 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1026 {
1027 /*
1028 * Not all ports (such as SCIFA) will support REIE. Rather than
1029 * special-casing the port type, we check the port initialization
1030 * IRQ enable mask to see whether the IRQ is desired at all. If
1031 * it's unset, it's logically inferred that there's no point in
1032 * testing for it.
1033 */
1034 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1035 }
1036
1037 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1038 {
1039 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1040 struct uart_port *port = ptr;
1041 struct sci_port *s = to_sci_port(port);
1042 irqreturn_t ret = IRQ_NONE;
1043
1044 ssr_status = serial_port_in(port, SCxSR);
1045 scr_status = serial_port_in(port, SCSCR);
1046 switch (port->type) {
1047 case PORT_SCIF:
1048 case PORT_HSCIF:
1049 orer_status = serial_port_in(port, SCLSR);
1050 break;
1051 case PORT_SCIFA:
1052 case PORT_SCIFB:
1053 orer_status = ssr_status;
1054 break;
1055 }
1056
1057 err_enabled = scr_status & port_rx_irq_mask(port);
1058
1059 /* Tx Interrupt */
1060 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1061 !s->chan_tx)
1062 ret = sci_tx_interrupt(irq, ptr);
1063
1064 /*
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1066 * DR flags
1067 */
1068 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1069 (scr_status & SCSCR_RIE)) {
1070 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1071 sci_handle_fifo_overrun(port);
1072 ret = sci_rx_interrupt(irq, ptr);
1073 }
1074
1075 /* Error Interrupt */
1076 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1077 ret = sci_er_interrupt(irq, ptr);
1078
1079 /* Break Interrupt */
1080 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1081 ret = sci_br_interrupt(irq, ptr);
1082
1083 /* Overrun Interrupt */
1084 if (orer_status & (1 << s->overrun_bit))
1085 sci_handle_fifo_overrun(port);
1086
1087 return ret;
1088 }
1089
1090 /*
1091 * Here we define a transition notifier so that we can update all of our
1092 * ports' baud rate when the peripheral clock changes.
1093 */
1094 static int sci_notifier(struct notifier_block *self,
1095 unsigned long phase, void *p)
1096 {
1097 struct sci_port *sci_port;
1098 unsigned long flags;
1099
1100 sci_port = container_of(self, struct sci_port, freq_transition);
1101
1102 if (phase == CPUFREQ_POSTCHANGE) {
1103 struct uart_port *port = &sci_port->port;
1104
1105 spin_lock_irqsave(&port->lock, flags);
1106 port->uartclk = clk_get_rate(sci_port->iclk);
1107 spin_unlock_irqrestore(&port->lock, flags);
1108 }
1109
1110 return NOTIFY_OK;
1111 }
1112
1113 static struct sci_irq_desc {
1114 const char *desc;
1115 irq_handler_t handler;
1116 } sci_irq_desc[] = {
1117 /*
1118 * Split out handlers, the default case.
1119 */
1120 [SCIx_ERI_IRQ] = {
1121 .desc = "rx err",
1122 .handler = sci_er_interrupt,
1123 },
1124
1125 [SCIx_RXI_IRQ] = {
1126 .desc = "rx full",
1127 .handler = sci_rx_interrupt,
1128 },
1129
1130 [SCIx_TXI_IRQ] = {
1131 .desc = "tx empty",
1132 .handler = sci_tx_interrupt,
1133 },
1134
1135 [SCIx_BRI_IRQ] = {
1136 .desc = "break",
1137 .handler = sci_br_interrupt,
1138 },
1139
1140 /*
1141 * Special muxed handler.
1142 */
1143 [SCIx_MUX_IRQ] = {
1144 .desc = "mux",
1145 .handler = sci_mpxed_interrupt,
1146 },
1147 };
1148
1149 static int sci_request_irq(struct sci_port *port)
1150 {
1151 struct uart_port *up = &port->port;
1152 int i, j, ret = 0;
1153
1154 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1155 struct sci_irq_desc *desc;
1156 int irq;
1157
1158 if (SCIx_IRQ_IS_MUXED(port)) {
1159 i = SCIx_MUX_IRQ;
1160 irq = up->irq;
1161 } else {
1162 irq = port->irqs[i];
1163
1164 /*
1165 * Certain port types won't support all of the
1166 * available interrupt sources.
1167 */
1168 if (unlikely(irq < 0))
1169 continue;
1170 }
1171
1172 desc = sci_irq_desc + i;
1173 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1174 dev_name(up->dev), desc->desc);
1175 if (!port->irqstr[j]) {
1176 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1177 desc->desc);
1178 goto out_nomem;
1179 }
1180
1181 ret = request_irq(irq, desc->handler, up->irqflags,
1182 port->irqstr[j], port);
1183 if (unlikely(ret)) {
1184 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1185 goto out_noirq;
1186 }
1187 }
1188
1189 return 0;
1190
1191 out_noirq:
1192 while (--i >= 0)
1193 free_irq(port->irqs[i], port);
1194
1195 out_nomem:
1196 while (--j >= 0)
1197 kfree(port->irqstr[j]);
1198
1199 return ret;
1200 }
1201
1202 static void sci_free_irq(struct sci_port *port)
1203 {
1204 int i;
1205
1206 /*
1207 * Intentionally in reverse order so we iterate over the muxed
1208 * IRQ first.
1209 */
1210 for (i = 0; i < SCIx_NR_IRQS; i++) {
1211 int irq = port->irqs[i];
1212
1213 /*
1214 * Certain port types won't support all of the available
1215 * interrupt sources.
1216 */
1217 if (unlikely(irq < 0))
1218 continue;
1219
1220 free_irq(port->irqs[i], port);
1221 kfree(port->irqstr[i]);
1222
1223 if (SCIx_IRQ_IS_MUXED(port)) {
1224 /* If there's only one IRQ, we're done. */
1225 return;
1226 }
1227 }
1228 }
1229
1230 static unsigned int sci_tx_empty(struct uart_port *port)
1231 {
1232 unsigned short status = serial_port_in(port, SCxSR);
1233 unsigned short in_tx_fifo = sci_txfill(port);
1234
1235 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1236 }
1237
1238 /*
1239 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1240 * CTS/RTS is supported in hardware by at least one port and controlled
1241 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1242 * handled via the ->init_pins() op, which is a bit of a one-way street,
1243 * lacking any ability to defer pin control -- this will later be
1244 * converted over to the GPIO framework).
1245 *
1246 * Other modes (such as loopback) are supported generically on certain
1247 * port types, but not others. For these it's sufficient to test for the
1248 * existence of the support register and simply ignore the port type.
1249 */
1250 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1251 {
1252 if (mctrl & TIOCM_LOOP) {
1253 struct plat_sci_reg *reg;
1254
1255 /*
1256 * Standard loopback mode for SCFCR ports.
1257 */
1258 reg = sci_getreg(port, SCFCR);
1259 if (reg->size)
1260 serial_port_out(port, SCFCR,
1261 serial_port_in(port, SCFCR) |
1262 SCFCR_LOOP);
1263 }
1264 }
1265
1266 static unsigned int sci_get_mctrl(struct uart_port *port)
1267 {
1268 /*
1269 * CTS/RTS is handled in hardware when supported, while nothing
1270 * else is wired up. Keep it simple and simply assert DSR/CAR.
1271 */
1272 return TIOCM_DSR | TIOCM_CAR;
1273 }
1274
1275 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1276 static void sci_dma_tx_complete(void *arg)
1277 {
1278 struct sci_port *s = arg;
1279 struct uart_port *port = &s->port;
1280 struct circ_buf *xmit = &port->state->xmit;
1281 unsigned long flags;
1282
1283 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1284
1285 spin_lock_irqsave(&port->lock, flags);
1286
1287 xmit->tail += sg_dma_len(&s->sg_tx);
1288 xmit->tail &= UART_XMIT_SIZE - 1;
1289
1290 port->icount.tx += sg_dma_len(&s->sg_tx);
1291
1292 async_tx_ack(s->desc_tx);
1293 s->desc_tx = NULL;
1294
1295 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1296 uart_write_wakeup(port);
1297
1298 if (!uart_circ_empty(xmit)) {
1299 s->cookie_tx = 0;
1300 schedule_work(&s->work_tx);
1301 } else {
1302 s->cookie_tx = -EINVAL;
1303 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1304 u16 ctrl = serial_port_in(port, SCSCR);
1305 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1306 }
1307 }
1308
1309 spin_unlock_irqrestore(&port->lock, flags);
1310 }
1311
1312 /* Locking: called with port lock held */
1313 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1314 {
1315 struct uart_port *port = &s->port;
1316 struct tty_port *tport = &port->state->port;
1317 int i, active, room;
1318
1319 room = tty_buffer_request_room(tport, count);
1320
1321 if (s->active_rx == s->cookie_rx[0]) {
1322 active = 0;
1323 } else if (s->active_rx == s->cookie_rx[1]) {
1324 active = 1;
1325 } else {
1326 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1327 return 0;
1328 }
1329
1330 if (room < count)
1331 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1332 count - room);
1333 if (!room)
1334 return room;
1335
1336 for (i = 0; i < room; i++)
1337 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1338 TTY_NORMAL);
1339
1340 port->icount.rx += room;
1341
1342 return room;
1343 }
1344
1345 static void sci_dma_rx_complete(void *arg)
1346 {
1347 struct sci_port *s = arg;
1348 struct uart_port *port = &s->port;
1349 unsigned long flags;
1350 int count;
1351
1352 dev_dbg(port->dev, "%s(%d) active #%d\n",
1353 __func__, port->line, s->active_rx);
1354
1355 spin_lock_irqsave(&port->lock, flags);
1356
1357 count = sci_dma_rx_push(s, s->buf_len_rx);
1358
1359 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1360
1361 spin_unlock_irqrestore(&port->lock, flags);
1362
1363 if (count)
1364 tty_flip_buffer_push(&port->state->port);
1365
1366 schedule_work(&s->work_rx);
1367 }
1368
1369 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1370 {
1371 struct dma_chan *chan = s->chan_rx;
1372 struct uart_port *port = &s->port;
1373
1374 s->chan_rx = NULL;
1375 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1376 dma_release_channel(chan);
1377 if (sg_dma_address(&s->sg_rx[0]))
1378 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1379 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1380 if (enable_pio)
1381 sci_start_rx(port);
1382 }
1383
1384 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1385 {
1386 struct dma_chan *chan = s->chan_tx;
1387 struct uart_port *port = &s->port;
1388
1389 s->chan_tx = NULL;
1390 s->cookie_tx = -EINVAL;
1391 dma_release_channel(chan);
1392 if (enable_pio)
1393 sci_start_tx(port);
1394 }
1395
1396 static void sci_submit_rx(struct sci_port *s)
1397 {
1398 struct dma_chan *chan = s->chan_rx;
1399 int i;
1400
1401 for (i = 0; i < 2; i++) {
1402 struct scatterlist *sg = &s->sg_rx[i];
1403 struct dma_async_tx_descriptor *desc;
1404
1405 desc = dmaengine_prep_slave_sg(chan,
1406 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1407
1408 if (desc) {
1409 s->desc_rx[i] = desc;
1410 desc->callback = sci_dma_rx_complete;
1411 desc->callback_param = s;
1412 s->cookie_rx[i] = desc->tx_submit(desc);
1413 }
1414
1415 if (!desc || s->cookie_rx[i] < 0) {
1416 if (i) {
1417 async_tx_ack(s->desc_rx[0]);
1418 s->cookie_rx[0] = -EINVAL;
1419 }
1420 if (desc) {
1421 async_tx_ack(desc);
1422 s->cookie_rx[i] = -EINVAL;
1423 }
1424 dev_warn(s->port.dev,
1425 "failed to re-start DMA, using PIO\n");
1426 sci_rx_dma_release(s, true);
1427 return;
1428 }
1429 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1430 __func__, s->cookie_rx[i], i);
1431 }
1432
1433 s->active_rx = s->cookie_rx[0];
1434
1435 dma_async_issue_pending(chan);
1436 }
1437
1438 static void work_fn_rx(struct work_struct *work)
1439 {
1440 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1441 struct uart_port *port = &s->port;
1442 struct dma_async_tx_descriptor *desc;
1443 int new;
1444
1445 if (s->active_rx == s->cookie_rx[0]) {
1446 new = 0;
1447 } else if (s->active_rx == s->cookie_rx[1]) {
1448 new = 1;
1449 } else {
1450 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1451 return;
1452 }
1453 desc = s->desc_rx[new];
1454
1455 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1456 DMA_COMPLETE) {
1457 /* Handle incomplete DMA receive */
1458 struct dma_chan *chan = s->chan_rx;
1459 struct shdma_desc *sh_desc = container_of(desc,
1460 struct shdma_desc, async_tx);
1461 unsigned long flags;
1462 int count;
1463
1464 dmaengine_terminate_all(chan);
1465 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1466 sh_desc->partial, sh_desc->cookie);
1467
1468 spin_lock_irqsave(&port->lock, flags);
1469 count = sci_dma_rx_push(s, sh_desc->partial);
1470 spin_unlock_irqrestore(&port->lock, flags);
1471
1472 if (count)
1473 tty_flip_buffer_push(&port->state->port);
1474
1475 sci_submit_rx(s);
1476
1477 return;
1478 }
1479
1480 s->cookie_rx[new] = desc->tx_submit(desc);
1481 if (s->cookie_rx[new] < 0) {
1482 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1483 sci_rx_dma_release(s, true);
1484 return;
1485 }
1486
1487 s->active_rx = s->cookie_rx[!new];
1488
1489 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1490 __func__, s->cookie_rx[new], new, s->active_rx);
1491 }
1492
1493 static void work_fn_tx(struct work_struct *work)
1494 {
1495 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1496 struct dma_async_tx_descriptor *desc;
1497 struct dma_chan *chan = s->chan_tx;
1498 struct uart_port *port = &s->port;
1499 struct circ_buf *xmit = &port->state->xmit;
1500 struct scatterlist *sg = &s->sg_tx;
1501
1502 /*
1503 * DMA is idle now.
1504 * Port xmit buffer is already mapped, and it is one page... Just adjust
1505 * offsets and lengths. Since it is a circular buffer, we have to
1506 * transmit till the end, and then the rest. Take the port lock to get a
1507 * consistent xmit buffer state.
1508 */
1509 spin_lock_irq(&port->lock);
1510 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1511 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1512 sg->offset;
1513 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1514 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1515 spin_unlock_irq(&port->lock);
1516
1517 BUG_ON(!sg_dma_len(sg));
1518
1519 desc = dmaengine_prep_slave_sg(chan,
1520 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1521 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1522 if (!desc) {
1523 /* switch to PIO */
1524 sci_tx_dma_release(s, true);
1525 return;
1526 }
1527
1528 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1529
1530 spin_lock_irq(&port->lock);
1531 s->desc_tx = desc;
1532 desc->callback = sci_dma_tx_complete;
1533 desc->callback_param = s;
1534 spin_unlock_irq(&port->lock);
1535 s->cookie_tx = desc->tx_submit(desc);
1536 if (s->cookie_tx < 0) {
1537 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1538 /* switch to PIO */
1539 sci_tx_dma_release(s, true);
1540 return;
1541 }
1542
1543 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1544 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1545
1546 dma_async_issue_pending(chan);
1547 }
1548 #endif
1549
1550 static void sci_start_tx(struct uart_port *port)
1551 {
1552 struct sci_port *s = to_sci_port(port);
1553 unsigned short ctrl;
1554
1555 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1556 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1557 u16 new, scr = serial_port_in(port, SCSCR);
1558 if (s->chan_tx)
1559 new = scr | SCSCR_TDRQE;
1560 else
1561 new = scr & ~SCSCR_TDRQE;
1562 if (new != scr)
1563 serial_port_out(port, SCSCR, new);
1564 }
1565
1566 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1567 s->cookie_tx < 0) {
1568 s->cookie_tx = 0;
1569 schedule_work(&s->work_tx);
1570 }
1571 #endif
1572
1573 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1574 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1575 ctrl = serial_port_in(port, SCSCR);
1576 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1577 }
1578 }
1579
1580 static void sci_stop_tx(struct uart_port *port)
1581 {
1582 unsigned short ctrl;
1583
1584 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1585 ctrl = serial_port_in(port, SCSCR);
1586
1587 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1588 ctrl &= ~SCSCR_TDRQE;
1589
1590 ctrl &= ~SCSCR_TIE;
1591
1592 serial_port_out(port, SCSCR, ctrl);
1593 }
1594
1595 static void sci_start_rx(struct uart_port *port)
1596 {
1597 unsigned short ctrl;
1598
1599 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1600
1601 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1602 ctrl &= ~SCSCR_RDRQE;
1603
1604 serial_port_out(port, SCSCR, ctrl);
1605 }
1606
1607 static void sci_stop_rx(struct uart_port *port)
1608 {
1609 unsigned short ctrl;
1610
1611 ctrl = serial_port_in(port, SCSCR);
1612
1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1614 ctrl &= ~SCSCR_RDRQE;
1615
1616 ctrl &= ~port_rx_irq_mask(port);
1617
1618 serial_port_out(port, SCSCR, ctrl);
1619 }
1620
1621 static void sci_break_ctl(struct uart_port *port, int break_state)
1622 {
1623 struct sci_port *s = to_sci_port(port);
1624 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1625 unsigned short scscr, scsptr;
1626
1627 /* check wheter the port has SCSPTR */
1628 if (!reg->size) {
1629 /*
1630 * Not supported by hardware. Most parts couple break and rx
1631 * interrupts together, with break detection always enabled.
1632 */
1633 return;
1634 }
1635
1636 scsptr = serial_port_in(port, SCSPTR);
1637 scscr = serial_port_in(port, SCSCR);
1638
1639 if (break_state == -1) {
1640 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1641 scscr &= ~SCSCR_TE;
1642 } else {
1643 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1644 scscr |= SCSCR_TE;
1645 }
1646
1647 serial_port_out(port, SCSPTR, scsptr);
1648 serial_port_out(port, SCSCR, scscr);
1649 }
1650
1651 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1652 static bool filter(struct dma_chan *chan, void *slave)
1653 {
1654 struct sh_dmae_slave *param = slave;
1655
1656 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1657 __func__, param->shdma_slave.slave_id);
1658
1659 chan->private = &param->shdma_slave;
1660 return true;
1661 }
1662
1663 static void rx_timer_fn(unsigned long arg)
1664 {
1665 struct sci_port *s = (struct sci_port *)arg;
1666 struct uart_port *port = &s->port;
1667 u16 scr = serial_port_in(port, SCSCR);
1668
1669 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1670 scr &= ~SCSCR_RDRQE;
1671 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1672 }
1673 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1674 dev_dbg(port->dev, "DMA Rx timed out\n");
1675 schedule_work(&s->work_rx);
1676 }
1677
1678 static void sci_request_dma(struct uart_port *port)
1679 {
1680 struct sci_port *s = to_sci_port(port);
1681 struct sh_dmae_slave *param;
1682 struct dma_chan *chan;
1683 dma_cap_mask_t mask;
1684 int nent;
1685
1686 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1687
1688 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1689 return;
1690
1691 dma_cap_zero(mask);
1692 dma_cap_set(DMA_SLAVE, mask);
1693
1694 param = &s->param_tx;
1695
1696 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1697 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1698
1699 s->cookie_tx = -EINVAL;
1700 chan = dma_request_channel(mask, filter, param);
1701 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1702 if (chan) {
1703 s->chan_tx = chan;
1704 sg_init_table(&s->sg_tx, 1);
1705 /* UART circular tx buffer is an aligned page. */
1706 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1707 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1708 UART_XMIT_SIZE,
1709 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1710 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1711 if (!nent)
1712 sci_tx_dma_release(s, false);
1713 else
1714 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1715 __func__,
1716 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1717 &sg_dma_address(&s->sg_tx));
1718
1719 s->sg_len_tx = nent;
1720
1721 INIT_WORK(&s->work_tx, work_fn_tx);
1722 }
1723
1724 param = &s->param_rx;
1725
1726 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1727 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1728
1729 chan = dma_request_channel(mask, filter, param);
1730 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1731 if (chan) {
1732 dma_addr_t dma[2];
1733 void *buf[2];
1734 int i;
1735
1736 s->chan_rx = chan;
1737
1738 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1739 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1740 &dma[0], GFP_KERNEL);
1741
1742 if (!buf[0]) {
1743 dev_warn(port->dev,
1744 "failed to allocate dma buffer, using PIO\n");
1745 sci_rx_dma_release(s, true);
1746 return;
1747 }
1748
1749 buf[1] = buf[0] + s->buf_len_rx;
1750 dma[1] = dma[0] + s->buf_len_rx;
1751
1752 for (i = 0; i < 2; i++) {
1753 struct scatterlist *sg = &s->sg_rx[i];
1754
1755 sg_init_table(sg, 1);
1756 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1757 (uintptr_t)buf[i] & ~PAGE_MASK);
1758 sg_dma_address(sg) = dma[i];
1759 }
1760
1761 INIT_WORK(&s->work_rx, work_fn_rx);
1762 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1763
1764 sci_submit_rx(s);
1765 }
1766 }
1767
1768 static void sci_free_dma(struct uart_port *port)
1769 {
1770 struct sci_port *s = to_sci_port(port);
1771
1772 if (s->chan_tx)
1773 sci_tx_dma_release(s, false);
1774 if (s->chan_rx)
1775 sci_rx_dma_release(s, false);
1776 }
1777 #else
1778 static inline void sci_request_dma(struct uart_port *port)
1779 {
1780 }
1781
1782 static inline void sci_free_dma(struct uart_port *port)
1783 {
1784 }
1785 #endif
1786
1787 static int sci_startup(struct uart_port *port)
1788 {
1789 struct sci_port *s = to_sci_port(port);
1790 unsigned long flags;
1791 int ret;
1792
1793 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1794
1795 ret = sci_request_irq(s);
1796 if (unlikely(ret < 0))
1797 return ret;
1798
1799 sci_request_dma(port);
1800
1801 spin_lock_irqsave(&port->lock, flags);
1802 sci_start_tx(port);
1803 sci_start_rx(port);
1804 spin_unlock_irqrestore(&port->lock, flags);
1805
1806 return 0;
1807 }
1808
1809 static void sci_shutdown(struct uart_port *port)
1810 {
1811 struct sci_port *s = to_sci_port(port);
1812 unsigned long flags;
1813
1814 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1815
1816 spin_lock_irqsave(&port->lock, flags);
1817 sci_stop_rx(port);
1818 sci_stop_tx(port);
1819 spin_unlock_irqrestore(&port->lock, flags);
1820
1821 sci_free_dma(port);
1822 sci_free_irq(s);
1823 }
1824
1825 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1826 unsigned long freq)
1827 {
1828 if (s->sampling_rate)
1829 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1830
1831 /* Warn, but use a safe default */
1832 WARN_ON(1);
1833
1834 return ((freq + 16 * bps) / (32 * bps) - 1);
1835 }
1836
1837 /* calculate frame length from SMR */
1838 static int sci_baud_calc_frame_len(unsigned int smr_val)
1839 {
1840 int len = 10;
1841
1842 if (smr_val & SCSMR_CHR)
1843 len--;
1844 if (smr_val & SCSMR_PE)
1845 len++;
1846 if (smr_val & SCSMR_STOP)
1847 len++;
1848
1849 return len;
1850 }
1851
1852
1853 /* calculate sample rate, BRR, and clock select for HSCIF */
1854 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1855 int *brr, unsigned int *srr,
1856 unsigned int *cks, int frame_len)
1857 {
1858 int sr, c, br, err, recv_margin;
1859 int min_err = 1000; /* 100% */
1860 int recv_max_margin = 0;
1861
1862 /* Find the combination of sample rate and clock select with the
1863 smallest deviation from the desired baud rate. */
1864 for (sr = 8; sr <= 32; sr++) {
1865 for (c = 0; c <= 3; c++) {
1866 /* integerized formulas from HSCIF documentation */
1867 br = DIV_ROUND_CLOSEST(freq, (sr *
1868 (1 << (2 * c + 1)) * bps)) - 1;
1869 br = clamp(br, 0, 255);
1870 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1871 (1 << (2 * c + 1)) / 1000)) -
1872 1000;
1873 /* Calc recv margin
1874 * M: Receive margin (%)
1875 * N: Ratio of bit rate to clock (N = sampling rate)
1876 * D: Clock duty (D = 0 to 1.0)
1877 * L: Frame length (L = 9 to 12)
1878 * F: Absolute value of clock frequency deviation
1879 *
1880 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1881 * (|D - 0.5| / N * (1 + F))|
1882 * NOTE: Usually, treat D for 0.5, F is 0 by this
1883 * calculation.
1884 */
1885 recv_margin = abs((500 -
1886 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1887 if (abs(min_err) > abs(err)) {
1888 min_err = err;
1889 recv_max_margin = recv_margin;
1890 } else if ((min_err == err) &&
1891 (recv_margin > recv_max_margin))
1892 recv_max_margin = recv_margin;
1893 else
1894 continue;
1895
1896 *brr = br;
1897 *srr = sr - 1;
1898 *cks = c;
1899 }
1900 }
1901
1902 if (min_err == 1000) {
1903 WARN_ON(1);
1904 /* use defaults */
1905 *brr = 255;
1906 *srr = 15;
1907 *cks = 0;
1908 }
1909 }
1910
1911 static void sci_reset(struct uart_port *port)
1912 {
1913 struct plat_sci_reg *reg;
1914 unsigned int status;
1915
1916 do {
1917 status = serial_port_in(port, SCxSR);
1918 } while (!(status & SCxSR_TEND(port)));
1919
1920 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1921
1922 reg = sci_getreg(port, SCFCR);
1923 if (reg->size)
1924 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1925 }
1926
1927 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1928 struct ktermios *old)
1929 {
1930 struct sci_port *s = to_sci_port(port);
1931 struct plat_sci_reg *reg;
1932 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1933 int t = -1;
1934 unsigned int srr = 15;
1935
1936 if ((termios->c_cflag & CSIZE) == CS7)
1937 smr_val |= SCSMR_CHR;
1938 if (termios->c_cflag & PARENB)
1939 smr_val |= SCSMR_PE;
1940 if (termios->c_cflag & PARODD)
1941 smr_val |= SCSMR_PE | SCSMR_ODD;
1942 if (termios->c_cflag & CSTOPB)
1943 smr_val |= SCSMR_STOP;
1944
1945 /*
1946 * earlyprintk comes here early on with port->uartclk set to zero.
1947 * the clock framework is not up and running at this point so here
1948 * we assume that 115200 is the maximum baud rate. please note that
1949 * the baud rate is not programmed during earlyprintk - it is assumed
1950 * that the previous boot loader has enabled required clocks and
1951 * setup the baud rate generator hardware for us already.
1952 */
1953 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1954
1955 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1956 if (likely(baud && port->uartclk)) {
1957 if (s->cfg->type == PORT_HSCIF) {
1958 int frame_len = sci_baud_calc_frame_len(smr_val);
1959 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1960 &cks, frame_len);
1961 } else {
1962 t = sci_scbrr_calc(s, baud, port->uartclk);
1963 for (cks = 0; t >= 256 && cks <= 3; cks++)
1964 t >>= 2;
1965 }
1966 }
1967
1968 sci_port_enable(s);
1969
1970 sci_reset(port);
1971
1972 smr_val |= serial_port_in(port, SCSMR) & 3;
1973
1974 uart_update_timeout(port, termios->c_cflag, baud);
1975
1976 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1977 __func__, smr_val, cks, t, s->cfg->scscr);
1978
1979 if (t >= 0) {
1980 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1981 serial_port_out(port, SCBRR, t);
1982 reg = sci_getreg(port, HSSRR);
1983 if (reg->size)
1984 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1985 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1986 } else
1987 serial_port_out(port, SCSMR, smr_val);
1988
1989 sci_init_pins(port, termios->c_cflag);
1990
1991 reg = sci_getreg(port, SCFCR);
1992 if (reg->size) {
1993 unsigned short ctrl = serial_port_in(port, SCFCR);
1994
1995 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1996 if (termios->c_cflag & CRTSCTS)
1997 ctrl |= SCFCR_MCE;
1998 else
1999 ctrl &= ~SCFCR_MCE;
2000 }
2001
2002 /*
2003 * As we've done a sci_reset() above, ensure we don't
2004 * interfere with the FIFOs while toggling MCE. As the
2005 * reset values could still be set, simply mask them out.
2006 */
2007 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2008
2009 serial_port_out(port, SCFCR, ctrl);
2010 }
2011
2012 serial_port_out(port, SCSCR, s->cfg->scscr);
2013
2014 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2015 /*
2016 * Calculate delay for 2 DMA buffers (4 FIFO).
2017 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
2018 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
2019 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
2020 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2021 * sizes), but when performing a faster transfer, value obtained by
2022 * this formula is may not enough. Therefore, if value is smaller than
2023 * 20msec, this sets 20msec as timeout of DMA.
2024 */
2025 if (s->chan_rx) {
2026 unsigned int bits;
2027
2028 /* byte size and parity */
2029 switch (termios->c_cflag & CSIZE) {
2030 case CS5:
2031 bits = 7;
2032 break;
2033 case CS6:
2034 bits = 8;
2035 break;
2036 case CS7:
2037 bits = 9;
2038 break;
2039 default:
2040 bits = 10;
2041 break;
2042 }
2043
2044 if (termios->c_cflag & CSTOPB)
2045 bits++;
2046 if (termios->c_cflag & PARENB)
2047 bits++;
2048 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2049 (baud / 10), 10);
2050 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2051 s->rx_timeout * 1000 / HZ, port->timeout);
2052 if (s->rx_timeout < msecs_to_jiffies(20))
2053 s->rx_timeout = msecs_to_jiffies(20);
2054 }
2055 #endif
2056
2057 if ((termios->c_cflag & CREAD) != 0)
2058 sci_start_rx(port);
2059
2060 sci_port_disable(s);
2061 }
2062
2063 static void sci_pm(struct uart_port *port, unsigned int state,
2064 unsigned int oldstate)
2065 {
2066 struct sci_port *sci_port = to_sci_port(port);
2067
2068 switch (state) {
2069 case UART_PM_STATE_OFF:
2070 sci_port_disable(sci_port);
2071 break;
2072 default:
2073 sci_port_enable(sci_port);
2074 break;
2075 }
2076 }
2077
2078 static const char *sci_type(struct uart_port *port)
2079 {
2080 switch (port->type) {
2081 case PORT_IRDA:
2082 return "irda";
2083 case PORT_SCI:
2084 return "sci";
2085 case PORT_SCIF:
2086 return "scif";
2087 case PORT_SCIFA:
2088 return "scifa";
2089 case PORT_SCIFB:
2090 return "scifb";
2091 case PORT_HSCIF:
2092 return "hscif";
2093 }
2094
2095 return NULL;
2096 }
2097
2098 static inline unsigned long sci_port_size(struct uart_port *port)
2099 {
2100 /*
2101 * Pick an arbitrary size that encapsulates all of the base
2102 * registers by default. This can be optimized later, or derived
2103 * from platform resource data at such a time that ports begin to
2104 * behave more erratically.
2105 */
2106 if (port->type == PORT_HSCIF)
2107 return 96;
2108 else
2109 return 64;
2110 }
2111
2112 static int sci_remap_port(struct uart_port *port)
2113 {
2114 unsigned long size = sci_port_size(port);
2115
2116 /*
2117 * Nothing to do if there's already an established membase.
2118 */
2119 if (port->membase)
2120 return 0;
2121
2122 if (port->flags & UPF_IOREMAP) {
2123 port->membase = ioremap_nocache(port->mapbase, size);
2124 if (unlikely(!port->membase)) {
2125 dev_err(port->dev, "can't remap port#%d\n", port->line);
2126 return -ENXIO;
2127 }
2128 } else {
2129 /*
2130 * For the simple (and majority of) cases where we don't
2131 * need to do any remapping, just cast the cookie
2132 * directly.
2133 */
2134 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2135 }
2136
2137 return 0;
2138 }
2139
2140 static void sci_release_port(struct uart_port *port)
2141 {
2142 if (port->flags & UPF_IOREMAP) {
2143 iounmap(port->membase);
2144 port->membase = NULL;
2145 }
2146
2147 release_mem_region(port->mapbase, sci_port_size(port));
2148 }
2149
2150 static int sci_request_port(struct uart_port *port)
2151 {
2152 unsigned long size = sci_port_size(port);
2153 struct resource *res;
2154 int ret;
2155
2156 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2157 if (unlikely(res == NULL))
2158 return -EBUSY;
2159
2160 ret = sci_remap_port(port);
2161 if (unlikely(ret != 0)) {
2162 release_resource(res);
2163 return ret;
2164 }
2165
2166 return 0;
2167 }
2168
2169 static void sci_config_port(struct uart_port *port, int flags)
2170 {
2171 if (flags & UART_CONFIG_TYPE) {
2172 struct sci_port *sport = to_sci_port(port);
2173
2174 port->type = sport->cfg->type;
2175 sci_request_port(port);
2176 }
2177 }
2178
2179 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2180 {
2181 if (ser->baud_base < 2400)
2182 /* No paper tape reader for Mitch.. */
2183 return -EINVAL;
2184
2185 return 0;
2186 }
2187
2188 static struct uart_ops sci_uart_ops = {
2189 .tx_empty = sci_tx_empty,
2190 .set_mctrl = sci_set_mctrl,
2191 .get_mctrl = sci_get_mctrl,
2192 .start_tx = sci_start_tx,
2193 .stop_tx = sci_stop_tx,
2194 .stop_rx = sci_stop_rx,
2195 .break_ctl = sci_break_ctl,
2196 .startup = sci_startup,
2197 .shutdown = sci_shutdown,
2198 .set_termios = sci_set_termios,
2199 .pm = sci_pm,
2200 .type = sci_type,
2201 .release_port = sci_release_port,
2202 .request_port = sci_request_port,
2203 .config_port = sci_config_port,
2204 .verify_port = sci_verify_port,
2205 #ifdef CONFIG_CONSOLE_POLL
2206 .poll_get_char = sci_poll_get_char,
2207 .poll_put_char = sci_poll_put_char,
2208 #endif
2209 };
2210
2211 static int sci_init_single(struct platform_device *dev,
2212 struct sci_port *sci_port, unsigned int index,
2213 struct plat_sci_port *p, bool early)
2214 {
2215 struct uart_port *port = &sci_port->port;
2216 const struct resource *res;
2217 unsigned int sampling_rate;
2218 unsigned int i;
2219 int ret;
2220
2221 sci_port->cfg = p;
2222
2223 port->ops = &sci_uart_ops;
2224 port->iotype = UPIO_MEM;
2225 port->line = index;
2226
2227 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2228 if (res == NULL)
2229 return -ENOMEM;
2230
2231 port->mapbase = res->start;
2232
2233 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2234 sci_port->irqs[i] = platform_get_irq(dev, i);
2235
2236 /* The SCI generates several interrupts. They can be muxed together or
2237 * connected to different interrupt lines. In the muxed case only one
2238 * interrupt resource is specified. In the non-muxed case three or four
2239 * interrupt resources are specified, as the BRI interrupt is optional.
2240 */
2241 if (sci_port->irqs[0] < 0)
2242 return -ENXIO;
2243
2244 if (sci_port->irqs[1] < 0) {
2245 sci_port->irqs[1] = sci_port->irqs[0];
2246 sci_port->irqs[2] = sci_port->irqs[0];
2247 sci_port->irqs[3] = sci_port->irqs[0];
2248 }
2249
2250 if (p->regtype == SCIx_PROBE_REGTYPE) {
2251 ret = sci_probe_regmap(p);
2252 if (unlikely(ret))
2253 return ret;
2254 }
2255
2256 switch (p->type) {
2257 case PORT_SCIFB:
2258 port->fifosize = 256;
2259 sci_port->overrun_bit = 9;
2260 sampling_rate = 16;
2261 break;
2262 case PORT_HSCIF:
2263 port->fifosize = 128;
2264 sampling_rate = 0;
2265 sci_port->overrun_bit = 0;
2266 break;
2267 case PORT_SCIFA:
2268 port->fifosize = 64;
2269 sci_port->overrun_bit = 9;
2270 sampling_rate = 16;
2271 break;
2272 case PORT_SCIF:
2273 port->fifosize = 16;
2274 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2275 sci_port->overrun_bit = 9;
2276 sampling_rate = 16;
2277 } else {
2278 sci_port->overrun_bit = 0;
2279 sampling_rate = 32;
2280 }
2281 break;
2282 default:
2283 port->fifosize = 1;
2284 sci_port->overrun_bit = 5;
2285 sampling_rate = 32;
2286 break;
2287 }
2288
2289 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2290 * match the SoC datasheet, this should be investigated. Let platform
2291 * data override the sampling rate for now.
2292 */
2293 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2294 : sampling_rate;
2295
2296 if (!early) {
2297 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2298 if (IS_ERR(sci_port->iclk)) {
2299 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2300 if (IS_ERR(sci_port->iclk)) {
2301 dev_err(&dev->dev, "can't get iclk\n");
2302 return PTR_ERR(sci_port->iclk);
2303 }
2304 }
2305
2306 /*
2307 * The function clock is optional, ignore it if we can't
2308 * find it.
2309 */
2310 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2311 if (IS_ERR(sci_port->fclk))
2312 sci_port->fclk = NULL;
2313
2314 port->dev = &dev->dev;
2315
2316 pm_runtime_enable(&dev->dev);
2317 }
2318
2319 sci_port->break_timer.data = (unsigned long)sci_port;
2320 sci_port->break_timer.function = sci_break_timer;
2321 init_timer(&sci_port->break_timer);
2322
2323 /*
2324 * Establish some sensible defaults for the error detection.
2325 */
2326 sci_port->error_mask = (p->type == PORT_SCI) ?
2327 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2328
2329 /*
2330 * Establish sensible defaults for the overrun detection, unless
2331 * the part has explicitly disabled support for it.
2332 */
2333
2334 /*
2335 * Make the error mask inclusive of overrun detection, if
2336 * supported.
2337 */
2338 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2339
2340 port->type = p->type;
2341 port->flags = UPF_FIXED_PORT | p->flags;
2342 port->regshift = p->regshift;
2343
2344 /*
2345 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2346 * for the multi-IRQ ports, which is where we are primarily
2347 * concerned with the shutdown path synchronization.
2348 *
2349 * For the muxed case there's nothing more to do.
2350 */
2351 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2352 port->irqflags = 0;
2353
2354 port->serial_in = sci_serial_in;
2355 port->serial_out = sci_serial_out;
2356
2357 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2358 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2359 p->dma_slave_tx, p->dma_slave_rx);
2360
2361 return 0;
2362 }
2363
2364 static void sci_cleanup_single(struct sci_port *port)
2365 {
2366 clk_put(port->iclk);
2367 clk_put(port->fclk);
2368
2369 pm_runtime_disable(port->port.dev);
2370 }
2371
2372 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2373 static void serial_console_putchar(struct uart_port *port, int ch)
2374 {
2375 sci_poll_put_char(port, ch);
2376 }
2377
2378 /*
2379 * Print a string to the serial port trying not to disturb
2380 * any possible real use of the port...
2381 */
2382 static void serial_console_write(struct console *co, const char *s,
2383 unsigned count)
2384 {
2385 struct sci_port *sci_port = &sci_ports[co->index];
2386 struct uart_port *port = &sci_port->port;
2387 unsigned short bits, ctrl;
2388 unsigned long flags;
2389 int locked = 1;
2390
2391 local_irq_save(flags);
2392 if (port->sysrq)
2393 locked = 0;
2394 else if (oops_in_progress)
2395 locked = spin_trylock(&port->lock);
2396 else
2397 spin_lock(&port->lock);
2398
2399 /* first save the SCSCR then disable the interrupts */
2400 ctrl = serial_port_in(port, SCSCR);
2401 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2402
2403 uart_console_write(port, s, count, serial_console_putchar);
2404
2405 /* wait until fifo is empty and last bit has been transmitted */
2406 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2407 while ((serial_port_in(port, SCxSR) & bits) != bits)
2408 cpu_relax();
2409
2410 /* restore the SCSCR */
2411 serial_port_out(port, SCSCR, ctrl);
2412
2413 if (locked)
2414 spin_unlock(&port->lock);
2415 local_irq_restore(flags);
2416 }
2417
2418 static int serial_console_setup(struct console *co, char *options)
2419 {
2420 struct sci_port *sci_port;
2421 struct uart_port *port;
2422 int baud = 115200;
2423 int bits = 8;
2424 int parity = 'n';
2425 int flow = 'n';
2426 int ret;
2427
2428 /*
2429 * Refuse to handle any bogus ports.
2430 */
2431 if (co->index < 0 || co->index >= SCI_NPORTS)
2432 return -ENODEV;
2433
2434 sci_port = &sci_ports[co->index];
2435 port = &sci_port->port;
2436
2437 /*
2438 * Refuse to handle uninitialized ports.
2439 */
2440 if (!port->ops)
2441 return -ENODEV;
2442
2443 ret = sci_remap_port(port);
2444 if (unlikely(ret != 0))
2445 return ret;
2446
2447 if (options)
2448 uart_parse_options(options, &baud, &parity, &bits, &flow);
2449
2450 return uart_set_options(port, co, baud, parity, bits, flow);
2451 }
2452
2453 static struct console serial_console = {
2454 .name = "ttySC",
2455 .device = uart_console_device,
2456 .write = serial_console_write,
2457 .setup = serial_console_setup,
2458 .flags = CON_PRINTBUFFER,
2459 .index = -1,
2460 .data = &sci_uart_driver,
2461 };
2462
2463 static struct console early_serial_console = {
2464 .name = "early_ttySC",
2465 .write = serial_console_write,
2466 .flags = CON_PRINTBUFFER,
2467 .index = -1,
2468 };
2469
2470 static char early_serial_buf[32];
2471
2472 static int sci_probe_earlyprintk(struct platform_device *pdev)
2473 {
2474 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2475
2476 if (early_serial_console.data)
2477 return -EEXIST;
2478
2479 early_serial_console.index = pdev->id;
2480
2481 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2482
2483 serial_console_setup(&early_serial_console, early_serial_buf);
2484
2485 if (!strstr(early_serial_buf, "keep"))
2486 early_serial_console.flags |= CON_BOOT;
2487
2488 register_console(&early_serial_console);
2489 return 0;
2490 }
2491
2492 #define SCI_CONSOLE (&serial_console)
2493
2494 #else
2495 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2496 {
2497 return -EINVAL;
2498 }
2499
2500 #define SCI_CONSOLE NULL
2501
2502 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2503
2504 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2505
2506 static struct uart_driver sci_uart_driver = {
2507 .owner = THIS_MODULE,
2508 .driver_name = "sci",
2509 .dev_name = "ttySC",
2510 .major = SCI_MAJOR,
2511 .minor = SCI_MINOR_START,
2512 .nr = SCI_NPORTS,
2513 .cons = SCI_CONSOLE,
2514 };
2515
2516 static int sci_remove(struct platform_device *dev)
2517 {
2518 struct sci_port *port = platform_get_drvdata(dev);
2519
2520 cpufreq_unregister_notifier(&port->freq_transition,
2521 CPUFREQ_TRANSITION_NOTIFIER);
2522
2523 uart_remove_one_port(&sci_uart_driver, &port->port);
2524
2525 sci_cleanup_single(port);
2526
2527 return 0;
2528 }
2529
2530 struct sci_port_info {
2531 unsigned int type;
2532 unsigned int regtype;
2533 };
2534
2535 static const struct of_device_id of_sci_match[] = {
2536 {
2537 .compatible = "renesas,scif",
2538 .data = &(const struct sci_port_info) {
2539 .type = PORT_SCIF,
2540 .regtype = SCIx_SH4_SCIF_REGTYPE,
2541 },
2542 }, {
2543 .compatible = "renesas,scifa",
2544 .data = &(const struct sci_port_info) {
2545 .type = PORT_SCIFA,
2546 .regtype = SCIx_SCIFA_REGTYPE,
2547 },
2548 }, {
2549 .compatible = "renesas,scifb",
2550 .data = &(const struct sci_port_info) {
2551 .type = PORT_SCIFB,
2552 .regtype = SCIx_SCIFB_REGTYPE,
2553 },
2554 }, {
2555 .compatible = "renesas,hscif",
2556 .data = &(const struct sci_port_info) {
2557 .type = PORT_HSCIF,
2558 .regtype = SCIx_HSCIF_REGTYPE,
2559 },
2560 }, {
2561 /* Terminator */
2562 },
2563 };
2564 MODULE_DEVICE_TABLE(of, of_sci_match);
2565
2566 static struct plat_sci_port *
2567 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2568 {
2569 struct device_node *np = pdev->dev.of_node;
2570 const struct of_device_id *match;
2571 const struct sci_port_info *info;
2572 struct plat_sci_port *p;
2573 int id;
2574
2575 if (!IS_ENABLED(CONFIG_OF) || !np)
2576 return NULL;
2577
2578 match = of_match_node(of_sci_match, pdev->dev.of_node);
2579 if (!match)
2580 return NULL;
2581
2582 info = match->data;
2583
2584 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2585 if (!p) {
2586 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2587 return NULL;
2588 }
2589
2590 /* Get the line number for the aliases node. */
2591 id = of_alias_get_id(np, "serial");
2592 if (id < 0) {
2593 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2594 return NULL;
2595 }
2596
2597 *dev_id = id;
2598
2599 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2600 p->type = info->type;
2601 p->regtype = info->regtype;
2602 p->scscr = SCSCR_RE | SCSCR_TE;
2603
2604 return p;
2605 }
2606
2607 static int sci_probe_single(struct platform_device *dev,
2608 unsigned int index,
2609 struct plat_sci_port *p,
2610 struct sci_port *sciport)
2611 {
2612 int ret;
2613
2614 /* Sanity check */
2615 if (unlikely(index >= SCI_NPORTS)) {
2616 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2617 index+1, SCI_NPORTS);
2618 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2619 return -EINVAL;
2620 }
2621
2622 ret = sci_init_single(dev, sciport, index, p, false);
2623 if (ret)
2624 return ret;
2625
2626 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2627 if (ret) {
2628 sci_cleanup_single(sciport);
2629 return ret;
2630 }
2631
2632 return 0;
2633 }
2634
2635 static int sci_probe(struct platform_device *dev)
2636 {
2637 struct plat_sci_port *p;
2638 struct sci_port *sp;
2639 unsigned int dev_id;
2640 int ret;
2641
2642 /*
2643 * If we've come here via earlyprintk initialization, head off to
2644 * the special early probe. We don't have sufficient device state
2645 * to make it beyond this yet.
2646 */
2647 if (is_early_platform_device(dev))
2648 return sci_probe_earlyprintk(dev);
2649
2650 if (dev->dev.of_node) {
2651 p = sci_parse_dt(dev, &dev_id);
2652 if (p == NULL)
2653 return -EINVAL;
2654 } else {
2655 p = dev->dev.platform_data;
2656 if (p == NULL) {
2657 dev_err(&dev->dev, "no platform data supplied\n");
2658 return -EINVAL;
2659 }
2660
2661 dev_id = dev->id;
2662 }
2663
2664 sp = &sci_ports[dev_id];
2665 platform_set_drvdata(dev, sp);
2666
2667 ret = sci_probe_single(dev, dev_id, p, sp);
2668 if (ret)
2669 return ret;
2670
2671 sp->freq_transition.notifier_call = sci_notifier;
2672
2673 ret = cpufreq_register_notifier(&sp->freq_transition,
2674 CPUFREQ_TRANSITION_NOTIFIER);
2675 if (unlikely(ret < 0)) {
2676 uart_remove_one_port(&sci_uart_driver, &sp->port);
2677 sci_cleanup_single(sp);
2678 return ret;
2679 }
2680
2681 #ifdef CONFIG_SH_STANDARD_BIOS
2682 sh_bios_gdb_detach();
2683 #endif
2684
2685 return 0;
2686 }
2687
2688 static __maybe_unused int sci_suspend(struct device *dev)
2689 {
2690 struct sci_port *sport = dev_get_drvdata(dev);
2691
2692 if (sport)
2693 uart_suspend_port(&sci_uart_driver, &sport->port);
2694
2695 return 0;
2696 }
2697
2698 static __maybe_unused int sci_resume(struct device *dev)
2699 {
2700 struct sci_port *sport = dev_get_drvdata(dev);
2701
2702 if (sport)
2703 uart_resume_port(&sci_uart_driver, &sport->port);
2704
2705 return 0;
2706 }
2707
2708 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2709
2710 static struct platform_driver sci_driver = {
2711 .probe = sci_probe,
2712 .remove = sci_remove,
2713 .driver = {
2714 .name = "sh-sci",
2715 .pm = &sci_dev_pm_ops,
2716 .of_match_table = of_match_ptr(of_sci_match),
2717 },
2718 };
2719
2720 static int __init sci_init(void)
2721 {
2722 int ret;
2723
2724 pr_info("%s\n", banner);
2725
2726 ret = uart_register_driver(&sci_uart_driver);
2727 if (likely(ret == 0)) {
2728 ret = platform_driver_register(&sci_driver);
2729 if (unlikely(ret))
2730 uart_unregister_driver(&sci_uart_driver);
2731 }
2732
2733 return ret;
2734 }
2735
2736 static void __exit sci_exit(void)
2737 {
2738 platform_driver_unregister(&sci_driver);
2739 uart_unregister_driver(&sci_uart_driver);
2740 }
2741
2742 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2743 early_platform_init_buffer("earlyprintk", &sci_driver,
2744 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2745 #endif
2746 module_init(sci_init);
2747 module_exit(sci_exit);
2748
2749 MODULE_LICENSE("GPL");
2750 MODULE_ALIAS("platform:sh-sci");
2751 MODULE_AUTHOR("Paul Mundt");
2752 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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