2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ
= SCIx_NR_IRQS
, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port
;
82 /* Platform configuration */
83 struct plat_sci_port
*cfg
;
85 unsigned int error_mask
;
86 unsigned int sampling_rate
;
90 struct timer_list break_timer
;
98 int irqs
[SCIx_NR_IRQS
];
99 char *irqstr
[SCIx_NR_IRQS
];
101 struct dma_chan
*chan_tx
;
102 struct dma_chan
*chan_rx
;
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 struct dma_async_tx_descriptor
*desc_tx
;
106 struct dma_async_tx_descriptor
*desc_rx
[2];
107 dma_cookie_t cookie_tx
;
108 dma_cookie_t cookie_rx
[2];
109 dma_cookie_t active_rx
;
110 struct scatterlist sg_tx
;
111 unsigned int sg_len_tx
;
112 struct scatterlist sg_rx
[2];
114 struct sh_dmae_slave param_tx
;
115 struct sh_dmae_slave param_rx
;
116 struct work_struct work_tx
;
117 struct work_struct work_rx
;
118 struct timer_list rx_timer
;
119 unsigned int rx_timeout
;
122 struct notifier_block freq_transition
;
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port
*port
);
127 static void sci_stop_tx(struct uart_port
*port
);
128 static void sci_start_rx(struct uart_port
*port
);
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
132 static struct sci_port sci_ports
[SCI_NPORTS
];
133 static struct uart_driver sci_uart_driver
;
135 static inline struct sci_port
*
136 to_sci_port(struct uart_port
*uart
)
138 return container_of(uart
, struct sci_port
, port
);
141 struct plat_sci_reg
{
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
148 static struct plat_sci_reg sci_regmap
[SCIx_NR_REGTYPES
][SCIx_NR_REGS
] = {
149 [SCIx_PROBE_REGTYPE
] = {
150 [0 ... SCIx_NR_REGS
- 1] = sci_reg_invalid
,
154 * Common SCI definitions, dependent on the port's regshift
157 [SCIx_SCI_REGTYPE
] = {
158 [SCSMR
] = { 0x00, 8 },
159 [SCBRR
] = { 0x01, 8 },
160 [SCSCR
] = { 0x02, 8 },
161 [SCxTDR
] = { 0x03, 8 },
162 [SCxSR
] = { 0x04, 8 },
163 [SCxRDR
] = { 0x05, 8 },
164 [SCFCR
] = sci_reg_invalid
,
165 [SCFDR
] = sci_reg_invalid
,
166 [SCTFDR
] = sci_reg_invalid
,
167 [SCRFDR
] = sci_reg_invalid
,
168 [SCSPTR
] = sci_reg_invalid
,
169 [SCLSR
] = sci_reg_invalid
,
170 [HSSRR
] = sci_reg_invalid
,
171 [SCPCR
] = sci_reg_invalid
,
172 [SCPDR
] = sci_reg_invalid
,
176 * Common definitions for legacy IrDA ports, dependent on
179 [SCIx_IRDA_REGTYPE
] = {
180 [SCSMR
] = { 0x00, 8 },
181 [SCBRR
] = { 0x01, 8 },
182 [SCSCR
] = { 0x02, 8 },
183 [SCxTDR
] = { 0x03, 8 },
184 [SCxSR
] = { 0x04, 8 },
185 [SCxRDR
] = { 0x05, 8 },
186 [SCFCR
] = { 0x06, 8 },
187 [SCFDR
] = { 0x07, 16 },
188 [SCTFDR
] = sci_reg_invalid
,
189 [SCRFDR
] = sci_reg_invalid
,
190 [SCSPTR
] = sci_reg_invalid
,
191 [SCLSR
] = sci_reg_invalid
,
192 [HSSRR
] = sci_reg_invalid
,
193 [SCPCR
] = sci_reg_invalid
,
194 [SCPDR
] = sci_reg_invalid
,
198 * Common SCIFA definitions.
200 [SCIx_SCIFA_REGTYPE
] = {
201 [SCSMR
] = { 0x00, 16 },
202 [SCBRR
] = { 0x04, 8 },
203 [SCSCR
] = { 0x08, 16 },
204 [SCxTDR
] = { 0x20, 8 },
205 [SCxSR
] = { 0x14, 16 },
206 [SCxRDR
] = { 0x24, 8 },
207 [SCFCR
] = { 0x18, 16 },
208 [SCFDR
] = { 0x1c, 16 },
209 [SCTFDR
] = sci_reg_invalid
,
210 [SCRFDR
] = sci_reg_invalid
,
211 [SCSPTR
] = sci_reg_invalid
,
212 [SCLSR
] = sci_reg_invalid
,
213 [HSSRR
] = sci_reg_invalid
,
214 [SCPCR
] = { 0x30, 16 },
215 [SCPDR
] = { 0x34, 16 },
219 * Common SCIFB definitions.
221 [SCIx_SCIFB_REGTYPE
] = {
222 [SCSMR
] = { 0x00, 16 },
223 [SCBRR
] = { 0x04, 8 },
224 [SCSCR
] = { 0x08, 16 },
225 [SCxTDR
] = { 0x40, 8 },
226 [SCxSR
] = { 0x14, 16 },
227 [SCxRDR
] = { 0x60, 8 },
228 [SCFCR
] = { 0x18, 16 },
229 [SCFDR
] = sci_reg_invalid
,
230 [SCTFDR
] = { 0x38, 16 },
231 [SCRFDR
] = { 0x3c, 16 },
232 [SCSPTR
] = sci_reg_invalid
,
233 [SCLSR
] = sci_reg_invalid
,
234 [HSSRR
] = sci_reg_invalid
,
235 [SCPCR
] = { 0x30, 16 },
236 [SCPDR
] = { 0x34, 16 },
240 * Common SH-2(A) SCIF definitions for ports with FIFO data
243 [SCIx_SH2_SCIF_FIFODATA_REGTYPE
] = {
244 [SCSMR
] = { 0x00, 16 },
245 [SCBRR
] = { 0x04, 8 },
246 [SCSCR
] = { 0x08, 16 },
247 [SCxTDR
] = { 0x0c, 8 },
248 [SCxSR
] = { 0x10, 16 },
249 [SCxRDR
] = { 0x14, 8 },
250 [SCFCR
] = { 0x18, 16 },
251 [SCFDR
] = { 0x1c, 16 },
252 [SCTFDR
] = sci_reg_invalid
,
253 [SCRFDR
] = sci_reg_invalid
,
254 [SCSPTR
] = { 0x20, 16 },
255 [SCLSR
] = { 0x24, 16 },
256 [HSSRR
] = sci_reg_invalid
,
257 [SCPCR
] = sci_reg_invalid
,
258 [SCPDR
] = sci_reg_invalid
,
262 * Common SH-3 SCIF definitions.
264 [SCIx_SH3_SCIF_REGTYPE
] = {
265 [SCSMR
] = { 0x00, 8 },
266 [SCBRR
] = { 0x02, 8 },
267 [SCSCR
] = { 0x04, 8 },
268 [SCxTDR
] = { 0x06, 8 },
269 [SCxSR
] = { 0x08, 16 },
270 [SCxRDR
] = { 0x0a, 8 },
271 [SCFCR
] = { 0x0c, 8 },
272 [SCFDR
] = { 0x0e, 16 },
273 [SCTFDR
] = sci_reg_invalid
,
274 [SCRFDR
] = sci_reg_invalid
,
275 [SCSPTR
] = sci_reg_invalid
,
276 [SCLSR
] = sci_reg_invalid
,
277 [HSSRR
] = sci_reg_invalid
,
278 [SCPCR
] = sci_reg_invalid
,
279 [SCPDR
] = sci_reg_invalid
,
283 * Common SH-4(A) SCIF(B) definitions.
285 [SCIx_SH4_SCIF_REGTYPE
] = {
286 [SCSMR
] = { 0x00, 16 },
287 [SCBRR
] = { 0x04, 8 },
288 [SCSCR
] = { 0x08, 16 },
289 [SCxTDR
] = { 0x0c, 8 },
290 [SCxSR
] = { 0x10, 16 },
291 [SCxRDR
] = { 0x14, 8 },
292 [SCFCR
] = { 0x18, 16 },
293 [SCFDR
] = { 0x1c, 16 },
294 [SCTFDR
] = sci_reg_invalid
,
295 [SCRFDR
] = sci_reg_invalid
,
296 [SCSPTR
] = { 0x20, 16 },
297 [SCLSR
] = { 0x24, 16 },
298 [HSSRR
] = sci_reg_invalid
,
299 [SCPCR
] = sci_reg_invalid
,
300 [SCPDR
] = sci_reg_invalid
,
304 * Common HSCIF definitions.
306 [SCIx_HSCIF_REGTYPE
] = {
307 [SCSMR
] = { 0x00, 16 },
308 [SCBRR
] = { 0x04, 8 },
309 [SCSCR
] = { 0x08, 16 },
310 [SCxTDR
] = { 0x0c, 8 },
311 [SCxSR
] = { 0x10, 16 },
312 [SCxRDR
] = { 0x14, 8 },
313 [SCFCR
] = { 0x18, 16 },
314 [SCFDR
] = { 0x1c, 16 },
315 [SCTFDR
] = sci_reg_invalid
,
316 [SCRFDR
] = sci_reg_invalid
,
317 [SCSPTR
] = { 0x20, 16 },
318 [SCLSR
] = { 0x24, 16 },
319 [HSSRR
] = { 0x40, 16 },
320 [SCPCR
] = sci_reg_invalid
,
321 [SCPDR
] = sci_reg_invalid
,
325 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
328 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE
] = {
329 [SCSMR
] = { 0x00, 16 },
330 [SCBRR
] = { 0x04, 8 },
331 [SCSCR
] = { 0x08, 16 },
332 [SCxTDR
] = { 0x0c, 8 },
333 [SCxSR
] = { 0x10, 16 },
334 [SCxRDR
] = { 0x14, 8 },
335 [SCFCR
] = { 0x18, 16 },
336 [SCFDR
] = { 0x1c, 16 },
337 [SCTFDR
] = sci_reg_invalid
,
338 [SCRFDR
] = sci_reg_invalid
,
339 [SCSPTR
] = sci_reg_invalid
,
340 [SCLSR
] = { 0x24, 16 },
341 [HSSRR
] = sci_reg_invalid
,
342 [SCPCR
] = sci_reg_invalid
,
343 [SCPDR
] = sci_reg_invalid
,
347 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
350 [SCIx_SH4_SCIF_FIFODATA_REGTYPE
] = {
351 [SCSMR
] = { 0x00, 16 },
352 [SCBRR
] = { 0x04, 8 },
353 [SCSCR
] = { 0x08, 16 },
354 [SCxTDR
] = { 0x0c, 8 },
355 [SCxSR
] = { 0x10, 16 },
356 [SCxRDR
] = { 0x14, 8 },
357 [SCFCR
] = { 0x18, 16 },
358 [SCFDR
] = { 0x1c, 16 },
359 [SCTFDR
] = { 0x1c, 16 }, /* aliased to SCFDR */
360 [SCRFDR
] = { 0x20, 16 },
361 [SCSPTR
] = { 0x24, 16 },
362 [SCLSR
] = { 0x28, 16 },
363 [HSSRR
] = sci_reg_invalid
,
364 [SCPCR
] = sci_reg_invalid
,
365 [SCPDR
] = sci_reg_invalid
,
369 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
372 [SCIx_SH7705_SCIF_REGTYPE
] = {
373 [SCSMR
] = { 0x00, 16 },
374 [SCBRR
] = { 0x04, 8 },
375 [SCSCR
] = { 0x08, 16 },
376 [SCxTDR
] = { 0x20, 8 },
377 [SCxSR
] = { 0x14, 16 },
378 [SCxRDR
] = { 0x24, 8 },
379 [SCFCR
] = { 0x18, 16 },
380 [SCFDR
] = { 0x1c, 16 },
381 [SCTFDR
] = sci_reg_invalid
,
382 [SCRFDR
] = sci_reg_invalid
,
383 [SCSPTR
] = sci_reg_invalid
,
384 [SCLSR
] = sci_reg_invalid
,
385 [HSSRR
] = sci_reg_invalid
,
386 [SCPCR
] = sci_reg_invalid
,
387 [SCPDR
] = sci_reg_invalid
,
391 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
394 * The "offset" here is rather misleading, in that it refers to an enum
395 * value relative to the port mapping rather than the fixed offset
396 * itself, which needs to be manually retrieved from the platform's
397 * register map for the given port.
399 static unsigned int sci_serial_in(struct uart_port
*p
, int offset
)
401 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
404 return ioread8(p
->membase
+ (reg
->offset
<< p
->regshift
));
405 else if (reg
->size
== 16)
406 return ioread16(p
->membase
+ (reg
->offset
<< p
->regshift
));
408 WARN(1, "Invalid register access\n");
413 static void sci_serial_out(struct uart_port
*p
, int offset
, int value
)
415 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
418 iowrite8(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
419 else if (reg
->size
== 16)
420 iowrite16(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
422 WARN(1, "Invalid register access\n");
425 static int sci_probe_regmap(struct plat_sci_port
*cfg
)
429 cfg
->regtype
= SCIx_SCI_REGTYPE
;
432 cfg
->regtype
= SCIx_IRDA_REGTYPE
;
435 cfg
->regtype
= SCIx_SCIFA_REGTYPE
;
438 cfg
->regtype
= SCIx_SCIFB_REGTYPE
;
442 * The SH-4 is a bit of a misnomer here, although that's
443 * where this particular port layout originated. This
444 * configuration (or some slight variation thereof)
445 * remains the dominant model for all SCIFs.
447 cfg
->regtype
= SCIx_SH4_SCIF_REGTYPE
;
450 cfg
->regtype
= SCIx_HSCIF_REGTYPE
;
453 pr_err("Can't probe register map for given port\n");
460 static void sci_port_enable(struct sci_port
*sci_port
)
462 if (!sci_port
->port
.dev
)
465 pm_runtime_get_sync(sci_port
->port
.dev
);
467 clk_prepare_enable(sci_port
->iclk
);
468 sci_port
->port
.uartclk
= clk_get_rate(sci_port
->iclk
);
469 clk_prepare_enable(sci_port
->fclk
);
472 static void sci_port_disable(struct sci_port
*sci_port
)
474 if (!sci_port
->port
.dev
)
477 /* Cancel the break timer to ensure that the timer handler will not try
478 * to access the hardware with clocks and power disabled. Reset the
479 * break flag to make the break debouncing state machine ready for the
482 del_timer_sync(&sci_port
->break_timer
);
483 sci_port
->break_flag
= 0;
485 clk_disable_unprepare(sci_port
->fclk
);
486 clk_disable_unprepare(sci_port
->iclk
);
488 pm_runtime_put_sync(sci_port
->port
.dev
);
491 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
493 #ifdef CONFIG_CONSOLE_POLL
494 static int sci_poll_get_char(struct uart_port
*port
)
496 unsigned short status
;
500 status
= serial_port_in(port
, SCxSR
);
501 if (status
& SCxSR_ERRORS(port
)) {
502 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
508 if (!(status
& SCxSR_RDxF(port
)))
511 c
= serial_port_in(port
, SCxRDR
);
514 serial_port_in(port
, SCxSR
);
515 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
521 static void sci_poll_put_char(struct uart_port
*port
, unsigned char c
)
523 unsigned short status
;
526 status
= serial_port_in(port
, SCxSR
);
527 } while (!(status
& SCxSR_TDxE(port
)));
529 serial_port_out(port
, SCxTDR
, c
);
530 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
) & ~SCxSR_TEND(port
));
532 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
534 static void sci_init_pins(struct uart_port
*port
, unsigned int cflag
)
536 struct sci_port
*s
= to_sci_port(port
);
537 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
540 * Use port-specific handler if provided.
542 if (s
->cfg
->ops
&& s
->cfg
->ops
->init_pins
) {
543 s
->cfg
->ops
->init_pins(port
, cflag
);
548 * For the generic path SCSPTR is necessary. Bail out if that's
554 if ((s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) &&
555 ((!(cflag
& CRTSCTS
)))) {
556 unsigned short status
;
558 status
= serial_port_in(port
, SCSPTR
);
559 status
&= ~SCSPTR_CTSIO
;
560 status
|= SCSPTR_RTSIO
;
561 serial_port_out(port
, SCSPTR
, status
); /* Set RTS = 1 */
565 static int sci_txfill(struct uart_port
*port
)
567 struct plat_sci_reg
*reg
;
569 reg
= sci_getreg(port
, SCTFDR
);
571 return serial_port_in(port
, SCTFDR
) & ((port
->fifosize
<< 1) - 1);
573 reg
= sci_getreg(port
, SCFDR
);
575 return serial_port_in(port
, SCFDR
) >> 8;
577 return !(serial_port_in(port
, SCxSR
) & SCI_TDRE
);
580 static int sci_txroom(struct uart_port
*port
)
582 return port
->fifosize
- sci_txfill(port
);
585 static int sci_rxfill(struct uart_port
*port
)
587 struct plat_sci_reg
*reg
;
589 reg
= sci_getreg(port
, SCRFDR
);
591 return serial_port_in(port
, SCRFDR
) & ((port
->fifosize
<< 1) - 1);
593 reg
= sci_getreg(port
, SCFDR
);
595 return serial_port_in(port
, SCFDR
) & ((port
->fifosize
<< 1) - 1);
597 return (serial_port_in(port
, SCxSR
) & SCxSR_RDxF(port
)) != 0;
601 * SCI helper for checking the state of the muxed port/RXD pins.
603 static inline int sci_rxd_in(struct uart_port
*port
)
605 struct sci_port
*s
= to_sci_port(port
);
607 if (s
->cfg
->port_reg
<= 0)
610 /* Cast for ARM damage */
611 return !!__raw_readb((void __iomem
*)(uintptr_t)s
->cfg
->port_reg
);
614 /* ********************************************************************** *
615 * the interrupt related routines *
616 * ********************************************************************** */
618 static void sci_transmit_chars(struct uart_port
*port
)
620 struct circ_buf
*xmit
= &port
->state
->xmit
;
621 unsigned int stopped
= uart_tx_stopped(port
);
622 unsigned short status
;
626 status
= serial_port_in(port
, SCxSR
);
627 if (!(status
& SCxSR_TDxE(port
))) {
628 ctrl
= serial_port_in(port
, SCSCR
);
629 if (uart_circ_empty(xmit
))
633 serial_port_out(port
, SCSCR
, ctrl
);
637 count
= sci_txroom(port
);
645 } else if (!uart_circ_empty(xmit
) && !stopped
) {
646 c
= xmit
->buf
[xmit
->tail
];
647 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
652 serial_port_out(port
, SCxTDR
, c
);
655 } while (--count
> 0);
657 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
659 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
660 uart_write_wakeup(port
);
661 if (uart_circ_empty(xmit
)) {
664 ctrl
= serial_port_in(port
, SCSCR
);
666 if (port
->type
!= PORT_SCI
) {
667 serial_port_in(port
, SCxSR
); /* Dummy read */
668 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
672 serial_port_out(port
, SCSCR
, ctrl
);
676 /* On SH3, SCIF may read end-of-break as a space->mark char */
677 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
679 static void sci_receive_chars(struct uart_port
*port
)
681 struct sci_port
*sci_port
= to_sci_port(port
);
682 struct tty_port
*tport
= &port
->state
->port
;
683 int i
, count
, copied
= 0;
684 unsigned short status
;
687 status
= serial_port_in(port
, SCxSR
);
688 if (!(status
& SCxSR_RDxF(port
)))
692 /* Don't copy more bytes than there is room for in the buffer */
693 count
= tty_buffer_request_room(tport
, sci_rxfill(port
));
695 /* If for any reason we can't copy more data, we're done! */
699 if (port
->type
== PORT_SCI
) {
700 char c
= serial_port_in(port
, SCxRDR
);
701 if (uart_handle_sysrq_char(port
, c
) ||
702 sci_port
->break_flag
)
705 tty_insert_flip_char(tport
, c
, TTY_NORMAL
);
707 for (i
= 0; i
< count
; i
++) {
708 char c
= serial_port_in(port
, SCxRDR
);
710 status
= serial_port_in(port
, SCxSR
);
711 #if defined(CONFIG_CPU_SH3)
712 /* Skip "chars" during break */
713 if (sci_port
->break_flag
) {
715 (status
& SCxSR_FER(port
))) {
720 /* Nonzero => end-of-break */
721 dev_dbg(port
->dev
, "debounce<%02x>\n", c
);
722 sci_port
->break_flag
= 0;
729 #endif /* CONFIG_CPU_SH3 */
730 if (uart_handle_sysrq_char(port
, c
)) {
735 /* Store data and status */
736 if (status
& SCxSR_FER(port
)) {
738 port
->icount
.frame
++;
739 dev_notice(port
->dev
, "frame error\n");
740 } else if (status
& SCxSR_PER(port
)) {
742 port
->icount
.parity
++;
743 dev_notice(port
->dev
, "parity error\n");
747 tty_insert_flip_char(tport
, c
, flag
);
751 serial_port_in(port
, SCxSR
); /* dummy read */
752 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
755 port
->icount
.rx
+= count
;
759 /* Tell the rest of the system the news. New characters! */
760 tty_flip_buffer_push(tport
);
762 serial_port_in(port
, SCxSR
); /* dummy read */
763 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
767 #define SCI_BREAK_JIFFIES (HZ/20)
770 * The sci generates interrupts during the break,
771 * 1 per millisecond or so during the break period, for 9600 baud.
772 * So dont bother disabling interrupts.
773 * But dont want more than 1 break event.
774 * Use a kernel timer to periodically poll the rx line until
775 * the break is finished.
777 static inline void sci_schedule_break_timer(struct sci_port
*port
)
779 mod_timer(&port
->break_timer
, jiffies
+ SCI_BREAK_JIFFIES
);
782 /* Ensure that two consecutive samples find the break over. */
783 static void sci_break_timer(unsigned long data
)
785 struct sci_port
*port
= (struct sci_port
*)data
;
787 if (sci_rxd_in(&port
->port
) == 0) {
788 port
->break_flag
= 1;
789 sci_schedule_break_timer(port
);
790 } else if (port
->break_flag
== 1) {
792 port
->break_flag
= 2;
793 sci_schedule_break_timer(port
);
795 port
->break_flag
= 0;
798 static int sci_handle_errors(struct uart_port
*port
)
801 unsigned short status
= serial_port_in(port
, SCxSR
);
802 struct tty_port
*tport
= &port
->state
->port
;
803 struct sci_port
*s
= to_sci_port(port
);
805 /* Handle overruns */
806 if (status
& (1 << s
->overrun_bit
)) {
807 port
->icount
.overrun
++;
810 if (tty_insert_flip_char(tport
, 0, TTY_OVERRUN
))
813 dev_notice(port
->dev
, "overrun error\n");
816 if (status
& SCxSR_FER(port
)) {
817 if (sci_rxd_in(port
) == 0) {
818 /* Notify of BREAK */
819 struct sci_port
*sci_port
= to_sci_port(port
);
821 if (!sci_port
->break_flag
) {
824 sci_port
->break_flag
= 1;
825 sci_schedule_break_timer(sci_port
);
827 /* Do sysrq handling. */
828 if (uart_handle_break(port
))
831 dev_dbg(port
->dev
, "BREAK detected\n");
833 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
839 port
->icount
.frame
++;
841 if (tty_insert_flip_char(tport
, 0, TTY_FRAME
))
844 dev_notice(port
->dev
, "frame error\n");
848 if (status
& SCxSR_PER(port
)) {
850 port
->icount
.parity
++;
852 if (tty_insert_flip_char(tport
, 0, TTY_PARITY
))
855 dev_notice(port
->dev
, "parity error\n");
859 tty_flip_buffer_push(tport
);
864 static int sci_handle_fifo_overrun(struct uart_port
*port
)
866 struct tty_port
*tport
= &port
->state
->port
;
867 struct sci_port
*s
= to_sci_port(port
);
868 struct plat_sci_reg
*reg
;
869 int copied
= 0, offset
;
872 switch (port
->type
) {
885 reg
= sci_getreg(port
, offset
);
889 status
= serial_port_in(port
, offset
);
890 bit
= 1 << s
->overrun_bit
;
894 serial_port_out(port
, offset
, status
);
896 port
->icount
.overrun
++;
898 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
899 tty_flip_buffer_push(tport
);
901 dev_dbg(port
->dev
, "overrun error\n");
908 static int sci_handle_breaks(struct uart_port
*port
)
911 unsigned short status
= serial_port_in(port
, SCxSR
);
912 struct tty_port
*tport
= &port
->state
->port
;
913 struct sci_port
*s
= to_sci_port(port
);
915 if (uart_handle_break(port
))
918 if (!s
->break_flag
&& status
& SCxSR_BRK(port
)) {
919 #if defined(CONFIG_CPU_SH3)
926 /* Notify of BREAK */
927 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
930 dev_dbg(port
->dev
, "BREAK detected\n");
934 tty_flip_buffer_push(tport
);
936 copied
+= sci_handle_fifo_overrun(port
);
941 static irqreturn_t
sci_rx_interrupt(int irq
, void *ptr
)
943 #ifdef CONFIG_SERIAL_SH_SCI_DMA
944 struct uart_port
*port
= ptr
;
945 struct sci_port
*s
= to_sci_port(port
);
948 u16 scr
= serial_port_in(port
, SCSCR
);
949 u16 ssr
= serial_port_in(port
, SCxSR
);
951 /* Disable future Rx interrupts */
952 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
953 disable_irq_nosync(irq
);
958 serial_port_out(port
, SCSCR
, scr
);
959 /* Clear current interrupt */
960 serial_port_out(port
, SCxSR
, ssr
& ~(1 | SCxSR_RDxF(port
)));
961 dev_dbg(port
->dev
, "Rx IRQ %lu: setup t-out in %u jiffies\n",
962 jiffies
, s
->rx_timeout
);
963 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
969 /* I think sci_receive_chars has to be called irrespective
970 * of whether the I_IXOFF is set, otherwise, how is the interrupt
973 sci_receive_chars(ptr
);
978 static irqreturn_t
sci_tx_interrupt(int irq
, void *ptr
)
980 struct uart_port
*port
= ptr
;
983 spin_lock_irqsave(&port
->lock
, flags
);
984 sci_transmit_chars(port
);
985 spin_unlock_irqrestore(&port
->lock
, flags
);
990 static irqreturn_t
sci_er_interrupt(int irq
, void *ptr
)
992 struct uart_port
*port
= ptr
;
995 if (port
->type
== PORT_SCI
) {
996 if (sci_handle_errors(port
)) {
997 /* discard character in rx buffer */
998 serial_port_in(port
, SCxSR
);
999 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
1002 sci_handle_fifo_overrun(port
);
1003 sci_rx_interrupt(irq
, ptr
);
1006 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
1008 /* Kick the transmission */
1009 sci_tx_interrupt(irq
, ptr
);
1014 static irqreturn_t
sci_br_interrupt(int irq
, void *ptr
)
1016 struct uart_port
*port
= ptr
;
1019 sci_handle_breaks(port
);
1020 serial_port_out(port
, SCxSR
, SCxSR_BREAK_CLEAR(port
));
1025 static inline unsigned long port_rx_irq_mask(struct uart_port
*port
)
1028 * Not all ports (such as SCIFA) will support REIE. Rather than
1029 * special-casing the port type, we check the port initialization
1030 * IRQ enable mask to see whether the IRQ is desired at all. If
1031 * it's unset, it's logically inferred that there's no point in
1034 return SCSCR_RIE
| (to_sci_port(port
)->cfg
->scscr
& SCSCR_REIE
);
1037 static irqreturn_t
sci_mpxed_interrupt(int irq
, void *ptr
)
1039 unsigned short ssr_status
, scr_status
, err_enabled
, orer_status
= 0;
1040 struct uart_port
*port
= ptr
;
1041 struct sci_port
*s
= to_sci_port(port
);
1042 irqreturn_t ret
= IRQ_NONE
;
1044 ssr_status
= serial_port_in(port
, SCxSR
);
1045 scr_status
= serial_port_in(port
, SCSCR
);
1046 switch (port
->type
) {
1049 orer_status
= serial_port_in(port
, SCLSR
);
1053 orer_status
= ssr_status
;
1057 err_enabled
= scr_status
& port_rx_irq_mask(port
);
1060 if ((ssr_status
& SCxSR_TDxE(port
)) && (scr_status
& SCSCR_TIE
) &&
1062 ret
= sci_tx_interrupt(irq
, ptr
);
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1068 if (((ssr_status
& SCxSR_RDxF(port
)) || s
->chan_rx
) &&
1069 (scr_status
& SCSCR_RIE
)) {
1070 if (port
->type
== PORT_SCIF
|| port
->type
== PORT_HSCIF
)
1071 sci_handle_fifo_overrun(port
);
1072 ret
= sci_rx_interrupt(irq
, ptr
);
1075 /* Error Interrupt */
1076 if ((ssr_status
& SCxSR_ERRORS(port
)) && err_enabled
)
1077 ret
= sci_er_interrupt(irq
, ptr
);
1079 /* Break Interrupt */
1080 if ((ssr_status
& SCxSR_BRK(port
)) && err_enabled
)
1081 ret
= sci_br_interrupt(irq
, ptr
);
1083 /* Overrun Interrupt */
1084 if (orer_status
& (1 << s
->overrun_bit
))
1085 sci_handle_fifo_overrun(port
);
1091 * Here we define a transition notifier so that we can update all of our
1092 * ports' baud rate when the peripheral clock changes.
1094 static int sci_notifier(struct notifier_block
*self
,
1095 unsigned long phase
, void *p
)
1097 struct sci_port
*sci_port
;
1098 unsigned long flags
;
1100 sci_port
= container_of(self
, struct sci_port
, freq_transition
);
1102 if (phase
== CPUFREQ_POSTCHANGE
) {
1103 struct uart_port
*port
= &sci_port
->port
;
1105 spin_lock_irqsave(&port
->lock
, flags
);
1106 port
->uartclk
= clk_get_rate(sci_port
->iclk
);
1107 spin_unlock_irqrestore(&port
->lock
, flags
);
1113 static struct sci_irq_desc
{
1115 irq_handler_t handler
;
1116 } sci_irq_desc
[] = {
1118 * Split out handlers, the default case.
1122 .handler
= sci_er_interrupt
,
1127 .handler
= sci_rx_interrupt
,
1132 .handler
= sci_tx_interrupt
,
1137 .handler
= sci_br_interrupt
,
1141 * Special muxed handler.
1145 .handler
= sci_mpxed_interrupt
,
1149 static int sci_request_irq(struct sci_port
*port
)
1151 struct uart_port
*up
= &port
->port
;
1154 for (i
= j
= 0; i
< SCIx_NR_IRQS
; i
++, j
++) {
1155 struct sci_irq_desc
*desc
;
1158 if (SCIx_IRQ_IS_MUXED(port
)) {
1162 irq
= port
->irqs
[i
];
1165 * Certain port types won't support all of the
1166 * available interrupt sources.
1168 if (unlikely(irq
< 0))
1172 desc
= sci_irq_desc
+ i
;
1173 port
->irqstr
[j
] = kasprintf(GFP_KERNEL
, "%s:%s",
1174 dev_name(up
->dev
), desc
->desc
);
1175 if (!port
->irqstr
[j
]) {
1176 dev_err(up
->dev
, "Failed to allocate %s IRQ string\n",
1181 ret
= request_irq(irq
, desc
->handler
, up
->irqflags
,
1182 port
->irqstr
[j
], port
);
1183 if (unlikely(ret
)) {
1184 dev_err(up
->dev
, "Can't allocate %s IRQ\n", desc
->desc
);
1193 free_irq(port
->irqs
[i
], port
);
1197 kfree(port
->irqstr
[j
]);
1202 static void sci_free_irq(struct sci_port
*port
)
1207 * Intentionally in reverse order so we iterate over the muxed
1210 for (i
= 0; i
< SCIx_NR_IRQS
; i
++) {
1211 int irq
= port
->irqs
[i
];
1214 * Certain port types won't support all of the available
1215 * interrupt sources.
1217 if (unlikely(irq
< 0))
1220 free_irq(port
->irqs
[i
], port
);
1221 kfree(port
->irqstr
[i
]);
1223 if (SCIx_IRQ_IS_MUXED(port
)) {
1224 /* If there's only one IRQ, we're done. */
1230 static unsigned int sci_tx_empty(struct uart_port
*port
)
1232 unsigned short status
= serial_port_in(port
, SCxSR
);
1233 unsigned short in_tx_fifo
= sci_txfill(port
);
1235 return (status
& SCxSR_TEND(port
)) && !in_tx_fifo
? TIOCSER_TEMT
: 0;
1239 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1240 * CTS/RTS is supported in hardware by at least one port and controlled
1241 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1242 * handled via the ->init_pins() op, which is a bit of a one-way street,
1243 * lacking any ability to defer pin control -- this will later be
1244 * converted over to the GPIO framework).
1246 * Other modes (such as loopback) are supported generically on certain
1247 * port types, but not others. For these it's sufficient to test for the
1248 * existence of the support register and simply ignore the port type.
1250 static void sci_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1252 if (mctrl
& TIOCM_LOOP
) {
1253 struct plat_sci_reg
*reg
;
1256 * Standard loopback mode for SCFCR ports.
1258 reg
= sci_getreg(port
, SCFCR
);
1260 serial_port_out(port
, SCFCR
,
1261 serial_port_in(port
, SCFCR
) |
1266 static unsigned int sci_get_mctrl(struct uart_port
*port
)
1269 * CTS/RTS is handled in hardware when supported, while nothing
1270 * else is wired up. Keep it simple and simply assert DSR/CAR.
1272 return TIOCM_DSR
| TIOCM_CAR
;
1275 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1276 static void sci_dma_tx_complete(void *arg
)
1278 struct sci_port
*s
= arg
;
1279 struct uart_port
*port
= &s
->port
;
1280 struct circ_buf
*xmit
= &port
->state
->xmit
;
1281 unsigned long flags
;
1283 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1285 spin_lock_irqsave(&port
->lock
, flags
);
1287 xmit
->tail
+= sg_dma_len(&s
->sg_tx
);
1288 xmit
->tail
&= UART_XMIT_SIZE
- 1;
1290 port
->icount
.tx
+= sg_dma_len(&s
->sg_tx
);
1292 async_tx_ack(s
->desc_tx
);
1295 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1296 uart_write_wakeup(port
);
1298 if (!uart_circ_empty(xmit
)) {
1300 schedule_work(&s
->work_tx
);
1302 s
->cookie_tx
= -EINVAL
;
1303 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1304 u16 ctrl
= serial_port_in(port
, SCSCR
);
1305 serial_port_out(port
, SCSCR
, ctrl
& ~SCSCR_TIE
);
1309 spin_unlock_irqrestore(&port
->lock
, flags
);
1312 /* Locking: called with port lock held */
1313 static int sci_dma_rx_push(struct sci_port
*s
, size_t count
)
1315 struct uart_port
*port
= &s
->port
;
1316 struct tty_port
*tport
= &port
->state
->port
;
1317 int i
, active
, room
;
1319 room
= tty_buffer_request_room(tport
, count
);
1321 if (s
->active_rx
== s
->cookie_rx
[0]) {
1323 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1326 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1331 dev_warn(port
->dev
, "Rx overrun: dropping %zu bytes\n",
1336 for (i
= 0; i
< room
; i
++)
1337 tty_insert_flip_char(tport
, ((u8
*)sg_virt(&s
->sg_rx
[active
]))[i
],
1340 port
->icount
.rx
+= room
;
1345 static void sci_dma_rx_complete(void *arg
)
1347 struct sci_port
*s
= arg
;
1348 struct uart_port
*port
= &s
->port
;
1349 unsigned long flags
;
1352 dev_dbg(port
->dev
, "%s(%d) active #%d\n",
1353 __func__
, port
->line
, s
->active_rx
);
1355 spin_lock_irqsave(&port
->lock
, flags
);
1357 count
= sci_dma_rx_push(s
, s
->buf_len_rx
);
1359 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
1361 spin_unlock_irqrestore(&port
->lock
, flags
);
1364 tty_flip_buffer_push(&port
->state
->port
);
1366 schedule_work(&s
->work_rx
);
1369 static void sci_rx_dma_release(struct sci_port
*s
, bool enable_pio
)
1371 struct dma_chan
*chan
= s
->chan_rx
;
1372 struct uart_port
*port
= &s
->port
;
1375 s
->cookie_rx
[0] = s
->cookie_rx
[1] = -EINVAL
;
1376 dma_release_channel(chan
);
1377 if (sg_dma_address(&s
->sg_rx
[0]))
1378 dma_free_coherent(port
->dev
, s
->buf_len_rx
* 2,
1379 sg_virt(&s
->sg_rx
[0]), sg_dma_address(&s
->sg_rx
[0]));
1384 static void sci_tx_dma_release(struct sci_port
*s
, bool enable_pio
)
1386 struct dma_chan
*chan
= s
->chan_tx
;
1387 struct uart_port
*port
= &s
->port
;
1390 s
->cookie_tx
= -EINVAL
;
1391 dma_release_channel(chan
);
1396 static void sci_submit_rx(struct sci_port
*s
)
1398 struct dma_chan
*chan
= s
->chan_rx
;
1401 for (i
= 0; i
< 2; i
++) {
1402 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1403 struct dma_async_tx_descriptor
*desc
;
1405 desc
= dmaengine_prep_slave_sg(chan
,
1406 sg
, 1, DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1409 s
->desc_rx
[i
] = desc
;
1410 desc
->callback
= sci_dma_rx_complete
;
1411 desc
->callback_param
= s
;
1412 s
->cookie_rx
[i
] = desc
->tx_submit(desc
);
1415 if (!desc
|| s
->cookie_rx
[i
] < 0) {
1417 async_tx_ack(s
->desc_rx
[0]);
1418 s
->cookie_rx
[0] = -EINVAL
;
1422 s
->cookie_rx
[i
] = -EINVAL
;
1424 dev_warn(s
->port
.dev
,
1425 "failed to re-start DMA, using PIO\n");
1426 sci_rx_dma_release(s
, true);
1429 dev_dbg(s
->port
.dev
, "%s(): cookie %d to #%d\n",
1430 __func__
, s
->cookie_rx
[i
], i
);
1433 s
->active_rx
= s
->cookie_rx
[0];
1435 dma_async_issue_pending(chan
);
1438 static void work_fn_rx(struct work_struct
*work
)
1440 struct sci_port
*s
= container_of(work
, struct sci_port
, work_rx
);
1441 struct uart_port
*port
= &s
->port
;
1442 struct dma_async_tx_descriptor
*desc
;
1445 if (s
->active_rx
== s
->cookie_rx
[0]) {
1447 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1450 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1453 desc
= s
->desc_rx
[new];
1455 if (dma_async_is_tx_complete(s
->chan_rx
, s
->active_rx
, NULL
, NULL
) !=
1457 /* Handle incomplete DMA receive */
1458 struct dma_chan
*chan
= s
->chan_rx
;
1459 struct shdma_desc
*sh_desc
= container_of(desc
,
1460 struct shdma_desc
, async_tx
);
1461 unsigned long flags
;
1464 dmaengine_terminate_all(chan
);
1465 dev_dbg(port
->dev
, "Read %zu bytes with cookie %d\n",
1466 sh_desc
->partial
, sh_desc
->cookie
);
1468 spin_lock_irqsave(&port
->lock
, flags
);
1469 count
= sci_dma_rx_push(s
, sh_desc
->partial
);
1470 spin_unlock_irqrestore(&port
->lock
, flags
);
1473 tty_flip_buffer_push(&port
->state
->port
);
1480 s
->cookie_rx
[new] = desc
->tx_submit(desc
);
1481 if (s
->cookie_rx
[new] < 0) {
1482 dev_warn(port
->dev
, "Failed submitting Rx DMA descriptor\n");
1483 sci_rx_dma_release(s
, true);
1487 s
->active_rx
= s
->cookie_rx
[!new];
1489 dev_dbg(port
->dev
, "%s: cookie %d #%d, new active #%d\n",
1490 __func__
, s
->cookie_rx
[new], new, s
->active_rx
);
1493 static void work_fn_tx(struct work_struct
*work
)
1495 struct sci_port
*s
= container_of(work
, struct sci_port
, work_tx
);
1496 struct dma_async_tx_descriptor
*desc
;
1497 struct dma_chan
*chan
= s
->chan_tx
;
1498 struct uart_port
*port
= &s
->port
;
1499 struct circ_buf
*xmit
= &port
->state
->xmit
;
1500 struct scatterlist
*sg
= &s
->sg_tx
;
1504 * Port xmit buffer is already mapped, and it is one page... Just adjust
1505 * offsets and lengths. Since it is a circular buffer, we have to
1506 * transmit till the end, and then the rest. Take the port lock to get a
1507 * consistent xmit buffer state.
1509 spin_lock_irq(&port
->lock
);
1510 sg
->offset
= xmit
->tail
& (UART_XMIT_SIZE
- 1);
1511 sg_dma_address(sg
) = (sg_dma_address(sg
) & ~(UART_XMIT_SIZE
- 1)) +
1513 sg_dma_len(sg
) = min((int)CIRC_CNT(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
),
1514 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
));
1515 spin_unlock_irq(&port
->lock
);
1517 BUG_ON(!sg_dma_len(sg
));
1519 desc
= dmaengine_prep_slave_sg(chan
,
1520 sg
, s
->sg_len_tx
, DMA_MEM_TO_DEV
,
1521 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1524 sci_tx_dma_release(s
, true);
1528 dma_sync_sg_for_device(port
->dev
, sg
, 1, DMA_TO_DEVICE
);
1530 spin_lock_irq(&port
->lock
);
1532 desc
->callback
= sci_dma_tx_complete
;
1533 desc
->callback_param
= s
;
1534 spin_unlock_irq(&port
->lock
);
1535 s
->cookie_tx
= desc
->tx_submit(desc
);
1536 if (s
->cookie_tx
< 0) {
1537 dev_warn(port
->dev
, "Failed submitting Tx DMA descriptor\n");
1539 sci_tx_dma_release(s
, true);
1543 dev_dbg(port
->dev
, "%s: %p: %d...%d, cookie %d\n",
1544 __func__
, xmit
->buf
, xmit
->tail
, xmit
->head
, s
->cookie_tx
);
1546 dma_async_issue_pending(chan
);
1550 static void sci_start_tx(struct uart_port
*port
)
1552 struct sci_port
*s
= to_sci_port(port
);
1553 unsigned short ctrl
;
1555 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1556 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1557 u16
new, scr
= serial_port_in(port
, SCSCR
);
1559 new = scr
| SCSCR_TDRQE
;
1561 new = scr
& ~SCSCR_TDRQE
;
1563 serial_port_out(port
, SCSCR
, new);
1566 if (s
->chan_tx
&& !uart_circ_empty(&s
->port
.state
->xmit
) &&
1569 schedule_work(&s
->work_tx
);
1573 if (!s
->chan_tx
|| port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1574 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1575 ctrl
= serial_port_in(port
, SCSCR
);
1576 serial_port_out(port
, SCSCR
, ctrl
| SCSCR_TIE
);
1580 static void sci_stop_tx(struct uart_port
*port
)
1582 unsigned short ctrl
;
1584 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1585 ctrl
= serial_port_in(port
, SCSCR
);
1587 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1588 ctrl
&= ~SCSCR_TDRQE
;
1592 serial_port_out(port
, SCSCR
, ctrl
);
1595 static void sci_start_rx(struct uart_port
*port
)
1597 unsigned short ctrl
;
1599 ctrl
= serial_port_in(port
, SCSCR
) | port_rx_irq_mask(port
);
1601 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1602 ctrl
&= ~SCSCR_RDRQE
;
1604 serial_port_out(port
, SCSCR
, ctrl
);
1607 static void sci_stop_rx(struct uart_port
*port
)
1609 unsigned short ctrl
;
1611 ctrl
= serial_port_in(port
, SCSCR
);
1613 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1614 ctrl
&= ~SCSCR_RDRQE
;
1616 ctrl
&= ~port_rx_irq_mask(port
);
1618 serial_port_out(port
, SCSCR
, ctrl
);
1621 static void sci_break_ctl(struct uart_port
*port
, int break_state
)
1623 struct sci_port
*s
= to_sci_port(port
);
1624 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
1625 unsigned short scscr
, scsptr
;
1627 /* check wheter the port has SCSPTR */
1630 * Not supported by hardware. Most parts couple break and rx
1631 * interrupts together, with break detection always enabled.
1636 scsptr
= serial_port_in(port
, SCSPTR
);
1637 scscr
= serial_port_in(port
, SCSCR
);
1639 if (break_state
== -1) {
1640 scsptr
= (scsptr
| SCSPTR_SPB2IO
) & ~SCSPTR_SPB2DT
;
1643 scsptr
= (scsptr
| SCSPTR_SPB2DT
) & ~SCSPTR_SPB2IO
;
1647 serial_port_out(port
, SCSPTR
, scsptr
);
1648 serial_port_out(port
, SCSCR
, scscr
);
1651 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1652 static bool filter(struct dma_chan
*chan
, void *slave
)
1654 struct sh_dmae_slave
*param
= slave
;
1656 dev_dbg(chan
->device
->dev
, "%s: slave ID %d\n",
1657 __func__
, param
->shdma_slave
.slave_id
);
1659 chan
->private = ¶m
->shdma_slave
;
1663 static void rx_timer_fn(unsigned long arg
)
1665 struct sci_port
*s
= (struct sci_port
*)arg
;
1666 struct uart_port
*port
= &s
->port
;
1667 u16 scr
= serial_port_in(port
, SCSCR
);
1669 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1670 scr
&= ~SCSCR_RDRQE
;
1671 enable_irq(s
->irqs
[SCIx_RXI_IRQ
]);
1673 serial_port_out(port
, SCSCR
, scr
| SCSCR_RIE
);
1674 dev_dbg(port
->dev
, "DMA Rx timed out\n");
1675 schedule_work(&s
->work_rx
);
1678 static void sci_request_dma(struct uart_port
*port
)
1680 struct sci_port
*s
= to_sci_port(port
);
1681 struct sh_dmae_slave
*param
;
1682 struct dma_chan
*chan
;
1683 dma_cap_mask_t mask
;
1686 dev_dbg(port
->dev
, "%s: port %d\n", __func__
, port
->line
);
1688 if (s
->cfg
->dma_slave_tx
<= 0 || s
->cfg
->dma_slave_rx
<= 0)
1692 dma_cap_set(DMA_SLAVE
, mask
);
1694 param
= &s
->param_tx
;
1696 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1697 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_tx
;
1699 s
->cookie_tx
= -EINVAL
;
1700 chan
= dma_request_channel(mask
, filter
, param
);
1701 dev_dbg(port
->dev
, "%s: TX: got channel %p\n", __func__
, chan
);
1704 sg_init_table(&s
->sg_tx
, 1);
1705 /* UART circular tx buffer is an aligned page. */
1706 BUG_ON((uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1707 sg_set_page(&s
->sg_tx
, virt_to_page(port
->state
->xmit
.buf
),
1709 (uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1710 nent
= dma_map_sg(port
->dev
, &s
->sg_tx
, 1, DMA_TO_DEVICE
);
1712 sci_tx_dma_release(s
, false);
1714 dev_dbg(port
->dev
, "%s: mapped %d@%p to %pad\n",
1716 sg_dma_len(&s
->sg_tx
), port
->state
->xmit
.buf
,
1717 &sg_dma_address(&s
->sg_tx
));
1719 s
->sg_len_tx
= nent
;
1721 INIT_WORK(&s
->work_tx
, work_fn_tx
);
1724 param
= &s
->param_rx
;
1726 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1727 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_rx
;
1729 chan
= dma_request_channel(mask
, filter
, param
);
1730 dev_dbg(port
->dev
, "%s: RX: got channel %p\n", __func__
, chan
);
1738 s
->buf_len_rx
= 2 * max(16, (int)port
->fifosize
);
1739 buf
[0] = dma_alloc_coherent(port
->dev
, s
->buf_len_rx
* 2,
1740 &dma
[0], GFP_KERNEL
);
1744 "failed to allocate dma buffer, using PIO\n");
1745 sci_rx_dma_release(s
, true);
1749 buf
[1] = buf
[0] + s
->buf_len_rx
;
1750 dma
[1] = dma
[0] + s
->buf_len_rx
;
1752 for (i
= 0; i
< 2; i
++) {
1753 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1755 sg_init_table(sg
, 1);
1756 sg_set_page(sg
, virt_to_page(buf
[i
]), s
->buf_len_rx
,
1757 (uintptr_t)buf
[i
] & ~PAGE_MASK
);
1758 sg_dma_address(sg
) = dma
[i
];
1761 INIT_WORK(&s
->work_rx
, work_fn_rx
);
1762 setup_timer(&s
->rx_timer
, rx_timer_fn
, (unsigned long)s
);
1768 static void sci_free_dma(struct uart_port
*port
)
1770 struct sci_port
*s
= to_sci_port(port
);
1773 sci_tx_dma_release(s
, false);
1775 sci_rx_dma_release(s
, false);
1778 static inline void sci_request_dma(struct uart_port
*port
)
1782 static inline void sci_free_dma(struct uart_port
*port
)
1787 static int sci_startup(struct uart_port
*port
)
1789 struct sci_port
*s
= to_sci_port(port
);
1790 unsigned long flags
;
1793 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1795 ret
= sci_request_irq(s
);
1796 if (unlikely(ret
< 0))
1799 sci_request_dma(port
);
1801 spin_lock_irqsave(&port
->lock
, flags
);
1804 spin_unlock_irqrestore(&port
->lock
, flags
);
1809 static void sci_shutdown(struct uart_port
*port
)
1811 struct sci_port
*s
= to_sci_port(port
);
1812 unsigned long flags
;
1814 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1816 spin_lock_irqsave(&port
->lock
, flags
);
1819 spin_unlock_irqrestore(&port
->lock
, flags
);
1825 static unsigned int sci_scbrr_calc(struct sci_port
*s
, unsigned int bps
,
1828 if (s
->sampling_rate
)
1829 return DIV_ROUND_CLOSEST(freq
, s
->sampling_rate
* bps
) - 1;
1831 /* Warn, but use a safe default */
1834 return ((freq
+ 16 * bps
) / (32 * bps
) - 1);
1837 /* calculate frame length from SMR */
1838 static int sci_baud_calc_frame_len(unsigned int smr_val
)
1842 if (smr_val
& SCSMR_CHR
)
1844 if (smr_val
& SCSMR_PE
)
1846 if (smr_val
& SCSMR_STOP
)
1853 /* calculate sample rate, BRR, and clock select for HSCIF */
1854 static void sci_baud_calc_hscif(unsigned int bps
, unsigned long freq
,
1855 int *brr
, unsigned int *srr
,
1856 unsigned int *cks
, int frame_len
)
1858 int sr
, c
, br
, err
, recv_margin
;
1859 int min_err
= 1000; /* 100% */
1860 int recv_max_margin
= 0;
1862 /* Find the combination of sample rate and clock select with the
1863 smallest deviation from the desired baud rate. */
1864 for (sr
= 8; sr
<= 32; sr
++) {
1865 for (c
= 0; c
<= 3; c
++) {
1866 /* integerized formulas from HSCIF documentation */
1867 br
= DIV_ROUND_CLOSEST(freq
, (sr
*
1868 (1 << (2 * c
+ 1)) * bps
)) - 1;
1869 br
= clamp(br
, 0, 255);
1870 err
= DIV_ROUND_CLOSEST(freq
, ((br
+ 1) * bps
* sr
*
1871 (1 << (2 * c
+ 1)) / 1000)) -
1874 * M: Receive margin (%)
1875 * N: Ratio of bit rate to clock (N = sampling rate)
1876 * D: Clock duty (D = 0 to 1.0)
1877 * L: Frame length (L = 9 to 12)
1878 * F: Absolute value of clock frequency deviation
1880 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1881 * (|D - 0.5| / N * (1 + F))|
1882 * NOTE: Usually, treat D for 0.5, F is 0 by this
1885 recv_margin
= abs((500 -
1886 DIV_ROUND_CLOSEST(1000, sr
<< 1)) / 10);
1887 if (abs(min_err
) > abs(err
)) {
1889 recv_max_margin
= recv_margin
;
1890 } else if ((min_err
== err
) &&
1891 (recv_margin
> recv_max_margin
))
1892 recv_max_margin
= recv_margin
;
1902 if (min_err
== 1000) {
1911 static void sci_reset(struct uart_port
*port
)
1913 struct plat_sci_reg
*reg
;
1914 unsigned int status
;
1917 status
= serial_port_in(port
, SCxSR
);
1918 } while (!(status
& SCxSR_TEND(port
)));
1920 serial_port_out(port
, SCSCR
, 0x00); /* TE=0, RE=0, CKE1=0 */
1922 reg
= sci_getreg(port
, SCFCR
);
1924 serial_port_out(port
, SCFCR
, SCFCR_RFRST
| SCFCR_TFRST
);
1927 static void sci_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1928 struct ktermios
*old
)
1930 struct sci_port
*s
= to_sci_port(port
);
1931 struct plat_sci_reg
*reg
;
1932 unsigned int baud
, smr_val
= 0, max_baud
, cks
= 0;
1934 unsigned int srr
= 15;
1936 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1937 smr_val
|= SCSMR_CHR
;
1938 if (termios
->c_cflag
& PARENB
)
1939 smr_val
|= SCSMR_PE
;
1940 if (termios
->c_cflag
& PARODD
)
1941 smr_val
|= SCSMR_PE
| SCSMR_ODD
;
1942 if (termios
->c_cflag
& CSTOPB
)
1943 smr_val
|= SCSMR_STOP
;
1946 * earlyprintk comes here early on with port->uartclk set to zero.
1947 * the clock framework is not up and running at this point so here
1948 * we assume that 115200 is the maximum baud rate. please note that
1949 * the baud rate is not programmed during earlyprintk - it is assumed
1950 * that the previous boot loader has enabled required clocks and
1951 * setup the baud rate generator hardware for us already.
1953 max_baud
= port
->uartclk
? port
->uartclk
/ 16 : 115200;
1955 baud
= uart_get_baud_rate(port
, termios
, old
, 0, max_baud
);
1956 if (likely(baud
&& port
->uartclk
)) {
1957 if (s
->cfg
->type
== PORT_HSCIF
) {
1958 int frame_len
= sci_baud_calc_frame_len(smr_val
);
1959 sci_baud_calc_hscif(baud
, port
->uartclk
, &t
, &srr
,
1962 t
= sci_scbrr_calc(s
, baud
, port
->uartclk
);
1963 for (cks
= 0; t
>= 256 && cks
<= 3; cks
++)
1972 smr_val
|= serial_port_in(port
, SCSMR
) & 3;
1974 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1976 dev_dbg(port
->dev
, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1977 __func__
, smr_val
, cks
, t
, s
->cfg
->scscr
);
1980 serial_port_out(port
, SCSMR
, (smr_val
& ~SCSMR_CKS
) | cks
);
1981 serial_port_out(port
, SCBRR
, t
);
1982 reg
= sci_getreg(port
, HSSRR
);
1984 serial_port_out(port
, HSSRR
, srr
| HSCIF_SRE
);
1985 udelay((1000000+(baud
-1)) / baud
); /* Wait one bit interval */
1987 serial_port_out(port
, SCSMR
, smr_val
);
1989 sci_init_pins(port
, termios
->c_cflag
);
1991 reg
= sci_getreg(port
, SCFCR
);
1993 unsigned short ctrl
= serial_port_in(port
, SCFCR
);
1995 if (s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) {
1996 if (termios
->c_cflag
& CRTSCTS
)
2003 * As we've done a sci_reset() above, ensure we don't
2004 * interfere with the FIFOs while toggling MCE. As the
2005 * reset values could still be set, simply mask them out.
2007 ctrl
&= ~(SCFCR_RFRST
| SCFCR_TFRST
);
2009 serial_port_out(port
, SCFCR
, ctrl
);
2012 serial_port_out(port
, SCSCR
, s
->cfg
->scscr
);
2014 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2016 * Calculate delay for 2 DMA buffers (4 FIFO).
2017 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
2018 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
2019 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
2020 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2021 * sizes), but when performing a faster transfer, value obtained by
2022 * this formula is may not enough. Therefore, if value is smaller than
2023 * 20msec, this sets 20msec as timeout of DMA.
2028 /* byte size and parity */
2029 switch (termios
->c_cflag
& CSIZE
) {
2044 if (termios
->c_cflag
& CSTOPB
)
2046 if (termios
->c_cflag
& PARENB
)
2048 s
->rx_timeout
= DIV_ROUND_UP((s
->buf_len_rx
* 2 * bits
* HZ
) /
2050 dev_dbg(port
->dev
, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2051 s
->rx_timeout
* 1000 / HZ
, port
->timeout
);
2052 if (s
->rx_timeout
< msecs_to_jiffies(20))
2053 s
->rx_timeout
= msecs_to_jiffies(20);
2057 if ((termios
->c_cflag
& CREAD
) != 0)
2060 sci_port_disable(s
);
2063 static void sci_pm(struct uart_port
*port
, unsigned int state
,
2064 unsigned int oldstate
)
2066 struct sci_port
*sci_port
= to_sci_port(port
);
2069 case UART_PM_STATE_OFF
:
2070 sci_port_disable(sci_port
);
2073 sci_port_enable(sci_port
);
2078 static const char *sci_type(struct uart_port
*port
)
2080 switch (port
->type
) {
2098 static inline unsigned long sci_port_size(struct uart_port
*port
)
2101 * Pick an arbitrary size that encapsulates all of the base
2102 * registers by default. This can be optimized later, or derived
2103 * from platform resource data at such a time that ports begin to
2104 * behave more erratically.
2106 if (port
->type
== PORT_HSCIF
)
2112 static int sci_remap_port(struct uart_port
*port
)
2114 unsigned long size
= sci_port_size(port
);
2117 * Nothing to do if there's already an established membase.
2122 if (port
->flags
& UPF_IOREMAP
) {
2123 port
->membase
= ioremap_nocache(port
->mapbase
, size
);
2124 if (unlikely(!port
->membase
)) {
2125 dev_err(port
->dev
, "can't remap port#%d\n", port
->line
);
2130 * For the simple (and majority of) cases where we don't
2131 * need to do any remapping, just cast the cookie
2134 port
->membase
= (void __iomem
*)(uintptr_t)port
->mapbase
;
2140 static void sci_release_port(struct uart_port
*port
)
2142 if (port
->flags
& UPF_IOREMAP
) {
2143 iounmap(port
->membase
);
2144 port
->membase
= NULL
;
2147 release_mem_region(port
->mapbase
, sci_port_size(port
));
2150 static int sci_request_port(struct uart_port
*port
)
2152 unsigned long size
= sci_port_size(port
);
2153 struct resource
*res
;
2156 res
= request_mem_region(port
->mapbase
, size
, dev_name(port
->dev
));
2157 if (unlikely(res
== NULL
))
2160 ret
= sci_remap_port(port
);
2161 if (unlikely(ret
!= 0)) {
2162 release_resource(res
);
2169 static void sci_config_port(struct uart_port
*port
, int flags
)
2171 if (flags
& UART_CONFIG_TYPE
) {
2172 struct sci_port
*sport
= to_sci_port(port
);
2174 port
->type
= sport
->cfg
->type
;
2175 sci_request_port(port
);
2179 static int sci_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2181 if (ser
->baud_base
< 2400)
2182 /* No paper tape reader for Mitch.. */
2188 static struct uart_ops sci_uart_ops
= {
2189 .tx_empty
= sci_tx_empty
,
2190 .set_mctrl
= sci_set_mctrl
,
2191 .get_mctrl
= sci_get_mctrl
,
2192 .start_tx
= sci_start_tx
,
2193 .stop_tx
= sci_stop_tx
,
2194 .stop_rx
= sci_stop_rx
,
2195 .break_ctl
= sci_break_ctl
,
2196 .startup
= sci_startup
,
2197 .shutdown
= sci_shutdown
,
2198 .set_termios
= sci_set_termios
,
2201 .release_port
= sci_release_port
,
2202 .request_port
= sci_request_port
,
2203 .config_port
= sci_config_port
,
2204 .verify_port
= sci_verify_port
,
2205 #ifdef CONFIG_CONSOLE_POLL
2206 .poll_get_char
= sci_poll_get_char
,
2207 .poll_put_char
= sci_poll_put_char
,
2211 static int sci_init_single(struct platform_device
*dev
,
2212 struct sci_port
*sci_port
, unsigned int index
,
2213 struct plat_sci_port
*p
, bool early
)
2215 struct uart_port
*port
= &sci_port
->port
;
2216 const struct resource
*res
;
2217 unsigned int sampling_rate
;
2223 port
->ops
= &sci_uart_ops
;
2224 port
->iotype
= UPIO_MEM
;
2227 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
2231 port
->mapbase
= res
->start
;
2233 for (i
= 0; i
< ARRAY_SIZE(sci_port
->irqs
); ++i
)
2234 sci_port
->irqs
[i
] = platform_get_irq(dev
, i
);
2236 /* The SCI generates several interrupts. They can be muxed together or
2237 * connected to different interrupt lines. In the muxed case only one
2238 * interrupt resource is specified. In the non-muxed case three or four
2239 * interrupt resources are specified, as the BRI interrupt is optional.
2241 if (sci_port
->irqs
[0] < 0)
2244 if (sci_port
->irqs
[1] < 0) {
2245 sci_port
->irqs
[1] = sci_port
->irqs
[0];
2246 sci_port
->irqs
[2] = sci_port
->irqs
[0];
2247 sci_port
->irqs
[3] = sci_port
->irqs
[0];
2250 if (p
->regtype
== SCIx_PROBE_REGTYPE
) {
2251 ret
= sci_probe_regmap(p
);
2258 port
->fifosize
= 256;
2259 sci_port
->overrun_bit
= 9;
2263 port
->fifosize
= 128;
2265 sci_port
->overrun_bit
= 0;
2268 port
->fifosize
= 64;
2269 sci_port
->overrun_bit
= 9;
2273 port
->fifosize
= 16;
2274 if (p
->regtype
== SCIx_SH7705_SCIF_REGTYPE
) {
2275 sci_port
->overrun_bit
= 9;
2278 sci_port
->overrun_bit
= 0;
2284 sci_port
->overrun_bit
= 5;
2289 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2290 * match the SoC datasheet, this should be investigated. Let platform
2291 * data override the sampling rate for now.
2293 sci_port
->sampling_rate
= p
->sampling_rate
? p
->sampling_rate
2297 sci_port
->iclk
= clk_get(&dev
->dev
, "sci_ick");
2298 if (IS_ERR(sci_port
->iclk
)) {
2299 sci_port
->iclk
= clk_get(&dev
->dev
, "peripheral_clk");
2300 if (IS_ERR(sci_port
->iclk
)) {
2301 dev_err(&dev
->dev
, "can't get iclk\n");
2302 return PTR_ERR(sci_port
->iclk
);
2307 * The function clock is optional, ignore it if we can't
2310 sci_port
->fclk
= clk_get(&dev
->dev
, "sci_fck");
2311 if (IS_ERR(sci_port
->fclk
))
2312 sci_port
->fclk
= NULL
;
2314 port
->dev
= &dev
->dev
;
2316 pm_runtime_enable(&dev
->dev
);
2319 sci_port
->break_timer
.data
= (unsigned long)sci_port
;
2320 sci_port
->break_timer
.function
= sci_break_timer
;
2321 init_timer(&sci_port
->break_timer
);
2324 * Establish some sensible defaults for the error detection.
2326 sci_port
->error_mask
= (p
->type
== PORT_SCI
) ?
2327 SCI_DEFAULT_ERROR_MASK
: SCIF_DEFAULT_ERROR_MASK
;
2330 * Establish sensible defaults for the overrun detection, unless
2331 * the part has explicitly disabled support for it.
2335 * Make the error mask inclusive of overrun detection, if
2338 sci_port
->error_mask
|= 1 << sci_port
->overrun_bit
;
2340 port
->type
= p
->type
;
2341 port
->flags
= UPF_FIXED_PORT
| p
->flags
;
2342 port
->regshift
= p
->regshift
;
2345 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2346 * for the multi-IRQ ports, which is where we are primarily
2347 * concerned with the shutdown path synchronization.
2349 * For the muxed case there's nothing more to do.
2351 port
->irq
= sci_port
->irqs
[SCIx_RXI_IRQ
];
2354 port
->serial_in
= sci_serial_in
;
2355 port
->serial_out
= sci_serial_out
;
2357 if (p
->dma_slave_tx
> 0 && p
->dma_slave_rx
> 0)
2358 dev_dbg(port
->dev
, "DMA tx %d, rx %d\n",
2359 p
->dma_slave_tx
, p
->dma_slave_rx
);
2364 static void sci_cleanup_single(struct sci_port
*port
)
2366 clk_put(port
->iclk
);
2367 clk_put(port
->fclk
);
2369 pm_runtime_disable(port
->port
.dev
);
2372 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2373 static void serial_console_putchar(struct uart_port
*port
, int ch
)
2375 sci_poll_put_char(port
, ch
);
2379 * Print a string to the serial port trying not to disturb
2380 * any possible real use of the port...
2382 static void serial_console_write(struct console
*co
, const char *s
,
2385 struct sci_port
*sci_port
= &sci_ports
[co
->index
];
2386 struct uart_port
*port
= &sci_port
->port
;
2387 unsigned short bits
, ctrl
;
2388 unsigned long flags
;
2391 local_irq_save(flags
);
2394 else if (oops_in_progress
)
2395 locked
= spin_trylock(&port
->lock
);
2397 spin_lock(&port
->lock
);
2399 /* first save the SCSCR then disable the interrupts */
2400 ctrl
= serial_port_in(port
, SCSCR
);
2401 serial_port_out(port
, SCSCR
, sci_port
->cfg
->scscr
);
2403 uart_console_write(port
, s
, count
, serial_console_putchar
);
2405 /* wait until fifo is empty and last bit has been transmitted */
2406 bits
= SCxSR_TDxE(port
) | SCxSR_TEND(port
);
2407 while ((serial_port_in(port
, SCxSR
) & bits
) != bits
)
2410 /* restore the SCSCR */
2411 serial_port_out(port
, SCSCR
, ctrl
);
2414 spin_unlock(&port
->lock
);
2415 local_irq_restore(flags
);
2418 static int serial_console_setup(struct console
*co
, char *options
)
2420 struct sci_port
*sci_port
;
2421 struct uart_port
*port
;
2429 * Refuse to handle any bogus ports.
2431 if (co
->index
< 0 || co
->index
>= SCI_NPORTS
)
2434 sci_port
= &sci_ports
[co
->index
];
2435 port
= &sci_port
->port
;
2438 * Refuse to handle uninitialized ports.
2443 ret
= sci_remap_port(port
);
2444 if (unlikely(ret
!= 0))
2448 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2450 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2453 static struct console serial_console
= {
2455 .device
= uart_console_device
,
2456 .write
= serial_console_write
,
2457 .setup
= serial_console_setup
,
2458 .flags
= CON_PRINTBUFFER
,
2460 .data
= &sci_uart_driver
,
2463 static struct console early_serial_console
= {
2464 .name
= "early_ttySC",
2465 .write
= serial_console_write
,
2466 .flags
= CON_PRINTBUFFER
,
2470 static char early_serial_buf
[32];
2472 static int sci_probe_earlyprintk(struct platform_device
*pdev
)
2474 struct plat_sci_port
*cfg
= dev_get_platdata(&pdev
->dev
);
2476 if (early_serial_console
.data
)
2479 early_serial_console
.index
= pdev
->id
;
2481 sci_init_single(pdev
, &sci_ports
[pdev
->id
], pdev
->id
, cfg
, true);
2483 serial_console_setup(&early_serial_console
, early_serial_buf
);
2485 if (!strstr(early_serial_buf
, "keep"))
2486 early_serial_console
.flags
|= CON_BOOT
;
2488 register_console(&early_serial_console
);
2492 #define SCI_CONSOLE (&serial_console)
2495 static inline int sci_probe_earlyprintk(struct platform_device
*pdev
)
2500 #define SCI_CONSOLE NULL
2502 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2504 static const char banner
[] __initconst
= "SuperH (H)SCI(F) driver initialized";
2506 static struct uart_driver sci_uart_driver
= {
2507 .owner
= THIS_MODULE
,
2508 .driver_name
= "sci",
2509 .dev_name
= "ttySC",
2511 .minor
= SCI_MINOR_START
,
2513 .cons
= SCI_CONSOLE
,
2516 static int sci_remove(struct platform_device
*dev
)
2518 struct sci_port
*port
= platform_get_drvdata(dev
);
2520 cpufreq_unregister_notifier(&port
->freq_transition
,
2521 CPUFREQ_TRANSITION_NOTIFIER
);
2523 uart_remove_one_port(&sci_uart_driver
, &port
->port
);
2525 sci_cleanup_single(port
);
2530 struct sci_port_info
{
2532 unsigned int regtype
;
2535 static const struct of_device_id of_sci_match
[] = {
2537 .compatible
= "renesas,scif",
2538 .data
= &(const struct sci_port_info
) {
2540 .regtype
= SCIx_SH4_SCIF_REGTYPE
,
2543 .compatible
= "renesas,scifa",
2544 .data
= &(const struct sci_port_info
) {
2546 .regtype
= SCIx_SCIFA_REGTYPE
,
2549 .compatible
= "renesas,scifb",
2550 .data
= &(const struct sci_port_info
) {
2552 .regtype
= SCIx_SCIFB_REGTYPE
,
2555 .compatible
= "renesas,hscif",
2556 .data
= &(const struct sci_port_info
) {
2558 .regtype
= SCIx_HSCIF_REGTYPE
,
2564 MODULE_DEVICE_TABLE(of
, of_sci_match
);
2566 static struct plat_sci_port
*
2567 sci_parse_dt(struct platform_device
*pdev
, unsigned int *dev_id
)
2569 struct device_node
*np
= pdev
->dev
.of_node
;
2570 const struct of_device_id
*match
;
2571 const struct sci_port_info
*info
;
2572 struct plat_sci_port
*p
;
2575 if (!IS_ENABLED(CONFIG_OF
) || !np
)
2578 match
= of_match_node(of_sci_match
, pdev
->dev
.of_node
);
2584 p
= devm_kzalloc(&pdev
->dev
, sizeof(struct plat_sci_port
), GFP_KERNEL
);
2586 dev_err(&pdev
->dev
, "failed to allocate DT config data\n");
2590 /* Get the line number for the aliases node. */
2591 id
= of_alias_get_id(np
, "serial");
2593 dev_err(&pdev
->dev
, "failed to get alias id (%d)\n", id
);
2599 p
->flags
= UPF_IOREMAP
| UPF_BOOT_AUTOCONF
;
2600 p
->type
= info
->type
;
2601 p
->regtype
= info
->regtype
;
2602 p
->scscr
= SCSCR_RE
| SCSCR_TE
;
2607 static int sci_probe_single(struct platform_device
*dev
,
2609 struct plat_sci_port
*p
,
2610 struct sci_port
*sciport
)
2615 if (unlikely(index
>= SCI_NPORTS
)) {
2616 dev_notice(&dev
->dev
, "Attempting to register port %d when only %d are available\n",
2617 index
+1, SCI_NPORTS
);
2618 dev_notice(&dev
->dev
, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2622 ret
= sci_init_single(dev
, sciport
, index
, p
, false);
2626 ret
= uart_add_one_port(&sci_uart_driver
, &sciport
->port
);
2628 sci_cleanup_single(sciport
);
2635 static int sci_probe(struct platform_device
*dev
)
2637 struct plat_sci_port
*p
;
2638 struct sci_port
*sp
;
2639 unsigned int dev_id
;
2643 * If we've come here via earlyprintk initialization, head off to
2644 * the special early probe. We don't have sufficient device state
2645 * to make it beyond this yet.
2647 if (is_early_platform_device(dev
))
2648 return sci_probe_earlyprintk(dev
);
2650 if (dev
->dev
.of_node
) {
2651 p
= sci_parse_dt(dev
, &dev_id
);
2655 p
= dev
->dev
.platform_data
;
2657 dev_err(&dev
->dev
, "no platform data supplied\n");
2664 sp
= &sci_ports
[dev_id
];
2665 platform_set_drvdata(dev
, sp
);
2667 ret
= sci_probe_single(dev
, dev_id
, p
, sp
);
2671 sp
->freq_transition
.notifier_call
= sci_notifier
;
2673 ret
= cpufreq_register_notifier(&sp
->freq_transition
,
2674 CPUFREQ_TRANSITION_NOTIFIER
);
2675 if (unlikely(ret
< 0)) {
2676 uart_remove_one_port(&sci_uart_driver
, &sp
->port
);
2677 sci_cleanup_single(sp
);
2681 #ifdef CONFIG_SH_STANDARD_BIOS
2682 sh_bios_gdb_detach();
2688 static __maybe_unused
int sci_suspend(struct device
*dev
)
2690 struct sci_port
*sport
= dev_get_drvdata(dev
);
2693 uart_suspend_port(&sci_uart_driver
, &sport
->port
);
2698 static __maybe_unused
int sci_resume(struct device
*dev
)
2700 struct sci_port
*sport
= dev_get_drvdata(dev
);
2703 uart_resume_port(&sci_uart_driver
, &sport
->port
);
2708 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops
, sci_suspend
, sci_resume
);
2710 static struct platform_driver sci_driver
= {
2712 .remove
= sci_remove
,
2715 .pm
= &sci_dev_pm_ops
,
2716 .of_match_table
= of_match_ptr(of_sci_match
),
2720 static int __init
sci_init(void)
2724 pr_info("%s\n", banner
);
2726 ret
= uart_register_driver(&sci_uart_driver
);
2727 if (likely(ret
== 0)) {
2728 ret
= platform_driver_register(&sci_driver
);
2730 uart_unregister_driver(&sci_uart_driver
);
2736 static void __exit
sci_exit(void)
2738 platform_driver_unregister(&sci_driver
);
2739 uart_unregister_driver(&sci_uart_driver
);
2742 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2743 early_platform_init_buffer("earlyprintk", &sci_driver
,
2744 early_serial_buf
, ARRAY_SIZE(early_serial_buf
));
2746 module_init(sci_init
);
2747 module_exit(sci_exit
);
2749 MODULE_LICENSE("GPL");
2750 MODULE_ALIAS("platform:sh-sci");
2751 MODULE_AUTHOR("Paul Mundt");
2752 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");