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84c15152e111b084cbb387e6a5c98b4ccb420cfc
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
90
91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
94
95 /* Interface clock */
96 struct clk *iclk;
97 /* Function clock */
98 struct clk *fclk;
99
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
102
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
105
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
112 struct scatterlist sg_rx[2];
113 void *rx_buf[2];
114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
120 #endif
121
122 struct notifier_block freq_transition;
123 };
124
125 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
126
127 static struct sci_port sci_ports[SCI_NPORTS];
128 static struct uart_driver sci_uart_driver;
129
130 static inline struct sci_port *
131 to_sci_port(struct uart_port *uart)
132 {
133 return container_of(uart, struct sci_port, port);
134 }
135
136 struct plat_sci_reg {
137 u8 offset, size;
138 };
139
140 /* Helper for invalidating specific entries of an inherited map. */
141 #define sci_reg_invalid { .offset = 0, .size = 0 }
142
143 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
144 [SCIx_PROBE_REGTYPE] = {
145 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
146 },
147
148 /*
149 * Common SCI definitions, dependent on the port's regshift
150 * value.
151 */
152 [SCIx_SCI_REGTYPE] = {
153 [SCSMR] = { 0x00, 8 },
154 [SCBRR] = { 0x01, 8 },
155 [SCSCR] = { 0x02, 8 },
156 [SCxTDR] = { 0x03, 8 },
157 [SCxSR] = { 0x04, 8 },
158 [SCxRDR] = { 0x05, 8 },
159 [SCFCR] = sci_reg_invalid,
160 [SCFDR] = sci_reg_invalid,
161 [SCTFDR] = sci_reg_invalid,
162 [SCRFDR] = sci_reg_invalid,
163 [SCSPTR] = sci_reg_invalid,
164 [SCLSR] = sci_reg_invalid,
165 [HSSRR] = sci_reg_invalid,
166 [SCPCR] = sci_reg_invalid,
167 [SCPDR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common definitions for legacy IrDA ports, dependent on
172 * regshift value.
173 */
174 [SCIx_IRDA_REGTYPE] = {
175 [SCSMR] = { 0x00, 8 },
176 [SCBRR] = { 0x01, 8 },
177 [SCSCR] = { 0x02, 8 },
178 [SCxTDR] = { 0x03, 8 },
179 [SCxSR] = { 0x04, 8 },
180 [SCxRDR] = { 0x05, 8 },
181 [SCFCR] = { 0x06, 8 },
182 [SCFDR] = { 0x07, 16 },
183 [SCTFDR] = sci_reg_invalid,
184 [SCRFDR] = sci_reg_invalid,
185 [SCSPTR] = sci_reg_invalid,
186 [SCLSR] = sci_reg_invalid,
187 [HSSRR] = sci_reg_invalid,
188 [SCPCR] = sci_reg_invalid,
189 [SCPDR] = sci_reg_invalid,
190 },
191
192 /*
193 * Common SCIFA definitions.
194 */
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
211 },
212
213 /*
214 * Common SCIFB definitions.
215 */
216 [SCIx_SCIFB_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x40, 8 },
221 [SCxSR] = { 0x14, 16 },
222 [SCxRDR] = { 0x60, 8 },
223 [SCFCR] = { 0x18, 16 },
224 [SCFDR] = sci_reg_invalid,
225 [SCTFDR] = { 0x38, 16 },
226 [SCRFDR] = { 0x3c, 16 },
227 [SCSPTR] = sci_reg_invalid,
228 [SCLSR] = sci_reg_invalid,
229 [HSSRR] = sci_reg_invalid,
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
232 },
233
234 /*
235 * Common SH-2(A) SCIF definitions for ports with FIFO data
236 * count registers.
237 */
238 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
239 [SCSMR] = { 0x00, 16 },
240 [SCBRR] = { 0x04, 8 },
241 [SCSCR] = { 0x08, 16 },
242 [SCxTDR] = { 0x0c, 8 },
243 [SCxSR] = { 0x10, 16 },
244 [SCxRDR] = { 0x14, 8 },
245 [SCFCR] = { 0x18, 16 },
246 [SCFDR] = { 0x1c, 16 },
247 [SCTFDR] = sci_reg_invalid,
248 [SCRFDR] = sci_reg_invalid,
249 [SCSPTR] = { 0x20, 16 },
250 [SCLSR] = { 0x24, 16 },
251 [HSSRR] = sci_reg_invalid,
252 [SCPCR] = sci_reg_invalid,
253 [SCPDR] = sci_reg_invalid,
254 },
255
256 /*
257 * Common SH-3 SCIF definitions.
258 */
259 [SCIx_SH3_SCIF_REGTYPE] = {
260 [SCSMR] = { 0x00, 8 },
261 [SCBRR] = { 0x02, 8 },
262 [SCSCR] = { 0x04, 8 },
263 [SCxTDR] = { 0x06, 8 },
264 [SCxSR] = { 0x08, 16 },
265 [SCxRDR] = { 0x0a, 8 },
266 [SCFCR] = { 0x0c, 8 },
267 [SCFDR] = { 0x0e, 16 },
268 [SCTFDR] = sci_reg_invalid,
269 [SCRFDR] = sci_reg_invalid,
270 [SCSPTR] = sci_reg_invalid,
271 [SCLSR] = sci_reg_invalid,
272 [HSSRR] = sci_reg_invalid,
273 [SCPCR] = sci_reg_invalid,
274 [SCPDR] = sci_reg_invalid,
275 },
276
277 /*
278 * Common SH-4(A) SCIF(B) definitions.
279 */
280 [SCIx_SH4_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x0c, 8 },
285 [SCxSR] = { 0x10, 16 },
286 [SCxRDR] = { 0x14, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = { 0x20, 16 },
292 [SCLSR] = { 0x24, 16 },
293 [HSSRR] = sci_reg_invalid,
294 [SCPCR] = sci_reg_invalid,
295 [SCPDR] = sci_reg_invalid,
296 },
297
298 /*
299 * Common HSCIF definitions.
300 */
301 [SCIx_HSCIF_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x04, 8 },
304 [SCSCR] = { 0x08, 16 },
305 [SCxTDR] = { 0x0c, 8 },
306 [SCxSR] = { 0x10, 16 },
307 [SCxRDR] = { 0x14, 8 },
308 [SCFCR] = { 0x18, 16 },
309 [SCFDR] = { 0x1c, 16 },
310 [SCTFDR] = sci_reg_invalid,
311 [SCRFDR] = sci_reg_invalid,
312 [SCSPTR] = { 0x20, 16 },
313 [SCLSR] = { 0x24, 16 },
314 [HSSRR] = { 0x40, 16 },
315 [SCPCR] = sci_reg_invalid,
316 [SCPDR] = sci_reg_invalid,
317 },
318
319 /*
320 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
321 * register.
322 */
323 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
324 [SCSMR] = { 0x00, 16 },
325 [SCBRR] = { 0x04, 8 },
326 [SCSCR] = { 0x08, 16 },
327 [SCxTDR] = { 0x0c, 8 },
328 [SCxSR] = { 0x10, 16 },
329 [SCxRDR] = { 0x14, 8 },
330 [SCFCR] = { 0x18, 16 },
331 [SCFDR] = { 0x1c, 16 },
332 [SCTFDR] = sci_reg_invalid,
333 [SCRFDR] = sci_reg_invalid,
334 [SCSPTR] = sci_reg_invalid,
335 [SCLSR] = { 0x24, 16 },
336 [HSSRR] = sci_reg_invalid,
337 [SCPCR] = sci_reg_invalid,
338 [SCPDR] = sci_reg_invalid,
339 },
340
341 /*
342 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
343 * count registers.
344 */
345 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
355 [SCRFDR] = { 0x20, 16 },
356 [SCSPTR] = { 0x24, 16 },
357 [SCLSR] = { 0x28, 16 },
358 [HSSRR] = sci_reg_invalid,
359 [SCPCR] = sci_reg_invalid,
360 [SCPDR] = sci_reg_invalid,
361 },
362
363 /*
364 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
365 * registers.
366 */
367 [SCIx_SH7705_SCIF_REGTYPE] = {
368 [SCSMR] = { 0x00, 16 },
369 [SCBRR] = { 0x04, 8 },
370 [SCSCR] = { 0x08, 16 },
371 [SCxTDR] = { 0x20, 8 },
372 [SCxSR] = { 0x14, 16 },
373 [SCxRDR] = { 0x24, 8 },
374 [SCFCR] = { 0x18, 16 },
375 [SCFDR] = { 0x1c, 16 },
376 [SCTFDR] = sci_reg_invalid,
377 [SCRFDR] = sci_reg_invalid,
378 [SCSPTR] = sci_reg_invalid,
379 [SCLSR] = sci_reg_invalid,
380 [HSSRR] = sci_reg_invalid,
381 [SCPCR] = sci_reg_invalid,
382 [SCPDR] = sci_reg_invalid,
383 },
384 };
385
386 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
387
388 /*
389 * The "offset" here is rather misleading, in that it refers to an enum
390 * value relative to the port mapping rather than the fixed offset
391 * itself, which needs to be manually retrieved from the platform's
392 * register map for the given port.
393 */
394 static unsigned int sci_serial_in(struct uart_port *p, int offset)
395 {
396 const struct plat_sci_reg *reg = sci_getreg(p, offset);
397
398 if (reg->size == 8)
399 return ioread8(p->membase + (reg->offset << p->regshift));
400 else if (reg->size == 16)
401 return ioread16(p->membase + (reg->offset << p->regshift));
402 else
403 WARN(1, "Invalid register access\n");
404
405 return 0;
406 }
407
408 static void sci_serial_out(struct uart_port *p, int offset, int value)
409 {
410 const struct plat_sci_reg *reg = sci_getreg(p, offset);
411
412 if (reg->size == 8)
413 iowrite8(value, p->membase + (reg->offset << p->regshift));
414 else if (reg->size == 16)
415 iowrite16(value, p->membase + (reg->offset << p->regshift));
416 else
417 WARN(1, "Invalid register access\n");
418 }
419
420 static int sci_probe_regmap(struct plat_sci_port *cfg)
421 {
422 switch (cfg->type) {
423 case PORT_SCI:
424 cfg->regtype = SCIx_SCI_REGTYPE;
425 break;
426 case PORT_IRDA:
427 cfg->regtype = SCIx_IRDA_REGTYPE;
428 break;
429 case PORT_SCIFA:
430 cfg->regtype = SCIx_SCIFA_REGTYPE;
431 break;
432 case PORT_SCIFB:
433 cfg->regtype = SCIx_SCIFB_REGTYPE;
434 break;
435 case PORT_SCIF:
436 /*
437 * The SH-4 is a bit of a misnomer here, although that's
438 * where this particular port layout originated. This
439 * configuration (or some slight variation thereof)
440 * remains the dominant model for all SCIFs.
441 */
442 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
443 break;
444 case PORT_HSCIF:
445 cfg->regtype = SCIx_HSCIF_REGTYPE;
446 break;
447 default:
448 pr_err("Can't probe register map for given port\n");
449 return -EINVAL;
450 }
451
452 return 0;
453 }
454
455 static void sci_port_enable(struct sci_port *sci_port)
456 {
457 if (!sci_port->port.dev)
458 return;
459
460 pm_runtime_get_sync(sci_port->port.dev);
461
462 clk_prepare_enable(sci_port->iclk);
463 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
464 clk_prepare_enable(sci_port->fclk);
465 }
466
467 static void sci_port_disable(struct sci_port *sci_port)
468 {
469 if (!sci_port->port.dev)
470 return;
471
472 /* Cancel the break timer to ensure that the timer handler will not try
473 * to access the hardware with clocks and power disabled. Reset the
474 * break flag to make the break debouncing state machine ready for the
475 * next break.
476 */
477 del_timer_sync(&sci_port->break_timer);
478 sci_port->break_flag = 0;
479
480 clk_disable_unprepare(sci_port->fclk);
481 clk_disable_unprepare(sci_port->iclk);
482
483 pm_runtime_put_sync(sci_port->port.dev);
484 }
485
486 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
487 {
488 /*
489 * Not all ports (such as SCIFA) will support REIE. Rather than
490 * special-casing the port type, we check the port initialization
491 * IRQ enable mask to see whether the IRQ is desired at all. If
492 * it's unset, it's logically inferred that there's no point in
493 * testing for it.
494 */
495 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
496 }
497
498 static void sci_start_tx(struct uart_port *port)
499 {
500 struct sci_port *s = to_sci_port(port);
501 unsigned short ctrl;
502
503 #ifdef CONFIG_SERIAL_SH_SCI_DMA
504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
505 u16 new, scr = serial_port_in(port, SCSCR);
506 if (s->chan_tx)
507 new = scr | SCSCR_TDRQE;
508 else
509 new = scr & ~SCSCR_TDRQE;
510 if (new != scr)
511 serial_port_out(port, SCSCR, new);
512 }
513
514 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
515 dma_submit_error(s->cookie_tx)) {
516 s->cookie_tx = 0;
517 schedule_work(&s->work_tx);
518 }
519 #endif
520
521 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
522 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
523 ctrl = serial_port_in(port, SCSCR);
524 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
525 }
526 }
527
528 static void sci_stop_tx(struct uart_port *port)
529 {
530 unsigned short ctrl;
531
532 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
533 ctrl = serial_port_in(port, SCSCR);
534
535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
536 ctrl &= ~SCSCR_TDRQE;
537
538 ctrl &= ~SCSCR_TIE;
539
540 serial_port_out(port, SCSCR, ctrl);
541 }
542
543 static void sci_start_rx(struct uart_port *port)
544 {
545 unsigned short ctrl;
546
547 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
548
549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
550 ctrl &= ~SCSCR_RDRQE;
551
552 serial_port_out(port, SCSCR, ctrl);
553 }
554
555 static void sci_stop_rx(struct uart_port *port)
556 {
557 unsigned short ctrl;
558
559 ctrl = serial_port_in(port, SCSCR);
560
561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
562 ctrl &= ~SCSCR_RDRQE;
563
564 ctrl &= ~port_rx_irq_mask(port);
565
566 serial_port_out(port, SCSCR, ctrl);
567 }
568
569 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
570 {
571 if (port->type == PORT_SCI) {
572 /* Just store the mask */
573 serial_port_out(port, SCxSR, mask);
574 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
575 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
576 /* Only clear the status bits we want to clear */
577 serial_port_out(port, SCxSR,
578 serial_port_in(port, SCxSR) & mask);
579 } else {
580 /* Store the mask, clear parity/framing errors */
581 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
582 }
583 }
584
585 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
586
587 #ifdef CONFIG_CONSOLE_POLL
588 static int sci_poll_get_char(struct uart_port *port)
589 {
590 unsigned short status;
591 int c;
592
593 do {
594 status = serial_port_in(port, SCxSR);
595 if (status & SCxSR_ERRORS(port)) {
596 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
597 continue;
598 }
599 break;
600 } while (1);
601
602 if (!(status & SCxSR_RDxF(port)))
603 return NO_POLL_CHAR;
604
605 c = serial_port_in(port, SCxRDR);
606
607 /* Dummy read */
608 serial_port_in(port, SCxSR);
609 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
610
611 return c;
612 }
613 #endif
614
615 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
616 {
617 unsigned short status;
618
619 do {
620 status = serial_port_in(port, SCxSR);
621 } while (!(status & SCxSR_TDxE(port)));
622
623 serial_port_out(port, SCxTDR, c);
624 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
625 }
626 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
627
628 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
629 {
630 struct sci_port *s = to_sci_port(port);
631 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
632
633 /*
634 * Use port-specific handler if provided.
635 */
636 if (s->cfg->ops && s->cfg->ops->init_pins) {
637 s->cfg->ops->init_pins(port, cflag);
638 return;
639 }
640
641 /*
642 * For the generic path SCSPTR is necessary. Bail out if that's
643 * unavailable, too.
644 */
645 if (!reg->size)
646 return;
647
648 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
649 ((!(cflag & CRTSCTS)))) {
650 unsigned short status;
651
652 status = serial_port_in(port, SCSPTR);
653 status &= ~SCSPTR_CTSIO;
654 status |= SCSPTR_RTSIO;
655 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
656 }
657 }
658
659 static int sci_txfill(struct uart_port *port)
660 {
661 const struct plat_sci_reg *reg;
662
663 reg = sci_getreg(port, SCTFDR);
664 if (reg->size)
665 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
666
667 reg = sci_getreg(port, SCFDR);
668 if (reg->size)
669 return serial_port_in(port, SCFDR) >> 8;
670
671 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
672 }
673
674 static int sci_txroom(struct uart_port *port)
675 {
676 return port->fifosize - sci_txfill(port);
677 }
678
679 static int sci_rxfill(struct uart_port *port)
680 {
681 const struct plat_sci_reg *reg;
682
683 reg = sci_getreg(port, SCRFDR);
684 if (reg->size)
685 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
686
687 reg = sci_getreg(port, SCFDR);
688 if (reg->size)
689 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
690
691 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
692 }
693
694 /*
695 * SCI helper for checking the state of the muxed port/RXD pins.
696 */
697 static inline int sci_rxd_in(struct uart_port *port)
698 {
699 struct sci_port *s = to_sci_port(port);
700
701 if (s->cfg->port_reg <= 0)
702 return 1;
703
704 /* Cast for ARM damage */
705 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
706 }
707
708 /* ********************************************************************** *
709 * the interrupt related routines *
710 * ********************************************************************** */
711
712 static void sci_transmit_chars(struct uart_port *port)
713 {
714 struct circ_buf *xmit = &port->state->xmit;
715 unsigned int stopped = uart_tx_stopped(port);
716 unsigned short status;
717 unsigned short ctrl;
718 int count;
719
720 status = serial_port_in(port, SCxSR);
721 if (!(status & SCxSR_TDxE(port))) {
722 ctrl = serial_port_in(port, SCSCR);
723 if (uart_circ_empty(xmit))
724 ctrl &= ~SCSCR_TIE;
725 else
726 ctrl |= SCSCR_TIE;
727 serial_port_out(port, SCSCR, ctrl);
728 return;
729 }
730
731 count = sci_txroom(port);
732
733 do {
734 unsigned char c;
735
736 if (port->x_char) {
737 c = port->x_char;
738 port->x_char = 0;
739 } else if (!uart_circ_empty(xmit) && !stopped) {
740 c = xmit->buf[xmit->tail];
741 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
742 } else {
743 break;
744 }
745
746 serial_port_out(port, SCxTDR, c);
747
748 port->icount.tx++;
749 } while (--count > 0);
750
751 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
752
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(port);
755 if (uart_circ_empty(xmit)) {
756 sci_stop_tx(port);
757 } else {
758 ctrl = serial_port_in(port, SCSCR);
759
760 if (port->type != PORT_SCI) {
761 serial_port_in(port, SCxSR); /* Dummy read */
762 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
763 }
764
765 ctrl |= SCSCR_TIE;
766 serial_port_out(port, SCSCR, ctrl);
767 }
768 }
769
770 /* On SH3, SCIF may read end-of-break as a space->mark char */
771 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
772
773 static void sci_receive_chars(struct uart_port *port)
774 {
775 struct sci_port *sci_port = to_sci_port(port);
776 struct tty_port *tport = &port->state->port;
777 int i, count, copied = 0;
778 unsigned short status;
779 unsigned char flag;
780
781 status = serial_port_in(port, SCxSR);
782 if (!(status & SCxSR_RDxF(port)))
783 return;
784
785 while (1) {
786 /* Don't copy more bytes than there is room for in the buffer */
787 count = tty_buffer_request_room(tport, sci_rxfill(port));
788
789 /* If for any reason we can't copy more data, we're done! */
790 if (count == 0)
791 break;
792
793 if (port->type == PORT_SCI) {
794 char c = serial_port_in(port, SCxRDR);
795 if (uart_handle_sysrq_char(port, c) ||
796 sci_port->break_flag)
797 count = 0;
798 else
799 tty_insert_flip_char(tport, c, TTY_NORMAL);
800 } else {
801 for (i = 0; i < count; i++) {
802 char c = serial_port_in(port, SCxRDR);
803
804 status = serial_port_in(port, SCxSR);
805 #if defined(CONFIG_CPU_SH3)
806 /* Skip "chars" during break */
807 if (sci_port->break_flag) {
808 if ((c == 0) &&
809 (status & SCxSR_FER(port))) {
810 count--; i--;
811 continue;
812 }
813
814 /* Nonzero => end-of-break */
815 dev_dbg(port->dev, "debounce<%02x>\n", c);
816 sci_port->break_flag = 0;
817
818 if (STEPFN(c)) {
819 count--; i--;
820 continue;
821 }
822 }
823 #endif /* CONFIG_CPU_SH3 */
824 if (uart_handle_sysrq_char(port, c)) {
825 count--; i--;
826 continue;
827 }
828
829 /* Store data and status */
830 if (status & SCxSR_FER(port)) {
831 flag = TTY_FRAME;
832 port->icount.frame++;
833 dev_notice(port->dev, "frame error\n");
834 } else if (status & SCxSR_PER(port)) {
835 flag = TTY_PARITY;
836 port->icount.parity++;
837 dev_notice(port->dev, "parity error\n");
838 } else
839 flag = TTY_NORMAL;
840
841 tty_insert_flip_char(tport, c, flag);
842 }
843 }
844
845 serial_port_in(port, SCxSR); /* dummy read */
846 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
847
848 copied += count;
849 port->icount.rx += count;
850 }
851
852 if (copied) {
853 /* Tell the rest of the system the news. New characters! */
854 tty_flip_buffer_push(tport);
855 } else {
856 serial_port_in(port, SCxSR); /* dummy read */
857 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
858 }
859 }
860
861 #define SCI_BREAK_JIFFIES (HZ/20)
862
863 /*
864 * The sci generates interrupts during the break,
865 * 1 per millisecond or so during the break period, for 9600 baud.
866 * So dont bother disabling interrupts.
867 * But dont want more than 1 break event.
868 * Use a kernel timer to periodically poll the rx line until
869 * the break is finished.
870 */
871 static inline void sci_schedule_break_timer(struct sci_port *port)
872 {
873 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
874 }
875
876 /* Ensure that two consecutive samples find the break over. */
877 static void sci_break_timer(unsigned long data)
878 {
879 struct sci_port *port = (struct sci_port *)data;
880
881 if (sci_rxd_in(&port->port) == 0) {
882 port->break_flag = 1;
883 sci_schedule_break_timer(port);
884 } else if (port->break_flag == 1) {
885 /* break is over. */
886 port->break_flag = 2;
887 sci_schedule_break_timer(port);
888 } else
889 port->break_flag = 0;
890 }
891
892 static int sci_handle_errors(struct uart_port *port)
893 {
894 int copied = 0;
895 unsigned short status = serial_port_in(port, SCxSR);
896 struct tty_port *tport = &port->state->port;
897 struct sci_port *s = to_sci_port(port);
898
899 /* Handle overruns */
900 if (status & s->overrun_mask) {
901 port->icount.overrun++;
902
903 /* overrun error */
904 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
905 copied++;
906
907 dev_notice(port->dev, "overrun error\n");
908 }
909
910 if (status & SCxSR_FER(port)) {
911 if (sci_rxd_in(port) == 0) {
912 /* Notify of BREAK */
913 struct sci_port *sci_port = to_sci_port(port);
914
915 if (!sci_port->break_flag) {
916 port->icount.brk++;
917
918 sci_port->break_flag = 1;
919 sci_schedule_break_timer(sci_port);
920
921 /* Do sysrq handling. */
922 if (uart_handle_break(port))
923 return 0;
924
925 dev_dbg(port->dev, "BREAK detected\n");
926
927 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
928 copied++;
929 }
930
931 } else {
932 /* frame error */
933 port->icount.frame++;
934
935 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
936 copied++;
937
938 dev_notice(port->dev, "frame error\n");
939 }
940 }
941
942 if (status & SCxSR_PER(port)) {
943 /* parity error */
944 port->icount.parity++;
945
946 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
947 copied++;
948
949 dev_notice(port->dev, "parity error\n");
950 }
951
952 if (copied)
953 tty_flip_buffer_push(tport);
954
955 return copied;
956 }
957
958 static int sci_handle_fifo_overrun(struct uart_port *port)
959 {
960 struct tty_port *tport = &port->state->port;
961 struct sci_port *s = to_sci_port(port);
962 const struct plat_sci_reg *reg;
963 int copied = 0;
964 u16 status;
965
966 reg = sci_getreg(port, s->overrun_reg);
967 if (!reg->size)
968 return 0;
969
970 status = serial_port_in(port, s->overrun_reg);
971 if (status & s->overrun_mask) {
972 status &= ~s->overrun_mask;
973 serial_port_out(port, s->overrun_reg, status);
974
975 port->icount.overrun++;
976
977 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
978 tty_flip_buffer_push(tport);
979
980 dev_dbg(port->dev, "overrun error\n");
981 copied++;
982 }
983
984 return copied;
985 }
986
987 static int sci_handle_breaks(struct uart_port *port)
988 {
989 int copied = 0;
990 unsigned short status = serial_port_in(port, SCxSR);
991 struct tty_port *tport = &port->state->port;
992 struct sci_port *s = to_sci_port(port);
993
994 if (uart_handle_break(port))
995 return 0;
996
997 if (!s->break_flag && status & SCxSR_BRK(port)) {
998 #if defined(CONFIG_CPU_SH3)
999 /* Debounce break */
1000 s->break_flag = 1;
1001 #endif
1002
1003 port->icount.brk++;
1004
1005 /* Notify of BREAK */
1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1007 copied++;
1008
1009 dev_dbg(port->dev, "BREAK detected\n");
1010 }
1011
1012 if (copied)
1013 tty_flip_buffer_push(tport);
1014
1015 copied += sci_handle_fifo_overrun(port);
1016
1017 return copied;
1018 }
1019
1020 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1021 static void sci_dma_tx_complete(void *arg)
1022 {
1023 struct sci_port *s = arg;
1024 struct uart_port *port = &s->port;
1025 struct circ_buf *xmit = &port->state->xmit;
1026 unsigned long flags;
1027
1028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1029
1030 spin_lock_irqsave(&port->lock, flags);
1031
1032 xmit->tail += s->tx_dma_len;
1033 xmit->tail &= UART_XMIT_SIZE - 1;
1034
1035 port->icount.tx += s->tx_dma_len;
1036
1037 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1038 uart_write_wakeup(port);
1039
1040 if (!uart_circ_empty(xmit)) {
1041 s->cookie_tx = 0;
1042 schedule_work(&s->work_tx);
1043 } else {
1044 s->cookie_tx = -EINVAL;
1045 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1046 u16 ctrl = serial_port_in(port, SCSCR);
1047 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1048 }
1049 }
1050
1051 spin_unlock_irqrestore(&port->lock, flags);
1052 }
1053
1054 /* Locking: called with port lock held */
1055 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1056 {
1057 struct uart_port *port = &s->port;
1058 struct tty_port *tport = &port->state->port;
1059 int copied;
1060
1061 copied = tty_insert_flip_string(tport, buf, count);
1062 if (copied < count) {
1063 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1064 count - copied);
1065 port->icount.buf_overrun++;
1066 }
1067
1068 port->icount.rx += copied;
1069
1070 return copied;
1071 }
1072
1073 static int sci_dma_rx_find_active(struct sci_port *s)
1074 {
1075 unsigned int i;
1076
1077 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1078 if (s->active_rx == s->cookie_rx[i])
1079 return i;
1080
1081 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1082 s->active_rx);
1083 return -1;
1084 }
1085
1086 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1087 {
1088 struct dma_chan *chan = s->chan_rx;
1089 struct uart_port *port = &s->port;
1090 unsigned long flags;
1091
1092 spin_lock_irqsave(&port->lock, flags);
1093 s->chan_rx = NULL;
1094 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1095 spin_unlock_irqrestore(&port->lock, flags);
1096 dmaengine_terminate_all(chan);
1097 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1098 sg_dma_address(&s->sg_rx[0]));
1099 dma_release_channel(chan);
1100 if (enable_pio)
1101 sci_start_rx(port);
1102 }
1103
1104 static void sci_dma_rx_complete(void *arg)
1105 {
1106 struct sci_port *s = arg;
1107 struct dma_chan *chan = s->chan_rx;
1108 struct uart_port *port = &s->port;
1109 struct dma_async_tx_descriptor *desc;
1110 unsigned long flags;
1111 int active, count = 0;
1112
1113 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1114 s->active_rx);
1115
1116 spin_lock_irqsave(&port->lock, flags);
1117
1118 active = sci_dma_rx_find_active(s);
1119 if (active >= 0)
1120 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1121
1122 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1123
1124 if (count)
1125 tty_flip_buffer_push(&port->state->port);
1126
1127 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1128 DMA_DEV_TO_MEM,
1129 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1130 if (!desc)
1131 goto fail;
1132
1133 desc->callback = sci_dma_rx_complete;
1134 desc->callback_param = s;
1135 s->cookie_rx[active] = dmaengine_submit(desc);
1136 if (dma_submit_error(s->cookie_rx[active]))
1137 goto fail;
1138
1139 s->active_rx = s->cookie_rx[!active];
1140
1141 dma_async_issue_pending(chan);
1142
1143 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1144 __func__, s->cookie_rx[active], active, s->active_rx);
1145 spin_unlock_irqrestore(&port->lock, flags);
1146 return;
1147
1148 fail:
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1151 sci_rx_dma_release(s, true);
1152 }
1153
1154 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1155 {
1156 struct dma_chan *chan = s->chan_tx;
1157 struct uart_port *port = &s->port;
1158 unsigned long flags;
1159
1160 spin_lock_irqsave(&port->lock, flags);
1161 s->chan_tx = NULL;
1162 s->cookie_tx = -EINVAL;
1163 spin_unlock_irqrestore(&port->lock, flags);
1164 dmaengine_terminate_all(chan);
1165 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1166 DMA_TO_DEVICE);
1167 dma_release_channel(chan);
1168 if (enable_pio)
1169 sci_start_tx(port);
1170 }
1171
1172 static void sci_submit_rx(struct sci_port *s)
1173 {
1174 struct dma_chan *chan = s->chan_rx;
1175 int i;
1176
1177 for (i = 0; i < 2; i++) {
1178 struct scatterlist *sg = &s->sg_rx[i];
1179 struct dma_async_tx_descriptor *desc;
1180
1181 desc = dmaengine_prep_slave_sg(chan,
1182 sg, 1, DMA_DEV_TO_MEM,
1183 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1184 if (!desc)
1185 goto fail;
1186
1187 desc->callback = sci_dma_rx_complete;
1188 desc->callback_param = s;
1189 s->cookie_rx[i] = dmaengine_submit(desc);
1190 if (dma_submit_error(s->cookie_rx[i]))
1191 goto fail;
1192
1193 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1194 s->cookie_rx[i], i);
1195 }
1196
1197 s->active_rx = s->cookie_rx[0];
1198
1199 dma_async_issue_pending(chan);
1200 return;
1201
1202 fail:
1203 if (i)
1204 dmaengine_terminate_all(chan);
1205 for (i = 0; i < 2; i++)
1206 s->cookie_rx[i] = -EINVAL;
1207 s->active_rx = -EINVAL;
1208 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1209 sci_rx_dma_release(s, true);
1210 }
1211
1212 static void work_fn_tx(struct work_struct *work)
1213 {
1214 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1215 struct dma_async_tx_descriptor *desc;
1216 struct dma_chan *chan = s->chan_tx;
1217 struct uart_port *port = &s->port;
1218 struct circ_buf *xmit = &port->state->xmit;
1219 dma_addr_t buf;
1220
1221 /*
1222 * DMA is idle now.
1223 * Port xmit buffer is already mapped, and it is one page... Just adjust
1224 * offsets and lengths. Since it is a circular buffer, we have to
1225 * transmit till the end, and then the rest. Take the port lock to get a
1226 * consistent xmit buffer state.
1227 */
1228 spin_lock_irq(&port->lock);
1229 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1230 s->tx_dma_len = min_t(unsigned int,
1231 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1232 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1233 spin_unlock_irq(&port->lock);
1234
1235 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1236 DMA_MEM_TO_DEV,
1237 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1238 if (!desc) {
1239 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1240 /* switch to PIO */
1241 sci_tx_dma_release(s, true);
1242 return;
1243 }
1244
1245 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1246 DMA_TO_DEVICE);
1247
1248 spin_lock_irq(&port->lock);
1249 desc->callback = sci_dma_tx_complete;
1250 desc->callback_param = s;
1251 spin_unlock_irq(&port->lock);
1252 s->cookie_tx = dmaengine_submit(desc);
1253 if (dma_submit_error(s->cookie_tx)) {
1254 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1255 /* switch to PIO */
1256 sci_tx_dma_release(s, true);
1257 return;
1258 }
1259
1260 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1261 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1262
1263 dma_async_issue_pending(chan);
1264 }
1265
1266 static bool filter(struct dma_chan *chan, void *slave)
1267 {
1268 struct sh_dmae_slave *param = slave;
1269
1270 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1271 __func__, param->shdma_slave.slave_id);
1272
1273 chan->private = &param->shdma_slave;
1274 return true;
1275 }
1276
1277 static void rx_timer_fn(unsigned long arg)
1278 {
1279 struct sci_port *s = (struct sci_port *)arg;
1280 struct uart_port *port = &s->port;
1281 struct dma_tx_state state;
1282 enum dma_status status;
1283 unsigned long flags;
1284 unsigned int read;
1285 int active, count;
1286 u16 scr;
1287
1288 spin_lock_irqsave(&port->lock, flags);
1289
1290 dev_dbg(port->dev, "DMA Rx timed out\n");
1291
1292 active = sci_dma_rx_find_active(s);
1293 if (active < 0) {
1294 spin_unlock_irqrestore(&port->lock, flags);
1295 return;
1296 }
1297
1298 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1299 if (status == DMA_COMPLETE)
1300 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1301 s->active_rx, active);
1302
1303 /* Handle incomplete DMA receive */
1304 dmaengine_terminate_all(s->chan_rx);
1305 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1306 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1307 s->active_rx);
1308
1309 if (read) {
1310 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1311 if (count)
1312 tty_flip_buffer_push(&port->state->port);
1313 }
1314
1315 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1316 sci_submit_rx(s);
1317
1318 /* Direct new serial port interrupts back to CPU */
1319 scr = serial_port_in(port, SCSCR);
1320 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1321 scr &= ~SCSCR_RDRQE;
1322 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1323 }
1324 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1325
1326 spin_unlock_irqrestore(&port->lock, flags);
1327 }
1328
1329 static void sci_request_dma(struct uart_port *port)
1330 {
1331 struct sci_port *s = to_sci_port(port);
1332 struct sh_dmae_slave *param;
1333 struct dma_chan *chan;
1334 dma_cap_mask_t mask;
1335
1336 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1337
1338 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1339 return;
1340
1341 dma_cap_zero(mask);
1342 dma_cap_set(DMA_SLAVE, mask);
1343
1344 param = &s->param_tx;
1345
1346 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1347 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1348
1349 s->cookie_tx = -EINVAL;
1350 chan = dma_request_channel(mask, filter, param);
1351 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1352 if (chan) {
1353 s->chan_tx = chan;
1354 /* UART circular tx buffer is an aligned page. */
1355 s->tx_dma_addr = dma_map_single(chan->device->dev,
1356 port->state->xmit.buf,
1357 UART_XMIT_SIZE,
1358 DMA_TO_DEVICE);
1359 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1360 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1361 dma_release_channel(chan);
1362 s->chan_tx = NULL;
1363 } else {
1364 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1365 __func__, UART_XMIT_SIZE,
1366 port->state->xmit.buf, &s->tx_dma_addr);
1367 }
1368
1369 INIT_WORK(&s->work_tx, work_fn_tx);
1370 }
1371
1372 param = &s->param_rx;
1373
1374 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1375 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1376
1377 chan = dma_request_channel(mask, filter, param);
1378 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1379 if (chan) {
1380 unsigned int i;
1381 dma_addr_t dma;
1382 void *buf;
1383
1384 s->chan_rx = chan;
1385
1386 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1387 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1388 &dma, GFP_KERNEL);
1389 if (!buf) {
1390 dev_warn(port->dev,
1391 "Failed to allocate Rx dma buffer, using PIO\n");
1392 dma_release_channel(chan);
1393 s->chan_rx = NULL;
1394 return;
1395 }
1396
1397 for (i = 0; i < 2; i++) {
1398 struct scatterlist *sg = &s->sg_rx[i];
1399
1400 sg_init_table(sg, 1);
1401 s->rx_buf[i] = buf;
1402 sg_dma_address(sg) = dma;
1403 sg->length = s->buf_len_rx;
1404
1405 buf += s->buf_len_rx;
1406 dma += s->buf_len_rx;
1407 }
1408
1409 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1410
1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1412 sci_submit_rx(s);
1413 }
1414 }
1415
1416 static void sci_free_dma(struct uart_port *port)
1417 {
1418 struct sci_port *s = to_sci_port(port);
1419
1420 if (s->chan_tx)
1421 sci_tx_dma_release(s, false);
1422 if (s->chan_rx)
1423 sci_rx_dma_release(s, false);
1424 }
1425 #else
1426 static inline void sci_request_dma(struct uart_port *port)
1427 {
1428 }
1429
1430 static inline void sci_free_dma(struct uart_port *port)
1431 {
1432 }
1433 #endif
1434
1435 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1436 {
1437 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1438 struct uart_port *port = ptr;
1439 struct sci_port *s = to_sci_port(port);
1440
1441 if (s->chan_rx) {
1442 u16 scr = serial_port_in(port, SCSCR);
1443 u16 ssr = serial_port_in(port, SCxSR);
1444
1445 /* Disable future Rx interrupts */
1446 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1447 disable_irq_nosync(irq);
1448 scr |= SCSCR_RDRQE;
1449 } else {
1450 scr &= ~SCSCR_RIE;
1451 sci_submit_rx(s);
1452 }
1453 serial_port_out(port, SCSCR, scr);
1454 /* Clear current interrupt */
1455 serial_port_out(port, SCxSR,
1456 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1457 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1458 jiffies, s->rx_timeout);
1459 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1460
1461 return IRQ_HANDLED;
1462 }
1463 #endif
1464
1465 /* I think sci_receive_chars has to be called irrespective
1466 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1467 * to be disabled?
1468 */
1469 sci_receive_chars(ptr);
1470
1471 return IRQ_HANDLED;
1472 }
1473
1474 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1475 {
1476 struct uart_port *port = ptr;
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&port->lock, flags);
1480 sci_transmit_chars(port);
1481 spin_unlock_irqrestore(&port->lock, flags);
1482
1483 return IRQ_HANDLED;
1484 }
1485
1486 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1487 {
1488 struct uart_port *port = ptr;
1489 struct sci_port *s = to_sci_port(port);
1490
1491 /* Handle errors */
1492 if (port->type == PORT_SCI) {
1493 if (sci_handle_errors(port)) {
1494 /* discard character in rx buffer */
1495 serial_port_in(port, SCxSR);
1496 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1497 }
1498 } else {
1499 sci_handle_fifo_overrun(port);
1500 if (!s->chan_rx)
1501 sci_receive_chars(ptr);
1502 }
1503
1504 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1505
1506 /* Kick the transmission */
1507 if (!s->chan_tx)
1508 sci_tx_interrupt(irq, ptr);
1509
1510 return IRQ_HANDLED;
1511 }
1512
1513 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1514 {
1515 struct uart_port *port = ptr;
1516
1517 /* Handle BREAKs */
1518 sci_handle_breaks(port);
1519 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1520
1521 return IRQ_HANDLED;
1522 }
1523
1524 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1525 {
1526 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1527 struct uart_port *port = ptr;
1528 struct sci_port *s = to_sci_port(port);
1529 irqreturn_t ret = IRQ_NONE;
1530
1531 ssr_status = serial_port_in(port, SCxSR);
1532 scr_status = serial_port_in(port, SCSCR);
1533 if (s->overrun_reg == SCxSR)
1534 orer_status = ssr_status;
1535 else {
1536 if (sci_getreg(port, s->overrun_reg)->size)
1537 orer_status = serial_port_in(port, s->overrun_reg);
1538 }
1539
1540 err_enabled = scr_status & port_rx_irq_mask(port);
1541
1542 /* Tx Interrupt */
1543 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1544 !s->chan_tx)
1545 ret = sci_tx_interrupt(irq, ptr);
1546
1547 /*
1548 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1549 * DR flags
1550 */
1551 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1552 (scr_status & SCSCR_RIE))
1553 ret = sci_rx_interrupt(irq, ptr);
1554
1555 /* Error Interrupt */
1556 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1557 ret = sci_er_interrupt(irq, ptr);
1558
1559 /* Break Interrupt */
1560 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1561 ret = sci_br_interrupt(irq, ptr);
1562
1563 /* Overrun Interrupt */
1564 if (orer_status & s->overrun_mask) {
1565 sci_handle_fifo_overrun(port);
1566 ret = IRQ_HANDLED;
1567 }
1568
1569 return ret;
1570 }
1571
1572 /*
1573 * Here we define a transition notifier so that we can update all of our
1574 * ports' baud rate when the peripheral clock changes.
1575 */
1576 static int sci_notifier(struct notifier_block *self,
1577 unsigned long phase, void *p)
1578 {
1579 struct sci_port *sci_port;
1580 unsigned long flags;
1581
1582 sci_port = container_of(self, struct sci_port, freq_transition);
1583
1584 if (phase == CPUFREQ_POSTCHANGE) {
1585 struct uart_port *port = &sci_port->port;
1586
1587 spin_lock_irqsave(&port->lock, flags);
1588 port->uartclk = clk_get_rate(sci_port->iclk);
1589 spin_unlock_irqrestore(&port->lock, flags);
1590 }
1591
1592 return NOTIFY_OK;
1593 }
1594
1595 static const struct sci_irq_desc {
1596 const char *desc;
1597 irq_handler_t handler;
1598 } sci_irq_desc[] = {
1599 /*
1600 * Split out handlers, the default case.
1601 */
1602 [SCIx_ERI_IRQ] = {
1603 .desc = "rx err",
1604 .handler = sci_er_interrupt,
1605 },
1606
1607 [SCIx_RXI_IRQ] = {
1608 .desc = "rx full",
1609 .handler = sci_rx_interrupt,
1610 },
1611
1612 [SCIx_TXI_IRQ] = {
1613 .desc = "tx empty",
1614 .handler = sci_tx_interrupt,
1615 },
1616
1617 [SCIx_BRI_IRQ] = {
1618 .desc = "break",
1619 .handler = sci_br_interrupt,
1620 },
1621
1622 /*
1623 * Special muxed handler.
1624 */
1625 [SCIx_MUX_IRQ] = {
1626 .desc = "mux",
1627 .handler = sci_mpxed_interrupt,
1628 },
1629 };
1630
1631 static int sci_request_irq(struct sci_port *port)
1632 {
1633 struct uart_port *up = &port->port;
1634 int i, j, ret = 0;
1635
1636 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1637 const struct sci_irq_desc *desc;
1638 int irq;
1639
1640 if (SCIx_IRQ_IS_MUXED(port)) {
1641 i = SCIx_MUX_IRQ;
1642 irq = up->irq;
1643 } else {
1644 irq = port->irqs[i];
1645
1646 /*
1647 * Certain port types won't support all of the
1648 * available interrupt sources.
1649 */
1650 if (unlikely(irq < 0))
1651 continue;
1652 }
1653
1654 desc = sci_irq_desc + i;
1655 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1656 dev_name(up->dev), desc->desc);
1657 if (!port->irqstr[j])
1658 goto out_nomem;
1659
1660 ret = request_irq(irq, desc->handler, up->irqflags,
1661 port->irqstr[j], port);
1662 if (unlikely(ret)) {
1663 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1664 goto out_noirq;
1665 }
1666 }
1667
1668 return 0;
1669
1670 out_noirq:
1671 while (--i >= 0)
1672 free_irq(port->irqs[i], port);
1673
1674 out_nomem:
1675 while (--j >= 0)
1676 kfree(port->irqstr[j]);
1677
1678 return ret;
1679 }
1680
1681 static void sci_free_irq(struct sci_port *port)
1682 {
1683 int i;
1684
1685 /*
1686 * Intentionally in reverse order so we iterate over the muxed
1687 * IRQ first.
1688 */
1689 for (i = 0; i < SCIx_NR_IRQS; i++) {
1690 int irq = port->irqs[i];
1691
1692 /*
1693 * Certain port types won't support all of the available
1694 * interrupt sources.
1695 */
1696 if (unlikely(irq < 0))
1697 continue;
1698
1699 free_irq(port->irqs[i], port);
1700 kfree(port->irqstr[i]);
1701
1702 if (SCIx_IRQ_IS_MUXED(port)) {
1703 /* If there's only one IRQ, we're done. */
1704 return;
1705 }
1706 }
1707 }
1708
1709 static unsigned int sci_tx_empty(struct uart_port *port)
1710 {
1711 unsigned short status = serial_port_in(port, SCxSR);
1712 unsigned short in_tx_fifo = sci_txfill(port);
1713
1714 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1715 }
1716
1717 /*
1718 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1719 * CTS/RTS is supported in hardware by at least one port and controlled
1720 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1721 * handled via the ->init_pins() op, which is a bit of a one-way street,
1722 * lacking any ability to defer pin control -- this will later be
1723 * converted over to the GPIO framework).
1724 *
1725 * Other modes (such as loopback) are supported generically on certain
1726 * port types, but not others. For these it's sufficient to test for the
1727 * existence of the support register and simply ignore the port type.
1728 */
1729 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1730 {
1731 if (mctrl & TIOCM_LOOP) {
1732 const struct plat_sci_reg *reg;
1733
1734 /*
1735 * Standard loopback mode for SCFCR ports.
1736 */
1737 reg = sci_getreg(port, SCFCR);
1738 if (reg->size)
1739 serial_port_out(port, SCFCR,
1740 serial_port_in(port, SCFCR) |
1741 SCFCR_LOOP);
1742 }
1743 }
1744
1745 static unsigned int sci_get_mctrl(struct uart_port *port)
1746 {
1747 /*
1748 * CTS/RTS is handled in hardware when supported, while nothing
1749 * else is wired up. Keep it simple and simply assert DSR/CAR.
1750 */
1751 return TIOCM_DSR | TIOCM_CAR;
1752 }
1753
1754 static void sci_break_ctl(struct uart_port *port, int break_state)
1755 {
1756 struct sci_port *s = to_sci_port(port);
1757 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1758 unsigned short scscr, scsptr;
1759
1760 /* check wheter the port has SCSPTR */
1761 if (!reg->size) {
1762 /*
1763 * Not supported by hardware. Most parts couple break and rx
1764 * interrupts together, with break detection always enabled.
1765 */
1766 return;
1767 }
1768
1769 scsptr = serial_port_in(port, SCSPTR);
1770 scscr = serial_port_in(port, SCSCR);
1771
1772 if (break_state == -1) {
1773 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1774 scscr &= ~SCSCR_TE;
1775 } else {
1776 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1777 scscr |= SCSCR_TE;
1778 }
1779
1780 serial_port_out(port, SCSPTR, scsptr);
1781 serial_port_out(port, SCSCR, scscr);
1782 }
1783
1784 static int sci_startup(struct uart_port *port)
1785 {
1786 struct sci_port *s = to_sci_port(port);
1787 unsigned long flags;
1788 int ret;
1789
1790 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1791
1792 ret = sci_request_irq(s);
1793 if (unlikely(ret < 0))
1794 return ret;
1795
1796 sci_request_dma(port);
1797
1798 spin_lock_irqsave(&port->lock, flags);
1799 sci_start_tx(port);
1800 sci_start_rx(port);
1801 spin_unlock_irqrestore(&port->lock, flags);
1802
1803 return 0;
1804 }
1805
1806 static void sci_shutdown(struct uart_port *port)
1807 {
1808 struct sci_port *s = to_sci_port(port);
1809 unsigned long flags;
1810
1811 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1812
1813 spin_lock_irqsave(&port->lock, flags);
1814 sci_stop_rx(port);
1815 sci_stop_tx(port);
1816 spin_unlock_irqrestore(&port->lock, flags);
1817
1818 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1819 if (s->chan_rx) {
1820 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1821 port->line);
1822 del_timer_sync(&s->rx_timer);
1823 }
1824 #endif
1825
1826 sci_free_dma(port);
1827 sci_free_irq(s);
1828 }
1829
1830 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1831 unsigned long freq)
1832 {
1833 if (s->sampling_rate)
1834 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1835
1836 /* Warn, but use a safe default */
1837 WARN_ON(1);
1838
1839 return ((freq + 16 * bps) / (32 * bps) - 1);
1840 }
1841
1842 /* calculate frame length from SMR */
1843 static int sci_baud_calc_frame_len(unsigned int smr_val)
1844 {
1845 int len = 10;
1846
1847 if (smr_val & SCSMR_CHR)
1848 len--;
1849 if (smr_val & SCSMR_PE)
1850 len++;
1851 if (smr_val & SCSMR_STOP)
1852 len++;
1853
1854 return len;
1855 }
1856
1857
1858 /* calculate sample rate, BRR, and clock select for HSCIF */
1859 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1860 int *brr, unsigned int *srr,
1861 unsigned int *cks, int frame_len)
1862 {
1863 int sr, c, br, err, recv_margin;
1864 int min_err = 1000; /* 100% */
1865 int recv_max_margin = 0;
1866
1867 /* Find the combination of sample rate and clock select with the
1868 smallest deviation from the desired baud rate. */
1869 for (sr = 8; sr <= 32; sr++) {
1870 for (c = 0; c <= 3; c++) {
1871 /* integerized formulas from HSCIF documentation */
1872 br = DIV_ROUND_CLOSEST(freq, (sr *
1873 (1 << (2 * c + 1)) * bps)) - 1;
1874 br = clamp(br, 0, 255);
1875 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1876 (1 << (2 * c + 1)) / 1000)) -
1877 1000;
1878 /* Calc recv margin
1879 * M: Receive margin (%)
1880 * N: Ratio of bit rate to clock (N = sampling rate)
1881 * D: Clock duty (D = 0 to 1.0)
1882 * L: Frame length (L = 9 to 12)
1883 * F: Absolute value of clock frequency deviation
1884 *
1885 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1886 * (|D - 0.5| / N * (1 + F))|
1887 * NOTE: Usually, treat D for 0.5, F is 0 by this
1888 * calculation.
1889 */
1890 recv_margin = abs((500 -
1891 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1892 if (abs(min_err) > abs(err)) {
1893 min_err = err;
1894 recv_max_margin = recv_margin;
1895 } else if ((min_err == err) &&
1896 (recv_margin > recv_max_margin))
1897 recv_max_margin = recv_margin;
1898 else
1899 continue;
1900
1901 *brr = br;
1902 *srr = sr - 1;
1903 *cks = c;
1904 }
1905 }
1906
1907 if (min_err == 1000) {
1908 WARN_ON(1);
1909 /* use defaults */
1910 *brr = 255;
1911 *srr = 15;
1912 *cks = 0;
1913 }
1914 }
1915
1916 static void sci_reset(struct uart_port *port)
1917 {
1918 const struct plat_sci_reg *reg;
1919 unsigned int status;
1920
1921 do {
1922 status = serial_port_in(port, SCxSR);
1923 } while (!(status & SCxSR_TEND(port)));
1924
1925 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1926
1927 reg = sci_getreg(port, SCFCR);
1928 if (reg->size)
1929 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1930 }
1931
1932 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1933 struct ktermios *old)
1934 {
1935 struct sci_port *s = to_sci_port(port);
1936 const struct plat_sci_reg *reg;
1937 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1938 int t = -1;
1939 unsigned int srr = 15;
1940
1941 if ((termios->c_cflag & CSIZE) == CS7)
1942 smr_val |= SCSMR_CHR;
1943 if (termios->c_cflag & PARENB)
1944 smr_val |= SCSMR_PE;
1945 if (termios->c_cflag & PARODD)
1946 smr_val |= SCSMR_PE | SCSMR_ODD;
1947 if (termios->c_cflag & CSTOPB)
1948 smr_val |= SCSMR_STOP;
1949
1950 /*
1951 * earlyprintk comes here early on with port->uartclk set to zero.
1952 * the clock framework is not up and running at this point so here
1953 * we assume that 115200 is the maximum baud rate. please note that
1954 * the baud rate is not programmed during earlyprintk - it is assumed
1955 * that the previous boot loader has enabled required clocks and
1956 * setup the baud rate generator hardware for us already.
1957 */
1958 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1959
1960 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1961 if (likely(baud && port->uartclk)) {
1962 if (s->cfg->type == PORT_HSCIF) {
1963 int frame_len = sci_baud_calc_frame_len(smr_val);
1964 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1965 &cks, frame_len);
1966 } else {
1967 t = sci_scbrr_calc(s, baud, port->uartclk);
1968 for (cks = 0; t >= 256 && cks <= 3; cks++)
1969 t >>= 2;
1970 }
1971 }
1972
1973 sci_port_enable(s);
1974
1975 sci_reset(port);
1976
1977 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1978
1979 uart_update_timeout(port, termios->c_cflag, baud);
1980
1981 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1982 __func__, smr_val, cks, t, s->cfg->scscr);
1983
1984 if (t >= 0) {
1985 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1986 serial_port_out(port, SCBRR, t);
1987 reg = sci_getreg(port, HSSRR);
1988 if (reg->size)
1989 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1990 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1991 } else
1992 serial_port_out(port, SCSMR, smr_val);
1993
1994 sci_init_pins(port, termios->c_cflag);
1995
1996 reg = sci_getreg(port, SCFCR);
1997 if (reg->size) {
1998 unsigned short ctrl = serial_port_in(port, SCFCR);
1999
2000 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2001 if (termios->c_cflag & CRTSCTS)
2002 ctrl |= SCFCR_MCE;
2003 else
2004 ctrl &= ~SCFCR_MCE;
2005 }
2006
2007 /*
2008 * As we've done a sci_reset() above, ensure we don't
2009 * interfere with the FIFOs while toggling MCE. As the
2010 * reset values could still be set, simply mask them out.
2011 */
2012 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2013
2014 serial_port_out(port, SCFCR, ctrl);
2015 }
2016
2017 serial_port_out(port, SCSCR, s->cfg->scscr);
2018
2019 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2020 /*
2021 * Calculate delay for 2 DMA buffers (4 FIFO).
2022 * See serial_core.c::uart_update_timeout().
2023 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2024 * function calculates 1 jiffie for the data plus 5 jiffies for the
2025 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2026 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2027 * value obtained by this formula is too small. Therefore, if the value
2028 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2029 */
2030 if (s->chan_rx) {
2031 unsigned int bits;
2032
2033 /* byte size and parity */
2034 switch (termios->c_cflag & CSIZE) {
2035 case CS5:
2036 bits = 7;
2037 break;
2038 case CS6:
2039 bits = 8;
2040 break;
2041 case CS7:
2042 bits = 9;
2043 break;
2044 default:
2045 bits = 10;
2046 break;
2047 }
2048
2049 if (termios->c_cflag & CSTOPB)
2050 bits++;
2051 if (termios->c_cflag & PARENB)
2052 bits++;
2053 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2054 (baud / 10), 10);
2055 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2056 s->rx_timeout * 1000 / HZ, port->timeout);
2057 if (s->rx_timeout < msecs_to_jiffies(20))
2058 s->rx_timeout = msecs_to_jiffies(20);
2059 }
2060 #endif
2061
2062 if ((termios->c_cflag & CREAD) != 0)
2063 sci_start_rx(port);
2064
2065 sci_port_disable(s);
2066 }
2067
2068 static void sci_pm(struct uart_port *port, unsigned int state,
2069 unsigned int oldstate)
2070 {
2071 struct sci_port *sci_port = to_sci_port(port);
2072
2073 switch (state) {
2074 case UART_PM_STATE_OFF:
2075 sci_port_disable(sci_port);
2076 break;
2077 default:
2078 sci_port_enable(sci_port);
2079 break;
2080 }
2081 }
2082
2083 static const char *sci_type(struct uart_port *port)
2084 {
2085 switch (port->type) {
2086 case PORT_IRDA:
2087 return "irda";
2088 case PORT_SCI:
2089 return "sci";
2090 case PORT_SCIF:
2091 return "scif";
2092 case PORT_SCIFA:
2093 return "scifa";
2094 case PORT_SCIFB:
2095 return "scifb";
2096 case PORT_HSCIF:
2097 return "hscif";
2098 }
2099
2100 return NULL;
2101 }
2102
2103 static int sci_remap_port(struct uart_port *port)
2104 {
2105 struct sci_port *sport = to_sci_port(port);
2106
2107 /*
2108 * Nothing to do if there's already an established membase.
2109 */
2110 if (port->membase)
2111 return 0;
2112
2113 if (port->flags & UPF_IOREMAP) {
2114 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2115 if (unlikely(!port->membase)) {
2116 dev_err(port->dev, "can't remap port#%d\n", port->line);
2117 return -ENXIO;
2118 }
2119 } else {
2120 /*
2121 * For the simple (and majority of) cases where we don't
2122 * need to do any remapping, just cast the cookie
2123 * directly.
2124 */
2125 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2126 }
2127
2128 return 0;
2129 }
2130
2131 static void sci_release_port(struct uart_port *port)
2132 {
2133 struct sci_port *sport = to_sci_port(port);
2134
2135 if (port->flags & UPF_IOREMAP) {
2136 iounmap(port->membase);
2137 port->membase = NULL;
2138 }
2139
2140 release_mem_region(port->mapbase, sport->reg_size);
2141 }
2142
2143 static int sci_request_port(struct uart_port *port)
2144 {
2145 struct resource *res;
2146 struct sci_port *sport = to_sci_port(port);
2147 int ret;
2148
2149 res = request_mem_region(port->mapbase, sport->reg_size,
2150 dev_name(port->dev));
2151 if (unlikely(res == NULL)) {
2152 dev_err(port->dev, "request_mem_region failed.");
2153 return -EBUSY;
2154 }
2155
2156 ret = sci_remap_port(port);
2157 if (unlikely(ret != 0)) {
2158 release_resource(res);
2159 return ret;
2160 }
2161
2162 return 0;
2163 }
2164
2165 static void sci_config_port(struct uart_port *port, int flags)
2166 {
2167 if (flags & UART_CONFIG_TYPE) {
2168 struct sci_port *sport = to_sci_port(port);
2169
2170 port->type = sport->cfg->type;
2171 sci_request_port(port);
2172 }
2173 }
2174
2175 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2176 {
2177 if (ser->baud_base < 2400)
2178 /* No paper tape reader for Mitch.. */
2179 return -EINVAL;
2180
2181 return 0;
2182 }
2183
2184 static struct uart_ops sci_uart_ops = {
2185 .tx_empty = sci_tx_empty,
2186 .set_mctrl = sci_set_mctrl,
2187 .get_mctrl = sci_get_mctrl,
2188 .start_tx = sci_start_tx,
2189 .stop_tx = sci_stop_tx,
2190 .stop_rx = sci_stop_rx,
2191 .break_ctl = sci_break_ctl,
2192 .startup = sci_startup,
2193 .shutdown = sci_shutdown,
2194 .set_termios = sci_set_termios,
2195 .pm = sci_pm,
2196 .type = sci_type,
2197 .release_port = sci_release_port,
2198 .request_port = sci_request_port,
2199 .config_port = sci_config_port,
2200 .verify_port = sci_verify_port,
2201 #ifdef CONFIG_CONSOLE_POLL
2202 .poll_get_char = sci_poll_get_char,
2203 .poll_put_char = sci_poll_put_char,
2204 #endif
2205 };
2206
2207 static int sci_init_single(struct platform_device *dev,
2208 struct sci_port *sci_port, unsigned int index,
2209 struct plat_sci_port *p, bool early)
2210 {
2211 struct uart_port *port = &sci_port->port;
2212 const struct resource *res;
2213 unsigned int i;
2214 int ret;
2215
2216 sci_port->cfg = p;
2217
2218 port->ops = &sci_uart_ops;
2219 port->iotype = UPIO_MEM;
2220 port->line = index;
2221
2222 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2223 if (res == NULL)
2224 return -ENOMEM;
2225
2226 port->mapbase = res->start;
2227 sci_port->reg_size = resource_size(res);
2228
2229 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2230 sci_port->irqs[i] = platform_get_irq(dev, i);
2231
2232 /* The SCI generates several interrupts. They can be muxed together or
2233 * connected to different interrupt lines. In the muxed case only one
2234 * interrupt resource is specified. In the non-muxed case three or four
2235 * interrupt resources are specified, as the BRI interrupt is optional.
2236 */
2237 if (sci_port->irqs[0] < 0)
2238 return -ENXIO;
2239
2240 if (sci_port->irqs[1] < 0) {
2241 sci_port->irqs[1] = sci_port->irqs[0];
2242 sci_port->irqs[2] = sci_port->irqs[0];
2243 sci_port->irqs[3] = sci_port->irqs[0];
2244 }
2245
2246 if (p->regtype == SCIx_PROBE_REGTYPE) {
2247 ret = sci_probe_regmap(p);
2248 if (unlikely(ret))
2249 return ret;
2250 }
2251
2252 switch (p->type) {
2253 case PORT_SCIFB:
2254 port->fifosize = 256;
2255 sci_port->overrun_reg = SCxSR;
2256 sci_port->overrun_mask = SCIFA_ORER;
2257 sci_port->sampling_rate = 16;
2258 break;
2259 case PORT_HSCIF:
2260 port->fifosize = 128;
2261 sci_port->overrun_reg = SCLSR;
2262 sci_port->overrun_mask = SCLSR_ORER;
2263 sci_port->sampling_rate = 0;
2264 break;
2265 case PORT_SCIFA:
2266 port->fifosize = 64;
2267 sci_port->overrun_reg = SCxSR;
2268 sci_port->overrun_mask = SCIFA_ORER;
2269 sci_port->sampling_rate = 16;
2270 break;
2271 case PORT_SCIF:
2272 port->fifosize = 16;
2273 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2274 sci_port->overrun_reg = SCxSR;
2275 sci_port->overrun_mask = SCIFA_ORER;
2276 sci_port->sampling_rate = 16;
2277 } else {
2278 sci_port->overrun_reg = SCLSR;
2279 sci_port->overrun_mask = SCLSR_ORER;
2280 sci_port->sampling_rate = 32;
2281 }
2282 break;
2283 default:
2284 port->fifosize = 1;
2285 sci_port->overrun_reg = SCxSR;
2286 sci_port->overrun_mask = SCI_ORER;
2287 sci_port->sampling_rate = 32;
2288 break;
2289 }
2290
2291 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2292 * match the SoC datasheet, this should be investigated. Let platform
2293 * data override the sampling rate for now.
2294 */
2295 if (p->sampling_rate)
2296 sci_port->sampling_rate = p->sampling_rate;
2297
2298 if (!early) {
2299 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2300 if (IS_ERR(sci_port->iclk)) {
2301 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2302 if (IS_ERR(sci_port->iclk)) {
2303 dev_err(&dev->dev, "can't get iclk\n");
2304 return PTR_ERR(sci_port->iclk);
2305 }
2306 }
2307
2308 /*
2309 * The function clock is optional, ignore it if we can't
2310 * find it.
2311 */
2312 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2313 if (IS_ERR(sci_port->fclk))
2314 sci_port->fclk = NULL;
2315
2316 port->dev = &dev->dev;
2317
2318 pm_runtime_enable(&dev->dev);
2319 }
2320
2321 sci_port->break_timer.data = (unsigned long)sci_port;
2322 sci_port->break_timer.function = sci_break_timer;
2323 init_timer(&sci_port->break_timer);
2324
2325 /*
2326 * Establish some sensible defaults for the error detection.
2327 */
2328 if (p->type == PORT_SCI) {
2329 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2330 sci_port->error_clear = SCI_ERROR_CLEAR;
2331 } else {
2332 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2333 sci_port->error_clear = SCIF_ERROR_CLEAR;
2334 }
2335
2336 /*
2337 * Make the error mask inclusive of overrun detection, if
2338 * supported.
2339 */
2340 if (sci_port->overrun_reg == SCxSR) {
2341 sci_port->error_mask |= sci_port->overrun_mask;
2342 sci_port->error_clear &= ~sci_port->overrun_mask;
2343 }
2344
2345 port->type = p->type;
2346 port->flags = UPF_FIXED_PORT | p->flags;
2347 port->regshift = p->regshift;
2348
2349 /*
2350 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2351 * for the multi-IRQ ports, which is where we are primarily
2352 * concerned with the shutdown path synchronization.
2353 *
2354 * For the muxed case there's nothing more to do.
2355 */
2356 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2357 port->irqflags = 0;
2358
2359 port->serial_in = sci_serial_in;
2360 port->serial_out = sci_serial_out;
2361
2362 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2363 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2364 p->dma_slave_tx, p->dma_slave_rx);
2365
2366 return 0;
2367 }
2368
2369 static void sci_cleanup_single(struct sci_port *port)
2370 {
2371 clk_put(port->iclk);
2372 clk_put(port->fclk);
2373
2374 pm_runtime_disable(port->port.dev);
2375 }
2376
2377 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2378 static void serial_console_putchar(struct uart_port *port, int ch)
2379 {
2380 sci_poll_put_char(port, ch);
2381 }
2382
2383 /*
2384 * Print a string to the serial port trying not to disturb
2385 * any possible real use of the port...
2386 */
2387 static void serial_console_write(struct console *co, const char *s,
2388 unsigned count)
2389 {
2390 struct sci_port *sci_port = &sci_ports[co->index];
2391 struct uart_port *port = &sci_port->port;
2392 unsigned short bits, ctrl;
2393 unsigned long flags;
2394 int locked = 1;
2395
2396 local_irq_save(flags);
2397 if (port->sysrq)
2398 locked = 0;
2399 else if (oops_in_progress)
2400 locked = spin_trylock(&port->lock);
2401 else
2402 spin_lock(&port->lock);
2403
2404 /* first save the SCSCR then disable the interrupts */
2405 ctrl = serial_port_in(port, SCSCR);
2406 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2407
2408 uart_console_write(port, s, count, serial_console_putchar);
2409
2410 /* wait until fifo is empty and last bit has been transmitted */
2411 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2412 while ((serial_port_in(port, SCxSR) & bits) != bits)
2413 cpu_relax();
2414
2415 /* restore the SCSCR */
2416 serial_port_out(port, SCSCR, ctrl);
2417
2418 if (locked)
2419 spin_unlock(&port->lock);
2420 local_irq_restore(flags);
2421 }
2422
2423 static int serial_console_setup(struct console *co, char *options)
2424 {
2425 struct sci_port *sci_port;
2426 struct uart_port *port;
2427 int baud = 115200;
2428 int bits = 8;
2429 int parity = 'n';
2430 int flow = 'n';
2431 int ret;
2432
2433 /*
2434 * Refuse to handle any bogus ports.
2435 */
2436 if (co->index < 0 || co->index >= SCI_NPORTS)
2437 return -ENODEV;
2438
2439 sci_port = &sci_ports[co->index];
2440 port = &sci_port->port;
2441
2442 /*
2443 * Refuse to handle uninitialized ports.
2444 */
2445 if (!port->ops)
2446 return -ENODEV;
2447
2448 ret = sci_remap_port(port);
2449 if (unlikely(ret != 0))
2450 return ret;
2451
2452 if (options)
2453 uart_parse_options(options, &baud, &parity, &bits, &flow);
2454
2455 return uart_set_options(port, co, baud, parity, bits, flow);
2456 }
2457
2458 static struct console serial_console = {
2459 .name = "ttySC",
2460 .device = uart_console_device,
2461 .write = serial_console_write,
2462 .setup = serial_console_setup,
2463 .flags = CON_PRINTBUFFER,
2464 .index = -1,
2465 .data = &sci_uart_driver,
2466 };
2467
2468 static struct console early_serial_console = {
2469 .name = "early_ttySC",
2470 .write = serial_console_write,
2471 .flags = CON_PRINTBUFFER,
2472 .index = -1,
2473 };
2474
2475 static char early_serial_buf[32];
2476
2477 static int sci_probe_earlyprintk(struct platform_device *pdev)
2478 {
2479 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2480
2481 if (early_serial_console.data)
2482 return -EEXIST;
2483
2484 early_serial_console.index = pdev->id;
2485
2486 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2487
2488 serial_console_setup(&early_serial_console, early_serial_buf);
2489
2490 if (!strstr(early_serial_buf, "keep"))
2491 early_serial_console.flags |= CON_BOOT;
2492
2493 register_console(&early_serial_console);
2494 return 0;
2495 }
2496
2497 #define SCI_CONSOLE (&serial_console)
2498
2499 #else
2500 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2501 {
2502 return -EINVAL;
2503 }
2504
2505 #define SCI_CONSOLE NULL
2506
2507 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2508
2509 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2510
2511 static struct uart_driver sci_uart_driver = {
2512 .owner = THIS_MODULE,
2513 .driver_name = "sci",
2514 .dev_name = "ttySC",
2515 .major = SCI_MAJOR,
2516 .minor = SCI_MINOR_START,
2517 .nr = SCI_NPORTS,
2518 .cons = SCI_CONSOLE,
2519 };
2520
2521 static int sci_remove(struct platform_device *dev)
2522 {
2523 struct sci_port *port = platform_get_drvdata(dev);
2524
2525 cpufreq_unregister_notifier(&port->freq_transition,
2526 CPUFREQ_TRANSITION_NOTIFIER);
2527
2528 uart_remove_one_port(&sci_uart_driver, &port->port);
2529
2530 sci_cleanup_single(port);
2531
2532 return 0;
2533 }
2534
2535 struct sci_port_info {
2536 unsigned int type;
2537 unsigned int regtype;
2538 };
2539
2540 static const struct of_device_id of_sci_match[] = {
2541 {
2542 .compatible = "renesas,scif",
2543 .data = &(const struct sci_port_info) {
2544 .type = PORT_SCIF,
2545 .regtype = SCIx_SH4_SCIF_REGTYPE,
2546 },
2547 }, {
2548 .compatible = "renesas,scifa",
2549 .data = &(const struct sci_port_info) {
2550 .type = PORT_SCIFA,
2551 .regtype = SCIx_SCIFA_REGTYPE,
2552 },
2553 }, {
2554 .compatible = "renesas,scifb",
2555 .data = &(const struct sci_port_info) {
2556 .type = PORT_SCIFB,
2557 .regtype = SCIx_SCIFB_REGTYPE,
2558 },
2559 }, {
2560 .compatible = "renesas,hscif",
2561 .data = &(const struct sci_port_info) {
2562 .type = PORT_HSCIF,
2563 .regtype = SCIx_HSCIF_REGTYPE,
2564 },
2565 }, {
2566 .compatible = "renesas,sci",
2567 .data = &(const struct sci_port_info) {
2568 .type = PORT_SCI,
2569 .regtype = SCIx_SCI_REGTYPE,
2570 },
2571 }, {
2572 /* Terminator */
2573 },
2574 };
2575 MODULE_DEVICE_TABLE(of, of_sci_match);
2576
2577 static struct plat_sci_port *
2578 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2579 {
2580 struct device_node *np = pdev->dev.of_node;
2581 const struct of_device_id *match;
2582 const struct sci_port_info *info;
2583 struct plat_sci_port *p;
2584 int id;
2585
2586 if (!IS_ENABLED(CONFIG_OF) || !np)
2587 return NULL;
2588
2589 match = of_match_node(of_sci_match, pdev->dev.of_node);
2590 if (!match)
2591 return NULL;
2592
2593 info = match->data;
2594
2595 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2596 if (!p)
2597 return NULL;
2598
2599 /* Get the line number for the aliases node. */
2600 id = of_alias_get_id(np, "serial");
2601 if (id < 0) {
2602 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2603 return NULL;
2604 }
2605
2606 *dev_id = id;
2607
2608 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2609 p->type = info->type;
2610 p->regtype = info->regtype;
2611 p->scscr = SCSCR_RE | SCSCR_TE;
2612
2613 return p;
2614 }
2615
2616 static int sci_probe_single(struct platform_device *dev,
2617 unsigned int index,
2618 struct plat_sci_port *p,
2619 struct sci_port *sciport)
2620 {
2621 int ret;
2622
2623 /* Sanity check */
2624 if (unlikely(index >= SCI_NPORTS)) {
2625 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2626 index+1, SCI_NPORTS);
2627 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2628 return -EINVAL;
2629 }
2630
2631 ret = sci_init_single(dev, sciport, index, p, false);
2632 if (ret)
2633 return ret;
2634
2635 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2636 if (ret) {
2637 sci_cleanup_single(sciport);
2638 return ret;
2639 }
2640
2641 return 0;
2642 }
2643
2644 static int sci_probe(struct platform_device *dev)
2645 {
2646 struct plat_sci_port *p;
2647 struct sci_port *sp;
2648 unsigned int dev_id;
2649 int ret;
2650
2651 /*
2652 * If we've come here via earlyprintk initialization, head off to
2653 * the special early probe. We don't have sufficient device state
2654 * to make it beyond this yet.
2655 */
2656 if (is_early_platform_device(dev))
2657 return sci_probe_earlyprintk(dev);
2658
2659 if (dev->dev.of_node) {
2660 p = sci_parse_dt(dev, &dev_id);
2661 if (p == NULL)
2662 return -EINVAL;
2663 } else {
2664 p = dev->dev.platform_data;
2665 if (p == NULL) {
2666 dev_err(&dev->dev, "no platform data supplied\n");
2667 return -EINVAL;
2668 }
2669
2670 dev_id = dev->id;
2671 }
2672
2673 sp = &sci_ports[dev_id];
2674 platform_set_drvdata(dev, sp);
2675
2676 ret = sci_probe_single(dev, dev_id, p, sp);
2677 if (ret)
2678 return ret;
2679
2680 sp->freq_transition.notifier_call = sci_notifier;
2681
2682 ret = cpufreq_register_notifier(&sp->freq_transition,
2683 CPUFREQ_TRANSITION_NOTIFIER);
2684 if (unlikely(ret < 0)) {
2685 uart_remove_one_port(&sci_uart_driver, &sp->port);
2686 sci_cleanup_single(sp);
2687 return ret;
2688 }
2689
2690 #ifdef CONFIG_SH_STANDARD_BIOS
2691 sh_bios_gdb_detach();
2692 #endif
2693
2694 return 0;
2695 }
2696
2697 static __maybe_unused int sci_suspend(struct device *dev)
2698 {
2699 struct sci_port *sport = dev_get_drvdata(dev);
2700
2701 if (sport)
2702 uart_suspend_port(&sci_uart_driver, &sport->port);
2703
2704 return 0;
2705 }
2706
2707 static __maybe_unused int sci_resume(struct device *dev)
2708 {
2709 struct sci_port *sport = dev_get_drvdata(dev);
2710
2711 if (sport)
2712 uart_resume_port(&sci_uart_driver, &sport->port);
2713
2714 return 0;
2715 }
2716
2717 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2718
2719 static struct platform_driver sci_driver = {
2720 .probe = sci_probe,
2721 .remove = sci_remove,
2722 .driver = {
2723 .name = "sh-sci",
2724 .pm = &sci_dev_pm_ops,
2725 .of_match_table = of_match_ptr(of_sci_match),
2726 },
2727 };
2728
2729 static int __init sci_init(void)
2730 {
2731 int ret;
2732
2733 pr_info("%s\n", banner);
2734
2735 ret = uart_register_driver(&sci_uart_driver);
2736 if (likely(ret == 0)) {
2737 ret = platform_driver_register(&sci_driver);
2738 if (unlikely(ret))
2739 uart_unregister_driver(&sci_uart_driver);
2740 }
2741
2742 return ret;
2743 }
2744
2745 static void __exit sci_exit(void)
2746 {
2747 platform_driver_unregister(&sci_driver);
2748 uart_unregister_driver(&sci_uart_driver);
2749 }
2750
2751 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2752 early_platform_init_buffer("earlyprintk", &sci_driver,
2753 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2754 #endif
2755 module_init(sci_init);
2756 module_exit(sci_exit);
2757
2758 MODULE_LICENSE("GPL");
2759 MODULE_ALIAS("platform:sh-sci");
2760 MODULE_AUTHOR("Paul Mundt");
2761 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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