2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ
= SCIx_NR_IRQS
, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port
;
82 /* Platform configuration */
83 struct plat_sci_port
*cfg
;
84 unsigned int overrun_reg
;
85 unsigned int overrun_mask
;
86 unsigned int error_mask
;
87 unsigned int error_clear
;
88 unsigned int sampling_rate
;
89 resource_size_t reg_size
;
92 struct timer_list break_timer
;
100 int irqs
[SCIx_NR_IRQS
];
101 char *irqstr
[SCIx_NR_IRQS
];
103 struct dma_chan
*chan_tx
;
104 struct dma_chan
*chan_rx
;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 struct dma_async_tx_descriptor
*desc_tx
;
108 struct dma_async_tx_descriptor
*desc_rx
[2];
109 dma_cookie_t cookie_tx
;
110 dma_cookie_t cookie_rx
[2];
111 dma_cookie_t active_rx
;
112 struct scatterlist sg_tx
;
113 unsigned int sg_len_tx
;
114 struct scatterlist sg_rx
[2];
116 struct sh_dmae_slave param_tx
;
117 struct sh_dmae_slave param_rx
;
118 struct work_struct work_tx
;
119 struct work_struct work_rx
;
120 struct timer_list rx_timer
;
121 unsigned int rx_timeout
;
124 struct notifier_block freq_transition
;
127 /* Function prototypes */
128 static void sci_start_tx(struct uart_port
*port
);
129 static void sci_stop_tx(struct uart_port
*port
);
130 static void sci_start_rx(struct uart_port
*port
);
132 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
134 static struct sci_port sci_ports
[SCI_NPORTS
];
135 static struct uart_driver sci_uart_driver
;
137 static inline struct sci_port
*
138 to_sci_port(struct uart_port
*uart
)
140 return container_of(uart
, struct sci_port
, port
);
143 struct plat_sci_reg
{
147 /* Helper for invalidating specific entries of an inherited map. */
148 #define sci_reg_invalid { .offset = 0, .size = 0 }
150 static const struct plat_sci_reg sci_regmap
[SCIx_NR_REGTYPES
][SCIx_NR_REGS
] = {
151 [SCIx_PROBE_REGTYPE
] = {
152 [0 ... SCIx_NR_REGS
- 1] = sci_reg_invalid
,
156 * Common SCI definitions, dependent on the port's regshift
159 [SCIx_SCI_REGTYPE
] = {
160 [SCSMR
] = { 0x00, 8 },
161 [SCBRR
] = { 0x01, 8 },
162 [SCSCR
] = { 0x02, 8 },
163 [SCxTDR
] = { 0x03, 8 },
164 [SCxSR
] = { 0x04, 8 },
165 [SCxRDR
] = { 0x05, 8 },
166 [SCFCR
] = sci_reg_invalid
,
167 [SCFDR
] = sci_reg_invalid
,
168 [SCTFDR
] = sci_reg_invalid
,
169 [SCRFDR
] = sci_reg_invalid
,
170 [SCSPTR
] = sci_reg_invalid
,
171 [SCLSR
] = sci_reg_invalid
,
172 [HSSRR
] = sci_reg_invalid
,
173 [SCPCR
] = sci_reg_invalid
,
174 [SCPDR
] = sci_reg_invalid
,
178 * Common definitions for legacy IrDA ports, dependent on
181 [SCIx_IRDA_REGTYPE
] = {
182 [SCSMR
] = { 0x00, 8 },
183 [SCBRR
] = { 0x01, 8 },
184 [SCSCR
] = { 0x02, 8 },
185 [SCxTDR
] = { 0x03, 8 },
186 [SCxSR
] = { 0x04, 8 },
187 [SCxRDR
] = { 0x05, 8 },
188 [SCFCR
] = { 0x06, 8 },
189 [SCFDR
] = { 0x07, 16 },
190 [SCTFDR
] = sci_reg_invalid
,
191 [SCRFDR
] = sci_reg_invalid
,
192 [SCSPTR
] = sci_reg_invalid
,
193 [SCLSR
] = sci_reg_invalid
,
194 [HSSRR
] = sci_reg_invalid
,
195 [SCPCR
] = sci_reg_invalid
,
196 [SCPDR
] = sci_reg_invalid
,
200 * Common SCIFA definitions.
202 [SCIx_SCIFA_REGTYPE
] = {
203 [SCSMR
] = { 0x00, 16 },
204 [SCBRR
] = { 0x04, 8 },
205 [SCSCR
] = { 0x08, 16 },
206 [SCxTDR
] = { 0x20, 8 },
207 [SCxSR
] = { 0x14, 16 },
208 [SCxRDR
] = { 0x24, 8 },
209 [SCFCR
] = { 0x18, 16 },
210 [SCFDR
] = { 0x1c, 16 },
211 [SCTFDR
] = sci_reg_invalid
,
212 [SCRFDR
] = sci_reg_invalid
,
213 [SCSPTR
] = sci_reg_invalid
,
214 [SCLSR
] = sci_reg_invalid
,
215 [HSSRR
] = sci_reg_invalid
,
216 [SCPCR
] = { 0x30, 16 },
217 [SCPDR
] = { 0x34, 16 },
221 * Common SCIFB definitions.
223 [SCIx_SCIFB_REGTYPE
] = {
224 [SCSMR
] = { 0x00, 16 },
225 [SCBRR
] = { 0x04, 8 },
226 [SCSCR
] = { 0x08, 16 },
227 [SCxTDR
] = { 0x40, 8 },
228 [SCxSR
] = { 0x14, 16 },
229 [SCxRDR
] = { 0x60, 8 },
230 [SCFCR
] = { 0x18, 16 },
231 [SCFDR
] = sci_reg_invalid
,
232 [SCTFDR
] = { 0x38, 16 },
233 [SCRFDR
] = { 0x3c, 16 },
234 [SCSPTR
] = sci_reg_invalid
,
235 [SCLSR
] = sci_reg_invalid
,
236 [HSSRR
] = sci_reg_invalid
,
237 [SCPCR
] = { 0x30, 16 },
238 [SCPDR
] = { 0x34, 16 },
242 * Common SH-2(A) SCIF definitions for ports with FIFO data
245 [SCIx_SH2_SCIF_FIFODATA_REGTYPE
] = {
246 [SCSMR
] = { 0x00, 16 },
247 [SCBRR
] = { 0x04, 8 },
248 [SCSCR
] = { 0x08, 16 },
249 [SCxTDR
] = { 0x0c, 8 },
250 [SCxSR
] = { 0x10, 16 },
251 [SCxRDR
] = { 0x14, 8 },
252 [SCFCR
] = { 0x18, 16 },
253 [SCFDR
] = { 0x1c, 16 },
254 [SCTFDR
] = sci_reg_invalid
,
255 [SCRFDR
] = sci_reg_invalid
,
256 [SCSPTR
] = { 0x20, 16 },
257 [SCLSR
] = { 0x24, 16 },
258 [HSSRR
] = sci_reg_invalid
,
259 [SCPCR
] = sci_reg_invalid
,
260 [SCPDR
] = sci_reg_invalid
,
264 * Common SH-3 SCIF definitions.
266 [SCIx_SH3_SCIF_REGTYPE
] = {
267 [SCSMR
] = { 0x00, 8 },
268 [SCBRR
] = { 0x02, 8 },
269 [SCSCR
] = { 0x04, 8 },
270 [SCxTDR
] = { 0x06, 8 },
271 [SCxSR
] = { 0x08, 16 },
272 [SCxRDR
] = { 0x0a, 8 },
273 [SCFCR
] = { 0x0c, 8 },
274 [SCFDR
] = { 0x0e, 16 },
275 [SCTFDR
] = sci_reg_invalid
,
276 [SCRFDR
] = sci_reg_invalid
,
277 [SCSPTR
] = sci_reg_invalid
,
278 [SCLSR
] = sci_reg_invalid
,
279 [HSSRR
] = sci_reg_invalid
,
280 [SCPCR
] = sci_reg_invalid
,
281 [SCPDR
] = sci_reg_invalid
,
285 * Common SH-4(A) SCIF(B) definitions.
287 [SCIx_SH4_SCIF_REGTYPE
] = {
288 [SCSMR
] = { 0x00, 16 },
289 [SCBRR
] = { 0x04, 8 },
290 [SCSCR
] = { 0x08, 16 },
291 [SCxTDR
] = { 0x0c, 8 },
292 [SCxSR
] = { 0x10, 16 },
293 [SCxRDR
] = { 0x14, 8 },
294 [SCFCR
] = { 0x18, 16 },
295 [SCFDR
] = { 0x1c, 16 },
296 [SCTFDR
] = sci_reg_invalid
,
297 [SCRFDR
] = sci_reg_invalid
,
298 [SCSPTR
] = { 0x20, 16 },
299 [SCLSR
] = { 0x24, 16 },
300 [HSSRR
] = sci_reg_invalid
,
301 [SCPCR
] = sci_reg_invalid
,
302 [SCPDR
] = sci_reg_invalid
,
306 * Common HSCIF definitions.
308 [SCIx_HSCIF_REGTYPE
] = {
309 [SCSMR
] = { 0x00, 16 },
310 [SCBRR
] = { 0x04, 8 },
311 [SCSCR
] = { 0x08, 16 },
312 [SCxTDR
] = { 0x0c, 8 },
313 [SCxSR
] = { 0x10, 16 },
314 [SCxRDR
] = { 0x14, 8 },
315 [SCFCR
] = { 0x18, 16 },
316 [SCFDR
] = { 0x1c, 16 },
317 [SCTFDR
] = sci_reg_invalid
,
318 [SCRFDR
] = sci_reg_invalid
,
319 [SCSPTR
] = { 0x20, 16 },
320 [SCLSR
] = { 0x24, 16 },
321 [HSSRR
] = { 0x40, 16 },
322 [SCPCR
] = sci_reg_invalid
,
323 [SCPDR
] = sci_reg_invalid
,
327 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
330 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE
] = {
331 [SCSMR
] = { 0x00, 16 },
332 [SCBRR
] = { 0x04, 8 },
333 [SCSCR
] = { 0x08, 16 },
334 [SCxTDR
] = { 0x0c, 8 },
335 [SCxSR
] = { 0x10, 16 },
336 [SCxRDR
] = { 0x14, 8 },
337 [SCFCR
] = { 0x18, 16 },
338 [SCFDR
] = { 0x1c, 16 },
339 [SCTFDR
] = sci_reg_invalid
,
340 [SCRFDR
] = sci_reg_invalid
,
341 [SCSPTR
] = sci_reg_invalid
,
342 [SCLSR
] = { 0x24, 16 },
343 [HSSRR
] = sci_reg_invalid
,
344 [SCPCR
] = sci_reg_invalid
,
345 [SCPDR
] = sci_reg_invalid
,
349 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
352 [SCIx_SH4_SCIF_FIFODATA_REGTYPE
] = {
353 [SCSMR
] = { 0x00, 16 },
354 [SCBRR
] = { 0x04, 8 },
355 [SCSCR
] = { 0x08, 16 },
356 [SCxTDR
] = { 0x0c, 8 },
357 [SCxSR
] = { 0x10, 16 },
358 [SCxRDR
] = { 0x14, 8 },
359 [SCFCR
] = { 0x18, 16 },
360 [SCFDR
] = { 0x1c, 16 },
361 [SCTFDR
] = { 0x1c, 16 }, /* aliased to SCFDR */
362 [SCRFDR
] = { 0x20, 16 },
363 [SCSPTR
] = { 0x24, 16 },
364 [SCLSR
] = { 0x28, 16 },
365 [HSSRR
] = sci_reg_invalid
,
366 [SCPCR
] = sci_reg_invalid
,
367 [SCPDR
] = sci_reg_invalid
,
371 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
374 [SCIx_SH7705_SCIF_REGTYPE
] = {
375 [SCSMR
] = { 0x00, 16 },
376 [SCBRR
] = { 0x04, 8 },
377 [SCSCR
] = { 0x08, 16 },
378 [SCxTDR
] = { 0x20, 8 },
379 [SCxSR
] = { 0x14, 16 },
380 [SCxRDR
] = { 0x24, 8 },
381 [SCFCR
] = { 0x18, 16 },
382 [SCFDR
] = { 0x1c, 16 },
383 [SCTFDR
] = sci_reg_invalid
,
384 [SCRFDR
] = sci_reg_invalid
,
385 [SCSPTR
] = sci_reg_invalid
,
386 [SCLSR
] = sci_reg_invalid
,
387 [HSSRR
] = sci_reg_invalid
,
388 [SCPCR
] = sci_reg_invalid
,
389 [SCPDR
] = sci_reg_invalid
,
393 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
396 * The "offset" here is rather misleading, in that it refers to an enum
397 * value relative to the port mapping rather than the fixed offset
398 * itself, which needs to be manually retrieved from the platform's
399 * register map for the given port.
401 static unsigned int sci_serial_in(struct uart_port
*p
, int offset
)
403 const struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
406 return ioread8(p
->membase
+ (reg
->offset
<< p
->regshift
));
407 else if (reg
->size
== 16)
408 return ioread16(p
->membase
+ (reg
->offset
<< p
->regshift
));
410 WARN(1, "Invalid register access\n");
415 static void sci_serial_out(struct uart_port
*p
, int offset
, int value
)
417 const struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
420 iowrite8(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
421 else if (reg
->size
== 16)
422 iowrite16(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
424 WARN(1, "Invalid register access\n");
427 static int sci_probe_regmap(struct plat_sci_port
*cfg
)
431 cfg
->regtype
= SCIx_SCI_REGTYPE
;
434 cfg
->regtype
= SCIx_IRDA_REGTYPE
;
437 cfg
->regtype
= SCIx_SCIFA_REGTYPE
;
440 cfg
->regtype
= SCIx_SCIFB_REGTYPE
;
444 * The SH-4 is a bit of a misnomer here, although that's
445 * where this particular port layout originated. This
446 * configuration (or some slight variation thereof)
447 * remains the dominant model for all SCIFs.
449 cfg
->regtype
= SCIx_SH4_SCIF_REGTYPE
;
452 cfg
->regtype
= SCIx_HSCIF_REGTYPE
;
455 pr_err("Can't probe register map for given port\n");
462 static void sci_port_enable(struct sci_port
*sci_port
)
464 if (!sci_port
->port
.dev
)
467 pm_runtime_get_sync(sci_port
->port
.dev
);
469 clk_prepare_enable(sci_port
->iclk
);
470 sci_port
->port
.uartclk
= clk_get_rate(sci_port
->iclk
);
471 clk_prepare_enable(sci_port
->fclk
);
474 static void sci_port_disable(struct sci_port
*sci_port
)
476 if (!sci_port
->port
.dev
)
479 /* Cancel the break timer to ensure that the timer handler will not try
480 * to access the hardware with clocks and power disabled. Reset the
481 * break flag to make the break debouncing state machine ready for the
484 del_timer_sync(&sci_port
->break_timer
);
485 sci_port
->break_flag
= 0;
487 clk_disable_unprepare(sci_port
->fclk
);
488 clk_disable_unprepare(sci_port
->iclk
);
490 pm_runtime_put_sync(sci_port
->port
.dev
);
493 static void sci_clear_SCxSR(struct uart_port
*port
, unsigned int mask
)
495 if (port
->type
== PORT_SCI
) {
496 /* Just store the mask */
497 serial_port_out(port
, SCxSR
, mask
);
498 } else if (to_sci_port(port
)->overrun_mask
== SCIFA_ORER
) {
499 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
500 /* Only clear the status bits we want to clear */
501 serial_port_out(port
, SCxSR
,
502 serial_port_in(port
, SCxSR
) & mask
);
504 /* Store the mask, clear parity/framing errors */
505 serial_port_out(port
, SCxSR
, mask
& ~(SCIF_FERC
| SCIF_PERC
));
509 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
511 #ifdef CONFIG_CONSOLE_POLL
512 static int sci_poll_get_char(struct uart_port
*port
)
514 unsigned short status
;
518 status
= serial_port_in(port
, SCxSR
);
519 if (status
& SCxSR_ERRORS(port
)) {
520 sci_clear_SCxSR(port
, SCxSR_ERROR_CLEAR(port
));
526 if (!(status
& SCxSR_RDxF(port
)))
529 c
= serial_port_in(port
, SCxRDR
);
532 serial_port_in(port
, SCxSR
);
533 sci_clear_SCxSR(port
, SCxSR_RDxF_CLEAR(port
));
539 static void sci_poll_put_char(struct uart_port
*port
, unsigned char c
)
541 unsigned short status
;
544 status
= serial_port_in(port
, SCxSR
);
545 } while (!(status
& SCxSR_TDxE(port
)));
547 serial_port_out(port
, SCxTDR
, c
);
548 sci_clear_SCxSR(port
, SCxSR_TDxE_CLEAR(port
) & ~SCxSR_TEND(port
));
550 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
552 static void sci_init_pins(struct uart_port
*port
, unsigned int cflag
)
554 struct sci_port
*s
= to_sci_port(port
);
555 const struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
558 * Use port-specific handler if provided.
560 if (s
->cfg
->ops
&& s
->cfg
->ops
->init_pins
) {
561 s
->cfg
->ops
->init_pins(port
, cflag
);
566 * For the generic path SCSPTR is necessary. Bail out if that's
572 if ((s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) &&
573 ((!(cflag
& CRTSCTS
)))) {
574 unsigned short status
;
576 status
= serial_port_in(port
, SCSPTR
);
577 status
&= ~SCSPTR_CTSIO
;
578 status
|= SCSPTR_RTSIO
;
579 serial_port_out(port
, SCSPTR
, status
); /* Set RTS = 1 */
583 static int sci_txfill(struct uart_port
*port
)
585 const struct plat_sci_reg
*reg
;
587 reg
= sci_getreg(port
, SCTFDR
);
589 return serial_port_in(port
, SCTFDR
) & ((port
->fifosize
<< 1) - 1);
591 reg
= sci_getreg(port
, SCFDR
);
593 return serial_port_in(port
, SCFDR
) >> 8;
595 return !(serial_port_in(port
, SCxSR
) & SCI_TDRE
);
598 static int sci_txroom(struct uart_port
*port
)
600 return port
->fifosize
- sci_txfill(port
);
603 static int sci_rxfill(struct uart_port
*port
)
605 const struct plat_sci_reg
*reg
;
607 reg
= sci_getreg(port
, SCRFDR
);
609 return serial_port_in(port
, SCRFDR
) & ((port
->fifosize
<< 1) - 1);
611 reg
= sci_getreg(port
, SCFDR
);
613 return serial_port_in(port
, SCFDR
) & ((port
->fifosize
<< 1) - 1);
615 return (serial_port_in(port
, SCxSR
) & SCxSR_RDxF(port
)) != 0;
619 * SCI helper for checking the state of the muxed port/RXD pins.
621 static inline int sci_rxd_in(struct uart_port
*port
)
623 struct sci_port
*s
= to_sci_port(port
);
625 if (s
->cfg
->port_reg
<= 0)
628 /* Cast for ARM damage */
629 return !!__raw_readb((void __iomem
*)(uintptr_t)s
->cfg
->port_reg
);
632 /* ********************************************************************** *
633 * the interrupt related routines *
634 * ********************************************************************** */
636 static void sci_transmit_chars(struct uart_port
*port
)
638 struct circ_buf
*xmit
= &port
->state
->xmit
;
639 unsigned int stopped
= uart_tx_stopped(port
);
640 unsigned short status
;
644 status
= serial_port_in(port
, SCxSR
);
645 if (!(status
& SCxSR_TDxE(port
))) {
646 ctrl
= serial_port_in(port
, SCSCR
);
647 if (uart_circ_empty(xmit
))
651 serial_port_out(port
, SCSCR
, ctrl
);
655 count
= sci_txroom(port
);
663 } else if (!uart_circ_empty(xmit
) && !stopped
) {
664 c
= xmit
->buf
[xmit
->tail
];
665 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
670 serial_port_out(port
, SCxTDR
, c
);
673 } while (--count
> 0);
675 sci_clear_SCxSR(port
, SCxSR_TDxE_CLEAR(port
));
677 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
678 uart_write_wakeup(port
);
679 if (uart_circ_empty(xmit
)) {
682 ctrl
= serial_port_in(port
, SCSCR
);
684 if (port
->type
!= PORT_SCI
) {
685 serial_port_in(port
, SCxSR
); /* Dummy read */
686 sci_clear_SCxSR(port
, SCxSR_TDxE_CLEAR(port
));
690 serial_port_out(port
, SCSCR
, ctrl
);
694 /* On SH3, SCIF may read end-of-break as a space->mark char */
695 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
697 static void sci_receive_chars(struct uart_port
*port
)
699 struct sci_port
*sci_port
= to_sci_port(port
);
700 struct tty_port
*tport
= &port
->state
->port
;
701 int i
, count
, copied
= 0;
702 unsigned short status
;
705 status
= serial_port_in(port
, SCxSR
);
706 if (!(status
& SCxSR_RDxF(port
)))
710 /* Don't copy more bytes than there is room for in the buffer */
711 count
= tty_buffer_request_room(tport
, sci_rxfill(port
));
713 /* If for any reason we can't copy more data, we're done! */
717 if (port
->type
== PORT_SCI
) {
718 char c
= serial_port_in(port
, SCxRDR
);
719 if (uart_handle_sysrq_char(port
, c
) ||
720 sci_port
->break_flag
)
723 tty_insert_flip_char(tport
, c
, TTY_NORMAL
);
725 for (i
= 0; i
< count
; i
++) {
726 char c
= serial_port_in(port
, SCxRDR
);
728 status
= serial_port_in(port
, SCxSR
);
729 #if defined(CONFIG_CPU_SH3)
730 /* Skip "chars" during break */
731 if (sci_port
->break_flag
) {
733 (status
& SCxSR_FER(port
))) {
738 /* Nonzero => end-of-break */
739 dev_dbg(port
->dev
, "debounce<%02x>\n", c
);
740 sci_port
->break_flag
= 0;
747 #endif /* CONFIG_CPU_SH3 */
748 if (uart_handle_sysrq_char(port
, c
)) {
753 /* Store data and status */
754 if (status
& SCxSR_FER(port
)) {
756 port
->icount
.frame
++;
757 dev_notice(port
->dev
, "frame error\n");
758 } else if (status
& SCxSR_PER(port
)) {
760 port
->icount
.parity
++;
761 dev_notice(port
->dev
, "parity error\n");
765 tty_insert_flip_char(tport
, c
, flag
);
769 serial_port_in(port
, SCxSR
); /* dummy read */
770 sci_clear_SCxSR(port
, SCxSR_RDxF_CLEAR(port
));
773 port
->icount
.rx
+= count
;
777 /* Tell the rest of the system the news. New characters! */
778 tty_flip_buffer_push(tport
);
780 serial_port_in(port
, SCxSR
); /* dummy read */
781 sci_clear_SCxSR(port
, SCxSR_RDxF_CLEAR(port
));
785 #define SCI_BREAK_JIFFIES (HZ/20)
788 * The sci generates interrupts during the break,
789 * 1 per millisecond or so during the break period, for 9600 baud.
790 * So dont bother disabling interrupts.
791 * But dont want more than 1 break event.
792 * Use a kernel timer to periodically poll the rx line until
793 * the break is finished.
795 static inline void sci_schedule_break_timer(struct sci_port
*port
)
797 mod_timer(&port
->break_timer
, jiffies
+ SCI_BREAK_JIFFIES
);
800 /* Ensure that two consecutive samples find the break over. */
801 static void sci_break_timer(unsigned long data
)
803 struct sci_port
*port
= (struct sci_port
*)data
;
805 if (sci_rxd_in(&port
->port
) == 0) {
806 port
->break_flag
= 1;
807 sci_schedule_break_timer(port
);
808 } else if (port
->break_flag
== 1) {
810 port
->break_flag
= 2;
811 sci_schedule_break_timer(port
);
813 port
->break_flag
= 0;
816 static int sci_handle_errors(struct uart_port
*port
)
819 unsigned short status
= serial_port_in(port
, SCxSR
);
820 struct tty_port
*tport
= &port
->state
->port
;
821 struct sci_port
*s
= to_sci_port(port
);
823 /* Handle overruns */
824 if (status
& s
->overrun_mask
) {
825 port
->icount
.overrun
++;
828 if (tty_insert_flip_char(tport
, 0, TTY_OVERRUN
))
831 dev_notice(port
->dev
, "overrun error\n");
834 if (status
& SCxSR_FER(port
)) {
835 if (sci_rxd_in(port
) == 0) {
836 /* Notify of BREAK */
837 struct sci_port
*sci_port
= to_sci_port(port
);
839 if (!sci_port
->break_flag
) {
842 sci_port
->break_flag
= 1;
843 sci_schedule_break_timer(sci_port
);
845 /* Do sysrq handling. */
846 if (uart_handle_break(port
))
849 dev_dbg(port
->dev
, "BREAK detected\n");
851 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
857 port
->icount
.frame
++;
859 if (tty_insert_flip_char(tport
, 0, TTY_FRAME
))
862 dev_notice(port
->dev
, "frame error\n");
866 if (status
& SCxSR_PER(port
)) {
868 port
->icount
.parity
++;
870 if (tty_insert_flip_char(tport
, 0, TTY_PARITY
))
873 dev_notice(port
->dev
, "parity error\n");
877 tty_flip_buffer_push(tport
);
882 static int sci_handle_fifo_overrun(struct uart_port
*port
)
884 struct tty_port
*tport
= &port
->state
->port
;
885 struct sci_port
*s
= to_sci_port(port
);
886 const struct plat_sci_reg
*reg
;
890 reg
= sci_getreg(port
, s
->overrun_reg
);
894 status
= serial_port_in(port
, s
->overrun_reg
);
895 if (status
& s
->overrun_mask
) {
896 status
&= ~s
->overrun_mask
;
897 serial_port_out(port
, s
->overrun_reg
, status
);
899 port
->icount
.overrun
++;
901 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
902 tty_flip_buffer_push(tport
);
904 dev_dbg(port
->dev
, "overrun error\n");
911 static int sci_handle_breaks(struct uart_port
*port
)
914 unsigned short status
= serial_port_in(port
, SCxSR
);
915 struct tty_port
*tport
= &port
->state
->port
;
916 struct sci_port
*s
= to_sci_port(port
);
918 if (uart_handle_break(port
))
921 if (!s
->break_flag
&& status
& SCxSR_BRK(port
)) {
922 #if defined(CONFIG_CPU_SH3)
929 /* Notify of BREAK */
930 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
933 dev_dbg(port
->dev
, "BREAK detected\n");
937 tty_flip_buffer_push(tport
);
939 copied
+= sci_handle_fifo_overrun(port
);
944 static irqreturn_t
sci_rx_interrupt(int irq
, void *ptr
)
946 #ifdef CONFIG_SERIAL_SH_SCI_DMA
947 struct uart_port
*port
= ptr
;
948 struct sci_port
*s
= to_sci_port(port
);
951 u16 scr
= serial_port_in(port
, SCSCR
);
952 u16 ssr
= serial_port_in(port
, SCxSR
);
954 /* Disable future Rx interrupts */
955 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
956 disable_irq_nosync(irq
);
961 serial_port_out(port
, SCSCR
, scr
);
962 /* Clear current interrupt */
963 serial_port_out(port
, SCxSR
,
964 ssr
& ~(SCIF_DR
| SCxSR_RDxF(port
)));
965 dev_dbg(port
->dev
, "Rx IRQ %lu: setup t-out in %u jiffies\n",
966 jiffies
, s
->rx_timeout
);
967 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
973 /* I think sci_receive_chars has to be called irrespective
974 * of whether the I_IXOFF is set, otherwise, how is the interrupt
977 sci_receive_chars(ptr
);
982 static irqreturn_t
sci_tx_interrupt(int irq
, void *ptr
)
984 struct uart_port
*port
= ptr
;
987 spin_lock_irqsave(&port
->lock
, flags
);
988 sci_transmit_chars(port
);
989 spin_unlock_irqrestore(&port
->lock
, flags
);
994 static irqreturn_t
sci_er_interrupt(int irq
, void *ptr
)
996 struct uart_port
*port
= ptr
;
999 if (port
->type
== PORT_SCI
) {
1000 if (sci_handle_errors(port
)) {
1001 /* discard character in rx buffer */
1002 serial_port_in(port
, SCxSR
);
1003 sci_clear_SCxSR(port
, SCxSR_RDxF_CLEAR(port
));
1006 sci_handle_fifo_overrun(port
);
1007 sci_rx_interrupt(irq
, ptr
);
1010 sci_clear_SCxSR(port
, SCxSR_ERROR_CLEAR(port
));
1012 /* Kick the transmission */
1013 sci_tx_interrupt(irq
, ptr
);
1018 static irqreturn_t
sci_br_interrupt(int irq
, void *ptr
)
1020 struct uart_port
*port
= ptr
;
1023 sci_handle_breaks(port
);
1024 sci_clear_SCxSR(port
, SCxSR_BREAK_CLEAR(port
));
1029 static inline unsigned long port_rx_irq_mask(struct uart_port
*port
)
1032 * Not all ports (such as SCIFA) will support REIE. Rather than
1033 * special-casing the port type, we check the port initialization
1034 * IRQ enable mask to see whether the IRQ is desired at all. If
1035 * it's unset, it's logically inferred that there's no point in
1038 return SCSCR_RIE
| (to_sci_port(port
)->cfg
->scscr
& SCSCR_REIE
);
1041 static irqreturn_t
sci_mpxed_interrupt(int irq
, void *ptr
)
1043 unsigned short ssr_status
, scr_status
, err_enabled
, orer_status
= 0;
1044 struct uart_port
*port
= ptr
;
1045 struct sci_port
*s
= to_sci_port(port
);
1046 irqreturn_t ret
= IRQ_NONE
;
1048 ssr_status
= serial_port_in(port
, SCxSR
);
1049 scr_status
= serial_port_in(port
, SCSCR
);
1050 if (s
->overrun_reg
== SCxSR
)
1051 orer_status
= ssr_status
;
1053 if (sci_getreg(port
, s
->overrun_reg
)->size
)
1054 orer_status
= serial_port_in(port
, s
->overrun_reg
);
1057 err_enabled
= scr_status
& port_rx_irq_mask(port
);
1060 if ((ssr_status
& SCxSR_TDxE(port
)) && (scr_status
& SCSCR_TIE
) &&
1062 ret
= sci_tx_interrupt(irq
, ptr
);
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1068 if (((ssr_status
& SCxSR_RDxF(port
)) || s
->chan_rx
) &&
1069 (scr_status
& SCSCR_RIE
))
1070 ret
= sci_rx_interrupt(irq
, ptr
);
1072 /* Error Interrupt */
1073 if ((ssr_status
& SCxSR_ERRORS(port
)) && err_enabled
)
1074 ret
= sci_er_interrupt(irq
, ptr
);
1076 /* Break Interrupt */
1077 if ((ssr_status
& SCxSR_BRK(port
)) && err_enabled
)
1078 ret
= sci_br_interrupt(irq
, ptr
);
1080 /* Overrun Interrupt */
1081 if (orer_status
& s
->overrun_mask
) {
1082 sci_handle_fifo_overrun(port
);
1090 * Here we define a transition notifier so that we can update all of our
1091 * ports' baud rate when the peripheral clock changes.
1093 static int sci_notifier(struct notifier_block
*self
,
1094 unsigned long phase
, void *p
)
1096 struct sci_port
*sci_port
;
1097 unsigned long flags
;
1099 sci_port
= container_of(self
, struct sci_port
, freq_transition
);
1101 if (phase
== CPUFREQ_POSTCHANGE
) {
1102 struct uart_port
*port
= &sci_port
->port
;
1104 spin_lock_irqsave(&port
->lock
, flags
);
1105 port
->uartclk
= clk_get_rate(sci_port
->iclk
);
1106 spin_unlock_irqrestore(&port
->lock
, flags
);
1112 static const struct sci_irq_desc
{
1114 irq_handler_t handler
;
1115 } sci_irq_desc
[] = {
1117 * Split out handlers, the default case.
1121 .handler
= sci_er_interrupt
,
1126 .handler
= sci_rx_interrupt
,
1131 .handler
= sci_tx_interrupt
,
1136 .handler
= sci_br_interrupt
,
1140 * Special muxed handler.
1144 .handler
= sci_mpxed_interrupt
,
1148 static int sci_request_irq(struct sci_port
*port
)
1150 struct uart_port
*up
= &port
->port
;
1153 for (i
= j
= 0; i
< SCIx_NR_IRQS
; i
++, j
++) {
1154 const struct sci_irq_desc
*desc
;
1157 if (SCIx_IRQ_IS_MUXED(port
)) {
1161 irq
= port
->irqs
[i
];
1164 * Certain port types won't support all of the
1165 * available interrupt sources.
1167 if (unlikely(irq
< 0))
1171 desc
= sci_irq_desc
+ i
;
1172 port
->irqstr
[j
] = kasprintf(GFP_KERNEL
, "%s:%s",
1173 dev_name(up
->dev
), desc
->desc
);
1174 if (!port
->irqstr
[j
])
1177 ret
= request_irq(irq
, desc
->handler
, up
->irqflags
,
1178 port
->irqstr
[j
], port
);
1179 if (unlikely(ret
)) {
1180 dev_err(up
->dev
, "Can't allocate %s IRQ\n", desc
->desc
);
1189 free_irq(port
->irqs
[i
], port
);
1193 kfree(port
->irqstr
[j
]);
1198 static void sci_free_irq(struct sci_port
*port
)
1203 * Intentionally in reverse order so we iterate over the muxed
1206 for (i
= 0; i
< SCIx_NR_IRQS
; i
++) {
1207 int irq
= port
->irqs
[i
];
1210 * Certain port types won't support all of the available
1211 * interrupt sources.
1213 if (unlikely(irq
< 0))
1216 free_irq(port
->irqs
[i
], port
);
1217 kfree(port
->irqstr
[i
]);
1219 if (SCIx_IRQ_IS_MUXED(port
)) {
1220 /* If there's only one IRQ, we're done. */
1226 static unsigned int sci_tx_empty(struct uart_port
*port
)
1228 unsigned short status
= serial_port_in(port
, SCxSR
);
1229 unsigned short in_tx_fifo
= sci_txfill(port
);
1231 return (status
& SCxSR_TEND(port
)) && !in_tx_fifo
? TIOCSER_TEMT
: 0;
1235 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1236 * CTS/RTS is supported in hardware by at least one port and controlled
1237 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1238 * handled via the ->init_pins() op, which is a bit of a one-way street,
1239 * lacking any ability to defer pin control -- this will later be
1240 * converted over to the GPIO framework).
1242 * Other modes (such as loopback) are supported generically on certain
1243 * port types, but not others. For these it's sufficient to test for the
1244 * existence of the support register and simply ignore the port type.
1246 static void sci_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1248 if (mctrl
& TIOCM_LOOP
) {
1249 const struct plat_sci_reg
*reg
;
1252 * Standard loopback mode for SCFCR ports.
1254 reg
= sci_getreg(port
, SCFCR
);
1256 serial_port_out(port
, SCFCR
,
1257 serial_port_in(port
, SCFCR
) |
1262 static unsigned int sci_get_mctrl(struct uart_port
*port
)
1265 * CTS/RTS is handled in hardware when supported, while nothing
1266 * else is wired up. Keep it simple and simply assert DSR/CAR.
1268 return TIOCM_DSR
| TIOCM_CAR
;
1271 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1272 static void sci_dma_tx_complete(void *arg
)
1274 struct sci_port
*s
= arg
;
1275 struct uart_port
*port
= &s
->port
;
1276 struct circ_buf
*xmit
= &port
->state
->xmit
;
1277 unsigned long flags
;
1279 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1281 spin_lock_irqsave(&port
->lock
, flags
);
1283 xmit
->tail
+= sg_dma_len(&s
->sg_tx
);
1284 xmit
->tail
&= UART_XMIT_SIZE
- 1;
1286 port
->icount
.tx
+= sg_dma_len(&s
->sg_tx
);
1288 async_tx_ack(s
->desc_tx
);
1291 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1292 uart_write_wakeup(port
);
1294 if (!uart_circ_empty(xmit
)) {
1296 schedule_work(&s
->work_tx
);
1298 s
->cookie_tx
= -EINVAL
;
1299 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1300 u16 ctrl
= serial_port_in(port
, SCSCR
);
1301 serial_port_out(port
, SCSCR
, ctrl
& ~SCSCR_TIE
);
1305 spin_unlock_irqrestore(&port
->lock
, flags
);
1308 /* Locking: called with port lock held */
1309 static int sci_dma_rx_push(struct sci_port
*s
, size_t count
)
1311 struct uart_port
*port
= &s
->port
;
1312 struct tty_port
*tport
= &port
->state
->port
;
1313 int i
, active
, room
;
1315 room
= tty_buffer_request_room(tport
, count
);
1317 if (s
->active_rx
== s
->cookie_rx
[0]) {
1319 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1322 dev_err(port
->dev
, "%s: Rx cookie %d not found!\n", __func__
,
1328 dev_warn(port
->dev
, "Rx overrun: dropping %zu bytes\n",
1333 for (i
= 0; i
< room
; i
++)
1334 tty_insert_flip_char(tport
, ((u8
*)sg_virt(&s
->sg_rx
[active
]))[i
],
1337 port
->icount
.rx
+= room
;
1342 static void sci_dma_rx_complete(void *arg
)
1344 struct sci_port
*s
= arg
;
1345 struct uart_port
*port
= &s
->port
;
1346 unsigned long flags
;
1349 dev_dbg(port
->dev
, "%s(%d) active cookie %d\n", __func__
, port
->line
,
1352 spin_lock_irqsave(&port
->lock
, flags
);
1354 count
= sci_dma_rx_push(s
, s
->buf_len_rx
);
1356 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
1358 spin_unlock_irqrestore(&port
->lock
, flags
);
1361 tty_flip_buffer_push(&port
->state
->port
);
1363 schedule_work(&s
->work_rx
);
1366 static void sci_rx_dma_release(struct sci_port
*s
, bool enable_pio
)
1368 struct dma_chan
*chan
= s
->chan_rx
;
1369 struct uart_port
*port
= &s
->port
;
1372 s
->cookie_rx
[0] = s
->cookie_rx
[1] = -EINVAL
;
1373 dma_free_coherent(chan
->device
->dev
, s
->buf_len_rx
* 2,
1374 sg_virt(&s
->sg_rx
[0]), sg_dma_address(&s
->sg_rx
[0]));
1375 dma_release_channel(chan
);
1380 static void sci_tx_dma_release(struct sci_port
*s
, bool enable_pio
)
1382 struct dma_chan
*chan
= s
->chan_tx
;
1383 struct uart_port
*port
= &s
->port
;
1386 s
->cookie_tx
= -EINVAL
;
1387 dma_release_channel(chan
);
1392 static void sci_submit_rx(struct sci_port
*s
)
1394 struct dma_chan
*chan
= s
->chan_rx
;
1397 for (i
= 0; i
< 2; i
++) {
1398 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1399 struct dma_async_tx_descriptor
*desc
;
1401 desc
= dmaengine_prep_slave_sg(chan
,
1402 sg
, 1, DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1405 s
->desc_rx
[i
] = desc
;
1406 desc
->callback
= sci_dma_rx_complete
;
1407 desc
->callback_param
= s
;
1408 s
->cookie_rx
[i
] = desc
->tx_submit(desc
);
1411 if (!desc
|| s
->cookie_rx
[i
] < 0) {
1413 async_tx_ack(s
->desc_rx
[0]);
1414 s
->cookie_rx
[0] = -EINVAL
;
1418 s
->cookie_rx
[i
] = -EINVAL
;
1420 dev_warn(s
->port
.dev
,
1421 "Failed to re-start Rx DMA, using PIO\n");
1422 sci_rx_dma_release(s
, true);
1425 dev_dbg(s
->port
.dev
, "%s(): cookie %d to #%d\n", __func__
,
1426 s
->cookie_rx
[i
], i
);
1429 s
->active_rx
= s
->cookie_rx
[0];
1431 dma_async_issue_pending(chan
);
1434 static void work_fn_rx(struct work_struct
*work
)
1436 struct sci_port
*s
= container_of(work
, struct sci_port
, work_rx
);
1437 struct uart_port
*port
= &s
->port
;
1438 struct dma_async_tx_descriptor
*desc
;
1441 if (s
->active_rx
== s
->cookie_rx
[0]) {
1443 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1446 dev_err(port
->dev
, "%s: Rx cookie %d not found!\n", __func__
,
1450 desc
= s
->desc_rx
[new];
1452 if (dma_async_is_tx_complete(s
->chan_rx
, s
->active_rx
, NULL
, NULL
) !=
1454 /* Handle incomplete DMA receive */
1455 struct dma_chan
*chan
= s
->chan_rx
;
1456 struct shdma_desc
*sh_desc
= container_of(desc
,
1457 struct shdma_desc
, async_tx
);
1458 unsigned long flags
;
1461 dmaengine_terminate_all(chan
);
1462 dev_dbg(port
->dev
, "Read %zu bytes with cookie %d\n",
1463 sh_desc
->partial
, sh_desc
->cookie
);
1465 spin_lock_irqsave(&port
->lock
, flags
);
1466 count
= sci_dma_rx_push(s
, sh_desc
->partial
);
1467 spin_unlock_irqrestore(&port
->lock
, flags
);
1470 tty_flip_buffer_push(&port
->state
->port
);
1477 s
->cookie_rx
[new] = desc
->tx_submit(desc
);
1478 if (s
->cookie_rx
[new] < 0) {
1479 dev_warn(port
->dev
, "Failed submitting Rx DMA descriptor\n");
1480 sci_rx_dma_release(s
, true);
1484 s
->active_rx
= s
->cookie_rx
[!new];
1486 dev_dbg(port
->dev
, "%s: cookie %d #%d, new active cookie %d\n",
1487 __func__
, s
->cookie_rx
[new], new, s
->active_rx
);
1490 static void work_fn_tx(struct work_struct
*work
)
1492 struct sci_port
*s
= container_of(work
, struct sci_port
, work_tx
);
1493 struct dma_async_tx_descriptor
*desc
;
1494 struct dma_chan
*chan
= s
->chan_tx
;
1495 struct uart_port
*port
= &s
->port
;
1496 struct circ_buf
*xmit
= &port
->state
->xmit
;
1497 struct scatterlist
*sg
= &s
->sg_tx
;
1501 * Port xmit buffer is already mapped, and it is one page... Just adjust
1502 * offsets and lengths. Since it is a circular buffer, we have to
1503 * transmit till the end, and then the rest. Take the port lock to get a
1504 * consistent xmit buffer state.
1506 spin_lock_irq(&port
->lock
);
1507 sg
->offset
= xmit
->tail
& (UART_XMIT_SIZE
- 1);
1508 sg_dma_address(sg
) = (sg_dma_address(sg
) & ~(UART_XMIT_SIZE
- 1)) +
1510 sg_dma_len(sg
) = min((int)CIRC_CNT(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
),
1511 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
));
1512 spin_unlock_irq(&port
->lock
);
1514 BUG_ON(!sg_dma_len(sg
));
1516 desc
= dmaengine_prep_slave_sg(chan
,
1517 sg
, s
->sg_len_tx
, DMA_MEM_TO_DEV
,
1518 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1520 dev_warn(port
->dev
, "Failed preparing Tx DMA descriptor\n");
1522 sci_tx_dma_release(s
, true);
1526 dma_sync_sg_for_device(chan
->device
->dev
, sg
, 1, DMA_TO_DEVICE
);
1528 spin_lock_irq(&port
->lock
);
1530 desc
->callback
= sci_dma_tx_complete
;
1531 desc
->callback_param
= s
;
1532 spin_unlock_irq(&port
->lock
);
1533 s
->cookie_tx
= desc
->tx_submit(desc
);
1534 if (s
->cookie_tx
< 0) {
1535 dev_warn(port
->dev
, "Failed submitting Tx DMA descriptor\n");
1537 sci_tx_dma_release(s
, true);
1541 dev_dbg(port
->dev
, "%s: %p: %d...%d, cookie %d\n",
1542 __func__
, xmit
->buf
, xmit
->tail
, xmit
->head
, s
->cookie_tx
);
1544 dma_async_issue_pending(chan
);
1548 static void sci_start_tx(struct uart_port
*port
)
1550 struct sci_port
*s
= to_sci_port(port
);
1551 unsigned short ctrl
;
1553 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1554 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1555 u16
new, scr
= serial_port_in(port
, SCSCR
);
1557 new = scr
| SCSCR_TDRQE
;
1559 new = scr
& ~SCSCR_TDRQE
;
1561 serial_port_out(port
, SCSCR
, new);
1564 if (s
->chan_tx
&& !uart_circ_empty(&s
->port
.state
->xmit
) &&
1567 schedule_work(&s
->work_tx
);
1571 if (!s
->chan_tx
|| port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1572 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1573 ctrl
= serial_port_in(port
, SCSCR
);
1574 serial_port_out(port
, SCSCR
, ctrl
| SCSCR_TIE
);
1578 static void sci_stop_tx(struct uart_port
*port
)
1580 unsigned short ctrl
;
1582 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1583 ctrl
= serial_port_in(port
, SCSCR
);
1585 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1586 ctrl
&= ~SCSCR_TDRQE
;
1590 serial_port_out(port
, SCSCR
, ctrl
);
1593 static void sci_start_rx(struct uart_port
*port
)
1595 unsigned short ctrl
;
1597 ctrl
= serial_port_in(port
, SCSCR
) | port_rx_irq_mask(port
);
1599 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1600 ctrl
&= ~SCSCR_RDRQE
;
1602 serial_port_out(port
, SCSCR
, ctrl
);
1605 static void sci_stop_rx(struct uart_port
*port
)
1607 unsigned short ctrl
;
1609 ctrl
= serial_port_in(port
, SCSCR
);
1611 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1612 ctrl
&= ~SCSCR_RDRQE
;
1614 ctrl
&= ~port_rx_irq_mask(port
);
1616 serial_port_out(port
, SCSCR
, ctrl
);
1619 static void sci_break_ctl(struct uart_port
*port
, int break_state
)
1621 struct sci_port
*s
= to_sci_port(port
);
1622 const struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
1623 unsigned short scscr
, scsptr
;
1625 /* check wheter the port has SCSPTR */
1628 * Not supported by hardware. Most parts couple break and rx
1629 * interrupts together, with break detection always enabled.
1634 scsptr
= serial_port_in(port
, SCSPTR
);
1635 scscr
= serial_port_in(port
, SCSCR
);
1637 if (break_state
== -1) {
1638 scsptr
= (scsptr
| SCSPTR_SPB2IO
) & ~SCSPTR_SPB2DT
;
1641 scsptr
= (scsptr
| SCSPTR_SPB2DT
) & ~SCSPTR_SPB2IO
;
1645 serial_port_out(port
, SCSPTR
, scsptr
);
1646 serial_port_out(port
, SCSCR
, scscr
);
1649 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1650 static bool filter(struct dma_chan
*chan
, void *slave
)
1652 struct sh_dmae_slave
*param
= slave
;
1654 dev_dbg(chan
->device
->dev
, "%s: slave ID %d\n",
1655 __func__
, param
->shdma_slave
.slave_id
);
1657 chan
->private = ¶m
->shdma_slave
;
1661 static void rx_timer_fn(unsigned long arg
)
1663 struct sci_port
*s
= (struct sci_port
*)arg
;
1664 struct uart_port
*port
= &s
->port
;
1665 u16 scr
= serial_port_in(port
, SCSCR
);
1667 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1668 scr
&= ~SCSCR_RDRQE
;
1669 enable_irq(s
->irqs
[SCIx_RXI_IRQ
]);
1671 serial_port_out(port
, SCSCR
, scr
| SCSCR_RIE
);
1672 dev_dbg(port
->dev
, "DMA Rx timed out\n");
1673 schedule_work(&s
->work_rx
);
1676 static void sci_request_dma(struct uart_port
*port
)
1678 struct sci_port
*s
= to_sci_port(port
);
1679 struct sh_dmae_slave
*param
;
1680 struct dma_chan
*chan
;
1681 dma_cap_mask_t mask
;
1684 dev_dbg(port
->dev
, "%s: port %d\n", __func__
, port
->line
);
1686 if (s
->cfg
->dma_slave_tx
<= 0 || s
->cfg
->dma_slave_rx
<= 0)
1690 dma_cap_set(DMA_SLAVE
, mask
);
1692 param
= &s
->param_tx
;
1694 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1695 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_tx
;
1697 s
->cookie_tx
= -EINVAL
;
1698 chan
= dma_request_channel(mask
, filter
, param
);
1699 dev_dbg(port
->dev
, "%s: TX: got channel %p\n", __func__
, chan
);
1702 sg_init_table(&s
->sg_tx
, 1);
1703 /* UART circular tx buffer is an aligned page. */
1704 BUG_ON((uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1705 sg_set_page(&s
->sg_tx
, virt_to_page(port
->state
->xmit
.buf
),
1707 (uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1708 nent
= dma_map_sg(chan
->device
->dev
, &s
->sg_tx
, 1,
1711 dev_warn(port
->dev
, "Failed mapping Tx DMA descriptor\n");
1712 dma_release_channel(chan
);
1715 dev_dbg(port
->dev
, "%s: mapped %d@%p to %pad\n",
1717 sg_dma_len(&s
->sg_tx
), port
->state
->xmit
.buf
,
1718 &sg_dma_address(&s
->sg_tx
));
1721 s
->sg_len_tx
= nent
;
1723 INIT_WORK(&s
->work_tx
, work_fn_tx
);
1726 param
= &s
->param_rx
;
1728 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1729 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_rx
;
1731 chan
= dma_request_channel(mask
, filter
, param
);
1732 dev_dbg(port
->dev
, "%s: RX: got channel %p\n", __func__
, chan
);
1740 s
->buf_len_rx
= 2 * max(16, (int)port
->fifosize
);
1741 buf
[0] = dma_alloc_coherent(chan
->device
->dev
,
1742 s
->buf_len_rx
* 2, &dma
[0],
1747 "Failed to allocate Rx dma buffer, using PIO\n");
1748 dma_release_channel(chan
);
1754 buf
[1] = buf
[0] + s
->buf_len_rx
;
1755 dma
[1] = dma
[0] + s
->buf_len_rx
;
1757 for (i
= 0; i
< 2; i
++) {
1758 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1760 sg_init_table(sg
, 1);
1761 sg_set_page(sg
, virt_to_page(buf
[i
]), s
->buf_len_rx
,
1762 (uintptr_t)buf
[i
] & ~PAGE_MASK
);
1763 sg_dma_address(sg
) = dma
[i
];
1766 INIT_WORK(&s
->work_rx
, work_fn_rx
);
1767 setup_timer(&s
->rx_timer
, rx_timer_fn
, (unsigned long)s
);
1773 static void sci_free_dma(struct uart_port
*port
)
1775 struct sci_port
*s
= to_sci_port(port
);
1778 sci_tx_dma_release(s
, false);
1780 sci_rx_dma_release(s
, false);
1783 static inline void sci_request_dma(struct uart_port
*port
)
1787 static inline void sci_free_dma(struct uart_port
*port
)
1792 static int sci_startup(struct uart_port
*port
)
1794 struct sci_port
*s
= to_sci_port(port
);
1795 unsigned long flags
;
1798 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1800 ret
= sci_request_irq(s
);
1801 if (unlikely(ret
< 0))
1804 sci_request_dma(port
);
1806 spin_lock_irqsave(&port
->lock
, flags
);
1809 spin_unlock_irqrestore(&port
->lock
, flags
);
1814 static void sci_shutdown(struct uart_port
*port
)
1816 struct sci_port
*s
= to_sci_port(port
);
1817 unsigned long flags
;
1819 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1821 spin_lock_irqsave(&port
->lock
, flags
);
1824 spin_unlock_irqrestore(&port
->lock
, flags
);
1830 static unsigned int sci_scbrr_calc(struct sci_port
*s
, unsigned int bps
,
1833 if (s
->sampling_rate
)
1834 return DIV_ROUND_CLOSEST(freq
, s
->sampling_rate
* bps
) - 1;
1836 /* Warn, but use a safe default */
1839 return ((freq
+ 16 * bps
) / (32 * bps
) - 1);
1842 /* calculate frame length from SMR */
1843 static int sci_baud_calc_frame_len(unsigned int smr_val
)
1847 if (smr_val
& SCSMR_CHR
)
1849 if (smr_val
& SCSMR_PE
)
1851 if (smr_val
& SCSMR_STOP
)
1858 /* calculate sample rate, BRR, and clock select for HSCIF */
1859 static void sci_baud_calc_hscif(unsigned int bps
, unsigned long freq
,
1860 int *brr
, unsigned int *srr
,
1861 unsigned int *cks
, int frame_len
)
1863 int sr
, c
, br
, err
, recv_margin
;
1864 int min_err
= 1000; /* 100% */
1865 int recv_max_margin
= 0;
1867 /* Find the combination of sample rate and clock select with the
1868 smallest deviation from the desired baud rate. */
1869 for (sr
= 8; sr
<= 32; sr
++) {
1870 for (c
= 0; c
<= 3; c
++) {
1871 /* integerized formulas from HSCIF documentation */
1872 br
= DIV_ROUND_CLOSEST(freq
, (sr
*
1873 (1 << (2 * c
+ 1)) * bps
)) - 1;
1874 br
= clamp(br
, 0, 255);
1875 err
= DIV_ROUND_CLOSEST(freq
, ((br
+ 1) * bps
* sr
*
1876 (1 << (2 * c
+ 1)) / 1000)) -
1879 * M: Receive margin (%)
1880 * N: Ratio of bit rate to clock (N = sampling rate)
1881 * D: Clock duty (D = 0 to 1.0)
1882 * L: Frame length (L = 9 to 12)
1883 * F: Absolute value of clock frequency deviation
1885 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1886 * (|D - 0.5| / N * (1 + F))|
1887 * NOTE: Usually, treat D for 0.5, F is 0 by this
1890 recv_margin
= abs((500 -
1891 DIV_ROUND_CLOSEST(1000, sr
<< 1)) / 10);
1892 if (abs(min_err
) > abs(err
)) {
1894 recv_max_margin
= recv_margin
;
1895 } else if ((min_err
== err
) &&
1896 (recv_margin
> recv_max_margin
))
1897 recv_max_margin
= recv_margin
;
1907 if (min_err
== 1000) {
1916 static void sci_reset(struct uart_port
*port
)
1918 const struct plat_sci_reg
*reg
;
1919 unsigned int status
;
1922 status
= serial_port_in(port
, SCxSR
);
1923 } while (!(status
& SCxSR_TEND(port
)));
1925 serial_port_out(port
, SCSCR
, 0x00); /* TE=0, RE=0, CKE1=0 */
1927 reg
= sci_getreg(port
, SCFCR
);
1929 serial_port_out(port
, SCFCR
, SCFCR_RFRST
| SCFCR_TFRST
);
1932 static void sci_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1933 struct ktermios
*old
)
1935 struct sci_port
*s
= to_sci_port(port
);
1936 const struct plat_sci_reg
*reg
;
1937 unsigned int baud
, smr_val
= 0, max_baud
, cks
= 0;
1939 unsigned int srr
= 15;
1941 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1942 smr_val
|= SCSMR_CHR
;
1943 if (termios
->c_cflag
& PARENB
)
1944 smr_val
|= SCSMR_PE
;
1945 if (termios
->c_cflag
& PARODD
)
1946 smr_val
|= SCSMR_PE
| SCSMR_ODD
;
1947 if (termios
->c_cflag
& CSTOPB
)
1948 smr_val
|= SCSMR_STOP
;
1951 * earlyprintk comes here early on with port->uartclk set to zero.
1952 * the clock framework is not up and running at this point so here
1953 * we assume that 115200 is the maximum baud rate. please note that
1954 * the baud rate is not programmed during earlyprintk - it is assumed
1955 * that the previous boot loader has enabled required clocks and
1956 * setup the baud rate generator hardware for us already.
1958 max_baud
= port
->uartclk
? port
->uartclk
/ 16 : 115200;
1960 baud
= uart_get_baud_rate(port
, termios
, old
, 0, max_baud
);
1961 if (likely(baud
&& port
->uartclk
)) {
1962 if (s
->cfg
->type
== PORT_HSCIF
) {
1963 int frame_len
= sci_baud_calc_frame_len(smr_val
);
1964 sci_baud_calc_hscif(baud
, port
->uartclk
, &t
, &srr
,
1967 t
= sci_scbrr_calc(s
, baud
, port
->uartclk
);
1968 for (cks
= 0; t
>= 256 && cks
<= 3; cks
++)
1977 smr_val
|= serial_port_in(port
, SCSMR
) & SCSMR_CKS
;
1979 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1981 dev_dbg(port
->dev
, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1982 __func__
, smr_val
, cks
, t
, s
->cfg
->scscr
);
1985 serial_port_out(port
, SCSMR
, (smr_val
& ~SCSMR_CKS
) | cks
);
1986 serial_port_out(port
, SCBRR
, t
);
1987 reg
= sci_getreg(port
, HSSRR
);
1989 serial_port_out(port
, HSSRR
, srr
| HSCIF_SRE
);
1990 udelay((1000000+(baud
-1)) / baud
); /* Wait one bit interval */
1992 serial_port_out(port
, SCSMR
, smr_val
);
1994 sci_init_pins(port
, termios
->c_cflag
);
1996 reg
= sci_getreg(port
, SCFCR
);
1998 unsigned short ctrl
= serial_port_in(port
, SCFCR
);
2000 if (s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) {
2001 if (termios
->c_cflag
& CRTSCTS
)
2008 * As we've done a sci_reset() above, ensure we don't
2009 * interfere with the FIFOs while toggling MCE. As the
2010 * reset values could still be set, simply mask them out.
2012 ctrl
&= ~(SCFCR_RFRST
| SCFCR_TFRST
);
2014 serial_port_out(port
, SCFCR
, ctrl
);
2017 serial_port_out(port
, SCSCR
, s
->cfg
->scscr
);
2019 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2021 * Calculate delay for 2 DMA buffers (4 FIFO).
2022 * See serial_core.c::uart_update_timeout().
2023 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2024 * function calculates 1 jiffie for the data plus 5 jiffies for the
2025 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2026 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2027 * value obtained by this formula is too small. Therefore, if the value
2028 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2033 /* byte size and parity */
2034 switch (termios
->c_cflag
& CSIZE
) {
2049 if (termios
->c_cflag
& CSTOPB
)
2051 if (termios
->c_cflag
& PARENB
)
2053 s
->rx_timeout
= DIV_ROUND_UP((s
->buf_len_rx
* 2 * bits
* HZ
) /
2055 dev_dbg(port
->dev
, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2056 s
->rx_timeout
* 1000 / HZ
, port
->timeout
);
2057 if (s
->rx_timeout
< msecs_to_jiffies(20))
2058 s
->rx_timeout
= msecs_to_jiffies(20);
2062 if ((termios
->c_cflag
& CREAD
) != 0)
2065 sci_port_disable(s
);
2068 static void sci_pm(struct uart_port
*port
, unsigned int state
,
2069 unsigned int oldstate
)
2071 struct sci_port
*sci_port
= to_sci_port(port
);
2074 case UART_PM_STATE_OFF
:
2075 sci_port_disable(sci_port
);
2078 sci_port_enable(sci_port
);
2083 static const char *sci_type(struct uart_port
*port
)
2085 switch (port
->type
) {
2103 static int sci_remap_port(struct uart_port
*port
)
2105 struct sci_port
*sport
= to_sci_port(port
);
2108 * Nothing to do if there's already an established membase.
2113 if (port
->flags
& UPF_IOREMAP
) {
2114 port
->membase
= ioremap_nocache(port
->mapbase
, sport
->reg_size
);
2115 if (unlikely(!port
->membase
)) {
2116 dev_err(port
->dev
, "can't remap port#%d\n", port
->line
);
2121 * For the simple (and majority of) cases where we don't
2122 * need to do any remapping, just cast the cookie
2125 port
->membase
= (void __iomem
*)(uintptr_t)port
->mapbase
;
2131 static void sci_release_port(struct uart_port
*port
)
2133 struct sci_port
*sport
= to_sci_port(port
);
2135 if (port
->flags
& UPF_IOREMAP
) {
2136 iounmap(port
->membase
);
2137 port
->membase
= NULL
;
2140 release_mem_region(port
->mapbase
, sport
->reg_size
);
2143 static int sci_request_port(struct uart_port
*port
)
2145 struct resource
*res
;
2146 struct sci_port
*sport
= to_sci_port(port
);
2149 res
= request_mem_region(port
->mapbase
, sport
->reg_size
,
2150 dev_name(port
->dev
));
2151 if (unlikely(res
== NULL
)) {
2152 dev_err(port
->dev
, "request_mem_region failed.");
2156 ret
= sci_remap_port(port
);
2157 if (unlikely(ret
!= 0)) {
2158 release_resource(res
);
2165 static void sci_config_port(struct uart_port
*port
, int flags
)
2167 if (flags
& UART_CONFIG_TYPE
) {
2168 struct sci_port
*sport
= to_sci_port(port
);
2170 port
->type
= sport
->cfg
->type
;
2171 sci_request_port(port
);
2175 static int sci_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2177 if (ser
->baud_base
< 2400)
2178 /* No paper tape reader for Mitch.. */
2184 static struct uart_ops sci_uart_ops
= {
2185 .tx_empty
= sci_tx_empty
,
2186 .set_mctrl
= sci_set_mctrl
,
2187 .get_mctrl
= sci_get_mctrl
,
2188 .start_tx
= sci_start_tx
,
2189 .stop_tx
= sci_stop_tx
,
2190 .stop_rx
= sci_stop_rx
,
2191 .break_ctl
= sci_break_ctl
,
2192 .startup
= sci_startup
,
2193 .shutdown
= sci_shutdown
,
2194 .set_termios
= sci_set_termios
,
2197 .release_port
= sci_release_port
,
2198 .request_port
= sci_request_port
,
2199 .config_port
= sci_config_port
,
2200 .verify_port
= sci_verify_port
,
2201 #ifdef CONFIG_CONSOLE_POLL
2202 .poll_get_char
= sci_poll_get_char
,
2203 .poll_put_char
= sci_poll_put_char
,
2207 static int sci_init_single(struct platform_device
*dev
,
2208 struct sci_port
*sci_port
, unsigned int index
,
2209 struct plat_sci_port
*p
, bool early
)
2211 struct uart_port
*port
= &sci_port
->port
;
2212 const struct resource
*res
;
2218 port
->ops
= &sci_uart_ops
;
2219 port
->iotype
= UPIO_MEM
;
2222 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
2226 port
->mapbase
= res
->start
;
2227 sci_port
->reg_size
= resource_size(res
);
2229 for (i
= 0; i
< ARRAY_SIZE(sci_port
->irqs
); ++i
)
2230 sci_port
->irqs
[i
] = platform_get_irq(dev
, i
);
2232 /* The SCI generates several interrupts. They can be muxed together or
2233 * connected to different interrupt lines. In the muxed case only one
2234 * interrupt resource is specified. In the non-muxed case three or four
2235 * interrupt resources are specified, as the BRI interrupt is optional.
2237 if (sci_port
->irqs
[0] < 0)
2240 if (sci_port
->irqs
[1] < 0) {
2241 sci_port
->irqs
[1] = sci_port
->irqs
[0];
2242 sci_port
->irqs
[2] = sci_port
->irqs
[0];
2243 sci_port
->irqs
[3] = sci_port
->irqs
[0];
2246 if (p
->regtype
== SCIx_PROBE_REGTYPE
) {
2247 ret
= sci_probe_regmap(p
);
2254 port
->fifosize
= 256;
2255 sci_port
->overrun_reg
= SCxSR
;
2256 sci_port
->overrun_mask
= SCIFA_ORER
;
2257 sci_port
->sampling_rate
= 16;
2260 port
->fifosize
= 128;
2261 sci_port
->overrun_reg
= SCLSR
;
2262 sci_port
->overrun_mask
= SCLSR_ORER
;
2263 sci_port
->sampling_rate
= 0;
2266 port
->fifosize
= 64;
2267 sci_port
->overrun_reg
= SCxSR
;
2268 sci_port
->overrun_mask
= SCIFA_ORER
;
2269 sci_port
->sampling_rate
= 16;
2272 port
->fifosize
= 16;
2273 if (p
->regtype
== SCIx_SH7705_SCIF_REGTYPE
) {
2274 sci_port
->overrun_reg
= SCxSR
;
2275 sci_port
->overrun_mask
= SCIFA_ORER
;
2276 sci_port
->sampling_rate
= 16;
2278 sci_port
->overrun_reg
= SCLSR
;
2279 sci_port
->overrun_mask
= SCLSR_ORER
;
2280 sci_port
->sampling_rate
= 32;
2285 sci_port
->overrun_reg
= SCxSR
;
2286 sci_port
->overrun_mask
= SCI_ORER
;
2287 sci_port
->sampling_rate
= 32;
2291 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2292 * match the SoC datasheet, this should be investigated. Let platform
2293 * data override the sampling rate for now.
2295 if (p
->sampling_rate
)
2296 sci_port
->sampling_rate
= p
->sampling_rate
;
2299 sci_port
->iclk
= clk_get(&dev
->dev
, "sci_ick");
2300 if (IS_ERR(sci_port
->iclk
)) {
2301 sci_port
->iclk
= clk_get(&dev
->dev
, "peripheral_clk");
2302 if (IS_ERR(sci_port
->iclk
)) {
2303 dev_err(&dev
->dev
, "can't get iclk\n");
2304 return PTR_ERR(sci_port
->iclk
);
2309 * The function clock is optional, ignore it if we can't
2312 sci_port
->fclk
= clk_get(&dev
->dev
, "sci_fck");
2313 if (IS_ERR(sci_port
->fclk
))
2314 sci_port
->fclk
= NULL
;
2316 port
->dev
= &dev
->dev
;
2318 pm_runtime_enable(&dev
->dev
);
2321 sci_port
->break_timer
.data
= (unsigned long)sci_port
;
2322 sci_port
->break_timer
.function
= sci_break_timer
;
2323 init_timer(&sci_port
->break_timer
);
2326 * Establish some sensible defaults for the error detection.
2328 if (p
->type
== PORT_SCI
) {
2329 sci_port
->error_mask
= SCI_DEFAULT_ERROR_MASK
;
2330 sci_port
->error_clear
= SCI_ERROR_CLEAR
;
2332 sci_port
->error_mask
= SCIF_DEFAULT_ERROR_MASK
;
2333 sci_port
->error_clear
= SCIF_ERROR_CLEAR
;
2337 * Make the error mask inclusive of overrun detection, if
2340 if (sci_port
->overrun_reg
== SCxSR
) {
2341 sci_port
->error_mask
|= sci_port
->overrun_mask
;
2342 sci_port
->error_clear
&= ~sci_port
->overrun_mask
;
2345 port
->type
= p
->type
;
2346 port
->flags
= UPF_FIXED_PORT
| p
->flags
;
2347 port
->regshift
= p
->regshift
;
2350 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2351 * for the multi-IRQ ports, which is where we are primarily
2352 * concerned with the shutdown path synchronization.
2354 * For the muxed case there's nothing more to do.
2356 port
->irq
= sci_port
->irqs
[SCIx_RXI_IRQ
];
2359 port
->serial_in
= sci_serial_in
;
2360 port
->serial_out
= sci_serial_out
;
2362 if (p
->dma_slave_tx
> 0 && p
->dma_slave_rx
> 0)
2363 dev_dbg(port
->dev
, "DMA tx %d, rx %d\n",
2364 p
->dma_slave_tx
, p
->dma_slave_rx
);
2369 static void sci_cleanup_single(struct sci_port
*port
)
2371 clk_put(port
->iclk
);
2372 clk_put(port
->fclk
);
2374 pm_runtime_disable(port
->port
.dev
);
2377 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2378 static void serial_console_putchar(struct uart_port
*port
, int ch
)
2380 sci_poll_put_char(port
, ch
);
2384 * Print a string to the serial port trying not to disturb
2385 * any possible real use of the port...
2387 static void serial_console_write(struct console
*co
, const char *s
,
2390 struct sci_port
*sci_port
= &sci_ports
[co
->index
];
2391 struct uart_port
*port
= &sci_port
->port
;
2392 unsigned short bits
, ctrl
;
2393 unsigned long flags
;
2396 local_irq_save(flags
);
2399 else if (oops_in_progress
)
2400 locked
= spin_trylock(&port
->lock
);
2402 spin_lock(&port
->lock
);
2404 /* first save the SCSCR then disable the interrupts */
2405 ctrl
= serial_port_in(port
, SCSCR
);
2406 serial_port_out(port
, SCSCR
, sci_port
->cfg
->scscr
);
2408 uart_console_write(port
, s
, count
, serial_console_putchar
);
2410 /* wait until fifo is empty and last bit has been transmitted */
2411 bits
= SCxSR_TDxE(port
) | SCxSR_TEND(port
);
2412 while ((serial_port_in(port
, SCxSR
) & bits
) != bits
)
2415 /* restore the SCSCR */
2416 serial_port_out(port
, SCSCR
, ctrl
);
2419 spin_unlock(&port
->lock
);
2420 local_irq_restore(flags
);
2423 static int serial_console_setup(struct console
*co
, char *options
)
2425 struct sci_port
*sci_port
;
2426 struct uart_port
*port
;
2434 * Refuse to handle any bogus ports.
2436 if (co
->index
< 0 || co
->index
>= SCI_NPORTS
)
2439 sci_port
= &sci_ports
[co
->index
];
2440 port
= &sci_port
->port
;
2443 * Refuse to handle uninitialized ports.
2448 ret
= sci_remap_port(port
);
2449 if (unlikely(ret
!= 0))
2453 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2455 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2458 static struct console serial_console
= {
2460 .device
= uart_console_device
,
2461 .write
= serial_console_write
,
2462 .setup
= serial_console_setup
,
2463 .flags
= CON_PRINTBUFFER
,
2465 .data
= &sci_uart_driver
,
2468 static struct console early_serial_console
= {
2469 .name
= "early_ttySC",
2470 .write
= serial_console_write
,
2471 .flags
= CON_PRINTBUFFER
,
2475 static char early_serial_buf
[32];
2477 static int sci_probe_earlyprintk(struct platform_device
*pdev
)
2479 struct plat_sci_port
*cfg
= dev_get_platdata(&pdev
->dev
);
2481 if (early_serial_console
.data
)
2484 early_serial_console
.index
= pdev
->id
;
2486 sci_init_single(pdev
, &sci_ports
[pdev
->id
], pdev
->id
, cfg
, true);
2488 serial_console_setup(&early_serial_console
, early_serial_buf
);
2490 if (!strstr(early_serial_buf
, "keep"))
2491 early_serial_console
.flags
|= CON_BOOT
;
2493 register_console(&early_serial_console
);
2497 #define SCI_CONSOLE (&serial_console)
2500 static inline int sci_probe_earlyprintk(struct platform_device
*pdev
)
2505 #define SCI_CONSOLE NULL
2507 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2509 static const char banner
[] __initconst
= "SuperH (H)SCI(F) driver initialized";
2511 static struct uart_driver sci_uart_driver
= {
2512 .owner
= THIS_MODULE
,
2513 .driver_name
= "sci",
2514 .dev_name
= "ttySC",
2516 .minor
= SCI_MINOR_START
,
2518 .cons
= SCI_CONSOLE
,
2521 static int sci_remove(struct platform_device
*dev
)
2523 struct sci_port
*port
= platform_get_drvdata(dev
);
2525 cpufreq_unregister_notifier(&port
->freq_transition
,
2526 CPUFREQ_TRANSITION_NOTIFIER
);
2528 uart_remove_one_port(&sci_uart_driver
, &port
->port
);
2530 sci_cleanup_single(port
);
2535 struct sci_port_info
{
2537 unsigned int regtype
;
2540 static const struct of_device_id of_sci_match
[] = {
2542 .compatible
= "renesas,scif",
2543 .data
= &(const struct sci_port_info
) {
2545 .regtype
= SCIx_SH4_SCIF_REGTYPE
,
2548 .compatible
= "renesas,scifa",
2549 .data
= &(const struct sci_port_info
) {
2551 .regtype
= SCIx_SCIFA_REGTYPE
,
2554 .compatible
= "renesas,scifb",
2555 .data
= &(const struct sci_port_info
) {
2557 .regtype
= SCIx_SCIFB_REGTYPE
,
2560 .compatible
= "renesas,hscif",
2561 .data
= &(const struct sci_port_info
) {
2563 .regtype
= SCIx_HSCIF_REGTYPE
,
2566 .compatible
= "renesas,sci",
2567 .data
= &(const struct sci_port_info
) {
2569 .regtype
= SCIx_SCI_REGTYPE
,
2575 MODULE_DEVICE_TABLE(of
, of_sci_match
);
2577 static struct plat_sci_port
*
2578 sci_parse_dt(struct platform_device
*pdev
, unsigned int *dev_id
)
2580 struct device_node
*np
= pdev
->dev
.of_node
;
2581 const struct of_device_id
*match
;
2582 const struct sci_port_info
*info
;
2583 struct plat_sci_port
*p
;
2586 if (!IS_ENABLED(CONFIG_OF
) || !np
)
2589 match
= of_match_node(of_sci_match
, pdev
->dev
.of_node
);
2595 p
= devm_kzalloc(&pdev
->dev
, sizeof(struct plat_sci_port
), GFP_KERNEL
);
2599 /* Get the line number for the aliases node. */
2600 id
= of_alias_get_id(np
, "serial");
2602 dev_err(&pdev
->dev
, "failed to get alias id (%d)\n", id
);
2608 p
->flags
= UPF_IOREMAP
| UPF_BOOT_AUTOCONF
;
2609 p
->type
= info
->type
;
2610 p
->regtype
= info
->regtype
;
2611 p
->scscr
= SCSCR_RE
| SCSCR_TE
;
2616 static int sci_probe_single(struct platform_device
*dev
,
2618 struct plat_sci_port
*p
,
2619 struct sci_port
*sciport
)
2624 if (unlikely(index
>= SCI_NPORTS
)) {
2625 dev_notice(&dev
->dev
, "Attempting to register port %d when only %d are available\n",
2626 index
+1, SCI_NPORTS
);
2627 dev_notice(&dev
->dev
, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2631 ret
= sci_init_single(dev
, sciport
, index
, p
, false);
2635 ret
= uart_add_one_port(&sci_uart_driver
, &sciport
->port
);
2637 sci_cleanup_single(sciport
);
2644 static int sci_probe(struct platform_device
*dev
)
2646 struct plat_sci_port
*p
;
2647 struct sci_port
*sp
;
2648 unsigned int dev_id
;
2652 * If we've come here via earlyprintk initialization, head off to
2653 * the special early probe. We don't have sufficient device state
2654 * to make it beyond this yet.
2656 if (is_early_platform_device(dev
))
2657 return sci_probe_earlyprintk(dev
);
2659 if (dev
->dev
.of_node
) {
2660 p
= sci_parse_dt(dev
, &dev_id
);
2664 p
= dev
->dev
.platform_data
;
2666 dev_err(&dev
->dev
, "no platform data supplied\n");
2673 sp
= &sci_ports
[dev_id
];
2674 platform_set_drvdata(dev
, sp
);
2676 ret
= sci_probe_single(dev
, dev_id
, p
, sp
);
2680 sp
->freq_transition
.notifier_call
= sci_notifier
;
2682 ret
= cpufreq_register_notifier(&sp
->freq_transition
,
2683 CPUFREQ_TRANSITION_NOTIFIER
);
2684 if (unlikely(ret
< 0)) {
2685 uart_remove_one_port(&sci_uart_driver
, &sp
->port
);
2686 sci_cleanup_single(sp
);
2690 #ifdef CONFIG_SH_STANDARD_BIOS
2691 sh_bios_gdb_detach();
2697 static __maybe_unused
int sci_suspend(struct device
*dev
)
2699 struct sci_port
*sport
= dev_get_drvdata(dev
);
2702 uart_suspend_port(&sci_uart_driver
, &sport
->port
);
2707 static __maybe_unused
int sci_resume(struct device
*dev
)
2709 struct sci_port
*sport
= dev_get_drvdata(dev
);
2712 uart_resume_port(&sci_uart_driver
, &sport
->port
);
2717 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops
, sci_suspend
, sci_resume
);
2719 static struct platform_driver sci_driver
= {
2721 .remove
= sci_remove
,
2724 .pm
= &sci_dev_pm_ops
,
2725 .of_match_table
= of_match_ptr(of_sci_match
),
2729 static int __init
sci_init(void)
2733 pr_info("%s\n", banner
);
2735 ret
= uart_register_driver(&sci_uart_driver
);
2736 if (likely(ret
== 0)) {
2737 ret
= platform_driver_register(&sci_driver
);
2739 uart_unregister_driver(&sci_uart_driver
);
2745 static void __exit
sci_exit(void)
2747 platform_driver_unregister(&sci_driver
);
2748 uart_unregister_driver(&sci_uart_driver
);
2751 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2752 early_platform_init_buffer("earlyprintk", &sci_driver
,
2753 early_serial_buf
, ARRAY_SIZE(early_serial_buf
));
2755 module_init(sci_init
);
2756 module_exit(sci_exit
);
2758 MODULE_LICENSE("GPL");
2759 MODULE_ALIAS("platform:sh-sci");
2760 MODULE_AUTHOR("Paul Mundt");
2761 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");