2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ
= SCIx_NR_IRQS
, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port
;
82 /* Platform configuration */
83 struct plat_sci_port
*cfg
;
85 unsigned int error_mask
;
86 unsigned int sampling_rate
;
90 struct timer_list break_timer
;
98 int irqs
[SCIx_NR_IRQS
];
99 char *irqstr
[SCIx_NR_IRQS
];
101 struct dma_chan
*chan_tx
;
102 struct dma_chan
*chan_rx
;
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 struct dma_async_tx_descriptor
*desc_tx
;
106 struct dma_async_tx_descriptor
*desc_rx
[2];
107 dma_cookie_t cookie_tx
;
108 dma_cookie_t cookie_rx
[2];
109 dma_cookie_t active_rx
;
110 struct scatterlist sg_tx
;
111 unsigned int sg_len_tx
;
112 struct scatterlist sg_rx
[2];
114 struct sh_dmae_slave param_tx
;
115 struct sh_dmae_slave param_rx
;
116 struct work_struct work_tx
;
117 struct work_struct work_rx
;
118 struct timer_list rx_timer
;
119 unsigned int rx_timeout
;
122 struct notifier_block freq_transition
;
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port
*port
);
127 static void sci_stop_tx(struct uart_port
*port
);
128 static void sci_start_rx(struct uart_port
*port
);
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
132 static struct sci_port sci_ports
[SCI_NPORTS
];
133 static struct uart_driver sci_uart_driver
;
135 static inline struct sci_port
*
136 to_sci_port(struct uart_port
*uart
)
138 return container_of(uart
, struct sci_port
, port
);
141 struct plat_sci_reg
{
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
148 static struct plat_sci_reg sci_regmap
[SCIx_NR_REGTYPES
][SCIx_NR_REGS
] = {
149 [SCIx_PROBE_REGTYPE
] = {
150 [0 ... SCIx_NR_REGS
- 1] = sci_reg_invalid
,
154 * Common SCI definitions, dependent on the port's regshift
157 [SCIx_SCI_REGTYPE
] = {
158 [SCSMR
] = { 0x00, 8 },
159 [SCBRR
] = { 0x01, 8 },
160 [SCSCR
] = { 0x02, 8 },
161 [SCxTDR
] = { 0x03, 8 },
162 [SCxSR
] = { 0x04, 8 },
163 [SCxRDR
] = { 0x05, 8 },
164 [SCFCR
] = sci_reg_invalid
,
165 [SCFDR
] = sci_reg_invalid
,
166 [SCTFDR
] = sci_reg_invalid
,
167 [SCRFDR
] = sci_reg_invalid
,
168 [SCSPTR
] = sci_reg_invalid
,
169 [SCLSR
] = sci_reg_invalid
,
170 [HSSRR
] = sci_reg_invalid
,
174 * Common definitions for legacy IrDA ports, dependent on
177 [SCIx_IRDA_REGTYPE
] = {
178 [SCSMR
] = { 0x00, 8 },
179 [SCBRR
] = { 0x01, 8 },
180 [SCSCR
] = { 0x02, 8 },
181 [SCxTDR
] = { 0x03, 8 },
182 [SCxSR
] = { 0x04, 8 },
183 [SCxRDR
] = { 0x05, 8 },
184 [SCFCR
] = { 0x06, 8 },
185 [SCFDR
] = { 0x07, 16 },
186 [SCTFDR
] = sci_reg_invalid
,
187 [SCRFDR
] = sci_reg_invalid
,
188 [SCSPTR
] = sci_reg_invalid
,
189 [SCLSR
] = sci_reg_invalid
,
190 [HSSRR
] = sci_reg_invalid
,
194 * Common SCIFA definitions.
196 [SCIx_SCIFA_REGTYPE
] = {
197 [SCSMR
] = { 0x00, 16 },
198 [SCBRR
] = { 0x04, 8 },
199 [SCSCR
] = { 0x08, 16 },
200 [SCxTDR
] = { 0x20, 8 },
201 [SCxSR
] = { 0x14, 16 },
202 [SCxRDR
] = { 0x24, 8 },
203 [SCFCR
] = { 0x18, 16 },
204 [SCFDR
] = { 0x1c, 16 },
205 [SCTFDR
] = sci_reg_invalid
,
206 [SCRFDR
] = sci_reg_invalid
,
207 [SCSPTR
] = sci_reg_invalid
,
208 [SCLSR
] = sci_reg_invalid
,
209 [HSSRR
] = sci_reg_invalid
,
213 * Common SCIFB definitions.
215 [SCIx_SCIFB_REGTYPE
] = {
216 [SCSMR
] = { 0x00, 16 },
217 [SCBRR
] = { 0x04, 8 },
218 [SCSCR
] = { 0x08, 16 },
219 [SCxTDR
] = { 0x40, 8 },
220 [SCxSR
] = { 0x14, 16 },
221 [SCxRDR
] = { 0x60, 8 },
222 [SCFCR
] = { 0x18, 16 },
223 [SCFDR
] = sci_reg_invalid
,
224 [SCTFDR
] = { 0x38, 16 },
225 [SCRFDR
] = { 0x3c, 16 },
226 [SCSPTR
] = sci_reg_invalid
,
227 [SCLSR
] = sci_reg_invalid
,
228 [HSSRR
] = sci_reg_invalid
,
232 * Common SH-2(A) SCIF definitions for ports with FIFO data
235 [SCIx_SH2_SCIF_FIFODATA_REGTYPE
] = {
236 [SCSMR
] = { 0x00, 16 },
237 [SCBRR
] = { 0x04, 8 },
238 [SCSCR
] = { 0x08, 16 },
239 [SCxTDR
] = { 0x0c, 8 },
240 [SCxSR
] = { 0x10, 16 },
241 [SCxRDR
] = { 0x14, 8 },
242 [SCFCR
] = { 0x18, 16 },
243 [SCFDR
] = { 0x1c, 16 },
244 [SCTFDR
] = sci_reg_invalid
,
245 [SCRFDR
] = sci_reg_invalid
,
246 [SCSPTR
] = { 0x20, 16 },
247 [SCLSR
] = { 0x24, 16 },
248 [HSSRR
] = sci_reg_invalid
,
252 * Common SH-3 SCIF definitions.
254 [SCIx_SH3_SCIF_REGTYPE
] = {
255 [SCSMR
] = { 0x00, 8 },
256 [SCBRR
] = { 0x02, 8 },
257 [SCSCR
] = { 0x04, 8 },
258 [SCxTDR
] = { 0x06, 8 },
259 [SCxSR
] = { 0x08, 16 },
260 [SCxRDR
] = { 0x0a, 8 },
261 [SCFCR
] = { 0x0c, 8 },
262 [SCFDR
] = { 0x0e, 16 },
263 [SCTFDR
] = sci_reg_invalid
,
264 [SCRFDR
] = sci_reg_invalid
,
265 [SCSPTR
] = sci_reg_invalid
,
266 [SCLSR
] = sci_reg_invalid
,
267 [HSSRR
] = sci_reg_invalid
,
271 * Common SH-4(A) SCIF(B) definitions.
273 [SCIx_SH4_SCIF_REGTYPE
] = {
274 [SCSMR
] = { 0x00, 16 },
275 [SCBRR
] = { 0x04, 8 },
276 [SCSCR
] = { 0x08, 16 },
277 [SCxTDR
] = { 0x0c, 8 },
278 [SCxSR
] = { 0x10, 16 },
279 [SCxRDR
] = { 0x14, 8 },
280 [SCFCR
] = { 0x18, 16 },
281 [SCFDR
] = { 0x1c, 16 },
282 [SCTFDR
] = sci_reg_invalid
,
283 [SCRFDR
] = sci_reg_invalid
,
284 [SCSPTR
] = { 0x20, 16 },
285 [SCLSR
] = { 0x24, 16 },
286 [HSSRR
] = sci_reg_invalid
,
290 * Common HSCIF definitions.
292 [SCIx_HSCIF_REGTYPE
] = {
293 [SCSMR
] = { 0x00, 16 },
294 [SCBRR
] = { 0x04, 8 },
295 [SCSCR
] = { 0x08, 16 },
296 [SCxTDR
] = { 0x0c, 8 },
297 [SCxSR
] = { 0x10, 16 },
298 [SCxRDR
] = { 0x14, 8 },
299 [SCFCR
] = { 0x18, 16 },
300 [SCFDR
] = { 0x1c, 16 },
301 [SCTFDR
] = sci_reg_invalid
,
302 [SCRFDR
] = sci_reg_invalid
,
303 [SCSPTR
] = { 0x20, 16 },
304 [SCLSR
] = { 0x24, 16 },
305 [HSSRR
] = { 0x40, 16 },
309 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
312 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE
] = {
313 [SCSMR
] = { 0x00, 16 },
314 [SCBRR
] = { 0x04, 8 },
315 [SCSCR
] = { 0x08, 16 },
316 [SCxTDR
] = { 0x0c, 8 },
317 [SCxSR
] = { 0x10, 16 },
318 [SCxRDR
] = { 0x14, 8 },
319 [SCFCR
] = { 0x18, 16 },
320 [SCFDR
] = { 0x1c, 16 },
321 [SCTFDR
] = sci_reg_invalid
,
322 [SCRFDR
] = sci_reg_invalid
,
323 [SCSPTR
] = sci_reg_invalid
,
324 [SCLSR
] = { 0x24, 16 },
325 [HSSRR
] = sci_reg_invalid
,
329 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
332 [SCIx_SH4_SCIF_FIFODATA_REGTYPE
] = {
333 [SCSMR
] = { 0x00, 16 },
334 [SCBRR
] = { 0x04, 8 },
335 [SCSCR
] = { 0x08, 16 },
336 [SCxTDR
] = { 0x0c, 8 },
337 [SCxSR
] = { 0x10, 16 },
338 [SCxRDR
] = { 0x14, 8 },
339 [SCFCR
] = { 0x18, 16 },
340 [SCFDR
] = { 0x1c, 16 },
341 [SCTFDR
] = { 0x1c, 16 }, /* aliased to SCFDR */
342 [SCRFDR
] = { 0x20, 16 },
343 [SCSPTR
] = { 0x24, 16 },
344 [SCLSR
] = { 0x28, 16 },
345 [HSSRR
] = sci_reg_invalid
,
349 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
352 [SCIx_SH7705_SCIF_REGTYPE
] = {
353 [SCSMR
] = { 0x00, 16 },
354 [SCBRR
] = { 0x04, 8 },
355 [SCSCR
] = { 0x08, 16 },
356 [SCxTDR
] = { 0x20, 8 },
357 [SCxSR
] = { 0x14, 16 },
358 [SCxRDR
] = { 0x24, 8 },
359 [SCFCR
] = { 0x18, 16 },
360 [SCFDR
] = { 0x1c, 16 },
361 [SCTFDR
] = sci_reg_invalid
,
362 [SCRFDR
] = sci_reg_invalid
,
363 [SCSPTR
] = sci_reg_invalid
,
364 [SCLSR
] = sci_reg_invalid
,
365 [HSSRR
] = sci_reg_invalid
,
369 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
372 * The "offset" here is rather misleading, in that it refers to an enum
373 * value relative to the port mapping rather than the fixed offset
374 * itself, which needs to be manually retrieved from the platform's
375 * register map for the given port.
377 static unsigned int sci_serial_in(struct uart_port
*p
, int offset
)
379 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
382 return ioread8(p
->membase
+ (reg
->offset
<< p
->regshift
));
383 else if (reg
->size
== 16)
384 return ioread16(p
->membase
+ (reg
->offset
<< p
->regshift
));
386 WARN(1, "Invalid register access\n");
391 static void sci_serial_out(struct uart_port
*p
, int offset
, int value
)
393 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
396 iowrite8(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
397 else if (reg
->size
== 16)
398 iowrite16(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
400 WARN(1, "Invalid register access\n");
403 static int sci_probe_regmap(struct plat_sci_port
*cfg
)
407 cfg
->regtype
= SCIx_SCI_REGTYPE
;
410 cfg
->regtype
= SCIx_IRDA_REGTYPE
;
413 cfg
->regtype
= SCIx_SCIFA_REGTYPE
;
416 cfg
->regtype
= SCIx_SCIFB_REGTYPE
;
420 * The SH-4 is a bit of a misnomer here, although that's
421 * where this particular port layout originated. This
422 * configuration (or some slight variation thereof)
423 * remains the dominant model for all SCIFs.
425 cfg
->regtype
= SCIx_SH4_SCIF_REGTYPE
;
428 cfg
->regtype
= SCIx_HSCIF_REGTYPE
;
431 pr_err("Can't probe register map for given port\n");
438 static void sci_port_enable(struct sci_port
*sci_port
)
440 if (!sci_port
->port
.dev
)
443 pm_runtime_get_sync(sci_port
->port
.dev
);
445 clk_prepare_enable(sci_port
->iclk
);
446 sci_port
->port
.uartclk
= clk_get_rate(sci_port
->iclk
);
447 clk_prepare_enable(sci_port
->fclk
);
450 static void sci_port_disable(struct sci_port
*sci_port
)
452 if (!sci_port
->port
.dev
)
455 /* Cancel the break timer to ensure that the timer handler will not try
456 * to access the hardware with clocks and power disabled. Reset the
457 * break flag to make the break debouncing state machine ready for the
460 del_timer_sync(&sci_port
->break_timer
);
461 sci_port
->break_flag
= 0;
463 clk_disable_unprepare(sci_port
->fclk
);
464 clk_disable_unprepare(sci_port
->iclk
);
466 pm_runtime_put_sync(sci_port
->port
.dev
);
469 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
471 #ifdef CONFIG_CONSOLE_POLL
472 static int sci_poll_get_char(struct uart_port
*port
)
474 unsigned short status
;
478 status
= serial_port_in(port
, SCxSR
);
479 if (status
& SCxSR_ERRORS(port
)) {
480 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
486 if (!(status
& SCxSR_RDxF(port
)))
489 c
= serial_port_in(port
, SCxRDR
);
492 serial_port_in(port
, SCxSR
);
493 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
499 static void sci_poll_put_char(struct uart_port
*port
, unsigned char c
)
501 unsigned short status
;
504 status
= serial_port_in(port
, SCxSR
);
505 } while (!(status
& SCxSR_TDxE(port
)));
507 serial_port_out(port
, SCxTDR
, c
);
508 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
) & ~SCxSR_TEND(port
));
510 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
512 static void sci_init_pins(struct uart_port
*port
, unsigned int cflag
)
514 struct sci_port
*s
= to_sci_port(port
);
515 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
518 * Use port-specific handler if provided.
520 if (s
->cfg
->ops
&& s
->cfg
->ops
->init_pins
) {
521 s
->cfg
->ops
->init_pins(port
, cflag
);
526 * For the generic path SCSPTR is necessary. Bail out if that's
532 if ((s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) &&
533 ((!(cflag
& CRTSCTS
)))) {
534 unsigned short status
;
536 status
= serial_port_in(port
, SCSPTR
);
537 status
&= ~SCSPTR_CTSIO
;
538 status
|= SCSPTR_RTSIO
;
539 serial_port_out(port
, SCSPTR
, status
); /* Set RTS = 1 */
543 static int sci_txfill(struct uart_port
*port
)
545 struct plat_sci_reg
*reg
;
547 reg
= sci_getreg(port
, SCTFDR
);
549 return serial_port_in(port
, SCTFDR
) & ((port
->fifosize
<< 1) - 1);
551 reg
= sci_getreg(port
, SCFDR
);
553 return serial_port_in(port
, SCFDR
) >> 8;
555 return !(serial_port_in(port
, SCxSR
) & SCI_TDRE
);
558 static int sci_txroom(struct uart_port
*port
)
560 return port
->fifosize
- sci_txfill(port
);
563 static int sci_rxfill(struct uart_port
*port
)
565 struct plat_sci_reg
*reg
;
567 reg
= sci_getreg(port
, SCRFDR
);
569 return serial_port_in(port
, SCRFDR
) & ((port
->fifosize
<< 1) - 1);
571 reg
= sci_getreg(port
, SCFDR
);
573 return serial_port_in(port
, SCFDR
) & ((port
->fifosize
<< 1) - 1);
575 return (serial_port_in(port
, SCxSR
) & SCxSR_RDxF(port
)) != 0;
579 * SCI helper for checking the state of the muxed port/RXD pins.
581 static inline int sci_rxd_in(struct uart_port
*port
)
583 struct sci_port
*s
= to_sci_port(port
);
585 if (s
->cfg
->port_reg
<= 0)
588 /* Cast for ARM damage */
589 return !!__raw_readb((void __iomem
*)(uintptr_t)s
->cfg
->port_reg
);
592 /* ********************************************************************** *
593 * the interrupt related routines *
594 * ********************************************************************** */
596 static void sci_transmit_chars(struct uart_port
*port
)
598 struct circ_buf
*xmit
= &port
->state
->xmit
;
599 unsigned int stopped
= uart_tx_stopped(port
);
600 unsigned short status
;
604 status
= serial_port_in(port
, SCxSR
);
605 if (!(status
& SCxSR_TDxE(port
))) {
606 ctrl
= serial_port_in(port
, SCSCR
);
607 if (uart_circ_empty(xmit
))
611 serial_port_out(port
, SCSCR
, ctrl
);
615 count
= sci_txroom(port
);
623 } else if (!uart_circ_empty(xmit
) && !stopped
) {
624 c
= xmit
->buf
[xmit
->tail
];
625 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
630 serial_port_out(port
, SCxTDR
, c
);
633 } while (--count
> 0);
635 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
637 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
638 uart_write_wakeup(port
);
639 if (uart_circ_empty(xmit
)) {
642 ctrl
= serial_port_in(port
, SCSCR
);
644 if (port
->type
!= PORT_SCI
) {
645 serial_port_in(port
, SCxSR
); /* Dummy read */
646 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
650 serial_port_out(port
, SCSCR
, ctrl
);
654 /* On SH3, SCIF may read end-of-break as a space->mark char */
655 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
657 static void sci_receive_chars(struct uart_port
*port
)
659 struct sci_port
*sci_port
= to_sci_port(port
);
660 struct tty_port
*tport
= &port
->state
->port
;
661 int i
, count
, copied
= 0;
662 unsigned short status
;
665 status
= serial_port_in(port
, SCxSR
);
666 if (!(status
& SCxSR_RDxF(port
)))
670 /* Don't copy more bytes than there is room for in the buffer */
671 count
= tty_buffer_request_room(tport
, sci_rxfill(port
));
673 /* If for any reason we can't copy more data, we're done! */
677 if (port
->type
== PORT_SCI
) {
678 char c
= serial_port_in(port
, SCxRDR
);
679 if (uart_handle_sysrq_char(port
, c
) ||
680 sci_port
->break_flag
)
683 tty_insert_flip_char(tport
, c
, TTY_NORMAL
);
685 for (i
= 0; i
< count
; i
++) {
686 char c
= serial_port_in(port
, SCxRDR
);
688 status
= serial_port_in(port
, SCxSR
);
689 #if defined(CONFIG_CPU_SH3)
690 /* Skip "chars" during break */
691 if (sci_port
->break_flag
) {
693 (status
& SCxSR_FER(port
))) {
698 /* Nonzero => end-of-break */
699 dev_dbg(port
->dev
, "debounce<%02x>\n", c
);
700 sci_port
->break_flag
= 0;
707 #endif /* CONFIG_CPU_SH3 */
708 if (uart_handle_sysrq_char(port
, c
)) {
713 /* Store data and status */
714 if (status
& SCxSR_FER(port
)) {
716 port
->icount
.frame
++;
717 dev_notice(port
->dev
, "frame error\n");
718 } else if (status
& SCxSR_PER(port
)) {
720 port
->icount
.parity
++;
721 dev_notice(port
->dev
, "parity error\n");
725 tty_insert_flip_char(tport
, c
, flag
);
729 serial_port_in(port
, SCxSR
); /* dummy read */
730 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
733 port
->icount
.rx
+= count
;
737 /* Tell the rest of the system the news. New characters! */
738 tty_flip_buffer_push(tport
);
740 serial_port_in(port
, SCxSR
); /* dummy read */
741 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
745 #define SCI_BREAK_JIFFIES (HZ/20)
748 * The sci generates interrupts during the break,
749 * 1 per millisecond or so during the break period, for 9600 baud.
750 * So dont bother disabling interrupts.
751 * But dont want more than 1 break event.
752 * Use a kernel timer to periodically poll the rx line until
753 * the break is finished.
755 static inline void sci_schedule_break_timer(struct sci_port
*port
)
757 mod_timer(&port
->break_timer
, jiffies
+ SCI_BREAK_JIFFIES
);
760 /* Ensure that two consecutive samples find the break over. */
761 static void sci_break_timer(unsigned long data
)
763 struct sci_port
*port
= (struct sci_port
*)data
;
765 if (sci_rxd_in(&port
->port
) == 0) {
766 port
->break_flag
= 1;
767 sci_schedule_break_timer(port
);
768 } else if (port
->break_flag
== 1) {
770 port
->break_flag
= 2;
771 sci_schedule_break_timer(port
);
773 port
->break_flag
= 0;
776 static int sci_handle_errors(struct uart_port
*port
)
779 unsigned short status
= serial_port_in(port
, SCxSR
);
780 struct tty_port
*tport
= &port
->state
->port
;
781 struct sci_port
*s
= to_sci_port(port
);
783 /* Handle overruns */
784 if (status
& (1 << s
->overrun_bit
)) {
785 port
->icount
.overrun
++;
788 if (tty_insert_flip_char(tport
, 0, TTY_OVERRUN
))
791 dev_notice(port
->dev
, "overrun error\n");
794 if (status
& SCxSR_FER(port
)) {
795 if (sci_rxd_in(port
) == 0) {
796 /* Notify of BREAK */
797 struct sci_port
*sci_port
= to_sci_port(port
);
799 if (!sci_port
->break_flag
) {
802 sci_port
->break_flag
= 1;
803 sci_schedule_break_timer(sci_port
);
805 /* Do sysrq handling. */
806 if (uart_handle_break(port
))
809 dev_dbg(port
->dev
, "BREAK detected\n");
811 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
817 port
->icount
.frame
++;
819 if (tty_insert_flip_char(tport
, 0, TTY_FRAME
))
822 dev_notice(port
->dev
, "frame error\n");
826 if (status
& SCxSR_PER(port
)) {
828 port
->icount
.parity
++;
830 if (tty_insert_flip_char(tport
, 0, TTY_PARITY
))
833 dev_notice(port
->dev
, "parity error\n");
837 tty_flip_buffer_push(tport
);
842 static int sci_handle_fifo_overrun(struct uart_port
*port
)
844 struct tty_port
*tport
= &port
->state
->port
;
845 struct sci_port
*s
= to_sci_port(port
);
846 struct plat_sci_reg
*reg
;
847 int copied
= 0, offset
;
850 switch (port
->type
) {
863 reg
= sci_getreg(port
, offset
);
867 status
= serial_port_in(port
, offset
);
868 bit
= 1 << s
->overrun_bit
;
872 serial_port_out(port
, offset
, status
);
874 port
->icount
.overrun
++;
876 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
877 tty_flip_buffer_push(tport
);
879 dev_dbg(port
->dev
, "overrun error\n");
886 static int sci_handle_breaks(struct uart_port
*port
)
889 unsigned short status
= serial_port_in(port
, SCxSR
);
890 struct tty_port
*tport
= &port
->state
->port
;
891 struct sci_port
*s
= to_sci_port(port
);
893 if (uart_handle_break(port
))
896 if (!s
->break_flag
&& status
& SCxSR_BRK(port
)) {
897 #if defined(CONFIG_CPU_SH3)
904 /* Notify of BREAK */
905 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
908 dev_dbg(port
->dev
, "BREAK detected\n");
912 tty_flip_buffer_push(tport
);
914 copied
+= sci_handle_fifo_overrun(port
);
919 static irqreturn_t
sci_rx_interrupt(int irq
, void *ptr
)
921 #ifdef CONFIG_SERIAL_SH_SCI_DMA
922 struct uart_port
*port
= ptr
;
923 struct sci_port
*s
= to_sci_port(port
);
926 u16 scr
= serial_port_in(port
, SCSCR
);
927 u16 ssr
= serial_port_in(port
, SCxSR
);
929 /* Disable future Rx interrupts */
930 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
931 disable_irq_nosync(irq
);
936 serial_port_out(port
, SCSCR
, scr
);
937 /* Clear current interrupt */
938 serial_port_out(port
, SCxSR
, ssr
& ~(1 | SCxSR_RDxF(port
)));
939 dev_dbg(port
->dev
, "Rx IRQ %lu: setup t-out in %u jiffies\n",
940 jiffies
, s
->rx_timeout
);
941 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
947 /* I think sci_receive_chars has to be called irrespective
948 * of whether the I_IXOFF is set, otherwise, how is the interrupt
951 sci_receive_chars(ptr
);
956 static irqreturn_t
sci_tx_interrupt(int irq
, void *ptr
)
958 struct uart_port
*port
= ptr
;
961 spin_lock_irqsave(&port
->lock
, flags
);
962 sci_transmit_chars(port
);
963 spin_unlock_irqrestore(&port
->lock
, flags
);
968 static irqreturn_t
sci_er_interrupt(int irq
, void *ptr
)
970 struct uart_port
*port
= ptr
;
973 if (port
->type
== PORT_SCI
) {
974 if (sci_handle_errors(port
)) {
975 /* discard character in rx buffer */
976 serial_port_in(port
, SCxSR
);
977 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
980 sci_handle_fifo_overrun(port
);
981 sci_rx_interrupt(irq
, ptr
);
984 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
986 /* Kick the transmission */
987 sci_tx_interrupt(irq
, ptr
);
992 static irqreturn_t
sci_br_interrupt(int irq
, void *ptr
)
994 struct uart_port
*port
= ptr
;
997 sci_handle_breaks(port
);
998 serial_port_out(port
, SCxSR
, SCxSR_BREAK_CLEAR(port
));
1003 static inline unsigned long port_rx_irq_mask(struct uart_port
*port
)
1006 * Not all ports (such as SCIFA) will support REIE. Rather than
1007 * special-casing the port type, we check the port initialization
1008 * IRQ enable mask to see whether the IRQ is desired at all. If
1009 * it's unset, it's logically inferred that there's no point in
1012 return SCSCR_RIE
| (to_sci_port(port
)->cfg
->scscr
& SCSCR_REIE
);
1015 static irqreturn_t
sci_mpxed_interrupt(int irq
, void *ptr
)
1017 unsigned short ssr_status
, scr_status
, err_enabled
, orer_status
= 0;
1018 struct uart_port
*port
= ptr
;
1019 struct sci_port
*s
= to_sci_port(port
);
1020 irqreturn_t ret
= IRQ_NONE
;
1022 ssr_status
= serial_port_in(port
, SCxSR
);
1023 scr_status
= serial_port_in(port
, SCSCR
);
1024 switch (port
->type
) {
1027 orer_status
= serial_port_in(port
, SCLSR
);
1031 orer_status
= ssr_status
;
1035 err_enabled
= scr_status
& port_rx_irq_mask(port
);
1038 if ((ssr_status
& SCxSR_TDxE(port
)) && (scr_status
& SCSCR_TIE
) &&
1040 ret
= sci_tx_interrupt(irq
, ptr
);
1043 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1046 if (((ssr_status
& SCxSR_RDxF(port
)) || s
->chan_rx
) &&
1047 (scr_status
& SCSCR_RIE
)) {
1048 if (port
->type
== PORT_SCIF
|| port
->type
== PORT_HSCIF
)
1049 sci_handle_fifo_overrun(port
);
1050 ret
= sci_rx_interrupt(irq
, ptr
);
1053 /* Error Interrupt */
1054 if ((ssr_status
& SCxSR_ERRORS(port
)) && err_enabled
)
1055 ret
= sci_er_interrupt(irq
, ptr
);
1057 /* Break Interrupt */
1058 if ((ssr_status
& SCxSR_BRK(port
)) && err_enabled
)
1059 ret
= sci_br_interrupt(irq
, ptr
);
1061 /* Overrun Interrupt */
1062 if (orer_status
& (1 << s
->overrun_bit
))
1063 sci_handle_fifo_overrun(port
);
1069 * Here we define a transition notifier so that we can update all of our
1070 * ports' baud rate when the peripheral clock changes.
1072 static int sci_notifier(struct notifier_block
*self
,
1073 unsigned long phase
, void *p
)
1075 struct sci_port
*sci_port
;
1076 unsigned long flags
;
1078 sci_port
= container_of(self
, struct sci_port
, freq_transition
);
1080 if (phase
== CPUFREQ_POSTCHANGE
) {
1081 struct uart_port
*port
= &sci_port
->port
;
1083 spin_lock_irqsave(&port
->lock
, flags
);
1084 port
->uartclk
= clk_get_rate(sci_port
->iclk
);
1085 spin_unlock_irqrestore(&port
->lock
, flags
);
1091 static struct sci_irq_desc
{
1093 irq_handler_t handler
;
1094 } sci_irq_desc
[] = {
1096 * Split out handlers, the default case.
1100 .handler
= sci_er_interrupt
,
1105 .handler
= sci_rx_interrupt
,
1110 .handler
= sci_tx_interrupt
,
1115 .handler
= sci_br_interrupt
,
1119 * Special muxed handler.
1123 .handler
= sci_mpxed_interrupt
,
1127 static int sci_request_irq(struct sci_port
*port
)
1129 struct uart_port
*up
= &port
->port
;
1132 for (i
= j
= 0; i
< SCIx_NR_IRQS
; i
++, j
++) {
1133 struct sci_irq_desc
*desc
;
1136 if (SCIx_IRQ_IS_MUXED(port
)) {
1140 irq
= port
->irqs
[i
];
1143 * Certain port types won't support all of the
1144 * available interrupt sources.
1146 if (unlikely(irq
< 0))
1150 desc
= sci_irq_desc
+ i
;
1151 port
->irqstr
[j
] = kasprintf(GFP_KERNEL
, "%s:%s",
1152 dev_name(up
->dev
), desc
->desc
);
1153 if (!port
->irqstr
[j
]) {
1154 dev_err(up
->dev
, "Failed to allocate %s IRQ string\n",
1159 ret
= request_irq(irq
, desc
->handler
, up
->irqflags
,
1160 port
->irqstr
[j
], port
);
1161 if (unlikely(ret
)) {
1162 dev_err(up
->dev
, "Can't allocate %s IRQ\n", desc
->desc
);
1171 free_irq(port
->irqs
[i
], port
);
1175 kfree(port
->irqstr
[j
]);
1180 static void sci_free_irq(struct sci_port
*port
)
1185 * Intentionally in reverse order so we iterate over the muxed
1188 for (i
= 0; i
< SCIx_NR_IRQS
; i
++) {
1189 int irq
= port
->irqs
[i
];
1192 * Certain port types won't support all of the available
1193 * interrupt sources.
1195 if (unlikely(irq
< 0))
1198 free_irq(port
->irqs
[i
], port
);
1199 kfree(port
->irqstr
[i
]);
1201 if (SCIx_IRQ_IS_MUXED(port
)) {
1202 /* If there's only one IRQ, we're done. */
1208 static unsigned int sci_tx_empty(struct uart_port
*port
)
1210 unsigned short status
= serial_port_in(port
, SCxSR
);
1211 unsigned short in_tx_fifo
= sci_txfill(port
);
1213 return (status
& SCxSR_TEND(port
)) && !in_tx_fifo
? TIOCSER_TEMT
: 0;
1217 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1218 * CTS/RTS is supported in hardware by at least one port and controlled
1219 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1220 * handled via the ->init_pins() op, which is a bit of a one-way street,
1221 * lacking any ability to defer pin control -- this will later be
1222 * converted over to the GPIO framework).
1224 * Other modes (such as loopback) are supported generically on certain
1225 * port types, but not others. For these it's sufficient to test for the
1226 * existence of the support register and simply ignore the port type.
1228 static void sci_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1230 if (mctrl
& TIOCM_LOOP
) {
1231 struct plat_sci_reg
*reg
;
1234 * Standard loopback mode for SCFCR ports.
1236 reg
= sci_getreg(port
, SCFCR
);
1238 serial_port_out(port
, SCFCR
,
1239 serial_port_in(port
, SCFCR
) |
1244 static unsigned int sci_get_mctrl(struct uart_port
*port
)
1247 * CTS/RTS is handled in hardware when supported, while nothing
1248 * else is wired up. Keep it simple and simply assert DSR/CAR.
1250 return TIOCM_DSR
| TIOCM_CAR
;
1253 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1254 static void sci_dma_tx_complete(void *arg
)
1256 struct sci_port
*s
= arg
;
1257 struct uart_port
*port
= &s
->port
;
1258 struct circ_buf
*xmit
= &port
->state
->xmit
;
1259 unsigned long flags
;
1261 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1263 spin_lock_irqsave(&port
->lock
, flags
);
1265 xmit
->tail
+= sg_dma_len(&s
->sg_tx
);
1266 xmit
->tail
&= UART_XMIT_SIZE
- 1;
1268 port
->icount
.tx
+= sg_dma_len(&s
->sg_tx
);
1270 async_tx_ack(s
->desc_tx
);
1273 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1274 uart_write_wakeup(port
);
1276 if (!uart_circ_empty(xmit
)) {
1278 schedule_work(&s
->work_tx
);
1280 s
->cookie_tx
= -EINVAL
;
1281 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1282 u16 ctrl
= serial_port_in(port
, SCSCR
);
1283 serial_port_out(port
, SCSCR
, ctrl
& ~SCSCR_TIE
);
1287 spin_unlock_irqrestore(&port
->lock
, flags
);
1290 /* Locking: called with port lock held */
1291 static int sci_dma_rx_push(struct sci_port
*s
, size_t count
)
1293 struct uart_port
*port
= &s
->port
;
1294 struct tty_port
*tport
= &port
->state
->port
;
1295 int i
, active
, room
;
1297 room
= tty_buffer_request_room(tport
, count
);
1299 if (s
->active_rx
== s
->cookie_rx
[0]) {
1301 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1304 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1309 dev_warn(port
->dev
, "Rx overrun: dropping %zu bytes\n",
1314 for (i
= 0; i
< room
; i
++)
1315 tty_insert_flip_char(tport
, ((u8
*)sg_virt(&s
->sg_rx
[active
]))[i
],
1318 port
->icount
.rx
+= room
;
1323 static void sci_dma_rx_complete(void *arg
)
1325 struct sci_port
*s
= arg
;
1326 struct uart_port
*port
= &s
->port
;
1327 unsigned long flags
;
1330 dev_dbg(port
->dev
, "%s(%d) active #%d\n",
1331 __func__
, port
->line
, s
->active_rx
);
1333 spin_lock_irqsave(&port
->lock
, flags
);
1335 count
= sci_dma_rx_push(s
, s
->buf_len_rx
);
1337 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
1339 spin_unlock_irqrestore(&port
->lock
, flags
);
1342 tty_flip_buffer_push(&port
->state
->port
);
1344 schedule_work(&s
->work_rx
);
1347 static void sci_rx_dma_release(struct sci_port
*s
, bool enable_pio
)
1349 struct dma_chan
*chan
= s
->chan_rx
;
1350 struct uart_port
*port
= &s
->port
;
1353 s
->cookie_rx
[0] = s
->cookie_rx
[1] = -EINVAL
;
1354 dma_release_channel(chan
);
1355 if (sg_dma_address(&s
->sg_rx
[0]))
1356 dma_free_coherent(port
->dev
, s
->buf_len_rx
* 2,
1357 sg_virt(&s
->sg_rx
[0]), sg_dma_address(&s
->sg_rx
[0]));
1362 static void sci_tx_dma_release(struct sci_port
*s
, bool enable_pio
)
1364 struct dma_chan
*chan
= s
->chan_tx
;
1365 struct uart_port
*port
= &s
->port
;
1368 s
->cookie_tx
= -EINVAL
;
1369 dma_release_channel(chan
);
1374 static void sci_submit_rx(struct sci_port
*s
)
1376 struct dma_chan
*chan
= s
->chan_rx
;
1379 for (i
= 0; i
< 2; i
++) {
1380 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1381 struct dma_async_tx_descriptor
*desc
;
1383 desc
= dmaengine_prep_slave_sg(chan
,
1384 sg
, 1, DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1387 s
->desc_rx
[i
] = desc
;
1388 desc
->callback
= sci_dma_rx_complete
;
1389 desc
->callback_param
= s
;
1390 s
->cookie_rx
[i
] = desc
->tx_submit(desc
);
1393 if (!desc
|| s
->cookie_rx
[i
] < 0) {
1395 async_tx_ack(s
->desc_rx
[0]);
1396 s
->cookie_rx
[0] = -EINVAL
;
1400 s
->cookie_rx
[i
] = -EINVAL
;
1402 dev_warn(s
->port
.dev
,
1403 "failed to re-start DMA, using PIO\n");
1404 sci_rx_dma_release(s
, true);
1407 dev_dbg(s
->port
.dev
, "%s(): cookie %d to #%d\n",
1408 __func__
, s
->cookie_rx
[i
], i
);
1411 s
->active_rx
= s
->cookie_rx
[0];
1413 dma_async_issue_pending(chan
);
1416 static void work_fn_rx(struct work_struct
*work
)
1418 struct sci_port
*s
= container_of(work
, struct sci_port
, work_rx
);
1419 struct uart_port
*port
= &s
->port
;
1420 struct dma_async_tx_descriptor
*desc
;
1423 if (s
->active_rx
== s
->cookie_rx
[0]) {
1425 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1428 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1431 desc
= s
->desc_rx
[new];
1433 if (dma_async_is_tx_complete(s
->chan_rx
, s
->active_rx
, NULL
, NULL
) !=
1435 /* Handle incomplete DMA receive */
1436 struct dma_chan
*chan
= s
->chan_rx
;
1437 struct shdma_desc
*sh_desc
= container_of(desc
,
1438 struct shdma_desc
, async_tx
);
1439 unsigned long flags
;
1442 dmaengine_terminate_all(chan
);
1443 dev_dbg(port
->dev
, "Read %zu bytes with cookie %d\n",
1444 sh_desc
->partial
, sh_desc
->cookie
);
1446 spin_lock_irqsave(&port
->lock
, flags
);
1447 count
= sci_dma_rx_push(s
, sh_desc
->partial
);
1448 spin_unlock_irqrestore(&port
->lock
, flags
);
1451 tty_flip_buffer_push(&port
->state
->port
);
1458 s
->cookie_rx
[new] = desc
->tx_submit(desc
);
1459 if (s
->cookie_rx
[new] < 0) {
1460 dev_warn(port
->dev
, "Failed submitting Rx DMA descriptor\n");
1461 sci_rx_dma_release(s
, true);
1465 s
->active_rx
= s
->cookie_rx
[!new];
1467 dev_dbg(port
->dev
, "%s: cookie %d #%d, new active #%d\n",
1468 __func__
, s
->cookie_rx
[new], new, s
->active_rx
);
1471 static void work_fn_tx(struct work_struct
*work
)
1473 struct sci_port
*s
= container_of(work
, struct sci_port
, work_tx
);
1474 struct dma_async_tx_descriptor
*desc
;
1475 struct dma_chan
*chan
= s
->chan_tx
;
1476 struct uart_port
*port
= &s
->port
;
1477 struct circ_buf
*xmit
= &port
->state
->xmit
;
1478 struct scatterlist
*sg
= &s
->sg_tx
;
1482 * Port xmit buffer is already mapped, and it is one page... Just adjust
1483 * offsets and lengths. Since it is a circular buffer, we have to
1484 * transmit till the end, and then the rest. Take the port lock to get a
1485 * consistent xmit buffer state.
1487 spin_lock_irq(&port
->lock
);
1488 sg
->offset
= xmit
->tail
& (UART_XMIT_SIZE
- 1);
1489 sg_dma_address(sg
) = (sg_dma_address(sg
) & ~(UART_XMIT_SIZE
- 1)) +
1491 sg_dma_len(sg
) = min((int)CIRC_CNT(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
),
1492 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
));
1493 spin_unlock_irq(&port
->lock
);
1495 BUG_ON(!sg_dma_len(sg
));
1497 desc
= dmaengine_prep_slave_sg(chan
,
1498 sg
, s
->sg_len_tx
, DMA_MEM_TO_DEV
,
1499 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1502 sci_tx_dma_release(s
, true);
1506 dma_sync_sg_for_device(port
->dev
, sg
, 1, DMA_TO_DEVICE
);
1508 spin_lock_irq(&port
->lock
);
1510 desc
->callback
= sci_dma_tx_complete
;
1511 desc
->callback_param
= s
;
1512 spin_unlock_irq(&port
->lock
);
1513 s
->cookie_tx
= desc
->tx_submit(desc
);
1514 if (s
->cookie_tx
< 0) {
1515 dev_warn(port
->dev
, "Failed submitting Tx DMA descriptor\n");
1517 sci_tx_dma_release(s
, true);
1521 dev_dbg(port
->dev
, "%s: %p: %d...%d, cookie %d\n",
1522 __func__
, xmit
->buf
, xmit
->tail
, xmit
->head
, s
->cookie_tx
);
1524 dma_async_issue_pending(chan
);
1528 static void sci_start_tx(struct uart_port
*port
)
1530 struct sci_port
*s
= to_sci_port(port
);
1531 unsigned short ctrl
;
1533 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1534 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1535 u16
new, scr
= serial_port_in(port
, SCSCR
);
1537 new = scr
| SCSCR_TDRQE
;
1539 new = scr
& ~SCSCR_TDRQE
;
1541 serial_port_out(port
, SCSCR
, new);
1544 if (s
->chan_tx
&& !uart_circ_empty(&s
->port
.state
->xmit
) &&
1547 schedule_work(&s
->work_tx
);
1551 if (!s
->chan_tx
|| port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1552 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1553 ctrl
= serial_port_in(port
, SCSCR
);
1554 serial_port_out(port
, SCSCR
, ctrl
| SCSCR_TIE
);
1558 static void sci_stop_tx(struct uart_port
*port
)
1560 unsigned short ctrl
;
1562 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1563 ctrl
= serial_port_in(port
, SCSCR
);
1565 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1566 ctrl
&= ~SCSCR_TDRQE
;
1570 serial_port_out(port
, SCSCR
, ctrl
);
1573 static void sci_start_rx(struct uart_port
*port
)
1575 unsigned short ctrl
;
1577 ctrl
= serial_port_in(port
, SCSCR
) | port_rx_irq_mask(port
);
1579 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1580 ctrl
&= ~SCSCR_RDRQE
;
1582 serial_port_out(port
, SCSCR
, ctrl
);
1585 static void sci_stop_rx(struct uart_port
*port
)
1587 unsigned short ctrl
;
1589 ctrl
= serial_port_in(port
, SCSCR
);
1591 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1592 ctrl
&= ~SCSCR_RDRQE
;
1594 ctrl
&= ~port_rx_irq_mask(port
);
1596 serial_port_out(port
, SCSCR
, ctrl
);
1599 static void sci_break_ctl(struct uart_port
*port
, int break_state
)
1601 struct sci_port
*s
= to_sci_port(port
);
1602 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
1603 unsigned short scscr
, scsptr
;
1605 /* check wheter the port has SCSPTR */
1608 * Not supported by hardware. Most parts couple break and rx
1609 * interrupts together, with break detection always enabled.
1614 scsptr
= serial_port_in(port
, SCSPTR
);
1615 scscr
= serial_port_in(port
, SCSCR
);
1617 if (break_state
== -1) {
1618 scsptr
= (scsptr
| SCSPTR_SPB2IO
) & ~SCSPTR_SPB2DT
;
1621 scsptr
= (scsptr
| SCSPTR_SPB2DT
) & ~SCSPTR_SPB2IO
;
1625 serial_port_out(port
, SCSPTR
, scsptr
);
1626 serial_port_out(port
, SCSCR
, scscr
);
1629 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1630 static bool filter(struct dma_chan
*chan
, void *slave
)
1632 struct sh_dmae_slave
*param
= slave
;
1634 dev_dbg(chan
->device
->dev
, "%s: slave ID %d\n",
1635 __func__
, param
->shdma_slave
.slave_id
);
1637 chan
->private = ¶m
->shdma_slave
;
1641 static void rx_timer_fn(unsigned long arg
)
1643 struct sci_port
*s
= (struct sci_port
*)arg
;
1644 struct uart_port
*port
= &s
->port
;
1645 u16 scr
= serial_port_in(port
, SCSCR
);
1647 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1648 scr
&= ~SCSCR_RDRQE
;
1649 enable_irq(s
->irqs
[SCIx_RXI_IRQ
]);
1651 serial_port_out(port
, SCSCR
, scr
| SCSCR_RIE
);
1652 dev_dbg(port
->dev
, "DMA Rx timed out\n");
1653 schedule_work(&s
->work_rx
);
1656 static void sci_request_dma(struct uart_port
*port
)
1658 struct sci_port
*s
= to_sci_port(port
);
1659 struct sh_dmae_slave
*param
;
1660 struct dma_chan
*chan
;
1661 dma_cap_mask_t mask
;
1664 dev_dbg(port
->dev
, "%s: port %d\n", __func__
, port
->line
);
1666 if (s
->cfg
->dma_slave_tx
<= 0 || s
->cfg
->dma_slave_rx
<= 0)
1670 dma_cap_set(DMA_SLAVE
, mask
);
1672 param
= &s
->param_tx
;
1674 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1675 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_tx
;
1677 s
->cookie_tx
= -EINVAL
;
1678 chan
= dma_request_channel(mask
, filter
, param
);
1679 dev_dbg(port
->dev
, "%s: TX: got channel %p\n", __func__
, chan
);
1682 sg_init_table(&s
->sg_tx
, 1);
1683 /* UART circular tx buffer is an aligned page. */
1684 BUG_ON((uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1685 sg_set_page(&s
->sg_tx
, virt_to_page(port
->state
->xmit
.buf
),
1687 (uintptr_t)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1688 nent
= dma_map_sg(port
->dev
, &s
->sg_tx
, 1, DMA_TO_DEVICE
);
1690 sci_tx_dma_release(s
, false);
1692 dev_dbg(port
->dev
, "%s: mapped %d@%p to %pad\n",
1694 sg_dma_len(&s
->sg_tx
), port
->state
->xmit
.buf
,
1695 &sg_dma_address(&s
->sg_tx
));
1697 s
->sg_len_tx
= nent
;
1699 INIT_WORK(&s
->work_tx
, work_fn_tx
);
1702 param
= &s
->param_rx
;
1704 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1705 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_rx
;
1707 chan
= dma_request_channel(mask
, filter
, param
);
1708 dev_dbg(port
->dev
, "%s: RX: got channel %p\n", __func__
, chan
);
1716 s
->buf_len_rx
= 2 * max(16, (int)port
->fifosize
);
1717 buf
[0] = dma_alloc_coherent(port
->dev
, s
->buf_len_rx
* 2,
1718 &dma
[0], GFP_KERNEL
);
1722 "failed to allocate dma buffer, using PIO\n");
1723 sci_rx_dma_release(s
, true);
1727 buf
[1] = buf
[0] + s
->buf_len_rx
;
1728 dma
[1] = dma
[0] + s
->buf_len_rx
;
1730 for (i
= 0; i
< 2; i
++) {
1731 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1733 sg_init_table(sg
, 1);
1734 sg_set_page(sg
, virt_to_page(buf
[i
]), s
->buf_len_rx
,
1735 (uintptr_t)buf
[i
] & ~PAGE_MASK
);
1736 sg_dma_address(sg
) = dma
[i
];
1739 INIT_WORK(&s
->work_rx
, work_fn_rx
);
1740 setup_timer(&s
->rx_timer
, rx_timer_fn
, (unsigned long)s
);
1746 static void sci_free_dma(struct uart_port
*port
)
1748 struct sci_port
*s
= to_sci_port(port
);
1751 sci_tx_dma_release(s
, false);
1753 sci_rx_dma_release(s
, false);
1756 static inline void sci_request_dma(struct uart_port
*port
)
1760 static inline void sci_free_dma(struct uart_port
*port
)
1765 static int sci_startup(struct uart_port
*port
)
1767 struct sci_port
*s
= to_sci_port(port
);
1768 unsigned long flags
;
1771 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1773 ret
= sci_request_irq(s
);
1774 if (unlikely(ret
< 0))
1777 sci_request_dma(port
);
1779 spin_lock_irqsave(&port
->lock
, flags
);
1782 spin_unlock_irqrestore(&port
->lock
, flags
);
1787 static void sci_shutdown(struct uart_port
*port
)
1789 struct sci_port
*s
= to_sci_port(port
);
1790 unsigned long flags
;
1792 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1794 spin_lock_irqsave(&port
->lock
, flags
);
1797 spin_unlock_irqrestore(&port
->lock
, flags
);
1803 static unsigned int sci_scbrr_calc(struct sci_port
*s
, unsigned int bps
,
1806 if (s
->sampling_rate
)
1807 return DIV_ROUND_CLOSEST(freq
, s
->sampling_rate
* bps
) - 1;
1809 /* Warn, but use a safe default */
1812 return ((freq
+ 16 * bps
) / (32 * bps
) - 1);
1815 /* calculate frame length from SMR */
1816 static int sci_baud_calc_frame_len(unsigned int smr_val
)
1820 if (smr_val
& SCSMR_CHR
)
1822 if (smr_val
& SCSMR_PE
)
1824 if (smr_val
& SCSMR_STOP
)
1831 /* calculate sample rate, BRR, and clock select for HSCIF */
1832 static void sci_baud_calc_hscif(unsigned int bps
, unsigned long freq
,
1833 int *brr
, unsigned int *srr
,
1834 unsigned int *cks
, int frame_len
)
1836 int sr
, c
, br
, err
, recv_margin
;
1837 int min_err
= 1000; /* 100% */
1838 int recv_max_margin
= 0;
1840 /* Find the combination of sample rate and clock select with the
1841 smallest deviation from the desired baud rate. */
1842 for (sr
= 8; sr
<= 32; sr
++) {
1843 for (c
= 0; c
<= 3; c
++) {
1844 /* integerized formulas from HSCIF documentation */
1845 br
= DIV_ROUND_CLOSEST(freq
, (sr
*
1846 (1 << (2 * c
+ 1)) * bps
)) - 1;
1847 br
= clamp(br
, 0, 255);
1848 err
= DIV_ROUND_CLOSEST(freq
, ((br
+ 1) * bps
* sr
*
1849 (1 << (2 * c
+ 1)) / 1000)) -
1852 * M: Receive margin (%)
1853 * N: Ratio of bit rate to clock (N = sampling rate)
1854 * D: Clock duty (D = 0 to 1.0)
1855 * L: Frame length (L = 9 to 12)
1856 * F: Absolute value of clock frequency deviation
1858 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1859 * (|D - 0.5| / N * (1 + F))|
1860 * NOTE: Usually, treat D for 0.5, F is 0 by this
1863 recv_margin
= abs((500 -
1864 DIV_ROUND_CLOSEST(1000, sr
<< 1)) / 10);
1865 if (abs(min_err
) > abs(err
)) {
1867 recv_max_margin
= recv_margin
;
1868 } else if ((min_err
== err
) &&
1869 (recv_margin
> recv_max_margin
))
1870 recv_max_margin
= recv_margin
;
1880 if (min_err
== 1000) {
1889 static void sci_reset(struct uart_port
*port
)
1891 struct plat_sci_reg
*reg
;
1892 unsigned int status
;
1895 status
= serial_port_in(port
, SCxSR
);
1896 } while (!(status
& SCxSR_TEND(port
)));
1898 serial_port_out(port
, SCSCR
, 0x00); /* TE=0, RE=0, CKE1=0 */
1900 reg
= sci_getreg(port
, SCFCR
);
1902 serial_port_out(port
, SCFCR
, SCFCR_RFRST
| SCFCR_TFRST
);
1905 static void sci_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1906 struct ktermios
*old
)
1908 struct sci_port
*s
= to_sci_port(port
);
1909 struct plat_sci_reg
*reg
;
1910 unsigned int baud
, smr_val
= 0, max_baud
, cks
= 0;
1912 unsigned int srr
= 15;
1914 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1915 smr_val
|= SCSMR_CHR
;
1916 if (termios
->c_cflag
& PARENB
)
1917 smr_val
|= SCSMR_PE
;
1918 if (termios
->c_cflag
& PARODD
)
1919 smr_val
|= SCSMR_PE
| SCSMR_ODD
;
1920 if (termios
->c_cflag
& CSTOPB
)
1921 smr_val
|= SCSMR_STOP
;
1924 * earlyprintk comes here early on with port->uartclk set to zero.
1925 * the clock framework is not up and running at this point so here
1926 * we assume that 115200 is the maximum baud rate. please note that
1927 * the baud rate is not programmed during earlyprintk - it is assumed
1928 * that the previous boot loader has enabled required clocks and
1929 * setup the baud rate generator hardware for us already.
1931 max_baud
= port
->uartclk
? port
->uartclk
/ 16 : 115200;
1933 baud
= uart_get_baud_rate(port
, termios
, old
, 0, max_baud
);
1934 if (likely(baud
&& port
->uartclk
)) {
1935 if (s
->cfg
->type
== PORT_HSCIF
) {
1936 int frame_len
= sci_baud_calc_frame_len(smr_val
);
1937 sci_baud_calc_hscif(baud
, port
->uartclk
, &t
, &srr
,
1940 t
= sci_scbrr_calc(s
, baud
, port
->uartclk
);
1941 for (cks
= 0; t
>= 256 && cks
<= 3; cks
++)
1950 smr_val
|= serial_port_in(port
, SCSMR
) & 3;
1952 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1954 dev_dbg(port
->dev
, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1955 __func__
, smr_val
, cks
, t
, s
->cfg
->scscr
);
1958 serial_port_out(port
, SCSMR
, (smr_val
& ~SCSMR_CKS
) | cks
);
1959 serial_port_out(port
, SCBRR
, t
);
1960 reg
= sci_getreg(port
, HSSRR
);
1962 serial_port_out(port
, HSSRR
, srr
| HSCIF_SRE
);
1963 udelay((1000000+(baud
-1)) / baud
); /* Wait one bit interval */
1965 serial_port_out(port
, SCSMR
, smr_val
);
1967 sci_init_pins(port
, termios
->c_cflag
);
1969 reg
= sci_getreg(port
, SCFCR
);
1971 unsigned short ctrl
= serial_port_in(port
, SCFCR
);
1973 if (s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) {
1974 if (termios
->c_cflag
& CRTSCTS
)
1981 * As we've done a sci_reset() above, ensure we don't
1982 * interfere with the FIFOs while toggling MCE. As the
1983 * reset values could still be set, simply mask them out.
1985 ctrl
&= ~(SCFCR_RFRST
| SCFCR_TFRST
);
1987 serial_port_out(port
, SCFCR
, ctrl
);
1990 serial_port_out(port
, SCSCR
, s
->cfg
->scscr
);
1992 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1994 * Calculate delay for 2 DMA buffers (4 FIFO).
1995 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
1996 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1997 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1998 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
1999 * sizes), but when performing a faster transfer, value obtained by
2000 * this formula is may not enough. Therefore, if value is smaller than
2001 * 20msec, this sets 20msec as timeout of DMA.
2006 /* byte size and parity */
2007 switch (termios
->c_cflag
& CSIZE
) {
2022 if (termios
->c_cflag
& CSTOPB
)
2024 if (termios
->c_cflag
& PARENB
)
2026 s
->rx_timeout
= DIV_ROUND_UP((s
->buf_len_rx
* 2 * bits
* HZ
) /
2028 dev_dbg(port
->dev
, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2029 s
->rx_timeout
* 1000 / HZ
, port
->timeout
);
2030 if (s
->rx_timeout
< msecs_to_jiffies(20))
2031 s
->rx_timeout
= msecs_to_jiffies(20);
2035 if ((termios
->c_cflag
& CREAD
) != 0)
2038 sci_port_disable(s
);
2041 static void sci_pm(struct uart_port
*port
, unsigned int state
,
2042 unsigned int oldstate
)
2044 struct sci_port
*sci_port
= to_sci_port(port
);
2047 case UART_PM_STATE_OFF
:
2048 sci_port_disable(sci_port
);
2051 sci_port_enable(sci_port
);
2056 static const char *sci_type(struct uart_port
*port
)
2058 switch (port
->type
) {
2076 static inline unsigned long sci_port_size(struct uart_port
*port
)
2079 * Pick an arbitrary size that encapsulates all of the base
2080 * registers by default. This can be optimized later, or derived
2081 * from platform resource data at such a time that ports begin to
2082 * behave more erratically.
2084 if (port
->type
== PORT_HSCIF
)
2090 static int sci_remap_port(struct uart_port
*port
)
2092 unsigned long size
= sci_port_size(port
);
2095 * Nothing to do if there's already an established membase.
2100 if (port
->flags
& UPF_IOREMAP
) {
2101 port
->membase
= ioremap_nocache(port
->mapbase
, size
);
2102 if (unlikely(!port
->membase
)) {
2103 dev_err(port
->dev
, "can't remap port#%d\n", port
->line
);
2108 * For the simple (and majority of) cases where we don't
2109 * need to do any remapping, just cast the cookie
2112 port
->membase
= (void __iomem
*)(uintptr_t)port
->mapbase
;
2118 static void sci_release_port(struct uart_port
*port
)
2120 if (port
->flags
& UPF_IOREMAP
) {
2121 iounmap(port
->membase
);
2122 port
->membase
= NULL
;
2125 release_mem_region(port
->mapbase
, sci_port_size(port
));
2128 static int sci_request_port(struct uart_port
*port
)
2130 unsigned long size
= sci_port_size(port
);
2131 struct resource
*res
;
2134 res
= request_mem_region(port
->mapbase
, size
, dev_name(port
->dev
));
2135 if (unlikely(res
== NULL
))
2138 ret
= sci_remap_port(port
);
2139 if (unlikely(ret
!= 0)) {
2140 release_resource(res
);
2147 static void sci_config_port(struct uart_port
*port
, int flags
)
2149 if (flags
& UART_CONFIG_TYPE
) {
2150 struct sci_port
*sport
= to_sci_port(port
);
2152 port
->type
= sport
->cfg
->type
;
2153 sci_request_port(port
);
2157 static int sci_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2159 if (ser
->baud_base
< 2400)
2160 /* No paper tape reader for Mitch.. */
2166 static struct uart_ops sci_uart_ops
= {
2167 .tx_empty
= sci_tx_empty
,
2168 .set_mctrl
= sci_set_mctrl
,
2169 .get_mctrl
= sci_get_mctrl
,
2170 .start_tx
= sci_start_tx
,
2171 .stop_tx
= sci_stop_tx
,
2172 .stop_rx
= sci_stop_rx
,
2173 .break_ctl
= sci_break_ctl
,
2174 .startup
= sci_startup
,
2175 .shutdown
= sci_shutdown
,
2176 .set_termios
= sci_set_termios
,
2179 .release_port
= sci_release_port
,
2180 .request_port
= sci_request_port
,
2181 .config_port
= sci_config_port
,
2182 .verify_port
= sci_verify_port
,
2183 #ifdef CONFIG_CONSOLE_POLL
2184 .poll_get_char
= sci_poll_get_char
,
2185 .poll_put_char
= sci_poll_put_char
,
2189 static int sci_init_single(struct platform_device
*dev
,
2190 struct sci_port
*sci_port
, unsigned int index
,
2191 struct plat_sci_port
*p
, bool early
)
2193 struct uart_port
*port
= &sci_port
->port
;
2194 const struct resource
*res
;
2195 unsigned int sampling_rate
;
2201 port
->ops
= &sci_uart_ops
;
2202 port
->iotype
= UPIO_MEM
;
2205 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
2209 port
->mapbase
= res
->start
;
2211 for (i
= 0; i
< ARRAY_SIZE(sci_port
->irqs
); ++i
)
2212 sci_port
->irqs
[i
] = platform_get_irq(dev
, i
);
2214 /* The SCI generates several interrupts. They can be muxed together or
2215 * connected to different interrupt lines. In the muxed case only one
2216 * interrupt resource is specified. In the non-muxed case three or four
2217 * interrupt resources are specified, as the BRI interrupt is optional.
2219 if (sci_port
->irqs
[0] < 0)
2222 if (sci_port
->irqs
[1] < 0) {
2223 sci_port
->irqs
[1] = sci_port
->irqs
[0];
2224 sci_port
->irqs
[2] = sci_port
->irqs
[0];
2225 sci_port
->irqs
[3] = sci_port
->irqs
[0];
2228 if (p
->regtype
== SCIx_PROBE_REGTYPE
) {
2229 ret
= sci_probe_regmap(p
);
2236 port
->fifosize
= 256;
2237 sci_port
->overrun_bit
= 9;
2241 port
->fifosize
= 128;
2243 sci_port
->overrun_bit
= 0;
2246 port
->fifosize
= 64;
2247 sci_port
->overrun_bit
= 9;
2251 port
->fifosize
= 16;
2252 if (p
->regtype
== SCIx_SH7705_SCIF_REGTYPE
) {
2253 sci_port
->overrun_bit
= 9;
2256 sci_port
->overrun_bit
= 0;
2262 sci_port
->overrun_bit
= 5;
2267 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2268 * match the SoC datasheet, this should be investigated. Let platform
2269 * data override the sampling rate for now.
2271 sci_port
->sampling_rate
= p
->sampling_rate
? p
->sampling_rate
2275 sci_port
->iclk
= clk_get(&dev
->dev
, "sci_ick");
2276 if (IS_ERR(sci_port
->iclk
)) {
2277 sci_port
->iclk
= clk_get(&dev
->dev
, "peripheral_clk");
2278 if (IS_ERR(sci_port
->iclk
)) {
2279 dev_err(&dev
->dev
, "can't get iclk\n");
2280 return PTR_ERR(sci_port
->iclk
);
2285 * The function clock is optional, ignore it if we can't
2288 sci_port
->fclk
= clk_get(&dev
->dev
, "sci_fck");
2289 if (IS_ERR(sci_port
->fclk
))
2290 sci_port
->fclk
= NULL
;
2292 port
->dev
= &dev
->dev
;
2294 pm_runtime_enable(&dev
->dev
);
2297 sci_port
->break_timer
.data
= (unsigned long)sci_port
;
2298 sci_port
->break_timer
.function
= sci_break_timer
;
2299 init_timer(&sci_port
->break_timer
);
2302 * Establish some sensible defaults for the error detection.
2304 sci_port
->error_mask
= (p
->type
== PORT_SCI
) ?
2305 SCI_DEFAULT_ERROR_MASK
: SCIF_DEFAULT_ERROR_MASK
;
2308 * Establish sensible defaults for the overrun detection, unless
2309 * the part has explicitly disabled support for it.
2313 * Make the error mask inclusive of overrun detection, if
2316 sci_port
->error_mask
|= 1 << sci_port
->overrun_bit
;
2318 port
->type
= p
->type
;
2319 port
->flags
= UPF_FIXED_PORT
| p
->flags
;
2320 port
->regshift
= p
->regshift
;
2323 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2324 * for the multi-IRQ ports, which is where we are primarily
2325 * concerned with the shutdown path synchronization.
2327 * For the muxed case there's nothing more to do.
2329 port
->irq
= sci_port
->irqs
[SCIx_RXI_IRQ
];
2332 port
->serial_in
= sci_serial_in
;
2333 port
->serial_out
= sci_serial_out
;
2335 if (p
->dma_slave_tx
> 0 && p
->dma_slave_rx
> 0)
2336 dev_dbg(port
->dev
, "DMA tx %d, rx %d\n",
2337 p
->dma_slave_tx
, p
->dma_slave_rx
);
2342 static void sci_cleanup_single(struct sci_port
*port
)
2344 clk_put(port
->iclk
);
2345 clk_put(port
->fclk
);
2347 pm_runtime_disable(port
->port
.dev
);
2350 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2351 static void serial_console_putchar(struct uart_port
*port
, int ch
)
2353 sci_poll_put_char(port
, ch
);
2357 * Print a string to the serial port trying not to disturb
2358 * any possible real use of the port...
2360 static void serial_console_write(struct console
*co
, const char *s
,
2363 struct sci_port
*sci_port
= &sci_ports
[co
->index
];
2364 struct uart_port
*port
= &sci_port
->port
;
2365 unsigned short bits
, ctrl
;
2366 unsigned long flags
;
2369 local_irq_save(flags
);
2372 else if (oops_in_progress
)
2373 locked
= spin_trylock(&port
->lock
);
2375 spin_lock(&port
->lock
);
2377 /* first save the SCSCR then disable the interrupts */
2378 ctrl
= serial_port_in(port
, SCSCR
);
2379 serial_port_out(port
, SCSCR
, sci_port
->cfg
->scscr
);
2381 uart_console_write(port
, s
, count
, serial_console_putchar
);
2383 /* wait until fifo is empty and last bit has been transmitted */
2384 bits
= SCxSR_TDxE(port
) | SCxSR_TEND(port
);
2385 while ((serial_port_in(port
, SCxSR
) & bits
) != bits
)
2388 /* restore the SCSCR */
2389 serial_port_out(port
, SCSCR
, ctrl
);
2392 spin_unlock(&port
->lock
);
2393 local_irq_restore(flags
);
2396 static int serial_console_setup(struct console
*co
, char *options
)
2398 struct sci_port
*sci_port
;
2399 struct uart_port
*port
;
2407 * Refuse to handle any bogus ports.
2409 if (co
->index
< 0 || co
->index
>= SCI_NPORTS
)
2412 sci_port
= &sci_ports
[co
->index
];
2413 port
= &sci_port
->port
;
2416 * Refuse to handle uninitialized ports.
2421 ret
= sci_remap_port(port
);
2422 if (unlikely(ret
!= 0))
2426 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2428 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2431 static struct console serial_console
= {
2433 .device
= uart_console_device
,
2434 .write
= serial_console_write
,
2435 .setup
= serial_console_setup
,
2436 .flags
= CON_PRINTBUFFER
,
2438 .data
= &sci_uart_driver
,
2441 static struct console early_serial_console
= {
2442 .name
= "early_ttySC",
2443 .write
= serial_console_write
,
2444 .flags
= CON_PRINTBUFFER
,
2448 static char early_serial_buf
[32];
2450 static int sci_probe_earlyprintk(struct platform_device
*pdev
)
2452 struct plat_sci_port
*cfg
= dev_get_platdata(&pdev
->dev
);
2454 if (early_serial_console
.data
)
2457 early_serial_console
.index
= pdev
->id
;
2459 sci_init_single(pdev
, &sci_ports
[pdev
->id
], pdev
->id
, cfg
, true);
2461 serial_console_setup(&early_serial_console
, early_serial_buf
);
2463 if (!strstr(early_serial_buf
, "keep"))
2464 early_serial_console
.flags
|= CON_BOOT
;
2466 register_console(&early_serial_console
);
2470 #define SCI_CONSOLE (&serial_console)
2473 static inline int sci_probe_earlyprintk(struct platform_device
*pdev
)
2478 #define SCI_CONSOLE NULL
2480 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2482 static const char banner
[] __initconst
= "SuperH (H)SCI(F) driver initialized";
2484 static struct uart_driver sci_uart_driver
= {
2485 .owner
= THIS_MODULE
,
2486 .driver_name
= "sci",
2487 .dev_name
= "ttySC",
2489 .minor
= SCI_MINOR_START
,
2491 .cons
= SCI_CONSOLE
,
2494 static int sci_remove(struct platform_device
*dev
)
2496 struct sci_port
*port
= platform_get_drvdata(dev
);
2498 cpufreq_unregister_notifier(&port
->freq_transition
,
2499 CPUFREQ_TRANSITION_NOTIFIER
);
2501 uart_remove_one_port(&sci_uart_driver
, &port
->port
);
2503 sci_cleanup_single(port
);
2508 struct sci_port_info
{
2510 unsigned int regtype
;
2513 static const struct of_device_id of_sci_match
[] = {
2515 .compatible
= "renesas,scif",
2516 .data
= &(const struct sci_port_info
) {
2518 .regtype
= SCIx_SH4_SCIF_REGTYPE
,
2521 .compatible
= "renesas,scifa",
2522 .data
= &(const struct sci_port_info
) {
2524 .regtype
= SCIx_SCIFA_REGTYPE
,
2527 .compatible
= "renesas,scifb",
2528 .data
= &(const struct sci_port_info
) {
2530 .regtype
= SCIx_SCIFB_REGTYPE
,
2533 .compatible
= "renesas,hscif",
2534 .data
= &(const struct sci_port_info
) {
2536 .regtype
= SCIx_HSCIF_REGTYPE
,
2542 MODULE_DEVICE_TABLE(of
, of_sci_match
);
2544 static struct plat_sci_port
*
2545 sci_parse_dt(struct platform_device
*pdev
, unsigned int *dev_id
)
2547 struct device_node
*np
= pdev
->dev
.of_node
;
2548 const struct of_device_id
*match
;
2549 const struct sci_port_info
*info
;
2550 struct plat_sci_port
*p
;
2553 if (!IS_ENABLED(CONFIG_OF
) || !np
)
2556 match
= of_match_node(of_sci_match
, pdev
->dev
.of_node
);
2562 p
= devm_kzalloc(&pdev
->dev
, sizeof(struct plat_sci_port
), GFP_KERNEL
);
2564 dev_err(&pdev
->dev
, "failed to allocate DT config data\n");
2568 /* Get the line number for the aliases node. */
2569 id
= of_alias_get_id(np
, "serial");
2571 dev_err(&pdev
->dev
, "failed to get alias id (%d)\n", id
);
2577 p
->flags
= UPF_IOREMAP
| UPF_BOOT_AUTOCONF
;
2578 p
->type
= info
->type
;
2579 p
->regtype
= info
->regtype
;
2580 p
->scscr
= SCSCR_RE
| SCSCR_TE
;
2585 static int sci_probe_single(struct platform_device
*dev
,
2587 struct plat_sci_port
*p
,
2588 struct sci_port
*sciport
)
2593 if (unlikely(index
>= SCI_NPORTS
)) {
2594 dev_notice(&dev
->dev
, "Attempting to register port %d when only %d are available\n",
2595 index
+1, SCI_NPORTS
);
2596 dev_notice(&dev
->dev
, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2600 ret
= sci_init_single(dev
, sciport
, index
, p
, false);
2604 ret
= uart_add_one_port(&sci_uart_driver
, &sciport
->port
);
2606 sci_cleanup_single(sciport
);
2613 static int sci_probe(struct platform_device
*dev
)
2615 struct plat_sci_port
*p
;
2616 struct sci_port
*sp
;
2617 unsigned int dev_id
;
2621 * If we've come here via earlyprintk initialization, head off to
2622 * the special early probe. We don't have sufficient device state
2623 * to make it beyond this yet.
2625 if (is_early_platform_device(dev
))
2626 return sci_probe_earlyprintk(dev
);
2628 if (dev
->dev
.of_node
) {
2629 p
= sci_parse_dt(dev
, &dev_id
);
2633 p
= dev
->dev
.platform_data
;
2635 dev_err(&dev
->dev
, "no platform data supplied\n");
2642 sp
= &sci_ports
[dev_id
];
2643 platform_set_drvdata(dev
, sp
);
2645 ret
= sci_probe_single(dev
, dev_id
, p
, sp
);
2649 sp
->freq_transition
.notifier_call
= sci_notifier
;
2651 ret
= cpufreq_register_notifier(&sp
->freq_transition
,
2652 CPUFREQ_TRANSITION_NOTIFIER
);
2653 if (unlikely(ret
< 0)) {
2654 uart_remove_one_port(&sci_uart_driver
, &sp
->port
);
2655 sci_cleanup_single(sp
);
2659 #ifdef CONFIG_SH_STANDARD_BIOS
2660 sh_bios_gdb_detach();
2666 static __maybe_unused
int sci_suspend(struct device
*dev
)
2668 struct sci_port
*sport
= dev_get_drvdata(dev
);
2671 uart_suspend_port(&sci_uart_driver
, &sport
->port
);
2676 static __maybe_unused
int sci_resume(struct device
*dev
)
2678 struct sci_port
*sport
= dev_get_drvdata(dev
);
2681 uart_resume_port(&sci_uart_driver
, &sport
->port
);
2686 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops
, sci_suspend
, sci_resume
);
2688 static struct platform_driver sci_driver
= {
2690 .remove
= sci_remove
,
2693 .pm
= &sci_dev_pm_ops
,
2694 .of_match_table
= of_match_ptr(of_sci_match
),
2698 static int __init
sci_init(void)
2702 pr_info("%s\n", banner
);
2704 ret
= uart_register_driver(&sci_uart_driver
);
2705 if (likely(ret
== 0)) {
2706 ret
= platform_driver_register(&sci_driver
);
2708 uart_unregister_driver(&sci_uart_driver
);
2714 static void __exit
sci_exit(void)
2716 platform_driver_unregister(&sci_driver
);
2717 uart_unregister_driver(&sci_uart_driver
);
2720 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2721 early_platform_init_buffer("earlyprintk", &sci_driver
,
2722 early_serial_buf
, ARRAY_SIZE(early_serial_buf
));
2724 module_init(sci_init
);
2725 module_exit(sci_exit
);
2727 MODULE_LICENSE("GPL");
2728 MODULE_ALIAS("platform:sh-sci");
2729 MODULE_AUTHOR("Paul Mundt");
2730 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");