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[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
90
91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
94
95 /* Interface clock */
96 struct clk *iclk;
97 /* Function clock */
98 struct clk *fclk;
99
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
102
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
105
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
120 #endif
121
122 struct notifier_block freq_transition;
123 };
124
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
137 {
138 return container_of(uart, struct sci_port, port);
139 }
140
141 struct plat_sci_reg {
142 u8 offset, size;
143 };
144
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147
148 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
171 [SCPCR] = sci_reg_invalid,
172 [SCPDR] = sci_reg_invalid,
173 },
174
175 /*
176 * Common definitions for legacy IrDA ports, dependent on
177 * regshift value.
178 */
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 [HSSRR] = sci_reg_invalid,
193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
195 },
196
197 /*
198 * Common SCIFA definitions.
199 */
200 [SCIx_SCIFA_REGTYPE] = {
201 [SCSMR] = { 0x00, 16 },
202 [SCBRR] = { 0x04, 8 },
203 [SCSCR] = { 0x08, 16 },
204 [SCxTDR] = { 0x20, 8 },
205 [SCxSR] = { 0x14, 16 },
206 [SCxRDR] = { 0x24, 8 },
207 [SCFCR] = { 0x18, 16 },
208 [SCFDR] = { 0x1c, 16 },
209 [SCTFDR] = sci_reg_invalid,
210 [SCRFDR] = sci_reg_invalid,
211 [SCSPTR] = sci_reg_invalid,
212 [SCLSR] = sci_reg_invalid,
213 [HSSRR] = sci_reg_invalid,
214 [SCPCR] = { 0x30, 16 },
215 [SCPDR] = { 0x34, 16 },
216 },
217
218 /*
219 * Common SCIFB definitions.
220 */
221 [SCIx_SCIFB_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x40, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x60, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = sci_reg_invalid,
230 [SCTFDR] = { 0x38, 16 },
231 [SCRFDR] = { 0x3c, 16 },
232 [SCSPTR] = sci_reg_invalid,
233 [SCLSR] = sci_reg_invalid,
234 [HSSRR] = sci_reg_invalid,
235 [SCPCR] = { 0x30, 16 },
236 [SCPDR] = { 0x34, 16 },
237 },
238
239 /*
240 * Common SH-2(A) SCIF definitions for ports with FIFO data
241 * count registers.
242 */
243 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x0c, 8 },
248 [SCxSR] = { 0x10, 16 },
249 [SCxRDR] = { 0x14, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = { 0x1c, 16 },
252 [SCTFDR] = sci_reg_invalid,
253 [SCRFDR] = sci_reg_invalid,
254 [SCSPTR] = { 0x20, 16 },
255 [SCLSR] = { 0x24, 16 },
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = sci_reg_invalid,
258 [SCPDR] = sci_reg_invalid,
259 },
260
261 /*
262 * Common SH-3 SCIF definitions.
263 */
264 [SCIx_SH3_SCIF_REGTYPE] = {
265 [SCSMR] = { 0x00, 8 },
266 [SCBRR] = { 0x02, 8 },
267 [SCSCR] = { 0x04, 8 },
268 [SCxTDR] = { 0x06, 8 },
269 [SCxSR] = { 0x08, 16 },
270 [SCxRDR] = { 0x0a, 8 },
271 [SCFCR] = { 0x0c, 8 },
272 [SCFDR] = { 0x0e, 16 },
273 [SCTFDR] = sci_reg_invalid,
274 [SCRFDR] = sci_reg_invalid,
275 [SCSPTR] = sci_reg_invalid,
276 [SCLSR] = sci_reg_invalid,
277 [HSSRR] = sci_reg_invalid,
278 [SCPCR] = sci_reg_invalid,
279 [SCPDR] = sci_reg_invalid,
280 },
281
282 /*
283 * Common SH-4(A) SCIF(B) definitions.
284 */
285 [SCIx_SH4_SCIF_REGTYPE] = {
286 [SCSMR] = { 0x00, 16 },
287 [SCBRR] = { 0x04, 8 },
288 [SCSCR] = { 0x08, 16 },
289 [SCxTDR] = { 0x0c, 8 },
290 [SCxSR] = { 0x10, 16 },
291 [SCxRDR] = { 0x14, 8 },
292 [SCFCR] = { 0x18, 16 },
293 [SCFDR] = { 0x1c, 16 },
294 [SCTFDR] = sci_reg_invalid,
295 [SCRFDR] = sci_reg_invalid,
296 [SCSPTR] = { 0x20, 16 },
297 [SCLSR] = { 0x24, 16 },
298 [HSSRR] = sci_reg_invalid,
299 [SCPCR] = sci_reg_invalid,
300 [SCPDR] = sci_reg_invalid,
301 },
302
303 /*
304 * Common HSCIF definitions.
305 */
306 [SCIx_HSCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x0c, 8 },
311 [SCxSR] = { 0x10, 16 },
312 [SCxRDR] = { 0x14, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = { 0x20, 16 },
318 [SCLSR] = { 0x24, 16 },
319 [HSSRR] = { 0x40, 16 },
320 [SCPCR] = sci_reg_invalid,
321 [SCPDR] = sci_reg_invalid,
322 },
323
324 /*
325 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
326 * register.
327 */
328 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
329 [SCSMR] = { 0x00, 16 },
330 [SCBRR] = { 0x04, 8 },
331 [SCSCR] = { 0x08, 16 },
332 [SCxTDR] = { 0x0c, 8 },
333 [SCxSR] = { 0x10, 16 },
334 [SCxRDR] = { 0x14, 8 },
335 [SCFCR] = { 0x18, 16 },
336 [SCFDR] = { 0x1c, 16 },
337 [SCTFDR] = sci_reg_invalid,
338 [SCRFDR] = sci_reg_invalid,
339 [SCSPTR] = sci_reg_invalid,
340 [SCLSR] = { 0x24, 16 },
341 [HSSRR] = sci_reg_invalid,
342 [SCPCR] = sci_reg_invalid,
343 [SCPDR] = sci_reg_invalid,
344 },
345
346 /*
347 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
348 * count registers.
349 */
350 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
351 [SCSMR] = { 0x00, 16 },
352 [SCBRR] = { 0x04, 8 },
353 [SCSCR] = { 0x08, 16 },
354 [SCxTDR] = { 0x0c, 8 },
355 [SCxSR] = { 0x10, 16 },
356 [SCxRDR] = { 0x14, 8 },
357 [SCFCR] = { 0x18, 16 },
358 [SCFDR] = { 0x1c, 16 },
359 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
360 [SCRFDR] = { 0x20, 16 },
361 [SCSPTR] = { 0x24, 16 },
362 [SCLSR] = { 0x28, 16 },
363 [HSSRR] = sci_reg_invalid,
364 [SCPCR] = sci_reg_invalid,
365 [SCPDR] = sci_reg_invalid,
366 },
367
368 /*
369 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
370 * registers.
371 */
372 [SCIx_SH7705_SCIF_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x20, 8 },
377 [SCxSR] = { 0x14, 16 },
378 [SCxRDR] = { 0x24, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCTFDR] = sci_reg_invalid,
382 [SCRFDR] = sci_reg_invalid,
383 [SCSPTR] = sci_reg_invalid,
384 [SCLSR] = sci_reg_invalid,
385 [HSSRR] = sci_reg_invalid,
386 [SCPCR] = sci_reg_invalid,
387 [SCPDR] = sci_reg_invalid,
388 },
389 };
390
391 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
392
393 /*
394 * The "offset" here is rather misleading, in that it refers to an enum
395 * value relative to the port mapping rather than the fixed offset
396 * itself, which needs to be manually retrieved from the platform's
397 * register map for the given port.
398 */
399 static unsigned int sci_serial_in(struct uart_port *p, int offset)
400 {
401 const struct plat_sci_reg *reg = sci_getreg(p, offset);
402
403 if (reg->size == 8)
404 return ioread8(p->membase + (reg->offset << p->regshift));
405 else if (reg->size == 16)
406 return ioread16(p->membase + (reg->offset << p->regshift));
407 else
408 WARN(1, "Invalid register access\n");
409
410 return 0;
411 }
412
413 static void sci_serial_out(struct uart_port *p, int offset, int value)
414 {
415 const struct plat_sci_reg *reg = sci_getreg(p, offset);
416
417 if (reg->size == 8)
418 iowrite8(value, p->membase + (reg->offset << p->regshift));
419 else if (reg->size == 16)
420 iowrite16(value, p->membase + (reg->offset << p->regshift));
421 else
422 WARN(1, "Invalid register access\n");
423 }
424
425 static int sci_probe_regmap(struct plat_sci_port *cfg)
426 {
427 switch (cfg->type) {
428 case PORT_SCI:
429 cfg->regtype = SCIx_SCI_REGTYPE;
430 break;
431 case PORT_IRDA:
432 cfg->regtype = SCIx_IRDA_REGTYPE;
433 break;
434 case PORT_SCIFA:
435 cfg->regtype = SCIx_SCIFA_REGTYPE;
436 break;
437 case PORT_SCIFB:
438 cfg->regtype = SCIx_SCIFB_REGTYPE;
439 break;
440 case PORT_SCIF:
441 /*
442 * The SH-4 is a bit of a misnomer here, although that's
443 * where this particular port layout originated. This
444 * configuration (or some slight variation thereof)
445 * remains the dominant model for all SCIFs.
446 */
447 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
448 break;
449 case PORT_HSCIF:
450 cfg->regtype = SCIx_HSCIF_REGTYPE;
451 break;
452 default:
453 pr_err("Can't probe register map for given port\n");
454 return -EINVAL;
455 }
456
457 return 0;
458 }
459
460 static void sci_port_enable(struct sci_port *sci_port)
461 {
462 if (!sci_port->port.dev)
463 return;
464
465 pm_runtime_get_sync(sci_port->port.dev);
466
467 clk_prepare_enable(sci_port->iclk);
468 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
469 clk_prepare_enable(sci_port->fclk);
470 }
471
472 static void sci_port_disable(struct sci_port *sci_port)
473 {
474 if (!sci_port->port.dev)
475 return;
476
477 /* Cancel the break timer to ensure that the timer handler will not try
478 * to access the hardware with clocks and power disabled. Reset the
479 * break flag to make the break debouncing state machine ready for the
480 * next break.
481 */
482 del_timer_sync(&sci_port->break_timer);
483 sci_port->break_flag = 0;
484
485 clk_disable_unprepare(sci_port->fclk);
486 clk_disable_unprepare(sci_port->iclk);
487
488 pm_runtime_put_sync(sci_port->port.dev);
489 }
490
491 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
492 {
493 if (port->type == PORT_SCI) {
494 /* Just store the mask */
495 serial_port_out(port, SCxSR, mask);
496 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
497 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
498 /* Only clear the status bits we want to clear */
499 serial_port_out(port, SCxSR,
500 serial_port_in(port, SCxSR) & mask);
501 } else {
502 /* Store the mask, clear parity/framing errors */
503 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
504 }
505 }
506
507 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
508
509 #ifdef CONFIG_CONSOLE_POLL
510 static int sci_poll_get_char(struct uart_port *port)
511 {
512 unsigned short status;
513 int c;
514
515 do {
516 status = serial_port_in(port, SCxSR);
517 if (status & SCxSR_ERRORS(port)) {
518 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
519 continue;
520 }
521 break;
522 } while (1);
523
524 if (!(status & SCxSR_RDxF(port)))
525 return NO_POLL_CHAR;
526
527 c = serial_port_in(port, SCxRDR);
528
529 /* Dummy read */
530 serial_port_in(port, SCxSR);
531 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
532
533 return c;
534 }
535 #endif
536
537 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
538 {
539 unsigned short status;
540
541 do {
542 status = serial_port_in(port, SCxSR);
543 } while (!(status & SCxSR_TDxE(port)));
544
545 serial_port_out(port, SCxTDR, c);
546 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
547 }
548 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
549
550 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
551 {
552 struct sci_port *s = to_sci_port(port);
553 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
554
555 /*
556 * Use port-specific handler if provided.
557 */
558 if (s->cfg->ops && s->cfg->ops->init_pins) {
559 s->cfg->ops->init_pins(port, cflag);
560 return;
561 }
562
563 /*
564 * For the generic path SCSPTR is necessary. Bail out if that's
565 * unavailable, too.
566 */
567 if (!reg->size)
568 return;
569
570 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
571 ((!(cflag & CRTSCTS)))) {
572 unsigned short status;
573
574 status = serial_port_in(port, SCSPTR);
575 status &= ~SCSPTR_CTSIO;
576 status |= SCSPTR_RTSIO;
577 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
578 }
579 }
580
581 static int sci_txfill(struct uart_port *port)
582 {
583 const struct plat_sci_reg *reg;
584
585 reg = sci_getreg(port, SCTFDR);
586 if (reg->size)
587 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
588
589 reg = sci_getreg(port, SCFDR);
590 if (reg->size)
591 return serial_port_in(port, SCFDR) >> 8;
592
593 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
594 }
595
596 static int sci_txroom(struct uart_port *port)
597 {
598 return port->fifosize - sci_txfill(port);
599 }
600
601 static int sci_rxfill(struct uart_port *port)
602 {
603 const struct plat_sci_reg *reg;
604
605 reg = sci_getreg(port, SCRFDR);
606 if (reg->size)
607 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
608
609 reg = sci_getreg(port, SCFDR);
610 if (reg->size)
611 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
612
613 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
614 }
615
616 /*
617 * SCI helper for checking the state of the muxed port/RXD pins.
618 */
619 static inline int sci_rxd_in(struct uart_port *port)
620 {
621 struct sci_port *s = to_sci_port(port);
622
623 if (s->cfg->port_reg <= 0)
624 return 1;
625
626 /* Cast for ARM damage */
627 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
628 }
629
630 /* ********************************************************************** *
631 * the interrupt related routines *
632 * ********************************************************************** */
633
634 static void sci_transmit_chars(struct uart_port *port)
635 {
636 struct circ_buf *xmit = &port->state->xmit;
637 unsigned int stopped = uart_tx_stopped(port);
638 unsigned short status;
639 unsigned short ctrl;
640 int count;
641
642 status = serial_port_in(port, SCxSR);
643 if (!(status & SCxSR_TDxE(port))) {
644 ctrl = serial_port_in(port, SCSCR);
645 if (uart_circ_empty(xmit))
646 ctrl &= ~SCSCR_TIE;
647 else
648 ctrl |= SCSCR_TIE;
649 serial_port_out(port, SCSCR, ctrl);
650 return;
651 }
652
653 count = sci_txroom(port);
654
655 do {
656 unsigned char c;
657
658 if (port->x_char) {
659 c = port->x_char;
660 port->x_char = 0;
661 } else if (!uart_circ_empty(xmit) && !stopped) {
662 c = xmit->buf[xmit->tail];
663 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
664 } else {
665 break;
666 }
667
668 serial_port_out(port, SCxTDR, c);
669
670 port->icount.tx++;
671 } while (--count > 0);
672
673 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
674
675 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
676 uart_write_wakeup(port);
677 if (uart_circ_empty(xmit)) {
678 sci_stop_tx(port);
679 } else {
680 ctrl = serial_port_in(port, SCSCR);
681
682 if (port->type != PORT_SCI) {
683 serial_port_in(port, SCxSR); /* Dummy read */
684 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
685 }
686
687 ctrl |= SCSCR_TIE;
688 serial_port_out(port, SCSCR, ctrl);
689 }
690 }
691
692 /* On SH3, SCIF may read end-of-break as a space->mark char */
693 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
694
695 static void sci_receive_chars(struct uart_port *port)
696 {
697 struct sci_port *sci_port = to_sci_port(port);
698 struct tty_port *tport = &port->state->port;
699 int i, count, copied = 0;
700 unsigned short status;
701 unsigned char flag;
702
703 status = serial_port_in(port, SCxSR);
704 if (!(status & SCxSR_RDxF(port)))
705 return;
706
707 while (1) {
708 /* Don't copy more bytes than there is room for in the buffer */
709 count = tty_buffer_request_room(tport, sci_rxfill(port));
710
711 /* If for any reason we can't copy more data, we're done! */
712 if (count == 0)
713 break;
714
715 if (port->type == PORT_SCI) {
716 char c = serial_port_in(port, SCxRDR);
717 if (uart_handle_sysrq_char(port, c) ||
718 sci_port->break_flag)
719 count = 0;
720 else
721 tty_insert_flip_char(tport, c, TTY_NORMAL);
722 } else {
723 for (i = 0; i < count; i++) {
724 char c = serial_port_in(port, SCxRDR);
725
726 status = serial_port_in(port, SCxSR);
727 #if defined(CONFIG_CPU_SH3)
728 /* Skip "chars" during break */
729 if (sci_port->break_flag) {
730 if ((c == 0) &&
731 (status & SCxSR_FER(port))) {
732 count--; i--;
733 continue;
734 }
735
736 /* Nonzero => end-of-break */
737 dev_dbg(port->dev, "debounce<%02x>\n", c);
738 sci_port->break_flag = 0;
739
740 if (STEPFN(c)) {
741 count--; i--;
742 continue;
743 }
744 }
745 #endif /* CONFIG_CPU_SH3 */
746 if (uart_handle_sysrq_char(port, c)) {
747 count--; i--;
748 continue;
749 }
750
751 /* Store data and status */
752 if (status & SCxSR_FER(port)) {
753 flag = TTY_FRAME;
754 port->icount.frame++;
755 dev_notice(port->dev, "frame error\n");
756 } else if (status & SCxSR_PER(port)) {
757 flag = TTY_PARITY;
758 port->icount.parity++;
759 dev_notice(port->dev, "parity error\n");
760 } else
761 flag = TTY_NORMAL;
762
763 tty_insert_flip_char(tport, c, flag);
764 }
765 }
766
767 serial_port_in(port, SCxSR); /* dummy read */
768 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
769
770 copied += count;
771 port->icount.rx += count;
772 }
773
774 if (copied) {
775 /* Tell the rest of the system the news. New characters! */
776 tty_flip_buffer_push(tport);
777 } else {
778 serial_port_in(port, SCxSR); /* dummy read */
779 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
780 }
781 }
782
783 #define SCI_BREAK_JIFFIES (HZ/20)
784
785 /*
786 * The sci generates interrupts during the break,
787 * 1 per millisecond or so during the break period, for 9600 baud.
788 * So dont bother disabling interrupts.
789 * But dont want more than 1 break event.
790 * Use a kernel timer to periodically poll the rx line until
791 * the break is finished.
792 */
793 static inline void sci_schedule_break_timer(struct sci_port *port)
794 {
795 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
796 }
797
798 /* Ensure that two consecutive samples find the break over. */
799 static void sci_break_timer(unsigned long data)
800 {
801 struct sci_port *port = (struct sci_port *)data;
802
803 if (sci_rxd_in(&port->port) == 0) {
804 port->break_flag = 1;
805 sci_schedule_break_timer(port);
806 } else if (port->break_flag == 1) {
807 /* break is over. */
808 port->break_flag = 2;
809 sci_schedule_break_timer(port);
810 } else
811 port->break_flag = 0;
812 }
813
814 static int sci_handle_errors(struct uart_port *port)
815 {
816 int copied = 0;
817 unsigned short status = serial_port_in(port, SCxSR);
818 struct tty_port *tport = &port->state->port;
819 struct sci_port *s = to_sci_port(port);
820
821 /* Handle overruns */
822 if (status & s->overrun_mask) {
823 port->icount.overrun++;
824
825 /* overrun error */
826 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
827 copied++;
828
829 dev_notice(port->dev, "overrun error\n");
830 }
831
832 if (status & SCxSR_FER(port)) {
833 if (sci_rxd_in(port) == 0) {
834 /* Notify of BREAK */
835 struct sci_port *sci_port = to_sci_port(port);
836
837 if (!sci_port->break_flag) {
838 port->icount.brk++;
839
840 sci_port->break_flag = 1;
841 sci_schedule_break_timer(sci_port);
842
843 /* Do sysrq handling. */
844 if (uart_handle_break(port))
845 return 0;
846
847 dev_dbg(port->dev, "BREAK detected\n");
848
849 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
850 copied++;
851 }
852
853 } else {
854 /* frame error */
855 port->icount.frame++;
856
857 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
858 copied++;
859
860 dev_notice(port->dev, "frame error\n");
861 }
862 }
863
864 if (status & SCxSR_PER(port)) {
865 /* parity error */
866 port->icount.parity++;
867
868 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
869 copied++;
870
871 dev_notice(port->dev, "parity error\n");
872 }
873
874 if (copied)
875 tty_flip_buffer_push(tport);
876
877 return copied;
878 }
879
880 static int sci_handle_fifo_overrun(struct uart_port *port)
881 {
882 struct tty_port *tport = &port->state->port;
883 struct sci_port *s = to_sci_port(port);
884 const struct plat_sci_reg *reg;
885 int copied = 0;
886 u16 status;
887
888 reg = sci_getreg(port, s->overrun_reg);
889 if (!reg->size)
890 return 0;
891
892 status = serial_port_in(port, s->overrun_reg);
893 if (status & s->overrun_mask) {
894 status &= ~s->overrun_mask;
895 serial_port_out(port, s->overrun_reg, status);
896
897 port->icount.overrun++;
898
899 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
900 tty_flip_buffer_push(tport);
901
902 dev_dbg(port->dev, "overrun error\n");
903 copied++;
904 }
905
906 return copied;
907 }
908
909 static int sci_handle_breaks(struct uart_port *port)
910 {
911 int copied = 0;
912 unsigned short status = serial_port_in(port, SCxSR);
913 struct tty_port *tport = &port->state->port;
914 struct sci_port *s = to_sci_port(port);
915
916 if (uart_handle_break(port))
917 return 0;
918
919 if (!s->break_flag && status & SCxSR_BRK(port)) {
920 #if defined(CONFIG_CPU_SH3)
921 /* Debounce break */
922 s->break_flag = 1;
923 #endif
924
925 port->icount.brk++;
926
927 /* Notify of BREAK */
928 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
929 copied++;
930
931 dev_dbg(port->dev, "BREAK detected\n");
932 }
933
934 if (copied)
935 tty_flip_buffer_push(tport);
936
937 copied += sci_handle_fifo_overrun(port);
938
939 return copied;
940 }
941
942 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
943 {
944 #ifdef CONFIG_SERIAL_SH_SCI_DMA
945 struct uart_port *port = ptr;
946 struct sci_port *s = to_sci_port(port);
947
948 if (s->chan_rx) {
949 u16 scr = serial_port_in(port, SCSCR);
950 u16 ssr = serial_port_in(port, SCxSR);
951
952 /* Disable future Rx interrupts */
953 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
954 disable_irq_nosync(irq);
955 scr |= SCSCR_RDRQE;
956 } else {
957 scr &= ~SCSCR_RIE;
958 }
959 serial_port_out(port, SCSCR, scr);
960 /* Clear current interrupt */
961 serial_port_out(port, SCxSR,
962 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
963 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
964 jiffies, s->rx_timeout);
965 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
966
967 return IRQ_HANDLED;
968 }
969 #endif
970
971 /* I think sci_receive_chars has to be called irrespective
972 * of whether the I_IXOFF is set, otherwise, how is the interrupt
973 * to be disabled?
974 */
975 sci_receive_chars(ptr);
976
977 return IRQ_HANDLED;
978 }
979
980 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
981 {
982 struct uart_port *port = ptr;
983 unsigned long flags;
984
985 spin_lock_irqsave(&port->lock, flags);
986 sci_transmit_chars(port);
987 spin_unlock_irqrestore(&port->lock, flags);
988
989 return IRQ_HANDLED;
990 }
991
992 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
993 {
994 struct uart_port *port = ptr;
995
996 /* Handle errors */
997 if (port->type == PORT_SCI) {
998 if (sci_handle_errors(port)) {
999 /* discard character in rx buffer */
1000 serial_port_in(port, SCxSR);
1001 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1002 }
1003 } else {
1004 sci_handle_fifo_overrun(port);
1005 sci_rx_interrupt(irq, ptr);
1006 }
1007
1008 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1009
1010 /* Kick the transmission */
1011 sci_tx_interrupt(irq, ptr);
1012
1013 return IRQ_HANDLED;
1014 }
1015
1016 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1017 {
1018 struct uart_port *port = ptr;
1019
1020 /* Handle BREAKs */
1021 sci_handle_breaks(port);
1022 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1023
1024 return IRQ_HANDLED;
1025 }
1026
1027 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1028 {
1029 /*
1030 * Not all ports (such as SCIFA) will support REIE. Rather than
1031 * special-casing the port type, we check the port initialization
1032 * IRQ enable mask to see whether the IRQ is desired at all. If
1033 * it's unset, it's logically inferred that there's no point in
1034 * testing for it.
1035 */
1036 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1037 }
1038
1039 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1040 {
1041 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1042 struct uart_port *port = ptr;
1043 struct sci_port *s = to_sci_port(port);
1044 irqreturn_t ret = IRQ_NONE;
1045
1046 ssr_status = serial_port_in(port, SCxSR);
1047 scr_status = serial_port_in(port, SCSCR);
1048 if (s->overrun_reg == SCxSR)
1049 orer_status = ssr_status;
1050 else {
1051 if (sci_getreg(port, s->overrun_reg)->size)
1052 orer_status = serial_port_in(port, s->overrun_reg);
1053 }
1054
1055 err_enabled = scr_status & port_rx_irq_mask(port);
1056
1057 /* Tx Interrupt */
1058 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1059 !s->chan_tx)
1060 ret = sci_tx_interrupt(irq, ptr);
1061
1062 /*
1063 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1064 * DR flags
1065 */
1066 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1067 (scr_status & SCSCR_RIE))
1068 ret = sci_rx_interrupt(irq, ptr);
1069
1070 /* Error Interrupt */
1071 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1072 ret = sci_er_interrupt(irq, ptr);
1073
1074 /* Break Interrupt */
1075 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1076 ret = sci_br_interrupt(irq, ptr);
1077
1078 /* Overrun Interrupt */
1079 if (orer_status & s->overrun_mask) {
1080 sci_handle_fifo_overrun(port);
1081 ret = IRQ_HANDLED;
1082 }
1083
1084 return ret;
1085 }
1086
1087 /*
1088 * Here we define a transition notifier so that we can update all of our
1089 * ports' baud rate when the peripheral clock changes.
1090 */
1091 static int sci_notifier(struct notifier_block *self,
1092 unsigned long phase, void *p)
1093 {
1094 struct sci_port *sci_port;
1095 unsigned long flags;
1096
1097 sci_port = container_of(self, struct sci_port, freq_transition);
1098
1099 if (phase == CPUFREQ_POSTCHANGE) {
1100 struct uart_port *port = &sci_port->port;
1101
1102 spin_lock_irqsave(&port->lock, flags);
1103 port->uartclk = clk_get_rate(sci_port->iclk);
1104 spin_unlock_irqrestore(&port->lock, flags);
1105 }
1106
1107 return NOTIFY_OK;
1108 }
1109
1110 static const struct sci_irq_desc {
1111 const char *desc;
1112 irq_handler_t handler;
1113 } sci_irq_desc[] = {
1114 /*
1115 * Split out handlers, the default case.
1116 */
1117 [SCIx_ERI_IRQ] = {
1118 .desc = "rx err",
1119 .handler = sci_er_interrupt,
1120 },
1121
1122 [SCIx_RXI_IRQ] = {
1123 .desc = "rx full",
1124 .handler = sci_rx_interrupt,
1125 },
1126
1127 [SCIx_TXI_IRQ] = {
1128 .desc = "tx empty",
1129 .handler = sci_tx_interrupt,
1130 },
1131
1132 [SCIx_BRI_IRQ] = {
1133 .desc = "break",
1134 .handler = sci_br_interrupt,
1135 },
1136
1137 /*
1138 * Special muxed handler.
1139 */
1140 [SCIx_MUX_IRQ] = {
1141 .desc = "mux",
1142 .handler = sci_mpxed_interrupt,
1143 },
1144 };
1145
1146 static int sci_request_irq(struct sci_port *port)
1147 {
1148 struct uart_port *up = &port->port;
1149 int i, j, ret = 0;
1150
1151 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1152 const struct sci_irq_desc *desc;
1153 int irq;
1154
1155 if (SCIx_IRQ_IS_MUXED(port)) {
1156 i = SCIx_MUX_IRQ;
1157 irq = up->irq;
1158 } else {
1159 irq = port->irqs[i];
1160
1161 /*
1162 * Certain port types won't support all of the
1163 * available interrupt sources.
1164 */
1165 if (unlikely(irq < 0))
1166 continue;
1167 }
1168
1169 desc = sci_irq_desc + i;
1170 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1171 dev_name(up->dev), desc->desc);
1172 if (!port->irqstr[j])
1173 goto out_nomem;
1174
1175 ret = request_irq(irq, desc->handler, up->irqflags,
1176 port->irqstr[j], port);
1177 if (unlikely(ret)) {
1178 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1179 goto out_noirq;
1180 }
1181 }
1182
1183 return 0;
1184
1185 out_noirq:
1186 while (--i >= 0)
1187 free_irq(port->irqs[i], port);
1188
1189 out_nomem:
1190 while (--j >= 0)
1191 kfree(port->irqstr[j]);
1192
1193 return ret;
1194 }
1195
1196 static void sci_free_irq(struct sci_port *port)
1197 {
1198 int i;
1199
1200 /*
1201 * Intentionally in reverse order so we iterate over the muxed
1202 * IRQ first.
1203 */
1204 for (i = 0; i < SCIx_NR_IRQS; i++) {
1205 int irq = port->irqs[i];
1206
1207 /*
1208 * Certain port types won't support all of the available
1209 * interrupt sources.
1210 */
1211 if (unlikely(irq < 0))
1212 continue;
1213
1214 free_irq(port->irqs[i], port);
1215 kfree(port->irqstr[i]);
1216
1217 if (SCIx_IRQ_IS_MUXED(port)) {
1218 /* If there's only one IRQ, we're done. */
1219 return;
1220 }
1221 }
1222 }
1223
1224 static unsigned int sci_tx_empty(struct uart_port *port)
1225 {
1226 unsigned short status = serial_port_in(port, SCxSR);
1227 unsigned short in_tx_fifo = sci_txfill(port);
1228
1229 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1230 }
1231
1232 /*
1233 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1234 * CTS/RTS is supported in hardware by at least one port and controlled
1235 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1236 * handled via the ->init_pins() op, which is a bit of a one-way street,
1237 * lacking any ability to defer pin control -- this will later be
1238 * converted over to the GPIO framework).
1239 *
1240 * Other modes (such as loopback) are supported generically on certain
1241 * port types, but not others. For these it's sufficient to test for the
1242 * existence of the support register and simply ignore the port type.
1243 */
1244 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1245 {
1246 if (mctrl & TIOCM_LOOP) {
1247 const struct plat_sci_reg *reg;
1248
1249 /*
1250 * Standard loopback mode for SCFCR ports.
1251 */
1252 reg = sci_getreg(port, SCFCR);
1253 if (reg->size)
1254 serial_port_out(port, SCFCR,
1255 serial_port_in(port, SCFCR) |
1256 SCFCR_LOOP);
1257 }
1258 }
1259
1260 static unsigned int sci_get_mctrl(struct uart_port *port)
1261 {
1262 /*
1263 * CTS/RTS is handled in hardware when supported, while nothing
1264 * else is wired up. Keep it simple and simply assert DSR/CAR.
1265 */
1266 return TIOCM_DSR | TIOCM_CAR;
1267 }
1268
1269 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1270 static void sci_dma_tx_complete(void *arg)
1271 {
1272 struct sci_port *s = arg;
1273 struct uart_port *port = &s->port;
1274 struct circ_buf *xmit = &port->state->xmit;
1275 unsigned long flags;
1276
1277 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1278
1279 spin_lock_irqsave(&port->lock, flags);
1280
1281 xmit->tail += s->tx_dma_len;
1282 xmit->tail &= UART_XMIT_SIZE - 1;
1283
1284 port->icount.tx += s->tx_dma_len;
1285
1286 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1287 uart_write_wakeup(port);
1288
1289 if (!uart_circ_empty(xmit)) {
1290 s->cookie_tx = 0;
1291 schedule_work(&s->work_tx);
1292 } else {
1293 s->cookie_tx = -EINVAL;
1294 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1295 u16 ctrl = serial_port_in(port, SCSCR);
1296 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1297 }
1298 }
1299
1300 spin_unlock_irqrestore(&port->lock, flags);
1301 }
1302
1303 /* Locking: called with port lock held */
1304 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1305 {
1306 struct uart_port *port = &s->port;
1307 struct tty_port *tport = &port->state->port;
1308 int i, active, room;
1309
1310 room = tty_buffer_request_room(tport, count);
1311
1312 if (s->active_rx == s->cookie_rx[0]) {
1313 active = 0;
1314 } else if (s->active_rx == s->cookie_rx[1]) {
1315 active = 1;
1316 } else {
1317 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1318 s->active_rx);
1319 return 0;
1320 }
1321
1322 if (room < count)
1323 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1324 count - room);
1325 if (!room)
1326 return room;
1327
1328 for (i = 0; i < room; i++)
1329 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1330 TTY_NORMAL);
1331
1332 port->icount.rx += room;
1333
1334 return room;
1335 }
1336
1337 static void sci_dma_rx_complete(void *arg)
1338 {
1339 struct sci_port *s = arg;
1340 struct uart_port *port = &s->port;
1341 unsigned long flags;
1342 int count;
1343
1344 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1345 s->active_rx);
1346
1347 spin_lock_irqsave(&port->lock, flags);
1348
1349 count = sci_dma_rx_push(s, s->buf_len_rx);
1350
1351 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1352
1353 spin_unlock_irqrestore(&port->lock, flags);
1354
1355 if (count)
1356 tty_flip_buffer_push(&port->state->port);
1357
1358 schedule_work(&s->work_rx);
1359 }
1360
1361 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1362 {
1363 struct dma_chan *chan = s->chan_rx;
1364 struct uart_port *port = &s->port;
1365
1366 s->chan_rx = NULL;
1367 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1368 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2,
1369 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1370 dma_release_channel(chan);
1371 if (enable_pio)
1372 sci_start_rx(port);
1373 }
1374
1375 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1376 {
1377 struct dma_chan *chan = s->chan_tx;
1378 struct uart_port *port = &s->port;
1379
1380 s->chan_tx = NULL;
1381 s->cookie_tx = -EINVAL;
1382 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1383 DMA_TO_DEVICE);
1384 dma_release_channel(chan);
1385 if (enable_pio)
1386 sci_start_tx(port);
1387 }
1388
1389 static void sci_submit_rx(struct sci_port *s)
1390 {
1391 struct dma_chan *chan = s->chan_rx;
1392 int i;
1393
1394 for (i = 0; i < 2; i++) {
1395 struct scatterlist *sg = &s->sg_rx[i];
1396 struct dma_async_tx_descriptor *desc;
1397
1398 desc = dmaengine_prep_slave_sg(chan,
1399 sg, 1, DMA_DEV_TO_MEM,
1400 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1401 if (!desc)
1402 goto fail;
1403
1404 desc->callback = sci_dma_rx_complete;
1405 desc->callback_param = s;
1406 s->cookie_rx[i] = dmaengine_submit(desc);
1407 if (dma_submit_error(s->cookie_rx[i]))
1408 goto fail;
1409
1410 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1411 s->cookie_rx[i], i);
1412 }
1413
1414 s->active_rx = s->cookie_rx[0];
1415
1416 dma_async_issue_pending(chan);
1417 return;
1418
1419 fail:
1420 if (i)
1421 dmaengine_terminate_all(chan);
1422 for (i = 0; i < 2; i++)
1423 s->cookie_rx[i] = -EINVAL;
1424 s->active_rx = -EINVAL;
1425 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1426 sci_rx_dma_release(s, true);
1427 }
1428
1429 static void work_fn_rx(struct work_struct *work)
1430 {
1431 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1432 struct uart_port *port = &s->port;
1433 struct dma_async_tx_descriptor *desc;
1434 struct dma_tx_state state;
1435 enum dma_status status;
1436 unsigned long flags;
1437 int new;
1438
1439 spin_lock_irqsave(&port->lock, flags);
1440 if (s->active_rx == s->cookie_rx[0]) {
1441 new = 0;
1442 } else if (s->active_rx == s->cookie_rx[1]) {
1443 new = 1;
1444 } else {
1445 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1446 s->active_rx);
1447 goto out;
1448 }
1449
1450 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1451 if (status != DMA_COMPLETE) {
1452 /* Handle incomplete DMA receive */
1453 struct dma_chan *chan = s->chan_rx;
1454 unsigned int read;
1455 int count;
1456
1457 dmaengine_terminate_all(chan);
1458 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1459 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1460 s->active_rx);
1461
1462 count = sci_dma_rx_push(s, read);
1463
1464 if (count)
1465 tty_flip_buffer_push(&port->state->port);
1466
1467 sci_submit_rx(s);
1468
1469 goto out;
1470 }
1471
1472 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1473 DMA_DEV_TO_MEM,
1474 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1475 if (!desc)
1476 goto fail;
1477
1478 desc->callback = sci_dma_rx_complete;
1479 desc->callback_param = s;
1480 s->cookie_rx[new] = dmaengine_submit(desc);
1481 if (dma_submit_error(s->cookie_rx[new]))
1482 goto fail;
1483
1484 s->active_rx = s->cookie_rx[!new];
1485
1486 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1487 __func__, s->cookie_rx[new], new, s->active_rx);
1488 out:
1489 spin_unlock_irqrestore(&port->lock, flags);
1490 return;
1491
1492 fail:
1493 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1494 sci_rx_dma_release(s, true);
1495 spin_unlock_irqrestore(&port->lock, flags);
1496 }
1497
1498 static void work_fn_tx(struct work_struct *work)
1499 {
1500 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1501 struct dma_async_tx_descriptor *desc;
1502 struct dma_chan *chan = s->chan_tx;
1503 struct uart_port *port = &s->port;
1504 struct circ_buf *xmit = &port->state->xmit;
1505 dma_addr_t buf;
1506
1507 /*
1508 * DMA is idle now.
1509 * Port xmit buffer is already mapped, and it is one page... Just adjust
1510 * offsets and lengths. Since it is a circular buffer, we have to
1511 * transmit till the end, and then the rest. Take the port lock to get a
1512 * consistent xmit buffer state.
1513 */
1514 spin_lock_irq(&port->lock);
1515 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1516 s->tx_dma_len = min_t(unsigned int,
1517 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1518 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1519 spin_unlock_irq(&port->lock);
1520
1521 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1522 DMA_MEM_TO_DEV,
1523 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1524 if (!desc) {
1525 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1526 /* switch to PIO */
1527 sci_tx_dma_release(s, true);
1528 return;
1529 }
1530
1531 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1532 DMA_TO_DEVICE);
1533
1534 spin_lock_irq(&port->lock);
1535 desc->callback = sci_dma_tx_complete;
1536 desc->callback_param = s;
1537 spin_unlock_irq(&port->lock);
1538 s->cookie_tx = dmaengine_submit(desc);
1539 if (dma_submit_error(s->cookie_tx)) {
1540 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1541 /* switch to PIO */
1542 sci_tx_dma_release(s, true);
1543 return;
1544 }
1545
1546 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1547 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1548
1549 dma_async_issue_pending(chan);
1550 }
1551 #endif
1552
1553 static void sci_start_tx(struct uart_port *port)
1554 {
1555 struct sci_port *s = to_sci_port(port);
1556 unsigned short ctrl;
1557
1558 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1560 u16 new, scr = serial_port_in(port, SCSCR);
1561 if (s->chan_tx)
1562 new = scr | SCSCR_TDRQE;
1563 else
1564 new = scr & ~SCSCR_TDRQE;
1565 if (new != scr)
1566 serial_port_out(port, SCSCR, new);
1567 }
1568
1569 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1570 dma_submit_error(s->cookie_tx)) {
1571 s->cookie_tx = 0;
1572 schedule_work(&s->work_tx);
1573 }
1574 #endif
1575
1576 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1577 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1578 ctrl = serial_port_in(port, SCSCR);
1579 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1580 }
1581 }
1582
1583 static void sci_stop_tx(struct uart_port *port)
1584 {
1585 unsigned short ctrl;
1586
1587 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1588 ctrl = serial_port_in(port, SCSCR);
1589
1590 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1591 ctrl &= ~SCSCR_TDRQE;
1592
1593 ctrl &= ~SCSCR_TIE;
1594
1595 serial_port_out(port, SCSCR, ctrl);
1596 }
1597
1598 static void sci_start_rx(struct uart_port *port)
1599 {
1600 unsigned short ctrl;
1601
1602 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1603
1604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1605 ctrl &= ~SCSCR_RDRQE;
1606
1607 serial_port_out(port, SCSCR, ctrl);
1608 }
1609
1610 static void sci_stop_rx(struct uart_port *port)
1611 {
1612 unsigned short ctrl;
1613
1614 ctrl = serial_port_in(port, SCSCR);
1615
1616 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1617 ctrl &= ~SCSCR_RDRQE;
1618
1619 ctrl &= ~port_rx_irq_mask(port);
1620
1621 serial_port_out(port, SCSCR, ctrl);
1622 }
1623
1624 static void sci_break_ctl(struct uart_port *port, int break_state)
1625 {
1626 struct sci_port *s = to_sci_port(port);
1627 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1628 unsigned short scscr, scsptr;
1629
1630 /* check wheter the port has SCSPTR */
1631 if (!reg->size) {
1632 /*
1633 * Not supported by hardware. Most parts couple break and rx
1634 * interrupts together, with break detection always enabled.
1635 */
1636 return;
1637 }
1638
1639 scsptr = serial_port_in(port, SCSPTR);
1640 scscr = serial_port_in(port, SCSCR);
1641
1642 if (break_state == -1) {
1643 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1644 scscr &= ~SCSCR_TE;
1645 } else {
1646 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1647 scscr |= SCSCR_TE;
1648 }
1649
1650 serial_port_out(port, SCSPTR, scsptr);
1651 serial_port_out(port, SCSCR, scscr);
1652 }
1653
1654 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1655 static bool filter(struct dma_chan *chan, void *slave)
1656 {
1657 struct sh_dmae_slave *param = slave;
1658
1659 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1660 __func__, param->shdma_slave.slave_id);
1661
1662 chan->private = &param->shdma_slave;
1663 return true;
1664 }
1665
1666 static void rx_timer_fn(unsigned long arg)
1667 {
1668 struct sci_port *s = (struct sci_port *)arg;
1669 struct uart_port *port = &s->port;
1670 u16 scr = serial_port_in(port, SCSCR);
1671
1672 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1673 scr &= ~SCSCR_RDRQE;
1674 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1675 }
1676 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1677 dev_dbg(port->dev, "DMA Rx timed out\n");
1678 schedule_work(&s->work_rx);
1679 }
1680
1681 static void sci_request_dma(struct uart_port *port)
1682 {
1683 struct sci_port *s = to_sci_port(port);
1684 struct sh_dmae_slave *param;
1685 struct dma_chan *chan;
1686 dma_cap_mask_t mask;
1687
1688 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1689
1690 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1691 return;
1692
1693 dma_cap_zero(mask);
1694 dma_cap_set(DMA_SLAVE, mask);
1695
1696 param = &s->param_tx;
1697
1698 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1699 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1700
1701 s->cookie_tx = -EINVAL;
1702 chan = dma_request_channel(mask, filter, param);
1703 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1704 if (chan) {
1705 s->chan_tx = chan;
1706 /* UART circular tx buffer is an aligned page. */
1707 s->tx_dma_addr = dma_map_single(chan->device->dev,
1708 port->state->xmit.buf,
1709 UART_XMIT_SIZE,
1710 DMA_TO_DEVICE);
1711 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1712 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1713 dma_release_channel(chan);
1714 s->chan_tx = NULL;
1715 } else {
1716 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1717 __func__, UART_XMIT_SIZE,
1718 port->state->xmit.buf, &s->tx_dma_addr);
1719 }
1720
1721 INIT_WORK(&s->work_tx, work_fn_tx);
1722 }
1723
1724 param = &s->param_rx;
1725
1726 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1727 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1728
1729 chan = dma_request_channel(mask, filter, param);
1730 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1731 if (chan) {
1732 dma_addr_t dma[2];
1733 void *buf[2];
1734 int i;
1735
1736 s->chan_rx = chan;
1737
1738 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1739 buf[0] = dma_alloc_coherent(chan->device->dev,
1740 s->buf_len_rx * 2, &dma[0],
1741 GFP_KERNEL);
1742
1743 if (!buf[0]) {
1744 dev_warn(port->dev,
1745 "Failed to allocate Rx dma buffer, using PIO\n");
1746 dma_release_channel(chan);
1747 s->chan_rx = NULL;
1748 sci_start_rx(port);
1749 return;
1750 }
1751
1752 buf[1] = buf[0] + s->buf_len_rx;
1753 dma[1] = dma[0] + s->buf_len_rx;
1754
1755 for (i = 0; i < 2; i++) {
1756 struct scatterlist *sg = &s->sg_rx[i];
1757
1758 sg_init_table(sg, 1);
1759 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1760 (uintptr_t)buf[i] & ~PAGE_MASK);
1761 sg_dma_address(sg) = dma[i];
1762 }
1763
1764 INIT_WORK(&s->work_rx, work_fn_rx);
1765 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1766
1767 sci_submit_rx(s);
1768 }
1769 }
1770
1771 static void sci_free_dma(struct uart_port *port)
1772 {
1773 struct sci_port *s = to_sci_port(port);
1774
1775 if (s->chan_tx)
1776 sci_tx_dma_release(s, false);
1777 if (s->chan_rx)
1778 sci_rx_dma_release(s, false);
1779 }
1780 #else
1781 static inline void sci_request_dma(struct uart_port *port)
1782 {
1783 }
1784
1785 static inline void sci_free_dma(struct uart_port *port)
1786 {
1787 }
1788 #endif
1789
1790 static int sci_startup(struct uart_port *port)
1791 {
1792 struct sci_port *s = to_sci_port(port);
1793 unsigned long flags;
1794 int ret;
1795
1796 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1797
1798 ret = sci_request_irq(s);
1799 if (unlikely(ret < 0))
1800 return ret;
1801
1802 sci_request_dma(port);
1803
1804 spin_lock_irqsave(&port->lock, flags);
1805 sci_start_tx(port);
1806 sci_start_rx(port);
1807 spin_unlock_irqrestore(&port->lock, flags);
1808
1809 return 0;
1810 }
1811
1812 static void sci_shutdown(struct uart_port *port)
1813 {
1814 struct sci_port *s = to_sci_port(port);
1815 unsigned long flags;
1816
1817 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1818
1819 spin_lock_irqsave(&port->lock, flags);
1820 sci_stop_rx(port);
1821 sci_stop_tx(port);
1822 spin_unlock_irqrestore(&port->lock, flags);
1823
1824 sci_free_dma(port);
1825 sci_free_irq(s);
1826 }
1827
1828 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1829 unsigned long freq)
1830 {
1831 if (s->sampling_rate)
1832 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1833
1834 /* Warn, but use a safe default */
1835 WARN_ON(1);
1836
1837 return ((freq + 16 * bps) / (32 * bps) - 1);
1838 }
1839
1840 /* calculate frame length from SMR */
1841 static int sci_baud_calc_frame_len(unsigned int smr_val)
1842 {
1843 int len = 10;
1844
1845 if (smr_val & SCSMR_CHR)
1846 len--;
1847 if (smr_val & SCSMR_PE)
1848 len++;
1849 if (smr_val & SCSMR_STOP)
1850 len++;
1851
1852 return len;
1853 }
1854
1855
1856 /* calculate sample rate, BRR, and clock select for HSCIF */
1857 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1858 int *brr, unsigned int *srr,
1859 unsigned int *cks, int frame_len)
1860 {
1861 int sr, c, br, err, recv_margin;
1862 int min_err = 1000; /* 100% */
1863 int recv_max_margin = 0;
1864
1865 /* Find the combination of sample rate and clock select with the
1866 smallest deviation from the desired baud rate. */
1867 for (sr = 8; sr <= 32; sr++) {
1868 for (c = 0; c <= 3; c++) {
1869 /* integerized formulas from HSCIF documentation */
1870 br = DIV_ROUND_CLOSEST(freq, (sr *
1871 (1 << (2 * c + 1)) * bps)) - 1;
1872 br = clamp(br, 0, 255);
1873 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1874 (1 << (2 * c + 1)) / 1000)) -
1875 1000;
1876 /* Calc recv margin
1877 * M: Receive margin (%)
1878 * N: Ratio of bit rate to clock (N = sampling rate)
1879 * D: Clock duty (D = 0 to 1.0)
1880 * L: Frame length (L = 9 to 12)
1881 * F: Absolute value of clock frequency deviation
1882 *
1883 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1884 * (|D - 0.5| / N * (1 + F))|
1885 * NOTE: Usually, treat D for 0.5, F is 0 by this
1886 * calculation.
1887 */
1888 recv_margin = abs((500 -
1889 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1890 if (abs(min_err) > abs(err)) {
1891 min_err = err;
1892 recv_max_margin = recv_margin;
1893 } else if ((min_err == err) &&
1894 (recv_margin > recv_max_margin))
1895 recv_max_margin = recv_margin;
1896 else
1897 continue;
1898
1899 *brr = br;
1900 *srr = sr - 1;
1901 *cks = c;
1902 }
1903 }
1904
1905 if (min_err == 1000) {
1906 WARN_ON(1);
1907 /* use defaults */
1908 *brr = 255;
1909 *srr = 15;
1910 *cks = 0;
1911 }
1912 }
1913
1914 static void sci_reset(struct uart_port *port)
1915 {
1916 const struct plat_sci_reg *reg;
1917 unsigned int status;
1918
1919 do {
1920 status = serial_port_in(port, SCxSR);
1921 } while (!(status & SCxSR_TEND(port)));
1922
1923 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1924
1925 reg = sci_getreg(port, SCFCR);
1926 if (reg->size)
1927 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1928 }
1929
1930 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1931 struct ktermios *old)
1932 {
1933 struct sci_port *s = to_sci_port(port);
1934 const struct plat_sci_reg *reg;
1935 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1936 int t = -1;
1937 unsigned int srr = 15;
1938
1939 if ((termios->c_cflag & CSIZE) == CS7)
1940 smr_val |= SCSMR_CHR;
1941 if (termios->c_cflag & PARENB)
1942 smr_val |= SCSMR_PE;
1943 if (termios->c_cflag & PARODD)
1944 smr_val |= SCSMR_PE | SCSMR_ODD;
1945 if (termios->c_cflag & CSTOPB)
1946 smr_val |= SCSMR_STOP;
1947
1948 /*
1949 * earlyprintk comes here early on with port->uartclk set to zero.
1950 * the clock framework is not up and running at this point so here
1951 * we assume that 115200 is the maximum baud rate. please note that
1952 * the baud rate is not programmed during earlyprintk - it is assumed
1953 * that the previous boot loader has enabled required clocks and
1954 * setup the baud rate generator hardware for us already.
1955 */
1956 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1957
1958 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1959 if (likely(baud && port->uartclk)) {
1960 if (s->cfg->type == PORT_HSCIF) {
1961 int frame_len = sci_baud_calc_frame_len(smr_val);
1962 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1963 &cks, frame_len);
1964 } else {
1965 t = sci_scbrr_calc(s, baud, port->uartclk);
1966 for (cks = 0; t >= 256 && cks <= 3; cks++)
1967 t >>= 2;
1968 }
1969 }
1970
1971 sci_port_enable(s);
1972
1973 sci_reset(port);
1974
1975 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1976
1977 uart_update_timeout(port, termios->c_cflag, baud);
1978
1979 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1980 __func__, smr_val, cks, t, s->cfg->scscr);
1981
1982 if (t >= 0) {
1983 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1984 serial_port_out(port, SCBRR, t);
1985 reg = sci_getreg(port, HSSRR);
1986 if (reg->size)
1987 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1988 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1989 } else
1990 serial_port_out(port, SCSMR, smr_val);
1991
1992 sci_init_pins(port, termios->c_cflag);
1993
1994 reg = sci_getreg(port, SCFCR);
1995 if (reg->size) {
1996 unsigned short ctrl = serial_port_in(port, SCFCR);
1997
1998 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1999 if (termios->c_cflag & CRTSCTS)
2000 ctrl |= SCFCR_MCE;
2001 else
2002 ctrl &= ~SCFCR_MCE;
2003 }
2004
2005 /*
2006 * As we've done a sci_reset() above, ensure we don't
2007 * interfere with the FIFOs while toggling MCE. As the
2008 * reset values could still be set, simply mask them out.
2009 */
2010 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2011
2012 serial_port_out(port, SCFCR, ctrl);
2013 }
2014
2015 serial_port_out(port, SCSCR, s->cfg->scscr);
2016
2017 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2018 /*
2019 * Calculate delay for 2 DMA buffers (4 FIFO).
2020 * See serial_core.c::uart_update_timeout().
2021 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2022 * function calculates 1 jiffie for the data plus 5 jiffies for the
2023 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2024 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2025 * value obtained by this formula is too small. Therefore, if the value
2026 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2027 */
2028 if (s->chan_rx) {
2029 unsigned int bits;
2030
2031 /* byte size and parity */
2032 switch (termios->c_cflag & CSIZE) {
2033 case CS5:
2034 bits = 7;
2035 break;
2036 case CS6:
2037 bits = 8;
2038 break;
2039 case CS7:
2040 bits = 9;
2041 break;
2042 default:
2043 bits = 10;
2044 break;
2045 }
2046
2047 if (termios->c_cflag & CSTOPB)
2048 bits++;
2049 if (termios->c_cflag & PARENB)
2050 bits++;
2051 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2052 (baud / 10), 10);
2053 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2054 s->rx_timeout * 1000 / HZ, port->timeout);
2055 if (s->rx_timeout < msecs_to_jiffies(20))
2056 s->rx_timeout = msecs_to_jiffies(20);
2057 }
2058 #endif
2059
2060 if ((termios->c_cflag & CREAD) != 0)
2061 sci_start_rx(port);
2062
2063 sci_port_disable(s);
2064 }
2065
2066 static void sci_pm(struct uart_port *port, unsigned int state,
2067 unsigned int oldstate)
2068 {
2069 struct sci_port *sci_port = to_sci_port(port);
2070
2071 switch (state) {
2072 case UART_PM_STATE_OFF:
2073 sci_port_disable(sci_port);
2074 break;
2075 default:
2076 sci_port_enable(sci_port);
2077 break;
2078 }
2079 }
2080
2081 static const char *sci_type(struct uart_port *port)
2082 {
2083 switch (port->type) {
2084 case PORT_IRDA:
2085 return "irda";
2086 case PORT_SCI:
2087 return "sci";
2088 case PORT_SCIF:
2089 return "scif";
2090 case PORT_SCIFA:
2091 return "scifa";
2092 case PORT_SCIFB:
2093 return "scifb";
2094 case PORT_HSCIF:
2095 return "hscif";
2096 }
2097
2098 return NULL;
2099 }
2100
2101 static int sci_remap_port(struct uart_port *port)
2102 {
2103 struct sci_port *sport = to_sci_port(port);
2104
2105 /*
2106 * Nothing to do if there's already an established membase.
2107 */
2108 if (port->membase)
2109 return 0;
2110
2111 if (port->flags & UPF_IOREMAP) {
2112 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2113 if (unlikely(!port->membase)) {
2114 dev_err(port->dev, "can't remap port#%d\n", port->line);
2115 return -ENXIO;
2116 }
2117 } else {
2118 /*
2119 * For the simple (and majority of) cases where we don't
2120 * need to do any remapping, just cast the cookie
2121 * directly.
2122 */
2123 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2124 }
2125
2126 return 0;
2127 }
2128
2129 static void sci_release_port(struct uart_port *port)
2130 {
2131 struct sci_port *sport = to_sci_port(port);
2132
2133 if (port->flags & UPF_IOREMAP) {
2134 iounmap(port->membase);
2135 port->membase = NULL;
2136 }
2137
2138 release_mem_region(port->mapbase, sport->reg_size);
2139 }
2140
2141 static int sci_request_port(struct uart_port *port)
2142 {
2143 struct resource *res;
2144 struct sci_port *sport = to_sci_port(port);
2145 int ret;
2146
2147 res = request_mem_region(port->mapbase, sport->reg_size,
2148 dev_name(port->dev));
2149 if (unlikely(res == NULL)) {
2150 dev_err(port->dev, "request_mem_region failed.");
2151 return -EBUSY;
2152 }
2153
2154 ret = sci_remap_port(port);
2155 if (unlikely(ret != 0)) {
2156 release_resource(res);
2157 return ret;
2158 }
2159
2160 return 0;
2161 }
2162
2163 static void sci_config_port(struct uart_port *port, int flags)
2164 {
2165 if (flags & UART_CONFIG_TYPE) {
2166 struct sci_port *sport = to_sci_port(port);
2167
2168 port->type = sport->cfg->type;
2169 sci_request_port(port);
2170 }
2171 }
2172
2173 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2174 {
2175 if (ser->baud_base < 2400)
2176 /* No paper tape reader for Mitch.. */
2177 return -EINVAL;
2178
2179 return 0;
2180 }
2181
2182 static struct uart_ops sci_uart_ops = {
2183 .tx_empty = sci_tx_empty,
2184 .set_mctrl = sci_set_mctrl,
2185 .get_mctrl = sci_get_mctrl,
2186 .start_tx = sci_start_tx,
2187 .stop_tx = sci_stop_tx,
2188 .stop_rx = sci_stop_rx,
2189 .break_ctl = sci_break_ctl,
2190 .startup = sci_startup,
2191 .shutdown = sci_shutdown,
2192 .set_termios = sci_set_termios,
2193 .pm = sci_pm,
2194 .type = sci_type,
2195 .release_port = sci_release_port,
2196 .request_port = sci_request_port,
2197 .config_port = sci_config_port,
2198 .verify_port = sci_verify_port,
2199 #ifdef CONFIG_CONSOLE_POLL
2200 .poll_get_char = sci_poll_get_char,
2201 .poll_put_char = sci_poll_put_char,
2202 #endif
2203 };
2204
2205 static int sci_init_single(struct platform_device *dev,
2206 struct sci_port *sci_port, unsigned int index,
2207 struct plat_sci_port *p, bool early)
2208 {
2209 struct uart_port *port = &sci_port->port;
2210 const struct resource *res;
2211 unsigned int i;
2212 int ret;
2213
2214 sci_port->cfg = p;
2215
2216 port->ops = &sci_uart_ops;
2217 port->iotype = UPIO_MEM;
2218 port->line = index;
2219
2220 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2221 if (res == NULL)
2222 return -ENOMEM;
2223
2224 port->mapbase = res->start;
2225 sci_port->reg_size = resource_size(res);
2226
2227 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2228 sci_port->irqs[i] = platform_get_irq(dev, i);
2229
2230 /* The SCI generates several interrupts. They can be muxed together or
2231 * connected to different interrupt lines. In the muxed case only one
2232 * interrupt resource is specified. In the non-muxed case three or four
2233 * interrupt resources are specified, as the BRI interrupt is optional.
2234 */
2235 if (sci_port->irqs[0] < 0)
2236 return -ENXIO;
2237
2238 if (sci_port->irqs[1] < 0) {
2239 sci_port->irqs[1] = sci_port->irqs[0];
2240 sci_port->irqs[2] = sci_port->irqs[0];
2241 sci_port->irqs[3] = sci_port->irqs[0];
2242 }
2243
2244 if (p->regtype == SCIx_PROBE_REGTYPE) {
2245 ret = sci_probe_regmap(p);
2246 if (unlikely(ret))
2247 return ret;
2248 }
2249
2250 switch (p->type) {
2251 case PORT_SCIFB:
2252 port->fifosize = 256;
2253 sci_port->overrun_reg = SCxSR;
2254 sci_port->overrun_mask = SCIFA_ORER;
2255 sci_port->sampling_rate = 16;
2256 break;
2257 case PORT_HSCIF:
2258 port->fifosize = 128;
2259 sci_port->overrun_reg = SCLSR;
2260 sci_port->overrun_mask = SCLSR_ORER;
2261 sci_port->sampling_rate = 0;
2262 break;
2263 case PORT_SCIFA:
2264 port->fifosize = 64;
2265 sci_port->overrun_reg = SCxSR;
2266 sci_port->overrun_mask = SCIFA_ORER;
2267 sci_port->sampling_rate = 16;
2268 break;
2269 case PORT_SCIF:
2270 port->fifosize = 16;
2271 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2272 sci_port->overrun_reg = SCxSR;
2273 sci_port->overrun_mask = SCIFA_ORER;
2274 sci_port->sampling_rate = 16;
2275 } else {
2276 sci_port->overrun_reg = SCLSR;
2277 sci_port->overrun_mask = SCLSR_ORER;
2278 sci_port->sampling_rate = 32;
2279 }
2280 break;
2281 default:
2282 port->fifosize = 1;
2283 sci_port->overrun_reg = SCxSR;
2284 sci_port->overrun_mask = SCI_ORER;
2285 sci_port->sampling_rate = 32;
2286 break;
2287 }
2288
2289 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2290 * match the SoC datasheet, this should be investigated. Let platform
2291 * data override the sampling rate for now.
2292 */
2293 if (p->sampling_rate)
2294 sci_port->sampling_rate = p->sampling_rate;
2295
2296 if (!early) {
2297 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2298 if (IS_ERR(sci_port->iclk)) {
2299 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2300 if (IS_ERR(sci_port->iclk)) {
2301 dev_err(&dev->dev, "can't get iclk\n");
2302 return PTR_ERR(sci_port->iclk);
2303 }
2304 }
2305
2306 /*
2307 * The function clock is optional, ignore it if we can't
2308 * find it.
2309 */
2310 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2311 if (IS_ERR(sci_port->fclk))
2312 sci_port->fclk = NULL;
2313
2314 port->dev = &dev->dev;
2315
2316 pm_runtime_enable(&dev->dev);
2317 }
2318
2319 sci_port->break_timer.data = (unsigned long)sci_port;
2320 sci_port->break_timer.function = sci_break_timer;
2321 init_timer(&sci_port->break_timer);
2322
2323 /*
2324 * Establish some sensible defaults for the error detection.
2325 */
2326 if (p->type == PORT_SCI) {
2327 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2328 sci_port->error_clear = SCI_ERROR_CLEAR;
2329 } else {
2330 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2331 sci_port->error_clear = SCIF_ERROR_CLEAR;
2332 }
2333
2334 /*
2335 * Make the error mask inclusive of overrun detection, if
2336 * supported.
2337 */
2338 if (sci_port->overrun_reg == SCxSR) {
2339 sci_port->error_mask |= sci_port->overrun_mask;
2340 sci_port->error_clear &= ~sci_port->overrun_mask;
2341 }
2342
2343 port->type = p->type;
2344 port->flags = UPF_FIXED_PORT | p->flags;
2345 port->regshift = p->regshift;
2346
2347 /*
2348 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2349 * for the multi-IRQ ports, which is where we are primarily
2350 * concerned with the shutdown path synchronization.
2351 *
2352 * For the muxed case there's nothing more to do.
2353 */
2354 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2355 port->irqflags = 0;
2356
2357 port->serial_in = sci_serial_in;
2358 port->serial_out = sci_serial_out;
2359
2360 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2361 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2362 p->dma_slave_tx, p->dma_slave_rx);
2363
2364 return 0;
2365 }
2366
2367 static void sci_cleanup_single(struct sci_port *port)
2368 {
2369 clk_put(port->iclk);
2370 clk_put(port->fclk);
2371
2372 pm_runtime_disable(port->port.dev);
2373 }
2374
2375 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2376 static void serial_console_putchar(struct uart_port *port, int ch)
2377 {
2378 sci_poll_put_char(port, ch);
2379 }
2380
2381 /*
2382 * Print a string to the serial port trying not to disturb
2383 * any possible real use of the port...
2384 */
2385 static void serial_console_write(struct console *co, const char *s,
2386 unsigned count)
2387 {
2388 struct sci_port *sci_port = &sci_ports[co->index];
2389 struct uart_port *port = &sci_port->port;
2390 unsigned short bits, ctrl;
2391 unsigned long flags;
2392 int locked = 1;
2393
2394 local_irq_save(flags);
2395 if (port->sysrq)
2396 locked = 0;
2397 else if (oops_in_progress)
2398 locked = spin_trylock(&port->lock);
2399 else
2400 spin_lock(&port->lock);
2401
2402 /* first save the SCSCR then disable the interrupts */
2403 ctrl = serial_port_in(port, SCSCR);
2404 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2405
2406 uart_console_write(port, s, count, serial_console_putchar);
2407
2408 /* wait until fifo is empty and last bit has been transmitted */
2409 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2410 while ((serial_port_in(port, SCxSR) & bits) != bits)
2411 cpu_relax();
2412
2413 /* restore the SCSCR */
2414 serial_port_out(port, SCSCR, ctrl);
2415
2416 if (locked)
2417 spin_unlock(&port->lock);
2418 local_irq_restore(flags);
2419 }
2420
2421 static int serial_console_setup(struct console *co, char *options)
2422 {
2423 struct sci_port *sci_port;
2424 struct uart_port *port;
2425 int baud = 115200;
2426 int bits = 8;
2427 int parity = 'n';
2428 int flow = 'n';
2429 int ret;
2430
2431 /*
2432 * Refuse to handle any bogus ports.
2433 */
2434 if (co->index < 0 || co->index >= SCI_NPORTS)
2435 return -ENODEV;
2436
2437 sci_port = &sci_ports[co->index];
2438 port = &sci_port->port;
2439
2440 /*
2441 * Refuse to handle uninitialized ports.
2442 */
2443 if (!port->ops)
2444 return -ENODEV;
2445
2446 ret = sci_remap_port(port);
2447 if (unlikely(ret != 0))
2448 return ret;
2449
2450 if (options)
2451 uart_parse_options(options, &baud, &parity, &bits, &flow);
2452
2453 return uart_set_options(port, co, baud, parity, bits, flow);
2454 }
2455
2456 static struct console serial_console = {
2457 .name = "ttySC",
2458 .device = uart_console_device,
2459 .write = serial_console_write,
2460 .setup = serial_console_setup,
2461 .flags = CON_PRINTBUFFER,
2462 .index = -1,
2463 .data = &sci_uart_driver,
2464 };
2465
2466 static struct console early_serial_console = {
2467 .name = "early_ttySC",
2468 .write = serial_console_write,
2469 .flags = CON_PRINTBUFFER,
2470 .index = -1,
2471 };
2472
2473 static char early_serial_buf[32];
2474
2475 static int sci_probe_earlyprintk(struct platform_device *pdev)
2476 {
2477 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2478
2479 if (early_serial_console.data)
2480 return -EEXIST;
2481
2482 early_serial_console.index = pdev->id;
2483
2484 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2485
2486 serial_console_setup(&early_serial_console, early_serial_buf);
2487
2488 if (!strstr(early_serial_buf, "keep"))
2489 early_serial_console.flags |= CON_BOOT;
2490
2491 register_console(&early_serial_console);
2492 return 0;
2493 }
2494
2495 #define SCI_CONSOLE (&serial_console)
2496
2497 #else
2498 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2499 {
2500 return -EINVAL;
2501 }
2502
2503 #define SCI_CONSOLE NULL
2504
2505 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2506
2507 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2508
2509 static struct uart_driver sci_uart_driver = {
2510 .owner = THIS_MODULE,
2511 .driver_name = "sci",
2512 .dev_name = "ttySC",
2513 .major = SCI_MAJOR,
2514 .minor = SCI_MINOR_START,
2515 .nr = SCI_NPORTS,
2516 .cons = SCI_CONSOLE,
2517 };
2518
2519 static int sci_remove(struct platform_device *dev)
2520 {
2521 struct sci_port *port = platform_get_drvdata(dev);
2522
2523 cpufreq_unregister_notifier(&port->freq_transition,
2524 CPUFREQ_TRANSITION_NOTIFIER);
2525
2526 uart_remove_one_port(&sci_uart_driver, &port->port);
2527
2528 sci_cleanup_single(port);
2529
2530 return 0;
2531 }
2532
2533 struct sci_port_info {
2534 unsigned int type;
2535 unsigned int regtype;
2536 };
2537
2538 static const struct of_device_id of_sci_match[] = {
2539 {
2540 .compatible = "renesas,scif",
2541 .data = &(const struct sci_port_info) {
2542 .type = PORT_SCIF,
2543 .regtype = SCIx_SH4_SCIF_REGTYPE,
2544 },
2545 }, {
2546 .compatible = "renesas,scifa",
2547 .data = &(const struct sci_port_info) {
2548 .type = PORT_SCIFA,
2549 .regtype = SCIx_SCIFA_REGTYPE,
2550 },
2551 }, {
2552 .compatible = "renesas,scifb",
2553 .data = &(const struct sci_port_info) {
2554 .type = PORT_SCIFB,
2555 .regtype = SCIx_SCIFB_REGTYPE,
2556 },
2557 }, {
2558 .compatible = "renesas,hscif",
2559 .data = &(const struct sci_port_info) {
2560 .type = PORT_HSCIF,
2561 .regtype = SCIx_HSCIF_REGTYPE,
2562 },
2563 }, {
2564 .compatible = "renesas,sci",
2565 .data = &(const struct sci_port_info) {
2566 .type = PORT_SCI,
2567 .regtype = SCIx_SCI_REGTYPE,
2568 },
2569 }, {
2570 /* Terminator */
2571 },
2572 };
2573 MODULE_DEVICE_TABLE(of, of_sci_match);
2574
2575 static struct plat_sci_port *
2576 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2577 {
2578 struct device_node *np = pdev->dev.of_node;
2579 const struct of_device_id *match;
2580 const struct sci_port_info *info;
2581 struct plat_sci_port *p;
2582 int id;
2583
2584 if (!IS_ENABLED(CONFIG_OF) || !np)
2585 return NULL;
2586
2587 match = of_match_node(of_sci_match, pdev->dev.of_node);
2588 if (!match)
2589 return NULL;
2590
2591 info = match->data;
2592
2593 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2594 if (!p)
2595 return NULL;
2596
2597 /* Get the line number for the aliases node. */
2598 id = of_alias_get_id(np, "serial");
2599 if (id < 0) {
2600 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2601 return NULL;
2602 }
2603
2604 *dev_id = id;
2605
2606 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2607 p->type = info->type;
2608 p->regtype = info->regtype;
2609 p->scscr = SCSCR_RE | SCSCR_TE;
2610
2611 return p;
2612 }
2613
2614 static int sci_probe_single(struct platform_device *dev,
2615 unsigned int index,
2616 struct plat_sci_port *p,
2617 struct sci_port *sciport)
2618 {
2619 int ret;
2620
2621 /* Sanity check */
2622 if (unlikely(index >= SCI_NPORTS)) {
2623 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2624 index+1, SCI_NPORTS);
2625 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2626 return -EINVAL;
2627 }
2628
2629 ret = sci_init_single(dev, sciport, index, p, false);
2630 if (ret)
2631 return ret;
2632
2633 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2634 if (ret) {
2635 sci_cleanup_single(sciport);
2636 return ret;
2637 }
2638
2639 return 0;
2640 }
2641
2642 static int sci_probe(struct platform_device *dev)
2643 {
2644 struct plat_sci_port *p;
2645 struct sci_port *sp;
2646 unsigned int dev_id;
2647 int ret;
2648
2649 /*
2650 * If we've come here via earlyprintk initialization, head off to
2651 * the special early probe. We don't have sufficient device state
2652 * to make it beyond this yet.
2653 */
2654 if (is_early_platform_device(dev))
2655 return sci_probe_earlyprintk(dev);
2656
2657 if (dev->dev.of_node) {
2658 p = sci_parse_dt(dev, &dev_id);
2659 if (p == NULL)
2660 return -EINVAL;
2661 } else {
2662 p = dev->dev.platform_data;
2663 if (p == NULL) {
2664 dev_err(&dev->dev, "no platform data supplied\n");
2665 return -EINVAL;
2666 }
2667
2668 dev_id = dev->id;
2669 }
2670
2671 sp = &sci_ports[dev_id];
2672 platform_set_drvdata(dev, sp);
2673
2674 ret = sci_probe_single(dev, dev_id, p, sp);
2675 if (ret)
2676 return ret;
2677
2678 sp->freq_transition.notifier_call = sci_notifier;
2679
2680 ret = cpufreq_register_notifier(&sp->freq_transition,
2681 CPUFREQ_TRANSITION_NOTIFIER);
2682 if (unlikely(ret < 0)) {
2683 uart_remove_one_port(&sci_uart_driver, &sp->port);
2684 sci_cleanup_single(sp);
2685 return ret;
2686 }
2687
2688 #ifdef CONFIG_SH_STANDARD_BIOS
2689 sh_bios_gdb_detach();
2690 #endif
2691
2692 return 0;
2693 }
2694
2695 static __maybe_unused int sci_suspend(struct device *dev)
2696 {
2697 struct sci_port *sport = dev_get_drvdata(dev);
2698
2699 if (sport)
2700 uart_suspend_port(&sci_uart_driver, &sport->port);
2701
2702 return 0;
2703 }
2704
2705 static __maybe_unused int sci_resume(struct device *dev)
2706 {
2707 struct sci_port *sport = dev_get_drvdata(dev);
2708
2709 if (sport)
2710 uart_resume_port(&sci_uart_driver, &sport->port);
2711
2712 return 0;
2713 }
2714
2715 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2716
2717 static struct platform_driver sci_driver = {
2718 .probe = sci_probe,
2719 .remove = sci_remove,
2720 .driver = {
2721 .name = "sh-sci",
2722 .pm = &sci_dev_pm_ops,
2723 .of_match_table = of_match_ptr(of_sci_match),
2724 },
2725 };
2726
2727 static int __init sci_init(void)
2728 {
2729 int ret;
2730
2731 pr_info("%s\n", banner);
2732
2733 ret = uart_register_driver(&sci_uart_driver);
2734 if (likely(ret == 0)) {
2735 ret = platform_driver_register(&sci_driver);
2736 if (unlikely(ret))
2737 uart_unregister_driver(&sci_uart_driver);
2738 }
2739
2740 return ret;
2741 }
2742
2743 static void __exit sci_exit(void)
2744 {
2745 platform_driver_unregister(&sci_driver);
2746 uart_unregister_driver(&sci_uart_driver);
2747 }
2748
2749 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2750 early_platform_init_buffer("earlyprintk", &sci_driver,
2751 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2752 #endif
2753 module_init(sci_init);
2754 module_exit(sci_exit);
2755
2756 MODULE_LICENSE("GPL");
2757 MODULE_ALIAS("platform:sh-sci");
2758 MODULE_AUTHOR("Paul Mundt");
2759 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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