drivers/tty/serial/sirfsoc_uart.h

   1 /*
   2  * Drivers for CSR SiRFprimaII onboard UARTs.
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8 #include <linux/bitops.h>
   9 #include <linux/log2.h>
  10 struct sirfsoc_uart_param {
  11         const char *uart_name;
  12         const char *port_name;
  13 };
  14
  15 struct sirfsoc_register {
  16         /* hardware uart specific */
  17         u32 sirfsoc_line_ctrl;
  18         u32 sirfsoc_divisor;
  19         /* uart - usp common */
  20         u32 sirfsoc_tx_rx_en;
  21         u32 sirfsoc_int_en_reg;
  22         u32 sirfsoc_int_st_reg;
  23         u32 sirfsoc_tx_dma_io_ctrl;
  24         u32 sirfsoc_tx_dma_io_len;
  25         u32 sirfsoc_tx_fifo_ctrl;
  26         u32 sirfsoc_tx_fifo_level_chk;
  27         u32 sirfsoc_tx_fifo_op;
  28         u32 sirfsoc_tx_fifo_status;
  29         u32 sirfsoc_tx_fifo_data;
  30         u32 sirfsoc_rx_dma_io_ctrl;
  31         u32 sirfsoc_rx_dma_io_len;
  32         u32 sirfsoc_rx_fifo_ctrl;
  33         u32 sirfsoc_rx_fifo_level_chk;
  34         u32 sirfsoc_rx_fifo_op;
  35         u32 sirfsoc_rx_fifo_status;
  36         u32 sirfsoc_rx_fifo_data;
  37         u32 sirfsoc_afc_ctrl;
  38         u32 sirfsoc_swh_dma_io;
  39         /* hardware usp specific */
  40         u32 sirfsoc_mode1;
  41         u32 sirfsoc_mode2;
  42         u32 sirfsoc_tx_frame_ctrl;
  43         u32 sirfsoc_rx_frame_ctrl;
  44         u32 sirfsoc_async_param_reg;
  45 };
  46
  47 typedef u32 (*fifo_full_mask)(struct uart_port *port);
  48 typedef u32 (*fifo_empty_mask)(struct uart_port *port);
  49
  50 struct sirfsoc_fifo_status {
  51         fifo_full_mask ff_full;
  52         fifo_empty_mask ff_empty;
  53 };
  54
  55 struct sirfsoc_int_en {
  56         u32 sirfsoc_rx_done_en;
  57         u32 sirfsoc_tx_done_en;
  58         u32 sirfsoc_rx_oflow_en;
  59         u32 sirfsoc_tx_allout_en;
  60         u32 sirfsoc_rx_io_dma_en;
  61         u32 sirfsoc_tx_io_dma_en;
  62         u32 sirfsoc_rxfifo_full_en;
  63         u32 sirfsoc_txfifo_empty_en;
  64         u32 sirfsoc_rxfifo_thd_en;
  65         u32 sirfsoc_txfifo_thd_en;
  66         u32 sirfsoc_frm_err_en;
  67         u32 sirfsoc_rxd_brk_en;
  68         u32 sirfsoc_rx_timeout_en;
  69         u32 sirfsoc_parity_err_en;
  70         u32 sirfsoc_cts_en;
  71         u32 sirfsoc_rts_en;
  72 };
  73
  74 struct sirfsoc_int_status {
  75         u32 sirfsoc_rx_done;
  76         u32 sirfsoc_tx_done;
  77         u32 sirfsoc_rx_oflow;
  78         u32 sirfsoc_tx_allout;
  79         u32 sirfsoc_rx_io_dma;
  80         u32 sirfsoc_tx_io_dma;
  81         u32 sirfsoc_rxfifo_full;
  82         u32 sirfsoc_txfifo_empty;
  83         u32 sirfsoc_rxfifo_thd;
  84         u32 sirfsoc_txfifo_thd;
  85         u32 sirfsoc_frm_err;
  86         u32 sirfsoc_rxd_brk;
  87         u32 sirfsoc_rx_timeout;
  88         u32 sirfsoc_parity_err;
  89         u32 sirfsoc_cts;
  90         u32 sirfsoc_rts;
  91 };
  92
  93 enum sirfsoc_uart_type {
  94         SIRF_REAL_UART,
  95         SIRF_USP_UART,
  96 };
  97
  98 struct sirfsoc_uart_register {
  99         struct sirfsoc_register uart_reg;
 100         struct sirfsoc_int_en uart_int_en;
 101         struct sirfsoc_int_status uart_int_st;
 102         struct sirfsoc_fifo_status fifo_status;
 103         struct sirfsoc_uart_param uart_param;
 104         enum sirfsoc_uart_type uart_type;
 105 };
 106
 107 u32 uart_usp_ff_full_mask(struct uart_port *port)
 108 {
 109         u32 full_bit;
 110
 111         full_bit = ilog2(port->fifosize);
 112         return (1 << full_bit);
 113 }
 114
 115 u32 uart_usp_ff_empty_mask(struct uart_port *port)
 116 {
 117         u32 empty_bit;
 118
 119         empty_bit = ilog2(port->fifosize);
 120         return (1 << empty_bit);
 121 }
 122 struct sirfsoc_uart_register sirfsoc_usp = {
 123         .uart_reg = {
 124                 .sirfsoc_mode1          = 0x0000,
 125                 .sirfsoc_mode2          = 0x0004,
 126                 .sirfsoc_tx_frame_ctrl  = 0x0008,
 127                 .sirfsoc_rx_frame_ctrl  = 0x000c,
 128                 .sirfsoc_tx_rx_en       = 0x0010,
 129                 .sirfsoc_int_en_reg     = 0x0014,
 130                 .sirfsoc_int_st_reg     = 0x0018,
 131                 .sirfsoc_async_param_reg = 0x0024,
 132                 .sirfsoc_tx_dma_io_ctrl = 0x0100,
 133                 .sirfsoc_tx_dma_io_len  = 0x0104,
 134                 .sirfsoc_tx_fifo_ctrl   = 0x0108,
 135                 .sirfsoc_tx_fifo_level_chk = 0x010c,
 136                 .sirfsoc_tx_fifo_op     = 0x0110,
 137                 .sirfsoc_tx_fifo_status = 0x0114,
 138                 .sirfsoc_tx_fifo_data   = 0x0118,
 139                 .sirfsoc_rx_dma_io_ctrl = 0x0120,
 140                 .sirfsoc_rx_dma_io_len  = 0x0124,
 141                 .sirfsoc_rx_fifo_ctrl   = 0x0128,
 142                 .sirfsoc_rx_fifo_level_chk = 0x012c,
 143                 .sirfsoc_rx_fifo_op     = 0x0130,
 144                 .sirfsoc_rx_fifo_status = 0x0134,
 145                 .sirfsoc_rx_fifo_data   = 0x0138,
 146         },
 147         .uart_int_en = {
 148                 .sirfsoc_rx_done_en     = BIT(0),
 149                 .sirfsoc_tx_done_en     = BIT(1),
 150                 .sirfsoc_rx_oflow_en    = BIT(2),
 151                 .sirfsoc_tx_allout_en   = BIT(3),
 152                 .sirfsoc_rx_io_dma_en   = BIT(4),
 153                 .sirfsoc_tx_io_dma_en   = BIT(5),
 154                 .sirfsoc_rxfifo_full_en = BIT(6),
 155                 .sirfsoc_txfifo_empty_en = BIT(7),
 156                 .sirfsoc_rxfifo_thd_en  = BIT(8),
 157                 .sirfsoc_txfifo_thd_en  = BIT(9),
 158                 .sirfsoc_frm_err_en     = BIT(10),
 159                 .sirfsoc_rx_timeout_en  = BIT(11),
 160                 .sirfsoc_rxd_brk_en     = BIT(15),
 161         },
 162         .uart_int_st = {
 163                 .sirfsoc_rx_done        = BIT(0),
 164                 .sirfsoc_tx_done        = BIT(1),
 165                 .sirfsoc_rx_oflow       = BIT(2),
 166                 .sirfsoc_tx_allout      = BIT(3),
 167                 .sirfsoc_rx_io_dma      = BIT(4),
 168                 .sirfsoc_tx_io_dma      = BIT(5),
 169                 .sirfsoc_rxfifo_full    = BIT(6),
 170                 .sirfsoc_txfifo_empty   = BIT(7),
 171                 .sirfsoc_rxfifo_thd     = BIT(8),
 172                 .sirfsoc_txfifo_thd     = BIT(9),
 173                 .sirfsoc_frm_err        = BIT(10),
 174                 .sirfsoc_rx_timeout     = BIT(11),
 175                 .sirfsoc_rxd_brk        = BIT(15),
 176         },
 177         .fifo_status = {
 178                 .ff_full                = uart_usp_ff_full_mask,
 179                 .ff_empty               = uart_usp_ff_empty_mask,
 180         },
 181         .uart_param = {
 182                 .uart_name = "ttySiRF",
 183                 .port_name = "sirfsoc-uart",
 184         },
 185 };
 186
 187 struct sirfsoc_uart_register sirfsoc_uart = {
 188         .uart_reg = {
 189                 .sirfsoc_line_ctrl      = 0x0040,
 190                 .sirfsoc_tx_rx_en       = 0x004c,
 191                 .sirfsoc_divisor        = 0x0050,
 192                 .sirfsoc_int_en_reg     = 0x0054,
 193                 .sirfsoc_int_st_reg     = 0x0058,
 194                 .sirfsoc_tx_dma_io_ctrl = 0x0100,
 195                 .sirfsoc_tx_dma_io_len  = 0x0104,
 196                 .sirfsoc_tx_fifo_ctrl   = 0x0108,
 197                 .sirfsoc_tx_fifo_level_chk = 0x010c,
 198                 .sirfsoc_tx_fifo_op     = 0x0110,
 199                 .sirfsoc_tx_fifo_status = 0x0114,
 200                 .sirfsoc_tx_fifo_data   = 0x0118,
 201                 .sirfsoc_rx_dma_io_ctrl = 0x0120,
 202                 .sirfsoc_rx_dma_io_len  = 0x0124,
 203                 .sirfsoc_rx_fifo_ctrl   = 0x0128,
 204                 .sirfsoc_rx_fifo_level_chk = 0x012c,
 205                 .sirfsoc_rx_fifo_op     = 0x0130,
 206                 .sirfsoc_rx_fifo_status = 0x0134,
 207                 .sirfsoc_rx_fifo_data   = 0x0138,
 208                 .sirfsoc_afc_ctrl       = 0x0140,
 209                 .sirfsoc_swh_dma_io     = 0x0148,
 210         },
 211         .uart_int_en = {
 212                 .sirfsoc_rx_done_en     = BIT(0),
 213                 .sirfsoc_tx_done_en     = BIT(1),
 214                 .sirfsoc_rx_oflow_en    = BIT(2),
 215                 .sirfsoc_tx_allout_en   = BIT(3),
 216                 .sirfsoc_rx_io_dma_en   = BIT(4),
 217                 .sirfsoc_tx_io_dma_en   = BIT(5),
 218                 .sirfsoc_rxfifo_full_en = BIT(6),
 219                 .sirfsoc_txfifo_empty_en = BIT(7),
 220                 .sirfsoc_rxfifo_thd_en  = BIT(8),
 221                 .sirfsoc_txfifo_thd_en  = BIT(9),
 222                 .sirfsoc_frm_err_en     = BIT(10),
 223                 .sirfsoc_rxd_brk_en     = BIT(11),
 224                 .sirfsoc_rx_timeout_en  = BIT(12),
 225                 .sirfsoc_parity_err_en  = BIT(13),
 226                 .sirfsoc_cts_en         = BIT(14),
 227                 .sirfsoc_rts_en         = BIT(15),
 228         },
 229         .uart_int_st = {
 230                 .sirfsoc_rx_done        = BIT(0),
 231                 .sirfsoc_tx_done        = BIT(1),
 232                 .sirfsoc_rx_oflow       = BIT(2),
 233                 .sirfsoc_tx_allout      = BIT(3),
 234                 .sirfsoc_rx_io_dma      = BIT(4),
 235                 .sirfsoc_tx_io_dma      = BIT(5),
 236                 .sirfsoc_rxfifo_full    = BIT(6),
 237                 .sirfsoc_txfifo_empty   = BIT(7),
 238                 .sirfsoc_rxfifo_thd     = BIT(8),
 239                 .sirfsoc_txfifo_thd     = BIT(9),
 240                 .sirfsoc_frm_err        = BIT(10),
 241                 .sirfsoc_rxd_brk        = BIT(11),
 242                 .sirfsoc_rx_timeout     = BIT(12),
 243                 .sirfsoc_parity_err     = BIT(13),
 244                 .sirfsoc_cts            = BIT(14),
 245                 .sirfsoc_rts            = BIT(15),
 246         },
 247         .fifo_status = {
 248                 .ff_full                = uart_usp_ff_full_mask,
 249                 .ff_empty               = uart_usp_ff_empty_mask,
 250         },
 251         .uart_param = {
 252                 .uart_name = "ttySiRF",
 253                 .port_name = "sirfsoc_uart",
 254         },
 255 };
 256 /* uart io ctrl */
 257 #define SIRFUART_DATA_BIT_LEN_MASK              0x3
 258 #define SIRFUART_DATA_BIT_LEN_5                 BIT(0)
 259 #define SIRFUART_DATA_BIT_LEN_6                 1
 260 #define SIRFUART_DATA_BIT_LEN_7                 2
 261 #define SIRFUART_DATA_BIT_LEN_8                 3
 262 #define SIRFUART_STOP_BIT_LEN_1                 0
 263 #define SIRFUART_STOP_BIT_LEN_2                 BIT(2)
 264 #define SIRFUART_PARITY_EN                      BIT(3)
 265 #define SIRFUART_EVEN_BIT                       BIT(4)
 266 #define SIRFUART_STICK_BIT_MASK                 (7 << 3)
 267 #define SIRFUART_STICK_BIT_NONE                 (0 << 3)
 268 #define SIRFUART_STICK_BIT_EVEN                 BIT(3)
 269 #define SIRFUART_STICK_BIT_ODD                  (3 << 3)
 270 #define SIRFUART_STICK_BIT_MARK                 (5 << 3)
 271 #define SIRFUART_STICK_BIT_SPACE                (7 << 3)
 272 #define SIRFUART_SET_BREAK                      BIT(6)
 273 #define SIRFUART_LOOP_BACK                      BIT(7)
 274 #define SIRFUART_PARITY_MASK                    (7 << 3)
 275 #define SIRFUART_DUMMY_READ                     BIT(16)
 276 #define SIRFUART_AFC_CTRL_RX_THD                0x70
 277 #define SIRFUART_AFC_RX_EN                      BIT(8)
 278 #define SIRFUART_AFC_TX_EN                      BIT(9)
 279 #define SIRFUART_AFC_CTS_CTRL                   BIT(10)
 280 #define SIRFUART_AFC_RTS_CTRL                   BIT(11)
 281 #define SIRFUART_AFC_CTS_STATUS                 BIT(12)
 282 #define SIRFUART_AFC_RTS_STATUS                 BIT(13)
 283 /* UART FIFO Register */
 284 #define SIRFUART_FIFO_STOP                      0x0
 285 #define SIRFUART_FIFO_RESET                     BIT(0)
 286 #define SIRFUART_FIFO_START                     BIT(1)
 287
 288 #define SIRFUART_RX_EN                          BIT(0)
 289 #define SIRFUART_TX_EN                          BIT(1)
 290
 291 #define SIRFUART_IO_MODE                        BIT(0)
 292 #define SIRFUART_DMA_MODE                       0x0
 293
 294 /* Macro Specific*/
 295 #define SIRFUART_INT_EN_CLR                    0x0060
 296 /* Baud Rate Calculation */
 297 #define SIRF_USP_MIN_SAMPLE_DIV                 0x1
 298 #define SIRF_MIN_SAMPLE_DIV                     0xf
 299 #define SIRF_MAX_SAMPLE_DIV                     0x3f
 300 #define SIRF_IOCLK_DIV_MAX                      0xffff
 301 #define SIRF_SAMPLE_DIV_SHIFT                   16
 302 #define SIRF_IOCLK_DIV_MASK                     0xffff
 303 #define SIRF_SAMPLE_DIV_MASK                    0x3f0000
 304 #define SIRF_BAUD_RATE_SUPPORT_NR               18
 305
 306 /* USP SPEC */
 307 #define SIRFSOC_USP_ENDIAN_CTRL_LSBF            BIT(4)
 308 #define SIRFSOC_USP_EN                          BIT(5)
 309 #define SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET      0
 310 #define SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET      8
 311 #define SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK      0x3ff
 312 #define SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET    21
 313 #define SIRFSOC_USP_TX_DATA_LEN_OFFSET          0
 314 #define SIRFSOC_USP_TX_SYNC_LEN_OFFSET          8
 315 #define SIRFSOC_USP_TX_FRAME_LEN_OFFSET         16
 316 #define SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET       24
 317 #define SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET       30
 318 #define SIRFSOC_USP_RX_DATA_LEN_OFFSET          0
 319 #define SIRFSOC_USP_RX_FRAME_LEN_OFFSET         8
 320 #define SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET       16
 321 #define SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET       24
 322 #define SIRFSOC_USP_ASYNC_DIV2_MASK             0x3f
 323 #define SIRFSOC_USP_ASYNC_DIV2_OFFSET           16
 324
 325 /* USP-UART Common */
 326 #define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000)
 327 #define SIRFUART_RECV_TIMEOUT_VALUE(x)  \
 328                                 (((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))
 329 #define SIRFUART_RECV_TIMEOUT(port, x)  \
 330                 (((port)->line > 2) ? (x & 0xFFFF) : ((x) & 0xFFFF) << 16)
 331
 332 #define SIRFUART_FIFO_THD(port)         (port->fifosize >> 1)
 333 #define SIRFUART_ERR_INT_STAT(port, unit_st)                    \
 334                                 (uint_st->sirfsoc_rx_oflow |            \
 335                                 uint_st->sirfsoc_frm_err |              \
 336                                 uint_st->sirfsoc_rxd_brk |              \
 337                 ((port->line > 2) ? 0 : uint_st->sirfsoc_parity_err))
 338 #define SIRFUART_RX_IO_INT_EN(port, uint_en)                            \
 339                                 (uint_en->sirfsoc_rx_timeout_en |\
 340                                  uint_en->sirfsoc_rxfifo_thd_en |\
 341                                  uint_en->sirfsoc_rxfifo_full_en |\
 342                                  uint_en->sirfsoc_frm_err_en |\
 343                                  uint_en->sirfsoc_rx_oflow_en |\
 344                                  uint_en->sirfsoc_rxd_brk_en |\
 345                 ((port->line > 2) ? 0 : uint_en->sirfsoc_parity_err_en))
 346 #define SIRFUART_RX_IO_INT_ST(uint_st)                          \
 347                                 (uint_st->sirfsoc_rx_timeout |\
 348                                  uint_st->sirfsoc_rxfifo_thd |\
 349                                  uint_st->sirfsoc_rxfifo_full)
 350 #define SIRFUART_CTS_INT_ST(uint_st)    (uint_st->sirfsoc_cts)
 351 #define SIRFUART_RX_DMA_INT_EN(port, uint_en)                           \
 352                                 (uint_en->sirfsoc_rx_timeout_en |\
 353                                  uint_en->sirfsoc_frm_err_en |\
 354                                  uint_en->sirfsoc_rx_oflow_en |\
 355                                  uint_en->sirfsoc_rxd_brk_en |\
 356                 ((port->line > 2) ? 0 : uint_en->sirfsoc_parity_err_en))
 357 /* Generic Definitions */
 358 #define SIRFSOC_UART_NAME                       "ttySiRF"
 359 #define SIRFSOC_UART_MAJOR                      0
 360 #define SIRFSOC_UART_MINOR                      0
 361 #define SIRFUART_PORT_NAME                      "sirfsoc-uart"
 362 #define SIRFUART_MAP_SIZE                       0x200
 363 #define SIRFSOC_UART_NR                         11
 364 #define SIRFSOC_PORT_TYPE                       0xa5
 365
 366 /* Uart Common Use Macro*/
 367 #define SIRFSOC_RX_DMA_BUF_SIZE 256
 368 #define BYTES_TO_ALIGN(dma_addr)        ((unsigned long)(dma_addr) & 0x3)
 369 /* Uart Fifo Level Chk */
 370 #define SIRFUART_TX_FIFO_SC_OFFSET      0
 371 #define SIRFUART_TX_FIFO_LC_OFFSET      10
 372 #define SIRFUART_TX_FIFO_HC_OFFSET      20
 373 #define SIRFUART_TX_FIFO_CHK_SC(line, value) ((((line) == 1) ? (value & 0x3) :\
 374                                 (value & 0x1f)) << SIRFUART_TX_FIFO_SC_OFFSET)
 375 #define SIRFUART_TX_FIFO_CHK_LC(line, value) ((((line) == 1) ? (value & 0x3) :\
 376                                 (value & 0x1f)) << SIRFUART_TX_FIFO_LC_OFFSET)
 377 #define SIRFUART_TX_FIFO_CHK_HC(line, value) ((((line) == 1) ? (value & 0x3) :\
 378                                 (value & 0x1f)) << SIRFUART_TX_FIFO_HC_OFFSET)
 379
 380 #define SIRFUART_RX_FIFO_CHK_SC SIRFUART_TX_FIFO_CHK_SC
 381 #define SIRFUART_RX_FIFO_CHK_LC SIRFUART_TX_FIFO_CHK_LC
 382 #define SIRFUART_RX_FIFO_CHK_HC SIRFUART_TX_FIFO_CHK_HC
 383 /* Indicate how many buffers used */
 384 #define SIRFSOC_RX_LOOP_BUF_CNT         2
 385
 386 /* For Fast Baud Rate Calculation */
 387 struct sirfsoc_baudrate_to_regv {
 388         unsigned int baud_rate;
 389         unsigned int reg_val;
 390 };
 391
 392 enum sirfsoc_tx_state {
 393         TX_DMA_IDLE,
 394         TX_DMA_RUNNING,
 395         TX_DMA_PAUSE,
 396 };
 397
 398 struct sirfsoc_loop_buffer {
 399         struct circ_buf                 xmit;
 400         dma_cookie_t                    cookie;
 401         struct dma_async_tx_descriptor  *desc;
 402         dma_addr_t                      dma_addr;
 403 };
 404
 405 struct sirfsoc_uart_port {
 406         bool                            hw_flow_ctrl;
 407         bool                            ms_enabled;
 408
 409         struct uart_port                port;
 410         struct clk                      *clk;
 411         /* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
 412         bool                            is_atlas7;
 413         struct sirfsoc_uart_register    *uart_reg;
 414         struct dma_chan                 *rx_dma_chan;
 415         struct dma_chan                 *tx_dma_chan;
 416         dma_addr_t                      tx_dma_addr;
 417         struct dma_async_tx_descriptor  *tx_dma_desc;
 418         struct tasklet_struct           rx_dma_complete_tasklet;
 419         struct tasklet_struct           rx_tmo_process_tasklet;
 420         unsigned int                    rx_io_count;
 421         unsigned long                   transfer_size;
 422         enum sirfsoc_tx_state           tx_dma_state;
 423         unsigned int                    cts_gpio;
 424         unsigned int                    rts_gpio;
 425
 426         struct sirfsoc_loop_buffer      rx_dma_items[SIRFSOC_RX_LOOP_BUF_CNT];
 427         int                             rx_completed;
 428         int                             rx_issued;
 429 };
 430
 431 /* Register Access Control */
 432 #define portaddr(port, reg)             ((port)->membase + (reg))
 433 #define rd_regl(port, reg)              (__raw_readl(portaddr(port, reg)))
 434 #define wr_regl(port, reg, val)         __raw_writel(val, portaddr(port, reg))
 435
 436 /* UART Port Mask */
 437 #define SIRFUART_FIFOLEVEL_MASK(port)   ((port->fifosize - 1) & 0xFFF)
 438 #define SIRFUART_FIFOFULL_MASK(port)    (port->fifosize & 0xFFF)
 439 #define SIRFUART_FIFOEMPTY_MASK(port)   ((port->fifosize & 0xFFF) << 1)