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tty: xuartps: Fix "may be used uninitialized" build warning
[deliverable/linux.git] / drivers / tty / serial / xilinx_uartps.c
1 /*
2 * Xilinx PS UART driver
3 *
4 * 2011 - 2013 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #define SUPPORT_SYSRQ
16 #endif
17
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/clk.h>
26 #include <linux/irq.h>
27 #include <linux/io.h>
28 #include <linux/of.h>
29 #include <linux/module.h>
30
31 #define XUARTPS_TTY_NAME "ttyPS"
32 #define XUARTPS_NAME "xuartps"
33 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34 #define XUARTPS_MINOR 0 /* works best with devtmpfs */
35 #define XUARTPS_NR_PORTS 2
36 #define XUARTPS_FIFO_SIZE 64 /* FIFO size */
37 #define XUARTPS_REGISTER_SPACE 0xFFF
38
39 #define xuartps_readl(offset) ioread32(port->membase + offset)
40 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
41
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47 /* Rx Timeout */
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52 /********************************Register Map********************************/
53 /** UART
54 *
55 * Register offsets for the UART.
56 *
57 */
58 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
59 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
60 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
61 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
62 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
63 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
64 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
65 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
66 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
67 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
68 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
69 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
70 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
71 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
72 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
73 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
74 Width [15:0] */
75 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
76 Width [7:0] */
77 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
78
79 /** Control Register
80 *
81 * The Control register (CR) controls the major functions of the device.
82 *
83 * Control Register Bit Definitions
84 */
85 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
94
95 /** Mode Register
96 *
97 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed.
100 *
101 * Mode Register Bit Definitions
102 *
103 */
104 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
107
108 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
110
111 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
112 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
116
117 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
120
121 /** Interrupt Registers
122 *
123 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an
126 * interrupt to the interrupt status register (ISR).
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00.
130 *
131 * All four registers have the same bit definitions.
132 */
133 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
135 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
144
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define XUARTPS_IXR_BRK 0x80000000
147
148 /** Channel Status Register
149 *
150 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register.
153 */
154 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
157 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
158
159 /* baud dividers min/max values */
160 #define XUARTPS_BDIV_MIN 4
161 #define XUARTPS_BDIV_MAX 255
162 #define XUARTPS_CD_MAX 65535
163
164 /**
165 * struct xuartps - device data
166 * @port Pointer to the UART port
167 * @refclk Reference clock
168 * @aperclk APB clock
169 * @baud Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes
171 */
172 struct xuartps {
173 struct uart_port *port;
174 struct clk *refclk;
175 struct clk *aperclk;
176 unsigned int baud;
177 struct notifier_block clk_rate_change_nb;
178 };
179 #define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
180
181 /**
182 * xuartps_isr - Interrupt handler
183 * @irq: Irq number
184 * @dev_id: Id of the port
185 *
186 * Returns IRQHANDLED
187 **/
188 static irqreturn_t xuartps_isr(int irq, void *dev_id)
189 {
190 struct uart_port *port = (struct uart_port *)dev_id;
191 unsigned long flags;
192 unsigned int isrstatus, numbytes;
193 unsigned int data;
194 char status = TTY_NORMAL;
195
196 spin_lock_irqsave(&port->lock, flags);
197
198 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active.
200 */
201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
202
203 /*
204 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence.
207 */
208
209 if (isrstatus & XUARTPS_IXR_FRAMING) {
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
211 XUARTPS_SR_RXEMPTY)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
213 port->read_status_mask |= XUARTPS_IXR_BRK;
214 isrstatus &= ~XUARTPS_IXR_FRAMING;
215 }
216 }
217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
218 }
219
220 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
223
224 isrstatus &= port->read_status_mask;
225 isrstatus &= ~port->ignore_status_mask;
226
227 if ((isrstatus & XUARTPS_IXR_TOUT) ||
228 (isrstatus & XUARTPS_IXR_RXTRIG)) {
229 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
232 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
233
234 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask &
236 XUARTPS_IXR_BRK)) {
237 port->read_status_mask &= ~XUARTPS_IXR_BRK;
238 port->icount.brk++;
239 if (uart_handle_break(port))
240 continue;
241 }
242
243 /*
244 * uart_handle_sysrq_char() doesn't work if
245 * spinlocked, for some reason
246 */
247 if (port->sysrq) {
248 spin_unlock(&port->lock);
249 if (uart_handle_sysrq_char(port,
250 (unsigned char)data)) {
251 spin_lock(&port->lock);
252 continue;
253 }
254 spin_lock(&port->lock);
255 }
256
257 port->icount.rx++;
258
259 if (isrstatus & XUARTPS_IXR_PARITY) {
260 port->icount.parity++;
261 status = TTY_PARITY;
262 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
263 port->icount.frame++;
264 status = TTY_FRAME;
265 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
266 port->icount.overrun++;
267
268 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
269 data, status);
270 }
271 spin_unlock(&port->lock);
272 tty_flip_buffer_push(&port->state->port);
273 spin_lock(&port->lock);
274 }
275
276 /* Dispatch an appropriate handler */
277 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
278 if (uart_circ_empty(&port->state->xmit)) {
279 xuartps_writel(XUARTPS_IXR_TXEMPTY,
280 XUARTPS_IDR_OFFSET);
281 } else {
282 numbytes = port->fifosize;
283 /* Break if no more data available in the UART buffer */
284 while (numbytes--) {
285 if (uart_circ_empty(&port->state->xmit))
286 break;
287 /* Get the data from the UART circular buffer
288 * and write it to the xuartps's TX_FIFO
289 * register.
290 */
291 xuartps_writel(
292 port->state->xmit.buf[port->state->xmit.
293 tail], XUARTPS_FIFO_OFFSET);
294
295 port->icount.tx++;
296
297 /* Adjust the tail of the UART buffer and wrap
298 * the buffer if it reaches limit.
299 */
300 port->state->xmit.tail =
301 (port->state->xmit.tail + 1) & \
302 (UART_XMIT_SIZE - 1);
303 }
304
305 if (uart_circ_chars_pending(
306 &port->state->xmit) < WAKEUP_CHARS)
307 uart_write_wakeup(port);
308 }
309 }
310
311 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
312
313 /* be sure to release the lock and tty before leaving */
314 spin_unlock_irqrestore(&port->lock, flags);
315
316 return IRQ_HANDLED;
317 }
318
319 /**
320 * xuartps_calc_baud_divs - Calculate baud rate divisors
321 * @clk: UART module input clock
322 * @baud: Desired baud rate
323 * @rbdiv: BDIV value (return value)
324 * @rcd: CD value (return value)
325 * @div8: Value for clk_sel bit in mod (return value)
326 * Returns baud rate, requested baud when possible, or actual baud when there
327 * was too much error, zero if no valid divisors are found.
328 *
329 * Formula to obtain baud rate is
330 * baud_tx/rx rate = clk/CD * (BDIV + 1)
331 * input_clk = (Uart User Defined Clock or Apb Clock)
332 * depends on UCLKEN in MR Reg
333 * clk = input_clk or input_clk/8;
334 * depends on CLKS in MR reg
335 * CD and BDIV depends on values in
336 * baud rate generate register
337 * baud rate clock divisor register
338 */
339 static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
340 u32 *rbdiv, u32 *rcd, int *div8)
341 {
342 u32 cd, bdiv;
343 unsigned int calc_baud;
344 unsigned int bestbaud = 0;
345 unsigned int bauderror;
346 unsigned int besterror = ~0;
347
348 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) {
349 *div8 = 1;
350 clk /= 8;
351 } else {
352 *div8 = 0;
353 }
354
355 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) {
356 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
357 if (cd < 1 || cd > XUARTPS_CD_MAX)
358 continue;
359
360 calc_baud = clk / (cd * (bdiv + 1));
361
362 if (baud > calc_baud)
363 bauderror = baud - calc_baud;
364 else
365 bauderror = calc_baud - baud;
366
367 if (besterror > bauderror) {
368 *rbdiv = bdiv;
369 *rcd = cd;
370 bestbaud = calc_baud;
371 besterror = bauderror;
372 }
373 }
374 /* use the values when percent error is acceptable */
375 if (((besterror * 100) / baud) < 3)
376 bestbaud = baud;
377
378 return bestbaud;
379 }
380
381 /**
382 * xuartps_set_baud_rate - Calculate and set the baud rate
383 * @port: Handle to the uart port structure
384 * @baud: Baud rate to set
385 * Returns baud rate, requested baud when possible, or actual baud when there
386 * was too much error, zero if no valid divisors are found.
387 */
388 static unsigned int xuartps_set_baud_rate(struct uart_port *port,
389 unsigned int baud)
390 {
391 unsigned int calc_baud;
392 u32 cd = 0, bdiv = 0;
393 u32 mreg;
394 int div8;
395 struct xuartps *xuartps = port->private_data;
396
397 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
398 &div8);
399
400 /* Write new divisors to hardware */
401 mreg = xuartps_readl(XUARTPS_MR_OFFSET);
402 if (div8)
403 mreg |= XUARTPS_MR_CLKSEL;
404 else
405 mreg &= ~XUARTPS_MR_CLKSEL;
406 xuartps_writel(mreg, XUARTPS_MR_OFFSET);
407 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET);
408 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET);
409 xuartps->baud = baud;
410
411 return calc_baud;
412 }
413
414 /**
415 * xuartps_clk_notitifer_cb - Clock notifier callback
416 * @nb: Notifier block
417 * @event: Notify event
418 * @data: Notifier data
419 * Returns NOTIFY_OK on success, NOTIFY_BAD on error.
420 */
421 static int xuartps_clk_notifier_cb(struct notifier_block *nb,
422 unsigned long event, void *data)
423 {
424 u32 ctrl_reg;
425 struct uart_port *port;
426 int locked = 0;
427 struct clk_notifier_data *ndata = data;
428 unsigned long flags = 0;
429 struct xuartps *xuartps = to_xuartps(nb);
430
431 port = xuartps->port;
432 if (port->suspended)
433 return NOTIFY_OK;
434
435 switch (event) {
436 case PRE_RATE_CHANGE:
437 {
438 u32 bdiv;
439 u32 cd;
440 int div8;
441
442 /*
443 * Find out if current baud-rate can be achieved with new clock
444 * frequency.
445 */
446 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud,
447 &bdiv, &cd, &div8))
448 return NOTIFY_BAD;
449
450 spin_lock_irqsave(&xuartps->port->lock, flags);
451
452 /* Disable the TX and RX to set baud rate */
453 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
454 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
455 XUARTPS_CR_OFFSET);
456
457 spin_unlock_irqrestore(&xuartps->port->lock, flags);
458
459 return NOTIFY_OK;
460 }
461 case POST_RATE_CHANGE:
462 /*
463 * Set clk dividers to generate correct baud with new clock
464 * frequency.
465 */
466
467 spin_lock_irqsave(&xuartps->port->lock, flags);
468
469 locked = 1;
470 port->uartclk = ndata->new_rate;
471
472 xuartps->baud = xuartps_set_baud_rate(xuartps->port,
473 xuartps->baud);
474 /* fall through */
475 case ABORT_RATE_CHANGE:
476 if (!locked)
477 spin_lock_irqsave(&xuartps->port->lock, flags);
478
479 /* Set TX/RX Reset */
480 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
481 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
482 XUARTPS_CR_OFFSET);
483
484 while (xuartps_readl(XUARTPS_CR_OFFSET) &
485 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
486 cpu_relax();
487
488 /*
489 * Clear the RX disable and TX disable bits and then set the TX
490 * enable bit and RX enable bit to enable the transmitter and
491 * receiver.
492 */
493 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
494 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
495 xuartps_writel(
496 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
497 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
498 XUARTPS_CR_OFFSET);
499
500 spin_unlock_irqrestore(&xuartps->port->lock, flags);
501
502 return NOTIFY_OK;
503 default:
504 return NOTIFY_DONE;
505 }
506 }
507
508 /*----------------------Uart Operations---------------------------*/
509
510 /**
511 * xuartps_start_tx - Start transmitting bytes
512 * @port: Handle to the uart port structure
513 *
514 **/
515 static void xuartps_start_tx(struct uart_port *port)
516 {
517 unsigned int status, numbytes = port->fifosize;
518
519 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
520 return;
521
522 status = xuartps_readl(XUARTPS_CR_OFFSET);
523 /* Set the TX enable bit and clear the TX disable bit to enable the
524 * transmitter.
525 */
526 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
527 XUARTPS_CR_OFFSET);
528
529 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
530 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
531
532 /* Break if no more data available in the UART buffer */
533 if (uart_circ_empty(&port->state->xmit))
534 break;
535
536 /* Get the data from the UART circular buffer and
537 * write it to the xuartps's TX_FIFO register.
538 */
539 xuartps_writel(
540 port->state->xmit.buf[port->state->xmit.tail],
541 XUARTPS_FIFO_OFFSET);
542 port->icount.tx++;
543
544 /* Adjust the tail of the UART buffer and wrap
545 * the buffer if it reaches limit.
546 */
547 port->state->xmit.tail = (port->state->xmit.tail + 1) &
548 (UART_XMIT_SIZE - 1);
549 }
550 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
551 /* Enable the TX Empty interrupt */
552 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
553
554 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
555 uart_write_wakeup(port);
556 }
557
558 /**
559 * xuartps_stop_tx - Stop TX
560 * @port: Handle to the uart port structure
561 *
562 **/
563 static void xuartps_stop_tx(struct uart_port *port)
564 {
565 unsigned int regval;
566
567 regval = xuartps_readl(XUARTPS_CR_OFFSET);
568 regval |= XUARTPS_CR_TX_DIS;
569 /* Disable the transmitter */
570 xuartps_writel(regval, XUARTPS_CR_OFFSET);
571 }
572
573 /**
574 * xuartps_stop_rx - Stop RX
575 * @port: Handle to the uart port structure
576 *
577 **/
578 static void xuartps_stop_rx(struct uart_port *port)
579 {
580 unsigned int regval;
581
582 regval = xuartps_readl(XUARTPS_CR_OFFSET);
583 regval |= XUARTPS_CR_RX_DIS;
584 /* Disable the receiver */
585 xuartps_writel(regval, XUARTPS_CR_OFFSET);
586 }
587
588 /**
589 * xuartps_tx_empty - Check whether TX is empty
590 * @port: Handle to the uart port structure
591 *
592 * Returns TIOCSER_TEMT on success, 0 otherwise
593 **/
594 static unsigned int xuartps_tx_empty(struct uart_port *port)
595 {
596 unsigned int status;
597
598 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
599 return status ? TIOCSER_TEMT : 0;
600 }
601
602 /**
603 * xuartps_break_ctl - Based on the input ctl we have to start or stop
604 * transmitting char breaks
605 * @port: Handle to the uart port structure
606 * @ctl: Value based on which start or stop decision is taken
607 *
608 **/
609 static void xuartps_break_ctl(struct uart_port *port, int ctl)
610 {
611 unsigned int status;
612 unsigned long flags;
613
614 spin_lock_irqsave(&port->lock, flags);
615
616 status = xuartps_readl(XUARTPS_CR_OFFSET);
617
618 if (ctl == -1)
619 xuartps_writel(XUARTPS_CR_STARTBRK | status,
620 XUARTPS_CR_OFFSET);
621 else {
622 if ((status & XUARTPS_CR_STOPBRK) == 0)
623 xuartps_writel(XUARTPS_CR_STOPBRK | status,
624 XUARTPS_CR_OFFSET);
625 }
626 spin_unlock_irqrestore(&port->lock, flags);
627 }
628
629 /**
630 * xuartps_set_termios - termios operations, handling data length, parity,
631 * stop bits, flow control, baud rate
632 * @port: Handle to the uart port structure
633 * @termios: Handle to the input termios structure
634 * @old: Values of the previously saved termios structure
635 *
636 **/
637 static void xuartps_set_termios(struct uart_port *port,
638 struct ktermios *termios, struct ktermios *old)
639 {
640 unsigned int cval = 0;
641 unsigned int baud, minbaud, maxbaud;
642 unsigned long flags;
643 unsigned int ctrl_reg, mode_reg;
644
645 spin_lock_irqsave(&port->lock, flags);
646
647 /* Empty the receive FIFO 1st before making changes */
648 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
649 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
650 xuartps_readl(XUARTPS_FIFO_OFFSET);
651 }
652
653 /* Disable the TX and RX to set baud rate */
654 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
655 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
656 XUARTPS_CR_OFFSET);
657
658 /*
659 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
660 * min and max baud should be calculated here based on port->uartclk.
661 * this way we get a valid baud and can safely call set_baud()
662 */
663 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8);
664 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1);
665 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
666 baud = xuartps_set_baud_rate(port, baud);
667 if (tty_termios_baud_rate(termios))
668 tty_termios_encode_baud_rate(termios, baud, baud);
669
670 /*
671 * Update the per-port timeout.
672 */
673 uart_update_timeout(port, termios->c_cflag, baud);
674
675 /* Set TX/RX Reset */
676 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
677 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
678 XUARTPS_CR_OFFSET);
679
680 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
681
682 /* Clear the RX disable and TX disable bits and then set the TX enable
683 * bit and RX enable bit to enable the transmitter and receiver.
684 */
685 xuartps_writel(
686 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
687 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
688 XUARTPS_CR_OFFSET);
689
690 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
691
692 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
693 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
694 port->ignore_status_mask = 0;
695
696 if (termios->c_iflag & INPCK)
697 port->read_status_mask |= XUARTPS_IXR_PARITY |
698 XUARTPS_IXR_FRAMING;
699
700 if (termios->c_iflag & IGNPAR)
701 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
702 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
703
704 /* ignore all characters if CREAD is not set */
705 if ((termios->c_cflag & CREAD) == 0)
706 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
707 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
708 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
709
710 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
711
712 /* Handling Data Size */
713 switch (termios->c_cflag & CSIZE) {
714 case CS6:
715 cval |= XUARTPS_MR_CHARLEN_6_BIT;
716 break;
717 case CS7:
718 cval |= XUARTPS_MR_CHARLEN_7_BIT;
719 break;
720 default:
721 case CS8:
722 cval |= XUARTPS_MR_CHARLEN_8_BIT;
723 termios->c_cflag &= ~CSIZE;
724 termios->c_cflag |= CS8;
725 break;
726 }
727
728 /* Handling Parity and Stop Bits length */
729 if (termios->c_cflag & CSTOPB)
730 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
731 else
732 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
733
734 if (termios->c_cflag & PARENB) {
735 /* Mark or Space parity */
736 if (termios->c_cflag & CMSPAR) {
737 if (termios->c_cflag & PARODD)
738 cval |= XUARTPS_MR_PARITY_MARK;
739 else
740 cval |= XUARTPS_MR_PARITY_SPACE;
741 } else {
742 if (termios->c_cflag & PARODD)
743 cval |= XUARTPS_MR_PARITY_ODD;
744 else
745 cval |= XUARTPS_MR_PARITY_EVEN;
746 }
747 } else {
748 cval |= XUARTPS_MR_PARITY_NONE;
749 }
750 cval |= mode_reg & 1;
751 xuartps_writel(cval, XUARTPS_MR_OFFSET);
752
753 spin_unlock_irqrestore(&port->lock, flags);
754 }
755
756 /**
757 * xuartps_startup - Called when an application opens a xuartps port
758 * @port: Handle to the uart port structure
759 *
760 * Returns 0 on success, negative error otherwise
761 **/
762 static int xuartps_startup(struct uart_port *port)
763 {
764 unsigned int retval = 0, status = 0;
765
766 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
767 (void *)port);
768 if (retval)
769 return retval;
770
771 /* Disable the TX and RX */
772 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
773 XUARTPS_CR_OFFSET);
774
775 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
776 * no break chars.
777 */
778 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
779 XUARTPS_CR_OFFSET);
780
781 status = xuartps_readl(XUARTPS_CR_OFFSET);
782
783 /* Clear the RX disable and TX disable bits and then set the TX enable
784 * bit and RX enable bit to enable the transmitter and receiver.
785 */
786 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
787 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
788 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
789
790 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
791 * no parity.
792 */
793 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
794 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
795 XUARTPS_MR_OFFSET);
796
797 /*
798 * Set the RX FIFO Trigger level to use most of the FIFO, but it
799 * can be tuned with a module parameter
800 */
801 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
802
803 /*
804 * Receive Timeout register is enabled but it
805 * can be tuned with a module parameter
806 */
807 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
808
809 /* Clear out any pending interrupts before enabling them */
810 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
811
812 /* Set the Interrupt Registers with desired interrupts */
813 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
814 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
815 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
816
817 return retval;
818 }
819
820 /**
821 * xuartps_shutdown - Called when an application closes a xuartps port
822 * @port: Handle to the uart port structure
823 *
824 **/
825 static void xuartps_shutdown(struct uart_port *port)
826 {
827 int status;
828
829 /* Disable interrupts */
830 status = xuartps_readl(XUARTPS_IMR_OFFSET);
831 xuartps_writel(status, XUARTPS_IDR_OFFSET);
832
833 /* Disable the TX and RX */
834 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
835 XUARTPS_CR_OFFSET);
836 free_irq(port->irq, port);
837 }
838
839 /**
840 * xuartps_type - Set UART type to xuartps port
841 * @port: Handle to the uart port structure
842 *
843 * Returns string on success, NULL otherwise
844 **/
845 static const char *xuartps_type(struct uart_port *port)
846 {
847 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
848 }
849
850 /**
851 * xuartps_verify_port - Verify the port params
852 * @port: Handle to the uart port structure
853 * @ser: Handle to the structure whose members are compared
854 *
855 * Returns 0 if success otherwise -EINVAL
856 **/
857 static int xuartps_verify_port(struct uart_port *port,
858 struct serial_struct *ser)
859 {
860 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
861 return -EINVAL;
862 if (port->irq != ser->irq)
863 return -EINVAL;
864 if (ser->io_type != UPIO_MEM)
865 return -EINVAL;
866 if (port->iobase != ser->port)
867 return -EINVAL;
868 if (ser->hub6 != 0)
869 return -EINVAL;
870 return 0;
871 }
872
873 /**
874 * xuartps_request_port - Claim the memory region attached to xuartps port,
875 * called when the driver adds a xuartps port via
876 * uart_add_one_port()
877 * @port: Handle to the uart port structure
878 *
879 * Returns 0, -ENOMEM if request fails
880 **/
881 static int xuartps_request_port(struct uart_port *port)
882 {
883 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
884 XUARTPS_NAME)) {
885 return -ENOMEM;
886 }
887
888 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
889 if (!port->membase) {
890 dev_err(port->dev, "Unable to map registers\n");
891 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
892 return -ENOMEM;
893 }
894 return 0;
895 }
896
897 /**
898 * xuartps_release_port - Release the memory region attached to a xuartps
899 * port, called when the driver removes a xuartps
900 * port via uart_remove_one_port().
901 * @port: Handle to the uart port structure
902 *
903 **/
904 static void xuartps_release_port(struct uart_port *port)
905 {
906 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
907 iounmap(port->membase);
908 port->membase = NULL;
909 }
910
911 /**
912 * xuartps_config_port - Configure xuartps, called when the driver adds a
913 * xuartps port
914 * @port: Handle to the uart port structure
915 * @flags: If any
916 *
917 **/
918 static void xuartps_config_port(struct uart_port *port, int flags)
919 {
920 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
921 port->type = PORT_XUARTPS;
922 }
923
924 /**
925 * xuartps_get_mctrl - Get the modem control state
926 *
927 * @port: Handle to the uart port structure
928 *
929 * Returns the modem control state
930 *
931 **/
932 static unsigned int xuartps_get_mctrl(struct uart_port *port)
933 {
934 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
935 }
936
937 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
938 {
939 /* N/A */
940 }
941
942 static void xuartps_enable_ms(struct uart_port *port)
943 {
944 /* N/A */
945 }
946
947 #ifdef CONFIG_CONSOLE_POLL
948 static int xuartps_poll_get_char(struct uart_port *port)
949 {
950 u32 imr;
951 int c;
952
953 /* Disable all interrupts */
954 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
955 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
956
957 /* Check if FIFO is empty */
958 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
959 c = NO_POLL_CHAR;
960 else /* Read a character */
961 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
962
963 /* Enable interrupts */
964 xuartps_writel(imr, XUARTPS_IER_OFFSET);
965
966 return c;
967 }
968
969 static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
970 {
971 u32 imr;
972
973 /* Disable all interrupts */
974 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
975 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
976
977 /* Wait until FIFO is empty */
978 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
979 cpu_relax();
980
981 /* Write a character */
982 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
983
984 /* Wait until FIFO is empty */
985 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
986 cpu_relax();
987
988 /* Enable interrupts */
989 xuartps_writel(imr, XUARTPS_IER_OFFSET);
990
991 return;
992 }
993 #endif
994
995 /** The UART operations structure
996 */
997 static struct uart_ops xuartps_ops = {
998 .set_mctrl = xuartps_set_mctrl,
999 .get_mctrl = xuartps_get_mctrl,
1000 .enable_ms = xuartps_enable_ms,
1001
1002 .start_tx = xuartps_start_tx, /* Start transmitting */
1003 .stop_tx = xuartps_stop_tx, /* Stop transmission */
1004 .stop_rx = xuartps_stop_rx, /* Stop reception */
1005 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
1006 .break_ctl = xuartps_break_ctl, /* Start/stop
1007 * transmitting break
1008 */
1009 .set_termios = xuartps_set_termios, /* Set termios */
1010 .startup = xuartps_startup, /* App opens xuartps */
1011 .shutdown = xuartps_shutdown, /* App closes xuartps */
1012 .type = xuartps_type, /* Set UART type */
1013 .verify_port = xuartps_verify_port, /* Verification of port
1014 * params
1015 */
1016 .request_port = xuartps_request_port, /* Claim resources
1017 * associated with a
1018 * xuartps port
1019 */
1020 .release_port = xuartps_release_port, /* Release resources
1021 * associated with a
1022 * xuartps port
1023 */
1024 .config_port = xuartps_config_port, /* Configure when driver
1025 * adds a xuartps port
1026 */
1027 #ifdef CONFIG_CONSOLE_POLL
1028 .poll_get_char = xuartps_poll_get_char,
1029 .poll_put_char = xuartps_poll_put_char,
1030 #endif
1031 };
1032
1033 static struct uart_port xuartps_port[2];
1034
1035 /**
1036 * xuartps_get_port - Configure the port from the platform device resource
1037 * info
1038 *
1039 * Returns a pointer to a uart_port or NULL for failure
1040 **/
1041 static struct uart_port *xuartps_get_port(void)
1042 {
1043 struct uart_port *port;
1044 int id;
1045
1046 /* Find the next unused port */
1047 for (id = 0; id < XUARTPS_NR_PORTS; id++)
1048 if (xuartps_port[id].mapbase == 0)
1049 break;
1050
1051 if (id >= XUARTPS_NR_PORTS)
1052 return NULL;
1053
1054 port = &xuartps_port[id];
1055
1056 /* At this point, we've got an empty uart_port struct, initialize it */
1057 spin_lock_init(&port->lock);
1058 port->membase = NULL;
1059 port->iobase = 1; /* mark port in use */
1060 port->irq = 0;
1061 port->type = PORT_UNKNOWN;
1062 port->iotype = UPIO_MEM32;
1063 port->flags = UPF_BOOT_AUTOCONF;
1064 port->ops = &xuartps_ops;
1065 port->fifosize = XUARTPS_FIFO_SIZE;
1066 port->line = id;
1067 port->dev = NULL;
1068 return port;
1069 }
1070
1071 /*-----------------------Console driver operations--------------------------*/
1072
1073 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1074 /**
1075 * xuartps_console_wait_tx - Wait for the TX to be full
1076 * @port: Handle to the uart port structure
1077 *
1078 **/
1079 static void xuartps_console_wait_tx(struct uart_port *port)
1080 {
1081 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
1082 != XUARTPS_SR_TXEMPTY)
1083 barrier();
1084 }
1085
1086 /**
1087 * xuartps_console_putchar - write the character to the FIFO buffer
1088 * @port: Handle to the uart port structure
1089 * @ch: Character to be written
1090 *
1091 **/
1092 static void xuartps_console_putchar(struct uart_port *port, int ch)
1093 {
1094 xuartps_console_wait_tx(port);
1095 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
1096 }
1097
1098 /**
1099 * xuartps_console_write - perform write operation
1100 * @port: Handle to the uart port structure
1101 * @s: Pointer to character array
1102 * @count: No of characters
1103 **/
1104 static void xuartps_console_write(struct console *co, const char *s,
1105 unsigned int count)
1106 {
1107 struct uart_port *port = &xuartps_port[co->index];
1108 unsigned long flags;
1109 unsigned int imr, ctrl;
1110 int locked = 1;
1111
1112 if (oops_in_progress)
1113 locked = spin_trylock_irqsave(&port->lock, flags);
1114 else
1115 spin_lock_irqsave(&port->lock, flags);
1116
1117 /* save and disable interrupt */
1118 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
1119 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
1120
1121 /*
1122 * Make sure that the tx part is enabled. Set the TX enable bit and
1123 * clear the TX disable bit to enable the transmitter.
1124 */
1125 ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
1126 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
1127 XUARTPS_CR_OFFSET);
1128
1129 uart_console_write(port, s, count, xuartps_console_putchar);
1130 xuartps_console_wait_tx(port);
1131
1132 xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
1133
1134 /* restore interrupt state, it seems like there may be a h/w bug
1135 * in that the interrupt enable register should not need to be
1136 * written based on the data sheet
1137 */
1138 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1139 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1140
1141 if (locked)
1142 spin_unlock_irqrestore(&port->lock, flags);
1143 }
1144
1145 /**
1146 * xuartps_console_setup - Initialize the uart to default config
1147 * @co: Console handle
1148 * @options: Initial settings of uart
1149 *
1150 * Returns 0, -ENODEV if no device
1151 **/
1152 static int __init xuartps_console_setup(struct console *co, char *options)
1153 {
1154 struct uart_port *port = &xuartps_port[co->index];
1155 int baud = 9600;
1156 int bits = 8;
1157 int parity = 'n';
1158 int flow = 'n';
1159
1160 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1161 return -EINVAL;
1162
1163 if (!port->mapbase) {
1164 pr_debug("console on ttyPS%i not present\n", co->index);
1165 return -ENODEV;
1166 }
1167
1168 if (options)
1169 uart_parse_options(options, &baud, &parity, &bits, &flow);
1170
1171 return uart_set_options(port, co, baud, parity, bits, flow);
1172 }
1173
1174 static struct uart_driver xuartps_uart_driver;
1175
1176 static struct console xuartps_console = {
1177 .name = XUARTPS_TTY_NAME,
1178 .write = xuartps_console_write,
1179 .device = uart_console_device,
1180 .setup = xuartps_console_setup,
1181 .flags = CON_PRINTBUFFER,
1182 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1183 .data = &xuartps_uart_driver,
1184 };
1185
1186 /**
1187 * xuartps_console_init - Initialization call
1188 *
1189 * Returns 0 on success, negative error otherwise
1190 **/
1191 static int __init xuartps_console_init(void)
1192 {
1193 register_console(&xuartps_console);
1194 return 0;
1195 }
1196
1197 console_initcall(xuartps_console_init);
1198
1199 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1200
1201 #ifdef CONFIG_PM_SLEEP
1202 /**
1203 * xuartps_suspend - suspend event
1204 * @device: Pointer to the device structure
1205 *
1206 * Returns 0
1207 */
1208 static int xuartps_suspend(struct device *device)
1209 {
1210 struct uart_port *port = dev_get_drvdata(device);
1211 struct tty_struct *tty;
1212 struct device *tty_dev;
1213 int may_wake = 0;
1214
1215 /* Get the tty which could be NULL so don't assume it's valid */
1216 tty = tty_port_tty_get(&port->state->port);
1217 if (tty) {
1218 tty_dev = tty->dev;
1219 may_wake = device_may_wakeup(tty_dev);
1220 tty_kref_put(tty);
1221 }
1222
1223 /*
1224 * Call the API provided in serial_core.c file which handles
1225 * the suspend.
1226 */
1227 uart_suspend_port(&xuartps_uart_driver, port);
1228 if (console_suspend_enabled && !may_wake) {
1229 struct xuartps *xuartps = port->private_data;
1230
1231 clk_disable(xuartps->refclk);
1232 clk_disable(xuartps->aperclk);
1233 } else {
1234 unsigned long flags = 0;
1235
1236 spin_lock_irqsave(&port->lock, flags);
1237 /* Empty the receive FIFO 1st before making changes */
1238 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY))
1239 xuartps_readl(XUARTPS_FIFO_OFFSET);
1240 /* set RX trigger level to 1 */
1241 xuartps_writel(1, XUARTPS_RXWM_OFFSET);
1242 /* disable RX timeout interrups */
1243 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET);
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 }
1246
1247 return 0;
1248 }
1249
1250 /**
1251 * xuartps_resume - Resume after a previous suspend
1252 * @device: Pointer to the device structure
1253 *
1254 * Returns 0
1255 */
1256 static int xuartps_resume(struct device *device)
1257 {
1258 struct uart_port *port = dev_get_drvdata(device);
1259 unsigned long flags = 0;
1260 u32 ctrl_reg;
1261 struct tty_struct *tty;
1262 struct device *tty_dev;
1263 int may_wake = 0;
1264
1265 /* Get the tty which could be NULL so don't assume it's valid */
1266 tty = tty_port_tty_get(&port->state->port);
1267 if (tty) {
1268 tty_dev = tty->dev;
1269 may_wake = device_may_wakeup(tty_dev);
1270 tty_kref_put(tty);
1271 }
1272
1273 if (console_suspend_enabled && !may_wake) {
1274 struct xuartps *xuartps = port->private_data;
1275
1276 clk_enable(xuartps->aperclk);
1277 clk_enable(xuartps->refclk);
1278
1279 spin_lock_irqsave(&port->lock, flags);
1280
1281 /* Set TX/RX Reset */
1282 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
1283 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
1284 XUARTPS_CR_OFFSET);
1285 while (xuartps_readl(XUARTPS_CR_OFFSET) &
1286 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
1287 cpu_relax();
1288
1289 /* restore rx timeout value */
1290 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
1291 /* Enable Tx/Rx */
1292 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
1293 xuartps_writel(
1294 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
1295 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
1296 XUARTPS_CR_OFFSET);
1297
1298 spin_unlock_irqrestore(&port->lock, flags);
1299 } else {
1300 spin_lock_irqsave(&port->lock, flags);
1301 /* restore original rx trigger level */
1302 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
1303 /* enable RX timeout interrupt */
1304 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
1305 spin_unlock_irqrestore(&port->lock, flags);
1306 }
1307
1308 return uart_resume_port(&xuartps_uart_driver, port);
1309 }
1310 #endif /* ! CONFIG_PM_SLEEP */
1311
1312 static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume);
1313
1314 /** Structure Definitions
1315 */
1316 static struct uart_driver xuartps_uart_driver = {
1317 .owner = THIS_MODULE, /* Owner */
1318 .driver_name = XUARTPS_NAME, /* Driver name */
1319 .dev_name = XUARTPS_TTY_NAME, /* Node name */
1320 .major = XUARTPS_MAJOR, /* Major number */
1321 .minor = XUARTPS_MINOR, /* Minor number */
1322 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1323 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1324 .cons = &xuartps_console, /* Console */
1325 #endif
1326 };
1327
1328 /* ---------------------------------------------------------------------
1329 * Platform bus binding
1330 */
1331 /**
1332 * xuartps_probe - Platform driver probe
1333 * @pdev: Pointer to the platform device structure
1334 *
1335 * Returns 0 on success, negative error otherwise
1336 **/
1337 static int xuartps_probe(struct platform_device *pdev)
1338 {
1339 int rc;
1340 struct uart_port *port;
1341 struct resource *res, *res2;
1342 struct xuartps *xuartps_data;
1343
1344 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1345 GFP_KERNEL);
1346 if (!xuartps_data)
1347 return -ENOMEM;
1348
1349 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1350 if (IS_ERR(xuartps_data->aperclk)) {
1351 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1352 return PTR_ERR(xuartps_data->aperclk);
1353 }
1354 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1355 if (IS_ERR(xuartps_data->refclk)) {
1356 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1357 return PTR_ERR(xuartps_data->refclk);
1358 }
1359
1360 rc = clk_prepare_enable(xuartps_data->aperclk);
1361 if (rc) {
1362 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1363 return rc;
1364 }
1365 rc = clk_prepare_enable(xuartps_data->refclk);
1366 if (rc) {
1367 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1368 goto err_out_clk_dis_aper;
1369 }
1370
1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372 if (!res) {
1373 rc = -ENODEV;
1374 goto err_out_clk_disable;
1375 }
1376
1377 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1378 if (!res2) {
1379 rc = -ENODEV;
1380 goto err_out_clk_disable;
1381 }
1382
1383 xuartps_data->clk_rate_change_nb.notifier_call =
1384 xuartps_clk_notifier_cb;
1385 if (clk_notifier_register(xuartps_data->refclk,
1386 &xuartps_data->clk_rate_change_nb))
1387 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1388
1389 /* Initialize the port structure */
1390 port = xuartps_get_port();
1391
1392 if (!port) {
1393 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1394 rc = -ENODEV;
1395 goto err_out_notif_unreg;
1396 } else {
1397 /* Register the port.
1398 * This function also registers this device with the tty layer
1399 * and triggers invocation of the config_port() entry point.
1400 */
1401 port->mapbase = res->start;
1402 port->irq = res2->start;
1403 port->dev = &pdev->dev;
1404 port->uartclk = clk_get_rate(xuartps_data->refclk);
1405 port->private_data = xuartps_data;
1406 xuartps_data->port = port;
1407 platform_set_drvdata(pdev, port);
1408 rc = uart_add_one_port(&xuartps_uart_driver, port);
1409 if (rc) {
1410 dev_err(&pdev->dev,
1411 "uart_add_one_port() failed; err=%i\n", rc);
1412 goto err_out_notif_unreg;
1413 }
1414 return 0;
1415 }
1416
1417 err_out_notif_unreg:
1418 clk_notifier_unregister(xuartps_data->refclk,
1419 &xuartps_data->clk_rate_change_nb);
1420 err_out_clk_disable:
1421 clk_disable_unprepare(xuartps_data->refclk);
1422 err_out_clk_dis_aper:
1423 clk_disable_unprepare(xuartps_data->aperclk);
1424
1425 return rc;
1426 }
1427
1428 /**
1429 * xuartps_remove - called when the platform driver is unregistered
1430 * @pdev: Pointer to the platform device structure
1431 *
1432 * Returns 0 on success, negative error otherwise
1433 **/
1434 static int xuartps_remove(struct platform_device *pdev)
1435 {
1436 struct uart_port *port = platform_get_drvdata(pdev);
1437 struct xuartps *xuartps_data = port->private_data;
1438 int rc;
1439
1440 /* Remove the xuartps port from the serial core */
1441 clk_notifier_unregister(xuartps_data->refclk,
1442 &xuartps_data->clk_rate_change_nb);
1443 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1444 port->mapbase = 0;
1445 clk_disable_unprepare(xuartps_data->refclk);
1446 clk_disable_unprepare(xuartps_data->aperclk);
1447 return rc;
1448 }
1449
1450 /* Match table for of_platform binding */
1451 static struct of_device_id xuartps_of_match[] = {
1452 { .compatible = "xlnx,xuartps", },
1453 {}
1454 };
1455 MODULE_DEVICE_TABLE(of, xuartps_of_match);
1456
1457 static struct platform_driver xuartps_platform_driver = {
1458 .probe = xuartps_probe, /* Probe method */
1459 .remove = xuartps_remove, /* Detach method */
1460 .driver = {
1461 .owner = THIS_MODULE,
1462 .name = XUARTPS_NAME, /* Driver name */
1463 .of_match_table = xuartps_of_match,
1464 .pm = &xuartps_dev_pm_ops,
1465 },
1466 };
1467
1468 /* ---------------------------------------------------------------------
1469 * Module Init and Exit
1470 */
1471 /**
1472 * xuartps_init - Initial driver registration call
1473 *
1474 * Returns whether the registration was successful or not
1475 **/
1476 static int __init xuartps_init(void)
1477 {
1478 int retval = 0;
1479
1480 /* Register the xuartps driver with the serial core */
1481 retval = uart_register_driver(&xuartps_uart_driver);
1482 if (retval)
1483 return retval;
1484
1485 /* Register the platform driver */
1486 retval = platform_driver_register(&xuartps_platform_driver);
1487 if (retval)
1488 uart_unregister_driver(&xuartps_uart_driver);
1489
1490 return retval;
1491 }
1492
1493 /**
1494 * xuartps_exit - Driver unregistration call
1495 **/
1496 static void __exit xuartps_exit(void)
1497 {
1498 /* The order of unregistration is important. Unregister the
1499 * UART driver before the platform driver crashes the system.
1500 */
1501
1502 /* Unregister the platform driver */
1503 platform_driver_unregister(&xuartps_platform_driver);
1504
1505 /* Unregister the xuartps driver */
1506 uart_unregister_driver(&xuartps_uart_driver);
1507 }
1508
1509 module_init(xuartps_init);
1510 module_exit(xuartps_exit);
1511
1512 MODULE_DESCRIPTION("Driver for PS UART");
1513 MODULE_AUTHOR("Xilinx Inc.");
1514 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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