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[deliverable/linux.git] / drivers / tty / serial / xilinx_uartps.c
1 /*
2 * Cadence UART driver (found in Xilinx Zynq)
3 *
4 * 2011 - 2014 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
15 */
16
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #define SUPPORT_SYSRQ
19 #endif
20
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
30 #include <linux/io.h>
31 #include <linux/of.h>
32 #include <linux/module.h>
33
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0x1000
41
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47 /* Rx Timeout */
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52 /* Register offsets for the UART. */
53 #define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
54 #define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
55 #define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
56 #define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
57 #define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
58 #define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
59 #define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
60 #define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
61 #define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
62 #define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
63 #define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
64 #define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
65 #define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
66 #define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
67 #define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
68 #define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
69 #define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
70 #define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
71
72 /* Control Register Bit Definitions */
73 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82
83 /*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92
93 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95
96 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101
102 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
105
106 /*
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
116 */
117 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
128
129 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
130 #define CDNS_UART_IXR_BRK 0x80000000
131
132 /*
133 * Modem Control register:
134 * The read/write Modem Control register controls the interface with the modem
135 * or data set, or a peripheral device emulating a modem.
136 */
137 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
138 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
139 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
140
141 /*
142 * Channel Status Register:
143 * The channel status register (CSR) is provided to enable the control logic
144 * to monitor the status of bits in the channel interrupt status register,
145 * even if these are masked out by the interrupt mask register.
146 */
147 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
148 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
149 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
150 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
151
152 /* baud dividers min/max values */
153 #define CDNS_UART_BDIV_MIN 4
154 #define CDNS_UART_BDIV_MAX 255
155 #define CDNS_UART_CD_MAX 65535
156
157 /**
158 * struct cdns_uart - device data
159 * @port: Pointer to the UART port
160 * @uartclk: Reference clock
161 * @pclk: APB clock
162 * @baud: Current baud rate
163 * @clk_rate_change_nb: Notifier block for clock changes
164 */
165 struct cdns_uart {
166 struct uart_port *port;
167 struct clk *uartclk;
168 struct clk *pclk;
169 unsigned int baud;
170 struct notifier_block clk_rate_change_nb;
171 };
172 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
173 clk_rate_change_nb);
174
175 /**
176 * cdns_uart_isr - Interrupt handler
177 * @irq: Irq number
178 * @dev_id: Id of the port
179 *
180 * Return: IRQHANDLED
181 */
182 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
183 {
184 struct uart_port *port = (struct uart_port *)dev_id;
185 unsigned long flags;
186 unsigned int isrstatus, numbytes;
187 unsigned int data;
188 char status = TTY_NORMAL;
189
190 spin_lock_irqsave(&port->lock, flags);
191
192 /* Read the interrupt status register to determine which
193 * interrupt(s) is/are active.
194 */
195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET);
196
197 /*
198 * There is no hardware break detection, so we interpret framing
199 * error with all-zeros data as a break sequence. Most of the time,
200 * there's another non-zero byte at the end of the sequence.
201 */
202 if (isrstatus & CDNS_UART_IXR_FRAMING) {
203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
204 CDNS_UART_SR_RXEMPTY)) {
205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) {
206 port->read_status_mask |= CDNS_UART_IXR_BRK;
207 isrstatus &= ~CDNS_UART_IXR_FRAMING;
208 }
209 }
210 writel(CDNS_UART_IXR_FRAMING,
211 port->membase + CDNS_UART_ISR_OFFSET);
212 }
213
214 /* drop byte with parity error if IGNPAR specified */
215 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
216 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
217
218 isrstatus &= port->read_status_mask;
219 isrstatus &= ~port->ignore_status_mask;
220
221 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
222 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
223 /* Receive Timeout Interrupt */
224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
225 CDNS_UART_SR_RXEMPTY)) {
226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET);
227
228 /* Non-NULL byte after BREAK is garbage (99%) */
229 if (data && (port->read_status_mask &
230 CDNS_UART_IXR_BRK)) {
231 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
232 port->icount.brk++;
233 if (uart_handle_break(port))
234 continue;
235 }
236
237 #ifdef SUPPORT_SYSRQ
238 /*
239 * uart_handle_sysrq_char() doesn't work if
240 * spinlocked, for some reason
241 */
242 if (port->sysrq) {
243 spin_unlock(&port->lock);
244 if (uart_handle_sysrq_char(port,
245 (unsigned char)data)) {
246 spin_lock(&port->lock);
247 continue;
248 }
249 spin_lock(&port->lock);
250 }
251 #endif
252
253 port->icount.rx++;
254
255 if (isrstatus & CDNS_UART_IXR_PARITY) {
256 port->icount.parity++;
257 status = TTY_PARITY;
258 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
259 port->icount.frame++;
260 status = TTY_FRAME;
261 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
262 port->icount.overrun++;
263 }
264
265 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
266 data, status);
267 }
268 spin_unlock(&port->lock);
269 tty_flip_buffer_push(&port->state->port);
270 spin_lock(&port->lock);
271 }
272
273 /* Dispatch an appropriate handler */
274 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
275 if (uart_circ_empty(&port->state->xmit)) {
276 writel(CDNS_UART_IXR_TXEMPTY,
277 port->membase + CDNS_UART_IDR_OFFSET);
278 } else {
279 numbytes = port->fifosize;
280 /* Break if no more data available in the UART buffer */
281 while (numbytes--) {
282 if (uart_circ_empty(&port->state->xmit))
283 break;
284 /* Get the data from the UART circular buffer
285 * and write it to the cdns_uart's TX_FIFO
286 * register.
287 */
288 writel(port->state->xmit.buf[
289 port->state->xmit.tail],
290 port->membase + CDNS_UART_FIFO_OFFSET);
291
292 port->icount.tx++;
293
294 /* Adjust the tail of the UART buffer and wrap
295 * the buffer if it reaches limit.
296 */
297 port->state->xmit.tail =
298 (port->state->xmit.tail + 1) &
299 (UART_XMIT_SIZE - 1);
300 }
301
302 if (uart_circ_chars_pending(
303 &port->state->xmit) < WAKEUP_CHARS)
304 uart_write_wakeup(port);
305 }
306 }
307
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET);
309
310 /* be sure to release the lock and tty before leaving */
311 spin_unlock_irqrestore(&port->lock, flags);
312
313 return IRQ_HANDLED;
314 }
315
316 /**
317 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
318 * @clk: UART module input clock
319 * @baud: Desired baud rate
320 * @rbdiv: BDIV value (return value)
321 * @rcd: CD value (return value)
322 * @div8: Value for clk_sel bit in mod (return value)
323 * Return: baud rate, requested baud when possible, or actual baud when there
324 * was too much error, zero if no valid divisors are found.
325 *
326 * Formula to obtain baud rate is
327 * baud_tx/rx rate = clk/CD * (BDIV + 1)
328 * input_clk = (Uart User Defined Clock or Apb Clock)
329 * depends on UCLKEN in MR Reg
330 * clk = input_clk or input_clk/8;
331 * depends on CLKS in MR reg
332 * CD and BDIV depends on values in
333 * baud rate generate register
334 * baud rate clock divisor register
335 */
336 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
337 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
338 {
339 u32 cd, bdiv;
340 unsigned int calc_baud;
341 unsigned int bestbaud = 0;
342 unsigned int bauderror;
343 unsigned int besterror = ~0;
344
345 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
346 *div8 = 1;
347 clk /= 8;
348 } else {
349 *div8 = 0;
350 }
351
352 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
353 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
354 if (cd < 1 || cd > CDNS_UART_CD_MAX)
355 continue;
356
357 calc_baud = clk / (cd * (bdiv + 1));
358
359 if (baud > calc_baud)
360 bauderror = baud - calc_baud;
361 else
362 bauderror = calc_baud - baud;
363
364 if (besterror > bauderror) {
365 *rbdiv = bdiv;
366 *rcd = cd;
367 bestbaud = calc_baud;
368 besterror = bauderror;
369 }
370 }
371 /* use the values when percent error is acceptable */
372 if (((besterror * 100) / baud) < 3)
373 bestbaud = baud;
374
375 return bestbaud;
376 }
377
378 /**
379 * cdns_uart_set_baud_rate - Calculate and set the baud rate
380 * @port: Handle to the uart port structure
381 * @baud: Baud rate to set
382 * Return: baud rate, requested baud when possible, or actual baud when there
383 * was too much error, zero if no valid divisors are found.
384 */
385 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
386 unsigned int baud)
387 {
388 unsigned int calc_baud;
389 u32 cd = 0, bdiv = 0;
390 u32 mreg;
391 int div8;
392 struct cdns_uart *cdns_uart = port->private_data;
393
394 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
395 &div8);
396
397 /* Write new divisors to hardware */
398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET);
399 if (div8)
400 mreg |= CDNS_UART_MR_CLKSEL;
401 else
402 mreg &= ~CDNS_UART_MR_CLKSEL;
403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET);
404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET);
405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET);
406 cdns_uart->baud = baud;
407
408 return calc_baud;
409 }
410
411 #ifdef CONFIG_COMMON_CLK
412 /**
413 * cdns_uart_clk_notitifer_cb - Clock notifier callback
414 * @nb: Notifier block
415 * @event: Notify event
416 * @data: Notifier data
417 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
418 */
419 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
420 unsigned long event, void *data)
421 {
422 u32 ctrl_reg;
423 struct uart_port *port;
424 int locked = 0;
425 struct clk_notifier_data *ndata = data;
426 unsigned long flags = 0;
427 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
428
429 port = cdns_uart->port;
430 if (port->suspended)
431 return NOTIFY_OK;
432
433 switch (event) {
434 case PRE_RATE_CHANGE:
435 {
436 u32 bdiv, cd;
437 int div8;
438
439 /*
440 * Find out if current baud-rate can be achieved with new clock
441 * frequency.
442 */
443 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
444 &bdiv, &cd, &div8)) {
445 dev_warn(port->dev, "clock rate change rejected\n");
446 return NOTIFY_BAD;
447 }
448
449 spin_lock_irqsave(&cdns_uart->port->lock, flags);
450
451 /* Disable the TX and RX to set baud rate */
452 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
453 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
455
456 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
457
458 return NOTIFY_OK;
459 }
460 case POST_RATE_CHANGE:
461 /*
462 * Set clk dividers to generate correct baud with new clock
463 * frequency.
464 */
465
466 spin_lock_irqsave(&cdns_uart->port->lock, flags);
467
468 locked = 1;
469 port->uartclk = ndata->new_rate;
470
471 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
472 cdns_uart->baud);
473 /* fall through */
474 case ABORT_RATE_CHANGE:
475 if (!locked)
476 spin_lock_irqsave(&cdns_uart->port->lock, flags);
477
478 /* Set TX/RX Reset */
479 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
480 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
482
483 while (readl(port->membase + CDNS_UART_CR_OFFSET) &
484 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
485 cpu_relax();
486
487 /*
488 * Clear the RX disable and TX disable bits and then set the TX
489 * enable bit and RX enable bit to enable the transmitter and
490 * receiver.
491 */
492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
493 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
494 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
495 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
496 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
497
498 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
499
500 return NOTIFY_OK;
501 default:
502 return NOTIFY_DONE;
503 }
504 }
505 #endif
506
507 /**
508 * cdns_uart_start_tx - Start transmitting bytes
509 * @port: Handle to the uart port structure
510 */
511 static void cdns_uart_start_tx(struct uart_port *port)
512 {
513 unsigned int status, numbytes = port->fifosize;
514
515 if (uart_tx_stopped(port))
516 return;
517
518 /*
519 * Set the TX enable bit and clear the TX disable bit to enable the
520 * transmitter.
521 */
522 status = readl(port->membase + CDNS_UART_CR_OFFSET);
523 status &= ~CDNS_UART_CR_TX_DIS;
524 status |= CDNS_UART_CR_TX_EN;
525 writel(status, port->membase + CDNS_UART_CR_OFFSET);
526
527 if (uart_circ_empty(&port->state->xmit))
528 return;
529
530 while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) &
531 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
532 /* Break if no more data available in the UART buffer */
533 if (uart_circ_empty(&port->state->xmit))
534 break;
535
536 /* Get the data from the UART circular buffer and
537 * write it to the cdns_uart's TX_FIFO register.
538 */
539 writel(port->state->xmit.buf[port->state->xmit.tail],
540 port->membase + CDNS_UART_FIFO_OFFSET);
541 port->icount.tx++;
542
543 /* Adjust the tail of the UART buffer and wrap
544 * the buffer if it reaches limit.
545 */
546 port->state->xmit.tail = (port->state->xmit.tail + 1) &
547 (UART_XMIT_SIZE - 1);
548 }
549 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET);
550 /* Enable the TX Empty interrupt */
551 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET);
552
553 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
554 uart_write_wakeup(port);
555 }
556
557 /**
558 * cdns_uart_stop_tx - Stop TX
559 * @port: Handle to the uart port structure
560 */
561 static void cdns_uart_stop_tx(struct uart_port *port)
562 {
563 unsigned int regval;
564
565 regval = readl(port->membase + CDNS_UART_CR_OFFSET);
566 regval |= CDNS_UART_CR_TX_DIS;
567 /* Disable the transmitter */
568 writel(regval, port->membase + CDNS_UART_CR_OFFSET);
569 }
570
571 /**
572 * cdns_uart_stop_rx - Stop RX
573 * @port: Handle to the uart port structure
574 */
575 static void cdns_uart_stop_rx(struct uart_port *port)
576 {
577 unsigned int regval;
578
579 regval = readl(port->membase + CDNS_UART_CR_OFFSET);
580 regval |= CDNS_UART_CR_RX_DIS;
581 /* Disable the receiver */
582 writel(regval, port->membase + CDNS_UART_CR_OFFSET);
583 }
584
585 /**
586 * cdns_uart_tx_empty - Check whether TX is empty
587 * @port: Handle to the uart port structure
588 *
589 * Return: TIOCSER_TEMT on success, 0 otherwise
590 */
591 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
592 {
593 unsigned int status;
594
595 status = readl(port->membase + CDNS_UART_SR_OFFSET) &
596 CDNS_UART_SR_TXEMPTY;
597 return status ? TIOCSER_TEMT : 0;
598 }
599
600 /**
601 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
602 * transmitting char breaks
603 * @port: Handle to the uart port structure
604 * @ctl: Value based on which start or stop decision is taken
605 */
606 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
607 {
608 unsigned int status;
609 unsigned long flags;
610
611 spin_lock_irqsave(&port->lock, flags);
612
613 status = readl(port->membase + CDNS_UART_CR_OFFSET);
614
615 if (ctl == -1)
616 writel(CDNS_UART_CR_STARTBRK | status,
617 port->membase + CDNS_UART_CR_OFFSET);
618 else {
619 if ((status & CDNS_UART_CR_STOPBRK) == 0)
620 writel(CDNS_UART_CR_STOPBRK | status,
621 port->membase + CDNS_UART_CR_OFFSET);
622 }
623 spin_unlock_irqrestore(&port->lock, flags);
624 }
625
626 /**
627 * cdns_uart_set_termios - termios operations, handling data length, parity,
628 * stop bits, flow control, baud rate
629 * @port: Handle to the uart port structure
630 * @termios: Handle to the input termios structure
631 * @old: Values of the previously saved termios structure
632 */
633 static void cdns_uart_set_termios(struct uart_port *port,
634 struct ktermios *termios, struct ktermios *old)
635 {
636 unsigned int cval = 0;
637 unsigned int baud, minbaud, maxbaud;
638 unsigned long flags;
639 unsigned int ctrl_reg, mode_reg;
640
641 spin_lock_irqsave(&port->lock, flags);
642
643 /* Wait for the transmit FIFO to empty before making changes */
644 if (!(readl(port->membase + CDNS_UART_CR_OFFSET) &
645 CDNS_UART_CR_TX_DIS)) {
646 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
647 CDNS_UART_SR_TXEMPTY)) {
648 cpu_relax();
649 }
650 }
651
652 /* Disable the TX and RX to set baud rate */
653 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
654 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
655 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
656
657 /*
658 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
659 * min and max baud should be calculated here based on port->uartclk.
660 * this way we get a valid baud and can safely call set_baud()
661 */
662 minbaud = port->uartclk /
663 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
664 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
665 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
666 baud = cdns_uart_set_baud_rate(port, baud);
667 if (tty_termios_baud_rate(termios))
668 tty_termios_encode_baud_rate(termios, baud, baud);
669
670 /* Update the per-port timeout. */
671 uart_update_timeout(port, termios->c_cflag, baud);
672
673 /* Set TX/RX Reset */
674 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
675 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
676 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
677
678 /*
679 * Clear the RX disable and TX disable bits and then set the TX enable
680 * bit and RX enable bit to enable the transmitter and receiver.
681 */
682 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
683 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
684 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
685 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
686
687 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
688
689 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
690 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
691 port->ignore_status_mask = 0;
692
693 if (termios->c_iflag & INPCK)
694 port->read_status_mask |= CDNS_UART_IXR_PARITY |
695 CDNS_UART_IXR_FRAMING;
696
697 if (termios->c_iflag & IGNPAR)
698 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
699 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
700
701 /* ignore all characters if CREAD is not set */
702 if ((termios->c_cflag & CREAD) == 0)
703 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
704 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
705 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
706
707 mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET);
708
709 /* Handling Data Size */
710 switch (termios->c_cflag & CSIZE) {
711 case CS6:
712 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
713 break;
714 case CS7:
715 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
716 break;
717 default:
718 case CS8:
719 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
720 termios->c_cflag &= ~CSIZE;
721 termios->c_cflag |= CS8;
722 break;
723 }
724
725 /* Handling Parity and Stop Bits length */
726 if (termios->c_cflag & CSTOPB)
727 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
728 else
729 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
730
731 if (termios->c_cflag & PARENB) {
732 /* Mark or Space parity */
733 if (termios->c_cflag & CMSPAR) {
734 if (termios->c_cflag & PARODD)
735 cval |= CDNS_UART_MR_PARITY_MARK;
736 else
737 cval |= CDNS_UART_MR_PARITY_SPACE;
738 } else {
739 if (termios->c_cflag & PARODD)
740 cval |= CDNS_UART_MR_PARITY_ODD;
741 else
742 cval |= CDNS_UART_MR_PARITY_EVEN;
743 }
744 } else {
745 cval |= CDNS_UART_MR_PARITY_NONE;
746 }
747 cval |= mode_reg & 1;
748 writel(cval, port->membase + CDNS_UART_MR_OFFSET);
749
750 spin_unlock_irqrestore(&port->lock, flags);
751 }
752
753 /**
754 * cdns_uart_startup - Called when an application opens a cdns_uart port
755 * @port: Handle to the uart port structure
756 *
757 * Return: 0 on success, negative errno otherwise
758 */
759 static int cdns_uart_startup(struct uart_port *port)
760 {
761 unsigned long flags;
762 unsigned int retval = 0, status = 0;
763
764 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
765 (void *)port);
766 if (retval)
767 return retval;
768
769 spin_lock_irqsave(&port->lock, flags);
770
771 /* Disable the TX and RX */
772 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
773 port->membase + CDNS_UART_CR_OFFSET);
774
775 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
776 * no break chars.
777 */
778 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
779 port->membase + CDNS_UART_CR_OFFSET);
780
781 /*
782 * Clear the RX disable bit and then set the RX enable bit to enable
783 * the receiver.
784 */
785 status = readl(port->membase + CDNS_UART_CR_OFFSET);
786 status &= CDNS_UART_CR_RX_DIS;
787 status |= CDNS_UART_CR_RX_EN;
788 writel(status, port->membase + CDNS_UART_CR_OFFSET);
789
790 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
791 * no parity.
792 */
793 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
794 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
795 port->membase + CDNS_UART_MR_OFFSET);
796
797 /*
798 * Set the RX FIFO Trigger level to use most of the FIFO, but it
799 * can be tuned with a module parameter
800 */
801 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET);
802
803 /*
804 * Receive Timeout register is enabled but it
805 * can be tuned with a module parameter
806 */
807 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
808
809 /* Clear out any pending interrupts before enabling them */
810 writel(readl(port->membase + CDNS_UART_ISR_OFFSET),
811 port->membase + CDNS_UART_ISR_OFFSET);
812
813 /* Set the Interrupt Registers with desired interrupts */
814 writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
815 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
816 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
817 port->membase + CDNS_UART_IER_OFFSET);
818
819 spin_unlock_irqrestore(&port->lock, flags);
820
821 return retval;
822 }
823
824 /**
825 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
826 * @port: Handle to the uart port structure
827 */
828 static void cdns_uart_shutdown(struct uart_port *port)
829 {
830 int status;
831
832 /* Disable interrupts */
833 status = readl(port->membase + CDNS_UART_IMR_OFFSET);
834 writel(status, port->membase + CDNS_UART_IDR_OFFSET);
835 writel(0xffffffff, port->membase + CDNS_UART_ISR_OFFSET);
836
837 /* Disable the TX and RX */
838 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
839 port->membase + CDNS_UART_CR_OFFSET);
840 free_irq(port->irq, port);
841 }
842
843 /**
844 * cdns_uart_type - Set UART type to cdns_uart port
845 * @port: Handle to the uart port structure
846 *
847 * Return: string on success, NULL otherwise
848 */
849 static const char *cdns_uart_type(struct uart_port *port)
850 {
851 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
852 }
853
854 /**
855 * cdns_uart_verify_port - Verify the port params
856 * @port: Handle to the uart port structure
857 * @ser: Handle to the structure whose members are compared
858 *
859 * Return: 0 on success, negative errno otherwise.
860 */
861 static int cdns_uart_verify_port(struct uart_port *port,
862 struct serial_struct *ser)
863 {
864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
865 return -EINVAL;
866 if (port->irq != ser->irq)
867 return -EINVAL;
868 if (ser->io_type != UPIO_MEM)
869 return -EINVAL;
870 if (port->iobase != ser->port)
871 return -EINVAL;
872 if (ser->hub6 != 0)
873 return -EINVAL;
874 return 0;
875 }
876
877 /**
878 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
879 * called when the driver adds a cdns_uart port via
880 * uart_add_one_port()
881 * @port: Handle to the uart port structure
882 *
883 * Return: 0 on success, negative errno otherwise.
884 */
885 static int cdns_uart_request_port(struct uart_port *port)
886 {
887 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
888 CDNS_UART_NAME)) {
889 return -ENOMEM;
890 }
891
892 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
893 if (!port->membase) {
894 dev_err(port->dev, "Unable to map registers\n");
895 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
896 return -ENOMEM;
897 }
898 return 0;
899 }
900
901 /**
902 * cdns_uart_release_port - Release UART port
903 * @port: Handle to the uart port structure
904 *
905 * Release the memory region attached to a cdns_uart port. Called when the
906 * driver removes a cdns_uart port via uart_remove_one_port().
907 */
908 static void cdns_uart_release_port(struct uart_port *port)
909 {
910 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
911 iounmap(port->membase);
912 port->membase = NULL;
913 }
914
915 /**
916 * cdns_uart_config_port - Configure UART port
917 * @port: Handle to the uart port structure
918 * @flags: If any
919 */
920 static void cdns_uart_config_port(struct uart_port *port, int flags)
921 {
922 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
923 port->type = PORT_XUARTPS;
924 }
925
926 /**
927 * cdns_uart_get_mctrl - Get the modem control state
928 * @port: Handle to the uart port structure
929 *
930 * Return: the modem control state
931 */
932 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
933 {
934 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
935 }
936
937 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
938 {
939 u32 val;
940
941 val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET);
942
943 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
944
945 if (mctrl & TIOCM_RTS)
946 val |= CDNS_UART_MODEMCR_RTS;
947 if (mctrl & TIOCM_DTR)
948 val |= CDNS_UART_MODEMCR_DTR;
949
950 writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET);
951 }
952
953 #ifdef CONFIG_CONSOLE_POLL
954 static int cdns_uart_poll_get_char(struct uart_port *port)
955 {
956 int c;
957 unsigned long flags;
958
959 spin_lock_irqsave(&port->lock, flags);
960
961 /* Check if FIFO is empty */
962 if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
963 c = NO_POLL_CHAR;
964 else /* Read a character */
965 c = (unsigned char) readl(
966 port->membase + CDNS_UART_FIFO_OFFSET);
967
968 spin_unlock_irqrestore(&port->lock, flags);
969
970 return c;
971 }
972
973 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
974 {
975 unsigned long flags;
976
977 spin_lock_irqsave(&port->lock, flags);
978
979 /* Wait until FIFO is empty */
980 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
981 CDNS_UART_SR_TXEMPTY))
982 cpu_relax();
983
984 /* Write a character */
985 writel(c, port->membase + CDNS_UART_FIFO_OFFSET);
986
987 /* Wait until FIFO is empty */
988 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
989 CDNS_UART_SR_TXEMPTY))
990 cpu_relax();
991
992 spin_unlock_irqrestore(&port->lock, flags);
993
994 return;
995 }
996 #endif
997
998 static struct uart_ops cdns_uart_ops = {
999 .set_mctrl = cdns_uart_set_mctrl,
1000 .get_mctrl = cdns_uart_get_mctrl,
1001 .start_tx = cdns_uart_start_tx,
1002 .stop_tx = cdns_uart_stop_tx,
1003 .stop_rx = cdns_uart_stop_rx,
1004 .tx_empty = cdns_uart_tx_empty,
1005 .break_ctl = cdns_uart_break_ctl,
1006 .set_termios = cdns_uart_set_termios,
1007 .startup = cdns_uart_startup,
1008 .shutdown = cdns_uart_shutdown,
1009 .type = cdns_uart_type,
1010 .verify_port = cdns_uart_verify_port,
1011 .request_port = cdns_uart_request_port,
1012 .release_port = cdns_uart_release_port,
1013 .config_port = cdns_uart_config_port,
1014 #ifdef CONFIG_CONSOLE_POLL
1015 .poll_get_char = cdns_uart_poll_get_char,
1016 .poll_put_char = cdns_uart_poll_put_char,
1017 #endif
1018 };
1019
1020 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1021
1022 /**
1023 * cdns_uart_get_port - Configure the port from platform device resource info
1024 * @id: Port id
1025 *
1026 * Return: a pointer to a uart_port or NULL for failure
1027 */
1028 static struct uart_port *cdns_uart_get_port(int id)
1029 {
1030 struct uart_port *port;
1031
1032 /* Try the given port id if failed use default method */
1033 if (cdns_uart_port[id].mapbase != 0) {
1034 /* Find the next unused port */
1035 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1036 if (cdns_uart_port[id].mapbase == 0)
1037 break;
1038 }
1039
1040 if (id >= CDNS_UART_NR_PORTS)
1041 return NULL;
1042
1043 port = &cdns_uart_port[id];
1044
1045 /* At this point, we've got an empty uart_port struct, initialize it */
1046 spin_lock_init(&port->lock);
1047 port->membase = NULL;
1048 port->irq = 0;
1049 port->type = PORT_UNKNOWN;
1050 port->iotype = UPIO_MEM32;
1051 port->flags = UPF_BOOT_AUTOCONF;
1052 port->ops = &cdns_uart_ops;
1053 port->fifosize = CDNS_UART_FIFO_SIZE;
1054 port->line = id;
1055 port->dev = NULL;
1056 return port;
1057 }
1058
1059 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1060 /**
1061 * cdns_uart_console_wait_tx - Wait for the TX to be full
1062 * @port: Handle to the uart port structure
1063 */
1064 static void cdns_uart_console_wait_tx(struct uart_port *port)
1065 {
1066 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
1067 CDNS_UART_SR_TXEMPTY))
1068 barrier();
1069 }
1070
1071 /**
1072 * cdns_uart_console_putchar - write the character to the FIFO buffer
1073 * @port: Handle to the uart port structure
1074 * @ch: Character to be written
1075 */
1076 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1077 {
1078 cdns_uart_console_wait_tx(port);
1079 writel(ch, port->membase + CDNS_UART_FIFO_OFFSET);
1080 }
1081
1082 static void __init cdns_early_write(struct console *con, const char *s,
1083 unsigned n)
1084 {
1085 struct earlycon_device *dev = con->data;
1086
1087 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1088 }
1089
1090 static int __init cdns_early_console_setup(struct earlycon_device *device,
1091 const char *opt)
1092 {
1093 if (!device->port.membase)
1094 return -ENODEV;
1095
1096 device->con->write = cdns_early_write;
1097
1098 return 0;
1099 }
1100 EARLYCON_DECLARE(cdns, cdns_early_console_setup);
1101
1102 /**
1103 * cdns_uart_console_write - perform write operation
1104 * @co: Console handle
1105 * @s: Pointer to character array
1106 * @count: No of characters
1107 */
1108 static void cdns_uart_console_write(struct console *co, const char *s,
1109 unsigned int count)
1110 {
1111 struct uart_port *port = &cdns_uart_port[co->index];
1112 unsigned long flags;
1113 unsigned int imr, ctrl;
1114 int locked = 1;
1115
1116 if (oops_in_progress)
1117 locked = spin_trylock_irqsave(&port->lock, flags);
1118 else
1119 spin_lock_irqsave(&port->lock, flags);
1120
1121 /* save and disable interrupt */
1122 imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
1123 writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
1124
1125 /*
1126 * Make sure that the tx part is enabled. Set the TX enable bit and
1127 * clear the TX disable bit to enable the transmitter.
1128 */
1129 ctrl = readl(port->membase + CDNS_UART_CR_OFFSET);
1130 ctrl &= ~CDNS_UART_CR_TX_DIS;
1131 ctrl |= CDNS_UART_CR_TX_EN;
1132 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
1133
1134 uart_console_write(port, s, count, cdns_uart_console_putchar);
1135 cdns_uart_console_wait_tx(port);
1136
1137 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
1138
1139 /* restore interrupt state */
1140 writel(imr, port->membase + CDNS_UART_IER_OFFSET);
1141
1142 if (locked)
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 }
1145
1146 /**
1147 * cdns_uart_console_setup - Initialize the uart to default config
1148 * @co: Console handle
1149 * @options: Initial settings of uart
1150 *
1151 * Return: 0 on success, negative errno otherwise.
1152 */
1153 static int __init cdns_uart_console_setup(struct console *co, char *options)
1154 {
1155 struct uart_port *port = &cdns_uart_port[co->index];
1156 int baud = 9600;
1157 int bits = 8;
1158 int parity = 'n';
1159 int flow = 'n';
1160
1161 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1162 return -EINVAL;
1163
1164 if (!port->membase) {
1165 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1166 co->index);
1167 return -ENODEV;
1168 }
1169
1170 if (options)
1171 uart_parse_options(options, &baud, &parity, &bits, &flow);
1172
1173 return uart_set_options(port, co, baud, parity, bits, flow);
1174 }
1175
1176 static struct uart_driver cdns_uart_uart_driver;
1177
1178 static struct console cdns_uart_console = {
1179 .name = CDNS_UART_TTY_NAME,
1180 .write = cdns_uart_console_write,
1181 .device = uart_console_device,
1182 .setup = cdns_uart_console_setup,
1183 .flags = CON_PRINTBUFFER,
1184 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1185 .data = &cdns_uart_uart_driver,
1186 };
1187
1188 /**
1189 * cdns_uart_console_init - Initialization call
1190 *
1191 * Return: 0 on success, negative errno otherwise
1192 */
1193 static int __init cdns_uart_console_init(void)
1194 {
1195 register_console(&cdns_uart_console);
1196 return 0;
1197 }
1198
1199 console_initcall(cdns_uart_console_init);
1200
1201 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1202
1203 static struct uart_driver cdns_uart_uart_driver = {
1204 .owner = THIS_MODULE,
1205 .driver_name = CDNS_UART_NAME,
1206 .dev_name = CDNS_UART_TTY_NAME,
1207 .major = CDNS_UART_MAJOR,
1208 .minor = CDNS_UART_MINOR,
1209 .nr = CDNS_UART_NR_PORTS,
1210 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1211 .cons = &cdns_uart_console,
1212 #endif
1213 };
1214
1215 #ifdef CONFIG_PM_SLEEP
1216 /**
1217 * cdns_uart_suspend - suspend event
1218 * @device: Pointer to the device structure
1219 *
1220 * Return: 0
1221 */
1222 static int cdns_uart_suspend(struct device *device)
1223 {
1224 struct uart_port *port = dev_get_drvdata(device);
1225 struct tty_struct *tty;
1226 struct device *tty_dev;
1227 int may_wake = 0;
1228
1229 /* Get the tty which could be NULL so don't assume it's valid */
1230 tty = tty_port_tty_get(&port->state->port);
1231 if (tty) {
1232 tty_dev = tty->dev;
1233 may_wake = device_may_wakeup(tty_dev);
1234 tty_kref_put(tty);
1235 }
1236
1237 /*
1238 * Call the API provided in serial_core.c file which handles
1239 * the suspend.
1240 */
1241 uart_suspend_port(&cdns_uart_uart_driver, port);
1242 if (console_suspend_enabled && !may_wake) {
1243 struct cdns_uart *cdns_uart = port->private_data;
1244
1245 clk_disable(cdns_uart->uartclk);
1246 clk_disable(cdns_uart->pclk);
1247 } else {
1248 unsigned long flags = 0;
1249
1250 spin_lock_irqsave(&port->lock, flags);
1251 /* Empty the receive FIFO 1st before making changes */
1252 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
1253 CDNS_UART_SR_RXEMPTY))
1254 readl(port->membase + CDNS_UART_FIFO_OFFSET);
1255 /* set RX trigger level to 1 */
1256 writel(1, port->membase + CDNS_UART_RXWM_OFFSET);
1257 /* disable RX timeout interrups */
1258 writel(CDNS_UART_IXR_TOUT,
1259 port->membase + CDNS_UART_IDR_OFFSET);
1260 spin_unlock_irqrestore(&port->lock, flags);
1261 }
1262
1263 return 0;
1264 }
1265
1266 /**
1267 * cdns_uart_resume - Resume after a previous suspend
1268 * @device: Pointer to the device structure
1269 *
1270 * Return: 0
1271 */
1272 static int cdns_uart_resume(struct device *device)
1273 {
1274 struct uart_port *port = dev_get_drvdata(device);
1275 unsigned long flags = 0;
1276 u32 ctrl_reg;
1277 struct tty_struct *tty;
1278 struct device *tty_dev;
1279 int may_wake = 0;
1280
1281 /* Get the tty which could be NULL so don't assume it's valid */
1282 tty = tty_port_tty_get(&port->state->port);
1283 if (tty) {
1284 tty_dev = tty->dev;
1285 may_wake = device_may_wakeup(tty_dev);
1286 tty_kref_put(tty);
1287 }
1288
1289 if (console_suspend_enabled && !may_wake) {
1290 struct cdns_uart *cdns_uart = port->private_data;
1291
1292 clk_enable(cdns_uart->pclk);
1293 clk_enable(cdns_uart->uartclk);
1294
1295 spin_lock_irqsave(&port->lock, flags);
1296
1297 /* Set TX/RX Reset */
1298 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
1299 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1300 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
1301 while (readl(port->membase + CDNS_UART_CR_OFFSET) &
1302 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1303 cpu_relax();
1304
1305 /* restore rx timeout value */
1306 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
1307 /* Enable Tx/Rx */
1308 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
1309 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1310 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1311 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
1312
1313 spin_unlock_irqrestore(&port->lock, flags);
1314 } else {
1315 spin_lock_irqsave(&port->lock, flags);
1316 /* restore original rx trigger level */
1317 writel(rx_trigger_level,
1318 port->membase + CDNS_UART_RXWM_OFFSET);
1319 /* enable RX timeout interrupt */
1320 writel(CDNS_UART_IXR_TOUT,
1321 port->membase + CDNS_UART_IER_OFFSET);
1322 spin_unlock_irqrestore(&port->lock, flags);
1323 }
1324
1325 return uart_resume_port(&cdns_uart_uart_driver, port);
1326 }
1327 #endif /* ! CONFIG_PM_SLEEP */
1328
1329 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1330 cdns_uart_resume);
1331
1332 /**
1333 * cdns_uart_probe - Platform driver probe
1334 * @pdev: Pointer to the platform device structure
1335 *
1336 * Return: 0 on success, negative errno otherwise
1337 */
1338 static int cdns_uart_probe(struct platform_device *pdev)
1339 {
1340 int rc, id, irq;
1341 struct uart_port *port;
1342 struct resource *res;
1343 struct cdns_uart *cdns_uart_data;
1344
1345 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1346 GFP_KERNEL);
1347 if (!cdns_uart_data)
1348 return -ENOMEM;
1349
1350 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1351 if (IS_ERR(cdns_uart_data->pclk)) {
1352 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1353 if (!IS_ERR(cdns_uart_data->pclk))
1354 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1355 }
1356 if (IS_ERR(cdns_uart_data->pclk)) {
1357 dev_err(&pdev->dev, "pclk clock not found.\n");
1358 return PTR_ERR(cdns_uart_data->pclk);
1359 }
1360
1361 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1362 if (IS_ERR(cdns_uart_data->uartclk)) {
1363 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1364 if (!IS_ERR(cdns_uart_data->uartclk))
1365 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1366 }
1367 if (IS_ERR(cdns_uart_data->uartclk)) {
1368 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1369 return PTR_ERR(cdns_uart_data->uartclk);
1370 }
1371
1372 rc = clk_prepare_enable(cdns_uart_data->pclk);
1373 if (rc) {
1374 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1375 return rc;
1376 }
1377 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1378 if (rc) {
1379 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1380 goto err_out_clk_dis_pclk;
1381 }
1382
1383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1384 if (!res) {
1385 rc = -ENODEV;
1386 goto err_out_clk_disable;
1387 }
1388
1389 irq = platform_get_irq(pdev, 0);
1390 if (irq <= 0) {
1391 rc = -ENXIO;
1392 goto err_out_clk_disable;
1393 }
1394
1395 #ifdef CONFIG_COMMON_CLK
1396 cdns_uart_data->clk_rate_change_nb.notifier_call =
1397 cdns_uart_clk_notifier_cb;
1398 if (clk_notifier_register(cdns_uart_data->uartclk,
1399 &cdns_uart_data->clk_rate_change_nb))
1400 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1401 #endif
1402 /* Look for a serialN alias */
1403 id = of_alias_get_id(pdev->dev.of_node, "serial");
1404 if (id < 0)
1405 id = 0;
1406
1407 /* Initialize the port structure */
1408 port = cdns_uart_get_port(id);
1409
1410 if (!port) {
1411 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1412 rc = -ENODEV;
1413 goto err_out_notif_unreg;
1414 } else {
1415 /* Register the port.
1416 * This function also registers this device with the tty layer
1417 * and triggers invocation of the config_port() entry point.
1418 */
1419 port->mapbase = res->start;
1420 port->irq = irq;
1421 port->dev = &pdev->dev;
1422 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1423 port->private_data = cdns_uart_data;
1424 cdns_uart_data->port = port;
1425 platform_set_drvdata(pdev, port);
1426 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1427 if (rc) {
1428 dev_err(&pdev->dev,
1429 "uart_add_one_port() failed; err=%i\n", rc);
1430 goto err_out_notif_unreg;
1431 }
1432 return 0;
1433 }
1434
1435 err_out_notif_unreg:
1436 #ifdef CONFIG_COMMON_CLK
1437 clk_notifier_unregister(cdns_uart_data->uartclk,
1438 &cdns_uart_data->clk_rate_change_nb);
1439 #endif
1440 err_out_clk_disable:
1441 clk_disable_unprepare(cdns_uart_data->uartclk);
1442 err_out_clk_dis_pclk:
1443 clk_disable_unprepare(cdns_uart_data->pclk);
1444
1445 return rc;
1446 }
1447
1448 /**
1449 * cdns_uart_remove - called when the platform driver is unregistered
1450 * @pdev: Pointer to the platform device structure
1451 *
1452 * Return: 0 on success, negative errno otherwise
1453 */
1454 static int cdns_uart_remove(struct platform_device *pdev)
1455 {
1456 struct uart_port *port = platform_get_drvdata(pdev);
1457 struct cdns_uart *cdns_uart_data = port->private_data;
1458 int rc;
1459
1460 /* Remove the cdns_uart port from the serial core */
1461 #ifdef CONFIG_COMMON_CLK
1462 clk_notifier_unregister(cdns_uart_data->uartclk,
1463 &cdns_uart_data->clk_rate_change_nb);
1464 #endif
1465 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1466 port->mapbase = 0;
1467 clk_disable_unprepare(cdns_uart_data->uartclk);
1468 clk_disable_unprepare(cdns_uart_data->pclk);
1469 return rc;
1470 }
1471
1472 /* Match table for of_platform binding */
1473 static const struct of_device_id cdns_uart_of_match[] = {
1474 { .compatible = "xlnx,xuartps", },
1475 { .compatible = "cdns,uart-r1p8", },
1476 {}
1477 };
1478 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1479
1480 static struct platform_driver cdns_uart_platform_driver = {
1481 .probe = cdns_uart_probe,
1482 .remove = cdns_uart_remove,
1483 .driver = {
1484 .name = CDNS_UART_NAME,
1485 .of_match_table = cdns_uart_of_match,
1486 .pm = &cdns_uart_dev_pm_ops,
1487 },
1488 };
1489
1490 static int __init cdns_uart_init(void)
1491 {
1492 int retval = 0;
1493
1494 /* Register the cdns_uart driver with the serial core */
1495 retval = uart_register_driver(&cdns_uart_uart_driver);
1496 if (retval)
1497 return retval;
1498
1499 /* Register the platform driver */
1500 retval = platform_driver_register(&cdns_uart_platform_driver);
1501 if (retval)
1502 uart_unregister_driver(&cdns_uart_uart_driver);
1503
1504 return retval;
1505 }
1506
1507 static void __exit cdns_uart_exit(void)
1508 {
1509 /* Unregister the platform driver */
1510 platform_driver_unregister(&cdns_uart_platform_driver);
1511
1512 /* Unregister the cdns_uart driver */
1513 uart_unregister_driver(&cdns_uart_uart_driver);
1514 }
1515
1516 module_init(cdns_uart_init);
1517 module_exit(cdns_uart_exit);
1518
1519 MODULE_DESCRIPTION("Driver for Cadence UART");
1520 MODULE_AUTHOR("Xilinx Inc.");
1521 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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