2 * Xilinx PS UART driver
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/clk.h>
26 #include <linux/irq.h>
29 #include <linux/module.h>
31 #define XUARTPS_TTY_NAME "ttyPS"
32 #define XUARTPS_NAME "xuartps"
33 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34 #define XUARTPS_MINOR 0 /* works best with devtmpfs */
35 #define XUARTPS_NR_PORTS 2
36 #define XUARTPS_FIFO_SIZE 64 /* FIFO size */
37 #define XUARTPS_REGISTER_SPACE 0xFFF
39 #define xuartps_readl(offset) ioread32(port->membase + offset)
40 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
42 /* Rx Trigger level */
43 static int rx_trigger_level
= 56;
44 module_param(rx_trigger_level
, uint
, S_IRUGO
);
45 MODULE_PARM_DESC(rx_trigger_level
, "Rx trigger level, 1-63 bytes");
48 static int rx_timeout
= 10;
49 module_param(rx_timeout
, uint
, S_IRUGO
);
50 MODULE_PARM_DESC(rx_timeout
, "Rx timeout, 1-255");
52 /********************************Register Map********************************/
55 * Register offsets for the UART.
58 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
59 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
60 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
61 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
62 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
63 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
64 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
65 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
66 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
67 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
68 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
69 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
70 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
71 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
72 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
73 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
75 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
77 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
81 * The Control register (CR) controls the major functions of the device.
83 * Control Register Bit Definitions
85 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
97 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed.
101 * Mode Register Bit Definitions
104 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
108 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
111 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
112 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
117 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
121 /** Interrupt Registers
123 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an
126 * interrupt to the interrupt status register (ISR).
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00.
131 * All four registers have the same bit definitions.
133 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
135 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define XUARTPS_IXR_BRK 0x80000000
148 /** Channel Status Register
150 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register.
154 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
157 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
159 /* baud dividers min/max values */
160 #define XUARTPS_BDIV_MIN 4
161 #define XUARTPS_BDIV_MAX 255
162 #define XUARTPS_CD_MAX 65535
165 * struct xuartps - device data
166 * @port Pointer to the UART port
167 * @refclk Reference clock
169 * @baud Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes
173 struct uart_port
*port
;
177 struct notifier_block clk_rate_change_nb
;
179 #define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
182 * xuartps_isr - Interrupt handler
184 * @dev_id: Id of the port
188 static irqreturn_t
xuartps_isr(int irq
, void *dev_id
)
190 struct uart_port
*port
= (struct uart_port
*)dev_id
;
192 unsigned int isrstatus
, numbytes
;
194 char status
= TTY_NORMAL
;
196 spin_lock_irqsave(&port
->lock
, flags
);
198 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active.
201 isrstatus
= xuartps_readl(XUARTPS_ISR_OFFSET
);
204 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence.
209 if (isrstatus
& XUARTPS_IXR_FRAMING
) {
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET
) &
211 XUARTPS_SR_RXEMPTY
)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET
)) {
213 port
->read_status_mask
|= XUARTPS_IXR_BRK
;
214 isrstatus
&= ~XUARTPS_IXR_FRAMING
;
217 xuartps_writel(XUARTPS_IXR_FRAMING
, XUARTPS_ISR_OFFSET
);
220 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus
& port
->ignore_status_mask
& XUARTPS_IXR_PARITY
)
222 isrstatus
&= ~(XUARTPS_IXR_RXTRIG
| XUARTPS_IXR_TOUT
);
224 isrstatus
&= port
->read_status_mask
;
225 isrstatus
&= ~port
->ignore_status_mask
;
227 if ((isrstatus
& XUARTPS_IXR_TOUT
) ||
228 (isrstatus
& XUARTPS_IXR_RXTRIG
)) {
229 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET
) &
231 XUARTPS_SR_RXEMPTY
) != XUARTPS_SR_RXEMPTY
) {
232 data
= xuartps_readl(XUARTPS_FIFO_OFFSET
);
234 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data
&& (port
->read_status_mask
&
237 port
->read_status_mask
&= ~XUARTPS_IXR_BRK
;
239 if (uart_handle_break(port
))
244 * uart_handle_sysrq_char() doesn't work if
245 * spinlocked, for some reason
248 spin_unlock(&port
->lock
);
249 if (uart_handle_sysrq_char(port
,
250 (unsigned char)data
)) {
251 spin_lock(&port
->lock
);
254 spin_lock(&port
->lock
);
259 if (isrstatus
& XUARTPS_IXR_PARITY
) {
260 port
->icount
.parity
++;
262 } else if (isrstatus
& XUARTPS_IXR_FRAMING
) {
263 port
->icount
.frame
++;
265 } else if (isrstatus
& XUARTPS_IXR_OVERRUN
)
266 port
->icount
.overrun
++;
268 uart_insert_char(port
, isrstatus
, XUARTPS_IXR_OVERRUN
,
271 spin_unlock(&port
->lock
);
272 tty_flip_buffer_push(&port
->state
->port
);
273 spin_lock(&port
->lock
);
276 /* Dispatch an appropriate handler */
277 if ((isrstatus
& XUARTPS_IXR_TXEMPTY
) == XUARTPS_IXR_TXEMPTY
) {
278 if (uart_circ_empty(&port
->state
->xmit
)) {
279 xuartps_writel(XUARTPS_IXR_TXEMPTY
,
282 numbytes
= port
->fifosize
;
283 /* Break if no more data available in the UART buffer */
285 if (uart_circ_empty(&port
->state
->xmit
))
287 /* Get the data from the UART circular buffer
288 * and write it to the xuartps's TX_FIFO
292 port
->state
->xmit
.buf
[port
->state
->xmit
.
293 tail
], XUARTPS_FIFO_OFFSET
);
297 /* Adjust the tail of the UART buffer and wrap
298 * the buffer if it reaches limit.
300 port
->state
->xmit
.tail
=
301 (port
->state
->xmit
.tail
+ 1) & \
302 (UART_XMIT_SIZE
- 1);
305 if (uart_circ_chars_pending(
306 &port
->state
->xmit
) < WAKEUP_CHARS
)
307 uart_write_wakeup(port
);
311 xuartps_writel(isrstatus
, XUARTPS_ISR_OFFSET
);
313 /* be sure to release the lock and tty before leaving */
314 spin_unlock_irqrestore(&port
->lock
, flags
);
320 * xuartps_calc_baud_divs - Calculate baud rate divisors
321 * @clk: UART module input clock
322 * @baud: Desired baud rate
323 * @rbdiv: BDIV value (return value)
324 * @rcd: CD value (return value)
325 * @div8: Value for clk_sel bit in mod (return value)
326 * Returns baud rate, requested baud when possible, or actual baud when there
327 * was too much error, zero if no valid divisors are found.
329 * Formula to obtain baud rate is
330 * baud_tx/rx rate = clk/CD * (BDIV + 1)
331 * input_clk = (Uart User Defined Clock or Apb Clock)
332 * depends on UCLKEN in MR Reg
333 * clk = input_clk or input_clk/8;
334 * depends on CLKS in MR reg
335 * CD and BDIV depends on values in
336 * baud rate generate register
337 * baud rate clock divisor register
339 static unsigned int xuartps_calc_baud_divs(unsigned int clk
, unsigned int baud
,
340 u32
*rbdiv
, u32
*rcd
, int *div8
)
343 unsigned int calc_baud
;
344 unsigned int bestbaud
= 0;
345 unsigned int bauderror
;
346 unsigned int besterror
= ~0;
348 if (baud
< clk
/ ((XUARTPS_BDIV_MAX
+ 1) * XUARTPS_CD_MAX
)) {
355 for (bdiv
= XUARTPS_BDIV_MIN
; bdiv
<= XUARTPS_BDIV_MAX
; bdiv
++) {
356 cd
= DIV_ROUND_CLOSEST(clk
, baud
* (bdiv
+ 1));
357 if (cd
< 1 || cd
> XUARTPS_CD_MAX
)
360 calc_baud
= clk
/ (cd
* (bdiv
+ 1));
362 if (baud
> calc_baud
)
363 bauderror
= baud
- calc_baud
;
365 bauderror
= calc_baud
- baud
;
367 if (besterror
> bauderror
) {
370 bestbaud
= calc_baud
;
371 besterror
= bauderror
;
374 /* use the values when percent error is acceptable */
375 if (((besterror
* 100) / baud
) < 3)
382 * xuartps_set_baud_rate - Calculate and set the baud rate
383 * @port: Handle to the uart port structure
384 * @baud: Baud rate to set
385 * Returns baud rate, requested baud when possible, or actual baud when there
386 * was too much error, zero if no valid divisors are found.
388 static unsigned int xuartps_set_baud_rate(struct uart_port
*port
,
391 unsigned int calc_baud
;
395 struct xuartps
*xuartps
= port
->private_data
;
397 calc_baud
= xuartps_calc_baud_divs(port
->uartclk
, baud
, &bdiv
, &cd
,
400 /* Write new divisors to hardware */
401 mreg
= xuartps_readl(XUARTPS_MR_OFFSET
);
403 mreg
|= XUARTPS_MR_CLKSEL
;
405 mreg
&= ~XUARTPS_MR_CLKSEL
;
406 xuartps_writel(mreg
, XUARTPS_MR_OFFSET
);
407 xuartps_writel(cd
, XUARTPS_BAUDGEN_OFFSET
);
408 xuartps_writel(bdiv
, XUARTPS_BAUDDIV_OFFSET
);
409 xuartps
->baud
= baud
;
415 * xuartps_clk_notitifer_cb - Clock notifier callback
416 * @nb: Notifier block
417 * @event: Notify event
418 * @data: Notifier data
419 * Returns NOTIFY_OK on success, NOTIFY_BAD on error.
421 static int xuartps_clk_notifier_cb(struct notifier_block
*nb
,
422 unsigned long event
, void *data
)
425 struct uart_port
*port
;
427 struct clk_notifier_data
*ndata
= data
;
428 unsigned long flags
= 0;
429 struct xuartps
*xuartps
= to_xuartps(nb
);
431 port
= xuartps
->port
;
436 case PRE_RATE_CHANGE
:
443 * Find out if current baud-rate can be achieved with new clock
446 if (!xuartps_calc_baud_divs(ndata
->new_rate
, xuartps
->baud
,
450 spin_lock_irqsave(&xuartps
->port
->lock
, flags
);
452 /* Disable the TX and RX to set baud rate */
453 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
454 (XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
),
457 spin_unlock_irqrestore(&xuartps
->port
->lock
, flags
);
461 case POST_RATE_CHANGE
:
463 * Set clk dividers to generate correct baud with new clock
467 spin_lock_irqsave(&xuartps
->port
->lock
, flags
);
470 port
->uartclk
= ndata
->new_rate
;
472 xuartps
->baud
= xuartps_set_baud_rate(xuartps
->port
,
475 case ABORT_RATE_CHANGE
:
477 spin_lock_irqsave(&xuartps
->port
->lock
, flags
);
479 /* Set TX/RX Reset */
480 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
481 (XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
),
484 while (xuartps_readl(XUARTPS_CR_OFFSET
) &
485 (XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
))
489 * Clear the RX disable and TX disable bits and then set the TX
490 * enable bit and RX enable bit to enable the transmitter and
493 xuartps_writel(rx_timeout
, XUARTPS_RXTOUT_OFFSET
);
494 ctrl_reg
= xuartps_readl(XUARTPS_CR_OFFSET
);
496 (ctrl_reg
& ~(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
)) |
497 (XUARTPS_CR_TX_EN
| XUARTPS_CR_RX_EN
),
500 spin_unlock_irqrestore(&xuartps
->port
->lock
, flags
);
508 /*----------------------Uart Operations---------------------------*/
511 * xuartps_start_tx - Start transmitting bytes
512 * @port: Handle to the uart port structure
515 static void xuartps_start_tx(struct uart_port
*port
)
517 unsigned int status
, numbytes
= port
->fifosize
;
519 if (uart_circ_empty(&port
->state
->xmit
) || uart_tx_stopped(port
))
522 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
523 /* Set the TX enable bit and clear the TX disable bit to enable the
526 xuartps_writel((status
& ~XUARTPS_CR_TX_DIS
) | XUARTPS_CR_TX_EN
,
529 while (numbytes
-- && ((xuartps_readl(XUARTPS_SR_OFFSET
)
530 & XUARTPS_SR_TXFULL
)) != XUARTPS_SR_TXFULL
) {
532 /* Break if no more data available in the UART buffer */
533 if (uart_circ_empty(&port
->state
->xmit
))
536 /* Get the data from the UART circular buffer and
537 * write it to the xuartps's TX_FIFO register.
540 port
->state
->xmit
.buf
[port
->state
->xmit
.tail
],
541 XUARTPS_FIFO_OFFSET
);
544 /* Adjust the tail of the UART buffer and wrap
545 * the buffer if it reaches limit.
547 port
->state
->xmit
.tail
= (port
->state
->xmit
.tail
+ 1) &
548 (UART_XMIT_SIZE
- 1);
550 xuartps_writel(XUARTPS_IXR_TXEMPTY
, XUARTPS_ISR_OFFSET
);
551 /* Enable the TX Empty interrupt */
552 xuartps_writel(XUARTPS_IXR_TXEMPTY
, XUARTPS_IER_OFFSET
);
554 if (uart_circ_chars_pending(&port
->state
->xmit
) < WAKEUP_CHARS
)
555 uart_write_wakeup(port
);
559 * xuartps_stop_tx - Stop TX
560 * @port: Handle to the uart port structure
563 static void xuartps_stop_tx(struct uart_port
*port
)
567 regval
= xuartps_readl(XUARTPS_CR_OFFSET
);
568 regval
|= XUARTPS_CR_TX_DIS
;
569 /* Disable the transmitter */
570 xuartps_writel(regval
, XUARTPS_CR_OFFSET
);
574 * xuartps_stop_rx - Stop RX
575 * @port: Handle to the uart port structure
578 static void xuartps_stop_rx(struct uart_port
*port
)
582 regval
= xuartps_readl(XUARTPS_CR_OFFSET
);
583 regval
|= XUARTPS_CR_RX_DIS
;
584 /* Disable the receiver */
585 xuartps_writel(regval
, XUARTPS_CR_OFFSET
);
589 * xuartps_tx_empty - Check whether TX is empty
590 * @port: Handle to the uart port structure
592 * Returns TIOCSER_TEMT on success, 0 otherwise
594 static unsigned int xuartps_tx_empty(struct uart_port
*port
)
598 status
= xuartps_readl(XUARTPS_ISR_OFFSET
) & XUARTPS_IXR_TXEMPTY
;
599 return status
? TIOCSER_TEMT
: 0;
603 * xuartps_break_ctl - Based on the input ctl we have to start or stop
604 * transmitting char breaks
605 * @port: Handle to the uart port structure
606 * @ctl: Value based on which start or stop decision is taken
609 static void xuartps_break_ctl(struct uart_port
*port
, int ctl
)
614 spin_lock_irqsave(&port
->lock
, flags
);
616 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
619 xuartps_writel(XUARTPS_CR_STARTBRK
| status
,
622 if ((status
& XUARTPS_CR_STOPBRK
) == 0)
623 xuartps_writel(XUARTPS_CR_STOPBRK
| status
,
626 spin_unlock_irqrestore(&port
->lock
, flags
);
630 * xuartps_set_termios - termios operations, handling data length, parity,
631 * stop bits, flow control, baud rate
632 * @port: Handle to the uart port structure
633 * @termios: Handle to the input termios structure
634 * @old: Values of the previously saved termios structure
637 static void xuartps_set_termios(struct uart_port
*port
,
638 struct ktermios
*termios
, struct ktermios
*old
)
640 unsigned int cval
= 0;
641 unsigned int baud
, minbaud
, maxbaud
;
643 unsigned int ctrl_reg
, mode_reg
;
645 spin_lock_irqsave(&port
->lock
, flags
);
647 /* Empty the receive FIFO 1st before making changes */
648 while ((xuartps_readl(XUARTPS_SR_OFFSET
) &
649 XUARTPS_SR_RXEMPTY
) != XUARTPS_SR_RXEMPTY
) {
650 xuartps_readl(XUARTPS_FIFO_OFFSET
);
653 /* Disable the TX and RX to set baud rate */
654 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
655 (XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
),
659 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
660 * min and max baud should be calculated here based on port->uartclk.
661 * this way we get a valid baud and can safely call set_baud()
663 minbaud
= port
->uartclk
/ ((XUARTPS_BDIV_MAX
+ 1) * XUARTPS_CD_MAX
* 8);
664 maxbaud
= port
->uartclk
/ (XUARTPS_BDIV_MIN
+ 1);
665 baud
= uart_get_baud_rate(port
, termios
, old
, minbaud
, maxbaud
);
666 baud
= xuartps_set_baud_rate(port
, baud
);
667 if (tty_termios_baud_rate(termios
))
668 tty_termios_encode_baud_rate(termios
, baud
, baud
);
671 * Update the per-port timeout.
673 uart_update_timeout(port
, termios
->c_cflag
, baud
);
675 /* Set TX/RX Reset */
676 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
677 (XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
),
680 ctrl_reg
= xuartps_readl(XUARTPS_CR_OFFSET
);
682 /* Clear the RX disable and TX disable bits and then set the TX enable
683 * bit and RX enable bit to enable the transmitter and receiver.
686 (ctrl_reg
& ~(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
))
687 | (XUARTPS_CR_TX_EN
| XUARTPS_CR_RX_EN
),
690 xuartps_writel(rx_timeout
, XUARTPS_RXTOUT_OFFSET
);
692 port
->read_status_mask
= XUARTPS_IXR_TXEMPTY
| XUARTPS_IXR_RXTRIG
|
693 XUARTPS_IXR_OVERRUN
| XUARTPS_IXR_TOUT
;
694 port
->ignore_status_mask
= 0;
696 if (termios
->c_iflag
& INPCK
)
697 port
->read_status_mask
|= XUARTPS_IXR_PARITY
|
700 if (termios
->c_iflag
& IGNPAR
)
701 port
->ignore_status_mask
|= XUARTPS_IXR_PARITY
|
702 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
;
704 /* ignore all characters if CREAD is not set */
705 if ((termios
->c_cflag
& CREAD
) == 0)
706 port
->ignore_status_mask
|= XUARTPS_IXR_RXTRIG
|
707 XUARTPS_IXR_TOUT
| XUARTPS_IXR_PARITY
|
708 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
;
710 mode_reg
= xuartps_readl(XUARTPS_MR_OFFSET
);
712 /* Handling Data Size */
713 switch (termios
->c_cflag
& CSIZE
) {
715 cval
|= XUARTPS_MR_CHARLEN_6_BIT
;
718 cval
|= XUARTPS_MR_CHARLEN_7_BIT
;
722 cval
|= XUARTPS_MR_CHARLEN_8_BIT
;
723 termios
->c_cflag
&= ~CSIZE
;
724 termios
->c_cflag
|= CS8
;
728 /* Handling Parity and Stop Bits length */
729 if (termios
->c_cflag
& CSTOPB
)
730 cval
|= XUARTPS_MR_STOPMODE_2_BIT
; /* 2 STOP bits */
732 cval
|= XUARTPS_MR_STOPMODE_1_BIT
; /* 1 STOP bit */
734 if (termios
->c_cflag
& PARENB
) {
735 /* Mark or Space parity */
736 if (termios
->c_cflag
& CMSPAR
) {
737 if (termios
->c_cflag
& PARODD
)
738 cval
|= XUARTPS_MR_PARITY_MARK
;
740 cval
|= XUARTPS_MR_PARITY_SPACE
;
742 if (termios
->c_cflag
& PARODD
)
743 cval
|= XUARTPS_MR_PARITY_ODD
;
745 cval
|= XUARTPS_MR_PARITY_EVEN
;
748 cval
|= XUARTPS_MR_PARITY_NONE
;
750 cval
|= mode_reg
& 1;
751 xuartps_writel(cval
, XUARTPS_MR_OFFSET
);
753 spin_unlock_irqrestore(&port
->lock
, flags
);
757 * xuartps_startup - Called when an application opens a xuartps port
758 * @port: Handle to the uart port structure
760 * Returns 0 on success, negative error otherwise
762 static int xuartps_startup(struct uart_port
*port
)
764 unsigned int retval
= 0, status
= 0;
766 retval
= request_irq(port
->irq
, xuartps_isr
, 0, XUARTPS_NAME
,
771 /* Disable the TX and RX */
772 xuartps_writel(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
,
775 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
778 xuartps_writel(XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
,
781 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
783 /* Clear the RX disable and TX disable bits and then set the TX enable
784 * bit and RX enable bit to enable the transmitter and receiver.
786 xuartps_writel((status
& ~(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
))
787 | (XUARTPS_CR_TX_EN
| XUARTPS_CR_RX_EN
|
788 XUARTPS_CR_STOPBRK
), XUARTPS_CR_OFFSET
);
790 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
793 xuartps_writel(XUARTPS_MR_CHMODE_NORM
| XUARTPS_MR_STOPMODE_1_BIT
794 | XUARTPS_MR_PARITY_NONE
| XUARTPS_MR_CHARLEN_8_BIT
,
798 * Set the RX FIFO Trigger level to use most of the FIFO, but it
799 * can be tuned with a module parameter
801 xuartps_writel(rx_trigger_level
, XUARTPS_RXWM_OFFSET
);
804 * Receive Timeout register is enabled but it
805 * can be tuned with a module parameter
807 xuartps_writel(rx_timeout
, XUARTPS_RXTOUT_OFFSET
);
809 /* Clear out any pending interrupts before enabling them */
810 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET
), XUARTPS_ISR_OFFSET
);
812 /* Set the Interrupt Registers with desired interrupts */
813 xuartps_writel(XUARTPS_IXR_TXEMPTY
| XUARTPS_IXR_PARITY
|
814 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
|
815 XUARTPS_IXR_RXTRIG
| XUARTPS_IXR_TOUT
, XUARTPS_IER_OFFSET
);
821 * xuartps_shutdown - Called when an application closes a xuartps port
822 * @port: Handle to the uart port structure
825 static void xuartps_shutdown(struct uart_port
*port
)
829 /* Disable interrupts */
830 status
= xuartps_readl(XUARTPS_IMR_OFFSET
);
831 xuartps_writel(status
, XUARTPS_IDR_OFFSET
);
833 /* Disable the TX and RX */
834 xuartps_writel(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
,
836 free_irq(port
->irq
, port
);
840 * xuartps_type - Set UART type to xuartps port
841 * @port: Handle to the uart port structure
843 * Returns string on success, NULL otherwise
845 static const char *xuartps_type(struct uart_port
*port
)
847 return port
->type
== PORT_XUARTPS
? XUARTPS_NAME
: NULL
;
851 * xuartps_verify_port - Verify the port params
852 * @port: Handle to the uart port structure
853 * @ser: Handle to the structure whose members are compared
855 * Returns 0 if success otherwise -EINVAL
857 static int xuartps_verify_port(struct uart_port
*port
,
858 struct serial_struct
*ser
)
860 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_XUARTPS
)
862 if (port
->irq
!= ser
->irq
)
864 if (ser
->io_type
!= UPIO_MEM
)
866 if (port
->iobase
!= ser
->port
)
874 * xuartps_request_port - Claim the memory region attached to xuartps port,
875 * called when the driver adds a xuartps port via
876 * uart_add_one_port()
877 * @port: Handle to the uart port structure
879 * Returns 0, -ENOMEM if request fails
881 static int xuartps_request_port(struct uart_port
*port
)
883 if (!request_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
,
888 port
->membase
= ioremap(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
889 if (!port
->membase
) {
890 dev_err(port
->dev
, "Unable to map registers\n");
891 release_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
898 * xuartps_release_port - Release the memory region attached to a xuartps
899 * port, called when the driver removes a xuartps
900 * port via uart_remove_one_port().
901 * @port: Handle to the uart port structure
904 static void xuartps_release_port(struct uart_port
*port
)
906 release_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
907 iounmap(port
->membase
);
908 port
->membase
= NULL
;
912 * xuartps_config_port - Configure xuartps, called when the driver adds a
914 * @port: Handle to the uart port structure
918 static void xuartps_config_port(struct uart_port
*port
, int flags
)
920 if (flags
& UART_CONFIG_TYPE
&& xuartps_request_port(port
) == 0)
921 port
->type
= PORT_XUARTPS
;
925 * xuartps_get_mctrl - Get the modem control state
927 * @port: Handle to the uart port structure
929 * Returns the modem control state
932 static unsigned int xuartps_get_mctrl(struct uart_port
*port
)
934 return TIOCM_CTS
| TIOCM_DSR
| TIOCM_CAR
;
937 static void xuartps_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
942 static void xuartps_enable_ms(struct uart_port
*port
)
947 #ifdef CONFIG_CONSOLE_POLL
948 static int xuartps_poll_get_char(struct uart_port
*port
)
953 /* Disable all interrupts */
954 imr
= xuartps_readl(XUARTPS_IMR_OFFSET
);
955 xuartps_writel(imr
, XUARTPS_IDR_OFFSET
);
957 /* Check if FIFO is empty */
958 if (xuartps_readl(XUARTPS_SR_OFFSET
) & XUARTPS_SR_RXEMPTY
)
960 else /* Read a character */
961 c
= (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET
);
963 /* Enable interrupts */
964 xuartps_writel(imr
, XUARTPS_IER_OFFSET
);
969 static void xuartps_poll_put_char(struct uart_port
*port
, unsigned char c
)
973 /* Disable all interrupts */
974 imr
= xuartps_readl(XUARTPS_IMR_OFFSET
);
975 xuartps_writel(imr
, XUARTPS_IDR_OFFSET
);
977 /* Wait until FIFO is empty */
978 while (!(xuartps_readl(XUARTPS_SR_OFFSET
) & XUARTPS_SR_TXEMPTY
))
981 /* Write a character */
982 xuartps_writel(c
, XUARTPS_FIFO_OFFSET
);
984 /* Wait until FIFO is empty */
985 while (!(xuartps_readl(XUARTPS_SR_OFFSET
) & XUARTPS_SR_TXEMPTY
))
988 /* Enable interrupts */
989 xuartps_writel(imr
, XUARTPS_IER_OFFSET
);
995 /** The UART operations structure
997 static struct uart_ops xuartps_ops
= {
998 .set_mctrl
= xuartps_set_mctrl
,
999 .get_mctrl
= xuartps_get_mctrl
,
1000 .enable_ms
= xuartps_enable_ms
,
1002 .start_tx
= xuartps_start_tx
, /* Start transmitting */
1003 .stop_tx
= xuartps_stop_tx
, /* Stop transmission */
1004 .stop_rx
= xuartps_stop_rx
, /* Stop reception */
1005 .tx_empty
= xuartps_tx_empty
, /* Transmitter busy? */
1006 .break_ctl
= xuartps_break_ctl
, /* Start/stop
1007 * transmitting break
1009 .set_termios
= xuartps_set_termios
, /* Set termios */
1010 .startup
= xuartps_startup
, /* App opens xuartps */
1011 .shutdown
= xuartps_shutdown
, /* App closes xuartps */
1012 .type
= xuartps_type
, /* Set UART type */
1013 .verify_port
= xuartps_verify_port
, /* Verification of port
1016 .request_port
= xuartps_request_port
, /* Claim resources
1020 .release_port
= xuartps_release_port
, /* Release resources
1024 .config_port
= xuartps_config_port
, /* Configure when driver
1025 * adds a xuartps port
1027 #ifdef CONFIG_CONSOLE_POLL
1028 .poll_get_char
= xuartps_poll_get_char
,
1029 .poll_put_char
= xuartps_poll_put_char
,
1033 static struct uart_port xuartps_port
[2];
1036 * xuartps_get_port - Configure the port from the platform device resource
1039 * Returns a pointer to a uart_port or NULL for failure
1041 static struct uart_port
*xuartps_get_port(void)
1043 struct uart_port
*port
;
1046 /* Find the next unused port */
1047 for (id
= 0; id
< XUARTPS_NR_PORTS
; id
++)
1048 if (xuartps_port
[id
].mapbase
== 0)
1051 if (id
>= XUARTPS_NR_PORTS
)
1054 port
= &xuartps_port
[id
];
1056 /* At this point, we've got an empty uart_port struct, initialize it */
1057 spin_lock_init(&port
->lock
);
1058 port
->membase
= NULL
;
1059 port
->iobase
= 1; /* mark port in use */
1061 port
->type
= PORT_UNKNOWN
;
1062 port
->iotype
= UPIO_MEM32
;
1063 port
->flags
= UPF_BOOT_AUTOCONF
;
1064 port
->ops
= &xuartps_ops
;
1065 port
->fifosize
= XUARTPS_FIFO_SIZE
;
1071 /*-----------------------Console driver operations--------------------------*/
1073 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1075 * xuartps_console_wait_tx - Wait for the TX to be full
1076 * @port: Handle to the uart port structure
1079 static void xuartps_console_wait_tx(struct uart_port
*port
)
1081 while ((xuartps_readl(XUARTPS_SR_OFFSET
) & XUARTPS_SR_TXEMPTY
)
1082 != XUARTPS_SR_TXEMPTY
)
1087 * xuartps_console_putchar - write the character to the FIFO buffer
1088 * @port: Handle to the uart port structure
1089 * @ch: Character to be written
1092 static void xuartps_console_putchar(struct uart_port
*port
, int ch
)
1094 xuartps_console_wait_tx(port
);
1095 xuartps_writel(ch
, XUARTPS_FIFO_OFFSET
);
1099 * xuartps_console_write - perform write operation
1100 * @port: Handle to the uart port structure
1101 * @s: Pointer to character array
1102 * @count: No of characters
1104 static void xuartps_console_write(struct console
*co
, const char *s
,
1107 struct uart_port
*port
= &xuartps_port
[co
->index
];
1108 unsigned long flags
;
1109 unsigned int imr
, ctrl
;
1112 if (oops_in_progress
)
1113 locked
= spin_trylock_irqsave(&port
->lock
, flags
);
1115 spin_lock_irqsave(&port
->lock
, flags
);
1117 /* save and disable interrupt */
1118 imr
= xuartps_readl(XUARTPS_IMR_OFFSET
);
1119 xuartps_writel(imr
, XUARTPS_IDR_OFFSET
);
1122 * Make sure that the tx part is enabled. Set the TX enable bit and
1123 * clear the TX disable bit to enable the transmitter.
1125 ctrl
= xuartps_readl(XUARTPS_CR_OFFSET
);
1126 xuartps_writel((ctrl
& ~XUARTPS_CR_TX_DIS
) | XUARTPS_CR_TX_EN
,
1129 uart_console_write(port
, s
, count
, xuartps_console_putchar
);
1130 xuartps_console_wait_tx(port
);
1132 xuartps_writel(ctrl
, XUARTPS_CR_OFFSET
);
1134 /* restore interrupt state, it seems like there may be a h/w bug
1135 * in that the interrupt enable register should not need to be
1136 * written based on the data sheet
1138 xuartps_writel(~imr
, XUARTPS_IDR_OFFSET
);
1139 xuartps_writel(imr
, XUARTPS_IER_OFFSET
);
1142 spin_unlock_irqrestore(&port
->lock
, flags
);
1146 * xuartps_console_setup - Initialize the uart to default config
1147 * @co: Console handle
1148 * @options: Initial settings of uart
1150 * Returns 0, -ENODEV if no device
1152 static int __init
xuartps_console_setup(struct console
*co
, char *options
)
1154 struct uart_port
*port
= &xuartps_port
[co
->index
];
1160 if (co
->index
< 0 || co
->index
>= XUARTPS_NR_PORTS
)
1163 if (!port
->mapbase
) {
1164 pr_debug("console on ttyPS%i not present\n", co
->index
);
1169 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1171 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1174 static struct uart_driver xuartps_uart_driver
;
1176 static struct console xuartps_console
= {
1177 .name
= XUARTPS_TTY_NAME
,
1178 .write
= xuartps_console_write
,
1179 .device
= uart_console_device
,
1180 .setup
= xuartps_console_setup
,
1181 .flags
= CON_PRINTBUFFER
,
1182 .index
= -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1183 .data
= &xuartps_uart_driver
,
1187 * xuartps_console_init - Initialization call
1189 * Returns 0 on success, negative error otherwise
1191 static int __init
xuartps_console_init(void)
1193 register_console(&xuartps_console
);
1197 console_initcall(xuartps_console_init
);
1199 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1201 /** Structure Definitions
1203 static struct uart_driver xuartps_uart_driver
= {
1204 .owner
= THIS_MODULE
, /* Owner */
1205 .driver_name
= XUARTPS_NAME
, /* Driver name */
1206 .dev_name
= XUARTPS_TTY_NAME
, /* Node name */
1207 .major
= XUARTPS_MAJOR
, /* Major number */
1208 .minor
= XUARTPS_MINOR
, /* Minor number */
1209 .nr
= XUARTPS_NR_PORTS
, /* Number of UART ports */
1210 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1211 .cons
= &xuartps_console
, /* Console */
1215 /* ---------------------------------------------------------------------
1216 * Platform bus binding
1219 * xuartps_probe - Platform driver probe
1220 * @pdev: Pointer to the platform device structure
1222 * Returns 0 on success, negative error otherwise
1224 static int xuartps_probe(struct platform_device
*pdev
)
1227 struct uart_port
*port
;
1228 struct resource
*res
, *res2
;
1229 struct xuartps
*xuartps_data
;
1231 xuartps_data
= devm_kzalloc(&pdev
->dev
, sizeof(*xuartps_data
),
1236 xuartps_data
->aperclk
= devm_clk_get(&pdev
->dev
, "aper_clk");
1237 if (IS_ERR(xuartps_data
->aperclk
)) {
1238 dev_err(&pdev
->dev
, "aper_clk clock not found.\n");
1239 return PTR_ERR(xuartps_data
->aperclk
);
1241 xuartps_data
->refclk
= devm_clk_get(&pdev
->dev
, "ref_clk");
1242 if (IS_ERR(xuartps_data
->refclk
)) {
1243 dev_err(&pdev
->dev
, "ref_clk clock not found.\n");
1244 return PTR_ERR(xuartps_data
->refclk
);
1247 rc
= clk_prepare_enable(xuartps_data
->aperclk
);
1249 dev_err(&pdev
->dev
, "Unable to enable APER clock.\n");
1252 rc
= clk_prepare_enable(xuartps_data
->refclk
);
1254 dev_err(&pdev
->dev
, "Unable to enable device clock.\n");
1255 goto err_out_clk_dis_aper
;
1258 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1261 goto err_out_clk_disable
;
1264 res2
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1267 goto err_out_clk_disable
;
1270 xuartps_data
->clk_rate_change_nb
.notifier_call
=
1271 xuartps_clk_notifier_cb
;
1272 if (clk_notifier_register(xuartps_data
->refclk
,
1273 &xuartps_data
->clk_rate_change_nb
))
1274 dev_warn(&pdev
->dev
, "Unable to register clock notifier.\n");
1276 /* Initialize the port structure */
1277 port
= xuartps_get_port();
1280 dev_err(&pdev
->dev
, "Cannot get uart_port structure\n");
1282 goto err_out_notif_unreg
;
1284 /* Register the port.
1285 * This function also registers this device with the tty layer
1286 * and triggers invocation of the config_port() entry point.
1288 port
->mapbase
= res
->start
;
1289 port
->irq
= res2
->start
;
1290 port
->dev
= &pdev
->dev
;
1291 port
->uartclk
= clk_get_rate(xuartps_data
->refclk
);
1292 port
->private_data
= xuartps_data
;
1293 xuartps_data
->port
= port
;
1294 platform_set_drvdata(pdev
, port
);
1295 rc
= uart_add_one_port(&xuartps_uart_driver
, port
);
1298 "uart_add_one_port() failed; err=%i\n", rc
);
1299 goto err_out_notif_unreg
;
1304 err_out_notif_unreg
:
1305 clk_notifier_unregister(xuartps_data
->refclk
,
1306 &xuartps_data
->clk_rate_change_nb
);
1307 err_out_clk_disable
:
1308 clk_disable_unprepare(xuartps_data
->refclk
);
1309 err_out_clk_dis_aper
:
1310 clk_disable_unprepare(xuartps_data
->aperclk
);
1316 * xuartps_remove - called when the platform driver is unregistered
1317 * @pdev: Pointer to the platform device structure
1319 * Returns 0 on success, negative error otherwise
1321 static int xuartps_remove(struct platform_device
*pdev
)
1323 struct uart_port
*port
= platform_get_drvdata(pdev
);
1324 struct xuartps
*xuartps_data
= port
->private_data
;
1327 /* Remove the xuartps port from the serial core */
1328 clk_notifier_unregister(xuartps_data
->refclk
,
1329 &xuartps_data
->clk_rate_change_nb
);
1330 rc
= uart_remove_one_port(&xuartps_uart_driver
, port
);
1332 clk_disable_unprepare(xuartps_data
->refclk
);
1333 clk_disable_unprepare(xuartps_data
->aperclk
);
1337 /* Match table for of_platform binding */
1338 static struct of_device_id xuartps_of_match
[] = {
1339 { .compatible
= "xlnx,xuartps", },
1342 MODULE_DEVICE_TABLE(of
, xuartps_of_match
);
1344 static struct platform_driver xuartps_platform_driver
= {
1345 .probe
= xuartps_probe
, /* Probe method */
1346 .remove
= xuartps_remove
, /* Detach method */
1348 .owner
= THIS_MODULE
,
1349 .name
= XUARTPS_NAME
, /* Driver name */
1350 .of_match_table
= xuartps_of_match
,
1354 /* ---------------------------------------------------------------------
1355 * Module Init and Exit
1358 * xuartps_init - Initial driver registration call
1360 * Returns whether the registration was successful or not
1362 static int __init
xuartps_init(void)
1366 /* Register the xuartps driver with the serial core */
1367 retval
= uart_register_driver(&xuartps_uart_driver
);
1371 /* Register the platform driver */
1372 retval
= platform_driver_register(&xuartps_platform_driver
);
1374 uart_unregister_driver(&xuartps_uart_driver
);
1380 * xuartps_exit - Driver unregistration call
1382 static void __exit
xuartps_exit(void)
1384 /* The order of unregistration is important. Unregister the
1385 * UART driver before the platform driver crashes the system.
1388 /* Unregister the platform driver */
1389 platform_driver_unregister(&xuartps_platform_driver
);
1391 /* Unregister the xuartps driver */
1392 uart_unregister_driver(&xuartps_uart_driver
);
1395 module_init(xuartps_init
);
1396 module_exit(xuartps_exit
);
1398 MODULE_DESCRIPTION("Driver for PS UART");
1399 MODULE_AUTHOR("Xilinx Inc.");
1400 MODULE_LICENSE("GPL");