2 * Xilinx PS UART driver
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
14 #include <linux/platform_device.h>
15 #include <linux/serial.h>
16 #include <linux/serial_core.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/console.h>
20 #include <linux/clk.h>
21 #include <linux/irq.h>
24 #include <linux/module.h>
26 #define XUARTPS_TTY_NAME "ttyPS"
27 #define XUARTPS_NAME "xuartps"
28 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */
29 #define XUARTPS_MINOR 0 /* works best with devtmpfs */
30 #define XUARTPS_NR_PORTS 2
31 #define XUARTPS_FIFO_SIZE 16 /* FIFO size */
32 #define XUARTPS_REGISTER_SPACE 0xFFF
34 #define xuartps_readl(offset) ioread32(port->membase + offset)
35 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
37 /********************************Register Map********************************/
40 * Register offsets for the UART.
43 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
44 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
45 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
46 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
47 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
48 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
49 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
50 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
51 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
52 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
53 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
54 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
55 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
56 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
57 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
58 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
60 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
62 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
66 * The Control register (CR) controls the major functions of the device.
68 * Control Register Bit Definitions
70 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
71 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
72 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
73 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
74 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
75 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
76 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
77 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
78 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82 * The mode register (MR) defines the mode of transfer as well as the data
83 * format. If this register is modified during transmission or reception,
84 * data validity cannot be guaranteed.
86 * Mode Register Bit Definitions
89 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
93 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
97 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106 /** Interrupt Registers
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
118 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
120 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
130 /** Channel Status Register
132 * The channel status register (CSR) is provided to enable the control logic
133 * to monitor the status of bits in the channel interrupt status register,
134 * even if these are masked out by the interrupt mask register.
136 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
137 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
138 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
139 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
142 * xuartps_isr - Interrupt handler
144 * @dev_id: Id of the port
148 static irqreturn_t
xuartps_isr(int irq
, void *dev_id
)
150 struct uart_port
*port
= (struct uart_port
*)dev_id
;
152 unsigned int isrstatus
, numbytes
;
154 char status
= TTY_NORMAL
;
156 spin_lock_irqsave(&port
->lock
, flags
);
158 /* Read the interrupt status register to determine which
159 * interrupt(s) is/are active.
161 isrstatus
= xuartps_readl(XUARTPS_ISR_OFFSET
);
163 /* drop byte with parity error if IGNPAR specified */
164 if (isrstatus
& port
->ignore_status_mask
& XUARTPS_IXR_PARITY
)
165 isrstatus
&= ~(XUARTPS_IXR_RXTRIG
| XUARTPS_IXR_TOUT
);
167 isrstatus
&= port
->read_status_mask
;
168 isrstatus
&= ~port
->ignore_status_mask
;
170 if ((isrstatus
& XUARTPS_IXR_TOUT
) ||
171 (isrstatus
& XUARTPS_IXR_RXTRIG
)) {
172 /* Receive Timeout Interrupt */
173 while ((xuartps_readl(XUARTPS_SR_OFFSET
) &
174 XUARTPS_SR_RXEMPTY
) != XUARTPS_SR_RXEMPTY
) {
175 data
= xuartps_readl(XUARTPS_FIFO_OFFSET
);
178 if (isrstatus
& XUARTPS_IXR_PARITY
) {
179 port
->icount
.parity
++;
181 } else if (isrstatus
& XUARTPS_IXR_FRAMING
) {
182 port
->icount
.frame
++;
184 } else if (isrstatus
& XUARTPS_IXR_OVERRUN
)
185 port
->icount
.overrun
++;
187 uart_insert_char(port
, isrstatus
, XUARTPS_IXR_OVERRUN
,
190 spin_unlock(&port
->lock
);
191 tty_flip_buffer_push(&port
->state
->port
);
192 spin_lock(&port
->lock
);
195 /* Dispatch an appropriate handler */
196 if ((isrstatus
& XUARTPS_IXR_TXEMPTY
) == XUARTPS_IXR_TXEMPTY
) {
197 if (uart_circ_empty(&port
->state
->xmit
)) {
198 xuartps_writel(XUARTPS_IXR_TXEMPTY
,
201 numbytes
= port
->fifosize
;
202 /* Break if no more data available in the UART buffer */
204 if (uart_circ_empty(&port
->state
->xmit
))
206 /* Get the data from the UART circular buffer
207 * and write it to the xuartps's TX_FIFO
211 port
->state
->xmit
.buf
[port
->state
->xmit
.
212 tail
], XUARTPS_FIFO_OFFSET
);
216 /* Adjust the tail of the UART buffer and wrap
217 * the buffer if it reaches limit.
219 port
->state
->xmit
.tail
=
220 (port
->state
->xmit
.tail
+ 1) & \
221 (UART_XMIT_SIZE
- 1);
224 if (uart_circ_chars_pending(
225 &port
->state
->xmit
) < WAKEUP_CHARS
)
226 uart_write_wakeup(port
);
230 xuartps_writel(isrstatus
, XUARTPS_ISR_OFFSET
);
232 /* be sure to release the lock and tty before leaving */
233 spin_unlock_irqrestore(&port
->lock
, flags
);
239 * xuartps_set_baud_rate - Calculate and set the baud rate
240 * @port: Handle to the uart port structure
241 * @baud: Baud rate to set
243 * Returns baud rate, requested baud when possible, or actual baud when there
246 static unsigned int xuartps_set_baud_rate(struct uart_port
*port
,
249 unsigned int sel_clk
;
250 unsigned int calc_baud
= 0;
251 unsigned int brgr_val
, brdiv_val
;
252 unsigned int bauderror
;
254 /* Formula to obtain baud rate is
255 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
256 * input_clk = (Uart User Defined Clock or Apb Clock)
257 * depends on UCLKEN in MR Reg
258 * sel_clk = input_clk or input_clk/8;
259 * depends on CLKS in MR reg
260 * CD and BDIV depends on values in
261 * baud rate generate register
262 * baud rate clock divisor register
264 sel_clk
= port
->uartclk
;
265 if (xuartps_readl(XUARTPS_MR_OFFSET
) & XUARTPS_MR_CLKSEL
)
266 sel_clk
= sel_clk
/ 8;
268 /* Find the best values for baud generation */
269 for (brdiv_val
= 4; brdiv_val
< 255; brdiv_val
++) {
271 brgr_val
= sel_clk
/ (baud
* (brdiv_val
+ 1));
272 if (brgr_val
< 2 || brgr_val
> 65535)
275 calc_baud
= sel_clk
/ (brgr_val
* (brdiv_val
+ 1));
277 if (baud
> calc_baud
)
278 bauderror
= baud
- calc_baud
;
280 bauderror
= calc_baud
- baud
;
282 /* use the values when percent error is acceptable */
283 if (((bauderror
* 100) / baud
) < 3) {
289 /* Set the values for the new baud rate */
290 xuartps_writel(brgr_val
, XUARTPS_BAUDGEN_OFFSET
);
291 xuartps_writel(brdiv_val
, XUARTPS_BAUDDIV_OFFSET
);
296 /*----------------------Uart Operations---------------------------*/
299 * xuartps_start_tx - Start transmitting bytes
300 * @port: Handle to the uart port structure
303 static void xuartps_start_tx(struct uart_port
*port
)
305 unsigned int status
, numbytes
= port
->fifosize
;
307 if (uart_circ_empty(&port
->state
->xmit
) || uart_tx_stopped(port
))
310 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
311 /* Set the TX enable bit and clear the TX disable bit to enable the
314 xuartps_writel((status
& ~XUARTPS_CR_TX_DIS
) | XUARTPS_CR_TX_EN
,
317 while (numbytes
-- && ((xuartps_readl(XUARTPS_SR_OFFSET
)
318 & XUARTPS_SR_TXFULL
)) != XUARTPS_SR_TXFULL
) {
320 /* Break if no more data available in the UART buffer */
321 if (uart_circ_empty(&port
->state
->xmit
))
324 /* Get the data from the UART circular buffer and
325 * write it to the xuartps's TX_FIFO register.
328 port
->state
->xmit
.buf
[port
->state
->xmit
.tail
],
329 XUARTPS_FIFO_OFFSET
);
332 /* Adjust the tail of the UART buffer and wrap
333 * the buffer if it reaches limit.
335 port
->state
->xmit
.tail
= (port
->state
->xmit
.tail
+ 1) &
336 (UART_XMIT_SIZE
- 1);
339 /* Enable the TX Empty interrupt */
340 xuartps_writel(XUARTPS_IXR_TXEMPTY
, XUARTPS_IER_OFFSET
);
342 if (uart_circ_chars_pending(&port
->state
->xmit
) < WAKEUP_CHARS
)
343 uart_write_wakeup(port
);
347 * xuartps_stop_tx - Stop TX
348 * @port: Handle to the uart port structure
351 static void xuartps_stop_tx(struct uart_port
*port
)
355 regval
= xuartps_readl(XUARTPS_CR_OFFSET
);
356 regval
|= XUARTPS_CR_TX_DIS
;
357 /* Disable the transmitter */
358 xuartps_writel(regval
, XUARTPS_CR_OFFSET
);
362 * xuartps_stop_rx - Stop RX
363 * @port: Handle to the uart port structure
366 static void xuartps_stop_rx(struct uart_port
*port
)
370 regval
= xuartps_readl(XUARTPS_CR_OFFSET
);
371 regval
|= XUARTPS_CR_RX_DIS
;
372 /* Disable the receiver */
373 xuartps_writel(regval
, XUARTPS_CR_OFFSET
);
377 * xuartps_tx_empty - Check whether TX is empty
378 * @port: Handle to the uart port structure
380 * Returns TIOCSER_TEMT on success, 0 otherwise
382 static unsigned int xuartps_tx_empty(struct uart_port
*port
)
386 status
= xuartps_readl(XUARTPS_ISR_OFFSET
) & XUARTPS_IXR_TXEMPTY
;
387 return status
? TIOCSER_TEMT
: 0;
391 * xuartps_break_ctl - Based on the input ctl we have to start or stop
392 * transmitting char breaks
393 * @port: Handle to the uart port structure
394 * @ctl: Value based on which start or stop decision is taken
397 static void xuartps_break_ctl(struct uart_port
*port
, int ctl
)
402 spin_lock_irqsave(&port
->lock
, flags
);
404 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
407 xuartps_writel(XUARTPS_CR_STARTBRK
| status
,
410 if ((status
& XUARTPS_CR_STOPBRK
) == 0)
411 xuartps_writel(XUARTPS_CR_STOPBRK
| status
,
414 spin_unlock_irqrestore(&port
->lock
, flags
);
418 * xuartps_set_termios - termios operations, handling data length, parity,
419 * stop bits, flow control, baud rate
420 * @port: Handle to the uart port structure
421 * @termios: Handle to the input termios structure
422 * @old: Values of the previously saved termios structure
425 static void xuartps_set_termios(struct uart_port
*port
,
426 struct ktermios
*termios
, struct ktermios
*old
)
428 unsigned int cval
= 0;
431 unsigned int ctrl_reg
, mode_reg
;
433 spin_lock_irqsave(&port
->lock
, flags
);
435 /* Empty the receive FIFO 1st before making changes */
436 while ((xuartps_readl(XUARTPS_SR_OFFSET
) &
437 XUARTPS_SR_RXEMPTY
) != XUARTPS_SR_RXEMPTY
) {
438 xuartps_readl(XUARTPS_FIFO_OFFSET
);
441 /* Disable the TX and RX to set baud rate */
442 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
443 (XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
),
446 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
447 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 10000000);
448 baud
= xuartps_set_baud_rate(port
, baud
);
449 if (tty_termios_baud_rate(termios
))
450 tty_termios_encode_baud_rate(termios
, baud
, baud
);
453 * Update the per-port timeout.
455 uart_update_timeout(port
, termios
->c_cflag
, baud
);
457 /* Set TX/RX Reset */
458 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET
) |
459 (XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
),
462 ctrl_reg
= xuartps_readl(XUARTPS_CR_OFFSET
);
464 /* Clear the RX disable and TX disable bits and then set the TX enable
465 * bit and RX enable bit to enable the transmitter and receiver.
468 (ctrl_reg
& ~(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
))
469 | (XUARTPS_CR_TX_EN
| XUARTPS_CR_RX_EN
),
472 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET
);
474 port
->read_status_mask
= XUARTPS_IXR_TXEMPTY
| XUARTPS_IXR_RXTRIG
|
475 XUARTPS_IXR_OVERRUN
| XUARTPS_IXR_TOUT
;
476 port
->ignore_status_mask
= 0;
478 if (termios
->c_iflag
& INPCK
)
479 port
->read_status_mask
|= XUARTPS_IXR_PARITY
|
482 if (termios
->c_iflag
& IGNPAR
)
483 port
->ignore_status_mask
|= XUARTPS_IXR_PARITY
|
484 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
;
486 /* ignore all characters if CREAD is not set */
487 if ((termios
->c_cflag
& CREAD
) == 0)
488 port
->ignore_status_mask
|= XUARTPS_IXR_RXTRIG
|
489 XUARTPS_IXR_TOUT
| XUARTPS_IXR_PARITY
|
490 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
;
492 mode_reg
= xuartps_readl(XUARTPS_MR_OFFSET
);
494 /* Handling Data Size */
495 switch (termios
->c_cflag
& CSIZE
) {
497 cval
|= XUARTPS_MR_CHARLEN_6_BIT
;
500 cval
|= XUARTPS_MR_CHARLEN_7_BIT
;
504 cval
|= XUARTPS_MR_CHARLEN_8_BIT
;
505 termios
->c_cflag
&= ~CSIZE
;
506 termios
->c_cflag
|= CS8
;
510 /* Handling Parity and Stop Bits length */
511 if (termios
->c_cflag
& CSTOPB
)
512 cval
|= XUARTPS_MR_STOPMODE_2_BIT
; /* 2 STOP bits */
514 cval
|= XUARTPS_MR_STOPMODE_1_BIT
; /* 1 STOP bit */
516 if (termios
->c_cflag
& PARENB
) {
517 /* Mark or Space parity */
518 if (termios
->c_cflag
& CMSPAR
) {
519 if (termios
->c_cflag
& PARODD
)
520 cval
|= XUARTPS_MR_PARITY_MARK
;
522 cval
|= XUARTPS_MR_PARITY_SPACE
;
523 } else if (termios
->c_cflag
& PARODD
)
524 cval
|= XUARTPS_MR_PARITY_ODD
;
526 cval
|= XUARTPS_MR_PARITY_EVEN
;
528 cval
|= XUARTPS_MR_PARITY_NONE
;
529 xuartps_writel(cval
, XUARTPS_MR_OFFSET
);
531 spin_unlock_irqrestore(&port
->lock
, flags
);
535 * xuartps_startup - Called when an application opens a xuartps port
536 * @port: Handle to the uart port structure
538 * Returns 0 on success, negative error otherwise
540 static int xuartps_startup(struct uart_port
*port
)
542 unsigned int retval
= 0, status
= 0;
544 retval
= request_irq(port
->irq
, xuartps_isr
, 0, XUARTPS_NAME
,
549 /* Disable the TX and RX */
550 xuartps_writel(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
,
553 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
556 xuartps_writel(XUARTPS_CR_TXRST
| XUARTPS_CR_RXRST
,
559 status
= xuartps_readl(XUARTPS_CR_OFFSET
);
561 /* Clear the RX disable and TX disable bits and then set the TX enable
562 * bit and RX enable bit to enable the transmitter and receiver.
564 xuartps_writel((status
& ~(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
))
565 | (XUARTPS_CR_TX_EN
| XUARTPS_CR_RX_EN
|
566 XUARTPS_CR_STOPBRK
), XUARTPS_CR_OFFSET
);
568 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
571 xuartps_writel(XUARTPS_MR_CHMODE_NORM
| XUARTPS_MR_STOPMODE_1_BIT
572 | XUARTPS_MR_PARITY_NONE
| XUARTPS_MR_CHARLEN_8_BIT
,
575 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
576 xuartps_writel(14, XUARTPS_RXWM_OFFSET
);
578 /* Receive Timeout register is enabled with value of 10 */
579 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET
);
582 /* Set the Interrupt Registers with desired interrupts */
583 xuartps_writel(XUARTPS_IXR_TXEMPTY
| XUARTPS_IXR_PARITY
|
584 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
|
585 XUARTPS_IXR_RXTRIG
| XUARTPS_IXR_TOUT
, XUARTPS_IER_OFFSET
);
586 xuartps_writel(~(XUARTPS_IXR_TXEMPTY
| XUARTPS_IXR_PARITY
|
587 XUARTPS_IXR_FRAMING
| XUARTPS_IXR_OVERRUN
|
588 XUARTPS_IXR_RXTRIG
| XUARTPS_IXR_TOUT
), XUARTPS_IDR_OFFSET
);
594 * xuartps_shutdown - Called when an application closes a xuartps port
595 * @port: Handle to the uart port structure
598 static void xuartps_shutdown(struct uart_port
*port
)
602 /* Disable interrupts */
603 status
= xuartps_readl(XUARTPS_IMR_OFFSET
);
604 xuartps_writel(status
, XUARTPS_IDR_OFFSET
);
606 /* Disable the TX and RX */
607 xuartps_writel(XUARTPS_CR_TX_DIS
| XUARTPS_CR_RX_DIS
,
609 free_irq(port
->irq
, port
);
613 * xuartps_type - Set UART type to xuartps port
614 * @port: Handle to the uart port structure
616 * Returns string on success, NULL otherwise
618 static const char *xuartps_type(struct uart_port
*port
)
620 return port
->type
== PORT_XUARTPS
? XUARTPS_NAME
: NULL
;
624 * xuartps_verify_port - Verify the port params
625 * @port: Handle to the uart port structure
626 * @ser: Handle to the structure whose members are compared
628 * Returns 0 if success otherwise -EINVAL
630 static int xuartps_verify_port(struct uart_port
*port
,
631 struct serial_struct
*ser
)
633 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_XUARTPS
)
635 if (port
->irq
!= ser
->irq
)
637 if (ser
->io_type
!= UPIO_MEM
)
639 if (port
->iobase
!= ser
->port
)
647 * xuartps_request_port - Claim the memory region attached to xuartps port,
648 * called when the driver adds a xuartps port via
649 * uart_add_one_port()
650 * @port: Handle to the uart port structure
652 * Returns 0, -ENOMEM if request fails
654 static int xuartps_request_port(struct uart_port
*port
)
656 if (!request_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
,
661 port
->membase
= ioremap(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
662 if (!port
->membase
) {
663 dev_err(port
->dev
, "Unable to map registers\n");
664 release_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
671 * xuartps_release_port - Release the memory region attached to a xuartps
672 * port, called when the driver removes a xuartps
673 * port via uart_remove_one_port().
674 * @port: Handle to the uart port structure
677 static void xuartps_release_port(struct uart_port
*port
)
679 release_mem_region(port
->mapbase
, XUARTPS_REGISTER_SPACE
);
680 iounmap(port
->membase
);
681 port
->membase
= NULL
;
685 * xuartps_config_port - Configure xuartps, called when the driver adds a
687 * @port: Handle to the uart port structure
691 static void xuartps_config_port(struct uart_port
*port
, int flags
)
693 if (flags
& UART_CONFIG_TYPE
&& xuartps_request_port(port
) == 0)
694 port
->type
= PORT_XUARTPS
;
698 * xuartps_get_mctrl - Get the modem control state
700 * @port: Handle to the uart port structure
702 * Returns the modem control state
705 static unsigned int xuartps_get_mctrl(struct uart_port
*port
)
707 return TIOCM_CTS
| TIOCM_DSR
| TIOCM_CAR
;
710 static void xuartps_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
715 static void xuartps_enable_ms(struct uart_port
*port
)
720 /** The UART operations structure
722 static struct uart_ops xuartps_ops
= {
723 .set_mctrl
= xuartps_set_mctrl
,
724 .get_mctrl
= xuartps_get_mctrl
,
725 .enable_ms
= xuartps_enable_ms
,
727 .start_tx
= xuartps_start_tx
, /* Start transmitting */
728 .stop_tx
= xuartps_stop_tx
, /* Stop transmission */
729 .stop_rx
= xuartps_stop_rx
, /* Stop reception */
730 .tx_empty
= xuartps_tx_empty
, /* Transmitter busy? */
731 .break_ctl
= xuartps_break_ctl
, /* Start/stop
734 .set_termios
= xuartps_set_termios
, /* Set termios */
735 .startup
= xuartps_startup
, /* App opens xuartps */
736 .shutdown
= xuartps_shutdown
, /* App closes xuartps */
737 .type
= xuartps_type
, /* Set UART type */
738 .verify_port
= xuartps_verify_port
, /* Verification of port
741 .request_port
= xuartps_request_port
, /* Claim resources
745 .release_port
= xuartps_release_port
, /* Release resources
749 .config_port
= xuartps_config_port
, /* Configure when driver
750 * adds a xuartps port
754 static struct uart_port xuartps_port
[2];
757 * xuartps_get_port - Configure the port from the platform device resource
760 * Returns a pointer to a uart_port or NULL for failure
762 static struct uart_port
*xuartps_get_port(void)
764 struct uart_port
*port
;
767 /* Find the next unused port */
768 for (id
= 0; id
< XUARTPS_NR_PORTS
; id
++)
769 if (xuartps_port
[id
].mapbase
== 0)
772 if (id
>= XUARTPS_NR_PORTS
)
775 port
= &xuartps_port
[id
];
777 /* At this point, we've got an empty uart_port struct, initialize it */
778 spin_lock_init(&port
->lock
);
779 port
->membase
= NULL
;
780 port
->iobase
= 1; /* mark port in use */
782 port
->type
= PORT_UNKNOWN
;
783 port
->iotype
= UPIO_MEM32
;
784 port
->flags
= UPF_BOOT_AUTOCONF
;
785 port
->ops
= &xuartps_ops
;
786 port
->fifosize
= XUARTPS_FIFO_SIZE
;
792 /*-----------------------Console driver operations--------------------------*/
794 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
796 * xuartps_console_wait_tx - Wait for the TX to be full
797 * @port: Handle to the uart port structure
800 static void xuartps_console_wait_tx(struct uart_port
*port
)
802 while ((xuartps_readl(XUARTPS_SR_OFFSET
) & XUARTPS_SR_TXEMPTY
)
803 != XUARTPS_SR_TXEMPTY
)
808 * xuartps_console_putchar - write the character to the FIFO buffer
809 * @port: Handle to the uart port structure
810 * @ch: Character to be written
813 static void xuartps_console_putchar(struct uart_port
*port
, int ch
)
815 xuartps_console_wait_tx(port
);
816 xuartps_writel(ch
, XUARTPS_FIFO_OFFSET
);
820 * xuartps_console_write - perform write operation
821 * @port: Handle to the uart port structure
822 * @s: Pointer to character array
823 * @count: No of characters
825 static void xuartps_console_write(struct console
*co
, const char *s
,
828 struct uart_port
*port
= &xuartps_port
[co
->index
];
833 if (oops_in_progress
)
834 locked
= spin_trylock_irqsave(&port
->lock
, flags
);
836 spin_lock_irqsave(&port
->lock
, flags
);
838 /* save and disable interrupt */
839 imr
= xuartps_readl(XUARTPS_IMR_OFFSET
);
840 xuartps_writel(imr
, XUARTPS_IDR_OFFSET
);
842 uart_console_write(port
, s
, count
, xuartps_console_putchar
);
843 xuartps_console_wait_tx(port
);
845 /* restore interrupt state, it seems like there may be a h/w bug
846 * in that the interrupt enable register should not need to be
847 * written based on the data sheet
849 xuartps_writel(~imr
, XUARTPS_IDR_OFFSET
);
850 xuartps_writel(imr
, XUARTPS_IER_OFFSET
);
853 spin_unlock_irqrestore(&port
->lock
, flags
);
857 * xuartps_console_setup - Initialize the uart to default config
858 * @co: Console handle
859 * @options: Initial settings of uart
861 * Returns 0, -ENODEV if no device
863 static int __init
xuartps_console_setup(struct console
*co
, char *options
)
865 struct uart_port
*port
= &xuartps_port
[co
->index
];
871 if (co
->index
< 0 || co
->index
>= XUARTPS_NR_PORTS
)
874 if (!port
->mapbase
) {
875 pr_debug("console on ttyPS%i not present\n", co
->index
);
880 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
882 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
885 static struct uart_driver xuartps_uart_driver
;
887 static struct console xuartps_console
= {
888 .name
= XUARTPS_TTY_NAME
,
889 .write
= xuartps_console_write
,
890 .device
= uart_console_device
,
891 .setup
= xuartps_console_setup
,
892 .flags
= CON_PRINTBUFFER
,
893 .index
= -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
894 .data
= &xuartps_uart_driver
,
898 * xuartps_console_init - Initialization call
900 * Returns 0 on success, negative error otherwise
902 static int __init
xuartps_console_init(void)
904 register_console(&xuartps_console
);
908 console_initcall(xuartps_console_init
);
910 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
912 /** Structure Definitions
914 static struct uart_driver xuartps_uart_driver
= {
915 .owner
= THIS_MODULE
, /* Owner */
916 .driver_name
= XUARTPS_NAME
, /* Driver name */
917 .dev_name
= XUARTPS_TTY_NAME
, /* Node name */
918 .major
= XUARTPS_MAJOR
, /* Major number */
919 .minor
= XUARTPS_MINOR
, /* Minor number */
920 .nr
= XUARTPS_NR_PORTS
, /* Number of UART ports */
921 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
922 .cons
= &xuartps_console
, /* Console */
926 /* ---------------------------------------------------------------------
927 * Platform bus binding
930 * xuartps_probe - Platform driver probe
931 * @pdev: Pointer to the platform device structure
933 * Returns 0 on success, negative error otherwise
935 static int xuartps_probe(struct platform_device
*pdev
)
938 struct uart_port
*port
;
939 struct resource
*res
, *res2
;
942 clk
= of_clk_get(pdev
->dev
.of_node
, 0);
944 dev_err(&pdev
->dev
, "no clock specified\n");
948 rc
= clk_prepare_enable(clk
);
950 dev_err(&pdev
->dev
, "could not enable clock\n");
954 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
958 res2
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
962 /* Initialize the port structure */
963 port
= xuartps_get_port();
966 dev_err(&pdev
->dev
, "Cannot get uart_port structure\n");
969 /* Register the port.
970 * This function also registers this device with the tty layer
971 * and triggers invocation of the config_port() entry point.
973 port
->mapbase
= res
->start
;
974 port
->irq
= res2
->start
;
975 port
->dev
= &pdev
->dev
;
976 port
->uartclk
= clk_get_rate(clk
);
977 port
->private_data
= clk
;
978 dev_set_drvdata(&pdev
->dev
, port
);
979 rc
= uart_add_one_port(&xuartps_uart_driver
, port
);
982 "uart_add_one_port() failed; err=%i\n", rc
);
983 dev_set_drvdata(&pdev
->dev
, NULL
);
991 * xuartps_remove - called when the platform driver is unregistered
992 * @pdev: Pointer to the platform device structure
994 * Returns 0 on success, negative error otherwise
996 static int xuartps_remove(struct platform_device
*pdev
)
998 struct uart_port
*port
= dev_get_drvdata(&pdev
->dev
);
999 struct clk
*clk
= port
->private_data
;
1002 /* Remove the xuartps port from the serial core */
1003 rc
= uart_remove_one_port(&xuartps_uart_driver
, port
);
1004 dev_set_drvdata(&pdev
->dev
, NULL
);
1006 clk_disable_unprepare(clk
);
1011 * xuartps_suspend - suspend event
1012 * @pdev: Pointer to the platform device structure
1013 * @state: State of the device
1017 static int xuartps_suspend(struct platform_device
*pdev
, pm_message_t state
)
1019 /* Call the API provided in serial_core.c file which handles
1022 uart_suspend_port(&xuartps_uart_driver
, &xuartps_port
[pdev
->id
]);
1027 * xuartps_resume - Resume after a previous suspend
1028 * @pdev: Pointer to the platform device structure
1032 static int xuartps_resume(struct platform_device
*pdev
)
1034 uart_resume_port(&xuartps_uart_driver
, &xuartps_port
[pdev
->id
]);
1038 /* Match table for of_platform binding */
1039 static struct of_device_id xuartps_of_match
[] = {
1040 { .compatible
= "xlnx,xuartps", },
1043 MODULE_DEVICE_TABLE(of
, xuartps_of_match
);
1045 static struct platform_driver xuartps_platform_driver
= {
1046 .probe
= xuartps_probe
, /* Probe method */
1047 .remove
= xuartps_remove
, /* Detach method */
1048 .suspend
= xuartps_suspend
, /* Suspend */
1049 .resume
= xuartps_resume
, /* Resume after a suspend */
1051 .owner
= THIS_MODULE
,
1052 .name
= XUARTPS_NAME
, /* Driver name */
1053 .of_match_table
= xuartps_of_match
,
1057 /* ---------------------------------------------------------------------
1058 * Module Init and Exit
1061 * xuartps_init - Initial driver registration call
1063 * Returns whether the registration was successful or not
1065 static int __init
xuartps_init(void)
1069 /* Register the xuartps driver with the serial core */
1070 retval
= uart_register_driver(&xuartps_uart_driver
);
1074 /* Register the platform driver */
1075 retval
= platform_driver_register(&xuartps_platform_driver
);
1077 uart_unregister_driver(&xuartps_uart_driver
);
1083 * xuartps_exit - Driver unregistration call
1085 static void __exit
xuartps_exit(void)
1087 /* The order of unregistration is important. Unregister the
1088 * UART driver before the platform driver crashes the system.
1091 /* Unregister the platform driver */
1092 platform_driver_unregister(&xuartps_platform_driver
);
1094 /* Unregister the xuartps driver */
1095 uart_unregister_driver(&xuartps_uart_driver
);
1098 module_init(xuartps_init
);
1099 module_exit(xuartps_exit
);
1101 MODULE_DESCRIPTION("Driver for PS UART");
1102 MODULE_AUTHOR("Xilinx Inc.");
1103 MODULE_LICENSE("GPL");