2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 * Original release 01/11/99
16 * This code is released under the GNU General Public License (GPL)
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
55 # define BREAKPOINT() asm(" int $3");
57 # define BREAKPOINT() { }
60 #define MAX_ISA_DEVICES 10
61 #define MAX_PCI_DEVICES 10
62 #define MAX_TOTAL_DEVICES 20
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/signal.h>
67 #include <linux/sched.h>
68 #include <linux/timer.h>
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/tty.h>
72 #include <linux/tty_flip.h>
73 #include <linux/serial.h>
74 #include <linux/major.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
80 #include <linux/seq_file.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/vmalloc.h>
85 #include <linux/init.h>
86 #include <linux/ioctl.h>
87 #include <linux/synclink.h>
92 #include <linux/bitops.h>
93 #include <asm/types.h>
94 #include <linux/termios.h>
95 #include <linux/workqueue.h>
96 #include <linux/hdlc.h>
97 #include <linux/dma-mapping.h>
99 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100 #define SYNCLINK_GENERIC_HDLC 1
102 #define SYNCLINK_GENERIC_HDLC 0
105 #define GET_USER(error,value,addr) error = get_user(value,addr)
106 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107 #define PUT_USER(error,value,addr) error = put_user(value,addr)
108 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
110 #include <asm/uaccess.h>
112 #define RCLRVALUE 0xffff
114 static MGSL_PARAMS default_params
= {
115 MGSL_MODE_HDLC
, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE
/* unsigned char parity; */
130 #define SHARED_MEM_ADDRESS_SIZE 0x40000
131 #define BUFFERLISTSIZE 4096
132 #define DMABUFFERSIZE 4096
133 #define MAXRXFRAMES 7
135 typedef struct _DMABUFFERENTRY
137 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
138 volatile u16 count
; /* buffer size/data count */
139 volatile u16 status
; /* Control/status field */
140 volatile u16 rcc
; /* character count field */
141 u16 reserved
; /* padding required by 16C32 */
142 u32 link
; /* 32-bit flat link to next buffer entry */
143 char *virt_addr
; /* virtual address of data buffer */
144 u32 phys_entry
; /* physical address of this buffer entry */
146 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
148 /* The queue of BH actions to be performed */
151 #define BH_TRANSMIT 2
154 #define IO_PIN_SHUTDOWN_LIMIT 100
156 struct _input_signal_events
{
167 /* transmit holding buffer definitions*/
168 #define MAX_TX_HOLDING_BUFFERS 5
169 struct tx_holding_buffer
{
171 unsigned char * buffer
;
176 * Device instance data structure
181 struct tty_port port
;
185 struct mgsl_icount icount
;
188 int x_char
; /* xon/xoff character */
189 u16 read_status_mask
;
190 u16 ignore_status_mask
;
191 unsigned char *xmit_buf
;
196 wait_queue_head_t status_event_wait_q
;
197 wait_queue_head_t event_wait_q
;
198 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
199 struct mgsl_struct
*next_device
; /* device list link */
201 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
202 struct work_struct task
; /* task structure for scheduling bh */
204 u32 EventMask
; /* event trigger mask */
205 u32 RecordedEvents
; /* pending events */
207 u32 max_frame_size
; /* as set by device config */
211 bool bh_running
; /* Protection from multiple */
215 int dcd_chkcount
; /* check counts to prevent */
216 int cts_chkcount
; /* too many IRQs if a signal */
217 int dsr_chkcount
; /* is floating */
220 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
221 u32 buffer_list_phys
;
222 dma_addr_t buffer_list_dma_addr
;
224 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
226 unsigned int current_rx_buffer
;
228 int num_tx_dma_buffers
; /* number of tx dma frames required */
229 int tx_dma_buffers_used
;
230 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
232 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer
; /* next tx dma buffer to be loaded */
235 unsigned char *intermediate_rxbuffer
;
237 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
238 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index
; /* next tx holding buffer to store user request */
240 int tx_holding_count
; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
245 bool rx_rcc_underrun
;
254 char device_name
[25]; /* device instance name */
256 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus
; /* expansion bus number (zero based) */
258 unsigned char function
; /* PCI device number */
260 unsigned int io_base
; /* base I/O address of adapter */
261 unsigned int io_addr_size
; /* size of the I/O address range */
262 bool io_addr_requested
; /* true if I/O address requested */
264 unsigned int irq_level
; /* interrupt level */
265 unsigned long irq_flags
;
266 bool irq_requested
; /* true if IRQ requested */
268 unsigned int dma_level
; /* DMA channel */
269 bool dma_requested
; /* true if dma channel requested */
275 MGSL_PARAMS params
; /* communications parameters */
277 unsigned char serial_signals
; /* current serial signal states */
279 bool irq_occurred
; /* for diagnostics use */
280 unsigned int init_error
; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
284 unsigned char* memory_base
; /* shared memory address (PCI only) */
285 u32 phys_memory_base
;
286 bool shared_mem_requested
;
288 unsigned char* lcr_base
; /* local config registers (PCI only) */
291 bool lcr_mem_requested
;
295 bool drop_rts_on_tx_done
;
297 bool loopmode_insert_requested
;
298 bool loopmode_send_done_requested
;
300 struct _input_signal_events input_signal_events
;
302 /* generic HDLC device parts */
306 #if SYNCLINK_GENERIC_HDLC
307 struct net_device
*netdev
;
311 #define MGSL_MAGIC 0x5401
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
316 #ifndef SERIAL_XMIT_SIZE
317 #define SERIAL_XMIT_SIZE 4096
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
326 #define DCPIN 2 /* Bit 1 of I/O address */
327 #define SDPIN 4 /* Bit 2 of I/O address */
329 #define DCAR 0 /* DMA command/address register */
330 #define CCAR SDPIN /* channel command/address register */
331 #define DATAREG DCPIN + SDPIN /* serial data register */
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
340 #define CMR 0x02 /* Channel mode Register */
341 #define CCSR 0x04 /* Channel Command/status Register */
342 #define CCR 0x06 /* Channel Control Register */
343 #define PSR 0x08 /* Port status Register */
344 #define PCR 0x0a /* Port Control Register */
345 #define TMDR 0x0c /* Test mode Data Register */
346 #define TMCR 0x0e /* Test mode Control Register */
347 #define CMCR 0x10 /* Clock mode Control Register */
348 #define HCR 0x12 /* Hardware Configuration Register */
349 #define IVR 0x14 /* Interrupt Vector Register */
350 #define IOCR 0x16 /* Input/Output Control Register */
351 #define ICR 0x18 /* Interrupt Control Register */
352 #define DCCR 0x1a /* Daisy Chain Control Register */
353 #define MISR 0x1c /* Misc Interrupt status Register */
354 #define SICR 0x1e /* status Interrupt Control Register */
355 #define RDR 0x20 /* Receive Data Register */
356 #define RMR 0x22 /* Receive mode Register */
357 #define RCSR 0x24 /* Receive Command/status Register */
358 #define RICR 0x26 /* Receive Interrupt Control Register */
359 #define RSR 0x28 /* Receive Sync Register */
360 #define RCLR 0x2a /* Receive count Limit Register */
361 #define RCCR 0x2c /* Receive Character count Register */
362 #define TC0R 0x2e /* Time Constant 0 Register */
363 #define TDR 0x30 /* Transmit Data Register */
364 #define TMR 0x32 /* Transmit mode Register */
365 #define TCSR 0x34 /* Transmit Command/status Register */
366 #define TICR 0x36 /* Transmit Interrupt Control Register */
367 #define TSR 0x38 /* Transmit Sync Register */
368 #define TCLR 0x3a /* Transmit count Limit Register */
369 #define TCCR 0x3c /* Transmit Character count Register */
370 #define TC1R 0x3e /* Time Constant 1 Register */
374 * MACRO DEFINITIONS FOR DMA REGISTERS
377 #define DCR 0x06 /* DMA Control Register (shared) */
378 #define DACR 0x08 /* DMA Array count Register (shared) */
379 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
385 #define TDMR 0x02 /* Transmit DMA mode Register */
386 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387 #define TBCR 0x2a /* Transmit Byte count Register */
388 #define TARL 0x2c /* Transmit Address Register (low) */
389 #define TARU 0x2e /* Transmit Address Register (high) */
390 #define NTBCR 0x3a /* Next Transmit Byte count Register */
391 #define NTARL 0x3c /* Next Transmit Address Register (low) */
392 #define NTARU 0x3e /* Next Transmit Address Register (high) */
394 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396 #define RBCR 0xaa /* Receive Byte count Register */
397 #define RARL 0xac /* Receive Address Register (low) */
398 #define RARU 0xae /* Receive Address Register (high) */
399 #define NRBCR 0xba /* Next Receive Byte count Register */
400 #define NRARL 0xbc /* Next Receive Address Register (low) */
401 #define NRARU 0xbe /* Next Receive Address Register (high) */
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
408 #define MODEMSTATUS_DTR 0x80
409 #define MODEMSTATUS_DSR 0x40
410 #define MODEMSTATUS_RTS 0x20
411 #define MODEMSTATUS_CTS 0x10
412 #define MODEMSTATUS_RI 0x04
413 #define MODEMSTATUS_DCD 0x01
417 * Channel Command/Address Register (CCAR) Command Codes
420 #define RTCmd_Null 0x0000
421 #define RTCmd_ResetHighestIus 0x1000
422 #define RTCmd_TriggerChannelLoadDma 0x2000
423 #define RTCmd_TriggerRxDma 0x2800
424 #define RTCmd_TriggerTxDma 0x3000
425 #define RTCmd_TriggerRxAndTxDma 0x3800
426 #define RTCmd_PurgeRxFifo 0x4800
427 #define RTCmd_PurgeTxFifo 0x5000
428 #define RTCmd_PurgeRxAndTxFifo 0x5800
429 #define RTCmd_LoadRcc 0x6800
430 #define RTCmd_LoadTcc 0x7000
431 #define RTCmd_LoadRccAndTcc 0x7800
432 #define RTCmd_LoadTC0 0x8800
433 #define RTCmd_LoadTC1 0x9000
434 #define RTCmd_LoadTC0AndTC1 0x9800
435 #define RTCmd_SerialDataLSBFirst 0xa000
436 #define RTCmd_SerialDataMSBFirst 0xa800
437 #define RTCmd_SelectBigEndian 0xb000
438 #define RTCmd_SelectLittleEndian 0xb800
442 * DMA Command/Address Register (DCAR) Command Codes
445 #define DmaCmd_Null 0x0000
446 #define DmaCmd_ResetTxChannel 0x1000
447 #define DmaCmd_ResetRxChannel 0x1200
448 #define DmaCmd_StartTxChannel 0x2000
449 #define DmaCmd_StartRxChannel 0x2200
450 #define DmaCmd_ContinueTxChannel 0x3000
451 #define DmaCmd_ContinueRxChannel 0x3200
452 #define DmaCmd_PauseTxChannel 0x4000
453 #define DmaCmd_PauseRxChannel 0x4200
454 #define DmaCmd_AbortTxChannel 0x5000
455 #define DmaCmd_AbortRxChannel 0x5200
456 #define DmaCmd_InitTxChannel 0x7000
457 #define DmaCmd_InitRxChannel 0x7200
458 #define DmaCmd_ResetHighestDmaIus 0x8000
459 #define DmaCmd_ResetAllChannels 0x9000
460 #define DmaCmd_StartAllChannels 0xa000
461 #define DmaCmd_ContinueAllChannels 0xb000
462 #define DmaCmd_PauseAllChannels 0xc000
463 #define DmaCmd_AbortAllChannels 0xd000
464 #define DmaCmd_InitAllChannels 0xf000
466 #define TCmd_Null 0x0000
467 #define TCmd_ClearTxCRC 0x2000
468 #define TCmd_SelectTicrTtsaData 0x4000
469 #define TCmd_SelectTicrTxFifostatus 0x5000
470 #define TCmd_SelectTicrIntLevel 0x6000
471 #define TCmd_SelectTicrdma_level 0x7000
472 #define TCmd_SendFrame 0x8000
473 #define TCmd_SendAbort 0x9000
474 #define TCmd_EnableDleInsertion 0xc000
475 #define TCmd_DisableDleInsertion 0xd000
476 #define TCmd_ClearEofEom 0xe000
477 #define TCmd_SetEofEom 0xf000
479 #define RCmd_Null 0x0000
480 #define RCmd_ClearRxCRC 0x2000
481 #define RCmd_EnterHuntmode 0x3000
482 #define RCmd_SelectRicrRtsaData 0x4000
483 #define RCmd_SelectRicrRxFifostatus 0x5000
484 #define RCmd_SelectRicrIntLevel 0x6000
485 #define RCmd_SelectRicrdma_level 0x7000
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
491 #define RECEIVE_STATUS BIT5
492 #define RECEIVE_DATA BIT4
493 #define TRANSMIT_STATUS BIT3
494 #define TRANSMIT_DATA BIT2
500 * Receive status Bits in Receive Command/status Register RCSR
503 #define RXSTATUS_SHORT_FRAME BIT8
504 #define RXSTATUS_CODE_VIOLATION BIT8
505 #define RXSTATUS_EXITED_HUNT BIT7
506 #define RXSTATUS_IDLE_RECEIVED BIT6
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
509 #define RXSTATUS_RXBOUND BIT4
510 #define RXSTATUS_CRC_ERROR BIT3
511 #define RXSTATUS_FRAMING_ERROR BIT3
512 #define RXSTATUS_ABORT BIT2
513 #define RXSTATUS_PARITY_ERROR BIT2
514 #define RXSTATUS_OVERRUN BIT1
515 #define RXSTATUS_DATA_AVAILABLE BIT0
516 #define RXSTATUS_ALL 0x01f6
517 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
523 #define IDLEMODE_FLAGS 0x0000
524 #define IDLEMODE_ALT_ONE_ZERO 0x0100
525 #define IDLEMODE_ZERO 0x0200
526 #define IDLEMODE_ONE 0x0300
527 #define IDLEMODE_ALT_MARK_SPACE 0x0500
528 #define IDLEMODE_SPACE 0x0600
529 #define IDLEMODE_MARK 0x0700
530 #define IDLEMODE_MASK 0x0700
533 * IUSC revision identifiers
535 #define IUSC_SL1660 0x4d44
536 #define IUSC_PRE_SL1660 0x4553
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
542 #define TCSR_PRESERVE 0x0F00
544 #define TCSR_UNDERWAIT BIT11
545 #define TXSTATUS_PREAMBLE_SENT BIT7
546 #define TXSTATUS_IDLE_SENT BIT6
547 #define TXSTATUS_ABORT_SENT BIT5
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
550 #define TXSTATUS_CRC_SENT BIT3
551 #define TXSTATUS_ALL_SENT BIT2
552 #define TXSTATUS_UNDERRUN BIT1
553 #define TXSTATUS_FIFO_EMPTY BIT0
554 #define TXSTATUS_ALL 0x00fa
555 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
558 #define MISCSTATUS_RXC_LATCHED BIT15
559 #define MISCSTATUS_RXC BIT14
560 #define MISCSTATUS_TXC_LATCHED BIT13
561 #define MISCSTATUS_TXC BIT12
562 #define MISCSTATUS_RI_LATCHED BIT11
563 #define MISCSTATUS_RI BIT10
564 #define MISCSTATUS_DSR_LATCHED BIT9
565 #define MISCSTATUS_DSR BIT8
566 #define MISCSTATUS_DCD_LATCHED BIT7
567 #define MISCSTATUS_DCD BIT6
568 #define MISCSTATUS_CTS_LATCHED BIT5
569 #define MISCSTATUS_CTS BIT4
570 #define MISCSTATUS_RCC_UNDERRUN BIT3
571 #define MISCSTATUS_DPLL_NO_SYNC BIT2
572 #define MISCSTATUS_BRG1_ZERO BIT1
573 #define MISCSTATUS_BRG0_ZERO BIT0
575 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578 #define SICR_RXC_ACTIVE BIT15
579 #define SICR_RXC_INACTIVE BIT14
580 #define SICR_RXC (BIT15|BIT14)
581 #define SICR_TXC_ACTIVE BIT13
582 #define SICR_TXC_INACTIVE BIT12
583 #define SICR_TXC (BIT13|BIT12)
584 #define SICR_RI_ACTIVE BIT11
585 #define SICR_RI_INACTIVE BIT10
586 #define SICR_RI (BIT11|BIT10)
587 #define SICR_DSR_ACTIVE BIT9
588 #define SICR_DSR_INACTIVE BIT8
589 #define SICR_DSR (BIT9|BIT8)
590 #define SICR_DCD_ACTIVE BIT7
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
593 #define SICR_CTS_ACTIVE BIT5
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5|BIT4)
596 #define SICR_RCC_UNDERFLOW BIT3
597 #define SICR_DPLL_NO_SYNC BIT2
598 #define SICR_BRG1_ZERO BIT1
599 #define SICR_BRG0_ZERO BIT0
601 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
602 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
603 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
604 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
605 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
607 #define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610 #define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613 #define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616 #define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
626 #define TXSTATUS_PREAMBLE_SENT BIT7
627 #define TXSTATUS_IDLE_SENT BIT6
628 #define TXSTATUS_ABORT_SENT BIT5
629 #define TXSTATUS_EOF BIT4
630 #define TXSTATUS_CRC_SENT BIT3
631 #define TXSTATUS_ALL_SENT BIT2
632 #define TXSTATUS_UNDERRUN BIT1
633 #define TXSTATUS_FIFO_EMPTY BIT0
635 #define DICR_MASTER BIT15
636 #define DICR_TRANSMIT BIT0
637 #define DICR_RECEIVE BIT1
639 #define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642 #define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645 #define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648 #define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651 /* Transmit status Bits in Transmit Control status Register (TCSR) */
652 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
655 #define DISABLE_UNCONDITIONAL 0
656 #define DISABLE_END_OF_FRAME 1
657 #define ENABLE_UNCONDITIONAL 2
658 #define ENABLE_AUTO_CTS 3
659 #define ENABLE_AUTO_DCD 3
660 #define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662 #define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
666 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
667 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
669 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
670 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
671 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
672 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
673 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
675 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
681 static void usc_start_receiver( struct mgsl_struct
*info
);
682 static void usc_stop_receiver( struct mgsl_struct
*info
);
684 static void usc_start_transmitter( struct mgsl_struct
*info
);
685 static void usc_stop_transmitter( struct mgsl_struct
*info
);
686 static void usc_set_txidle( struct mgsl_struct
*info
);
687 static void usc_load_txfifo( struct mgsl_struct
*info
);
689 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
690 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
692 static void usc_get_serial_signals( struct mgsl_struct
*info
);
693 static void usc_set_serial_signals( struct mgsl_struct
*info
);
695 static void usc_reset( struct mgsl_struct
*info
);
697 static void usc_set_sync_mode( struct mgsl_struct
*info
);
698 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
699 static void usc_set_async_mode( struct mgsl_struct
*info
);
700 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
702 static void usc_loopback_frame( struct mgsl_struct
*info
);
704 static void mgsl_tx_timeout(unsigned long context
);
707 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
708 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
709 static int usc_loopmode_active( struct mgsl_struct
* info
);
710 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
712 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
714 #if SYNCLINK_GENERIC_HDLC
715 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
716 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
717 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
718 static int hdlcdev_init(struct mgsl_struct
*info
);
719 static void hdlcdev_exit(struct mgsl_struct
*info
);
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
727 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
738 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
741 * Adapter diagnostic routines
743 static bool mgsl_register_test( struct mgsl_struct
*info
);
744 static bool mgsl_irq_test( struct mgsl_struct
*info
);
745 static bool mgsl_dma_test( struct mgsl_struct
*info
);
746 static bool mgsl_memory_test( struct mgsl_struct
*info
);
747 static int mgsl_adapter_test( struct mgsl_struct
*info
);
750 * device and resource management routines
752 static int mgsl_claim_resources(struct mgsl_struct
*info
);
753 static void mgsl_release_resources(struct mgsl_struct
*info
);
754 static void mgsl_add_device(struct mgsl_struct
*info
);
755 static struct mgsl_struct
* mgsl_allocate_device(void);
758 * DMA buffer manupulation functions.
760 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
761 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
762 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
763 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
764 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
765 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
766 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
767 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
770 * DMA and Shared Memory buffer allocation and formatting
772 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
773 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
774 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
775 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
776 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
777 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
778 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
779 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
780 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
781 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
782 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
783 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
786 * Bottom half interrupt handlers
788 static void mgsl_bh_handler(struct work_struct
*work
);
789 static void mgsl_bh_receive(struct mgsl_struct
*info
);
790 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
791 static void mgsl_bh_status(struct mgsl_struct
*info
);
794 * Interrupt handler routines and dispatch table.
796 static void mgsl_isr_null( struct mgsl_struct
*info
);
797 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
798 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
799 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
800 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
801 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
802 static void mgsl_isr_misc( struct mgsl_struct
*info
);
803 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
804 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
806 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
808 static isr_dispatch_func UscIsrTable
[7] =
813 mgsl_isr_transmit_data
,
814 mgsl_isr_transmit_status
,
815 mgsl_isr_receive_data
,
816 mgsl_isr_receive_status
820 * ioctl call handlers
822 static int tiocmget(struct tty_struct
*tty
);
823 static int tiocmset(struct tty_struct
*tty
,
824 unsigned int set
, unsigned int clear
);
825 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
826 __user
*user_icount
);
827 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
828 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
829 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
830 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
831 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
832 static int mgsl_txabort(struct mgsl_struct
* info
);
833 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
834 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
835 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
837 /* set non-zero on successful registration with PCI subsystem */
838 static bool pci_registered
;
841 * Global linked list of SyncLink devices
843 static struct mgsl_struct
*mgsl_device_list
;
844 static int mgsl_device_count
;
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
851 static bool break_on_load
;
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
860 * Array of user specified options for ISA adapters.
862 static int io
[MAX_ISA_DEVICES
];
863 static int irq
[MAX_ISA_DEVICES
];
864 static int dma
[MAX_ISA_DEVICES
];
865 static int debug_level
;
866 static int maxframe
[MAX_TOTAL_DEVICES
];
867 static int txdmabufs
[MAX_TOTAL_DEVICES
];
868 static int txholdbufs
[MAX_TOTAL_DEVICES
];
870 module_param(break_on_load
, bool, 0);
871 module_param(ttymajor
, int, 0);
872 module_param_array(io
, int, NULL
, 0);
873 module_param_array(irq
, int, NULL
, 0);
874 module_param_array(dma
, int, NULL
, 0);
875 module_param(debug_level
, int, 0);
876 module_param_array(maxframe
, int, NULL
, 0);
877 module_param_array(txdmabufs
, int, NULL
, 0);
878 module_param_array(txholdbufs
, int, NULL
, 0);
880 static char *driver_name
= "SyncLink serial driver";
881 static char *driver_version
= "$Revision: 4.38 $";
883 static int synclink_init_one (struct pci_dev
*dev
,
884 const struct pci_device_id
*ent
);
885 static void synclink_remove_one (struct pci_dev
*dev
);
887 static struct pci_device_id synclink_pci_tbl
[] = {
888 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
889 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
890 { 0, }, /* terminate list */
892 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
894 MODULE_LICENSE("GPL");
896 static struct pci_driver synclink_pci_driver
= {
898 .id_table
= synclink_pci_tbl
,
899 .probe
= synclink_init_one
,
900 .remove
= synclink_remove_one
,
903 static struct tty_driver
*serial_driver
;
905 /* number of characters left in xmit buffer before we ask for more */
906 #define WAKEUP_CHARS 256
909 static void mgsl_change_params(struct mgsl_struct
*info
);
910 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
918 static void* mgsl_get_text_ptr(void)
920 return mgsl_get_text_ptr
;
923 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
924 char *name
, const char *routine
)
926 #ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic
=
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo
=
930 "Warning: null mgsl_struct for (%s) in %s\n";
933 printk(badinfo
, name
, routine
);
936 if (info
->magic
!= MGSL_MAGIC
) {
937 printk(badmagic
, name
, routine
);
948 * line discipline callback wrappers
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
953 * ldisc_receive_buf - pass receive data to line discipline
956 static void ldisc_receive_buf(struct tty_struct
*tty
,
957 const __u8
*data
, char *flags
, int count
)
959 struct tty_ldisc
*ld
;
962 ld
= tty_ldisc_ref(tty
);
964 if (ld
->ops
->receive_buf
)
965 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
970 /* mgsl_stop() throttle (stop) transmitter
972 * Arguments: tty pointer to tty info structure
975 static void mgsl_stop(struct tty_struct
*tty
)
977 struct mgsl_struct
*info
= tty
->driver_data
;
980 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
983 if ( debug_level
>= DEBUG_LEVEL_INFO
)
984 printk("mgsl_stop(%s)\n",info
->device_name
);
986 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
987 if (info
->tx_enabled
)
988 usc_stop_transmitter(info
);
989 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
991 } /* end of mgsl_stop() */
993 /* mgsl_start() release (start) transmitter
995 * Arguments: tty pointer to tty info structure
998 static void mgsl_start(struct tty_struct
*tty
)
1000 struct mgsl_struct
*info
= tty
->driver_data
;
1001 unsigned long flags
;
1003 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1006 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1007 printk("mgsl_start(%s)\n",info
->device_name
);
1009 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1010 if (!info
->tx_enabled
)
1011 usc_start_transmitter(info
);
1012 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1014 } /* end of mgsl_start() */
1017 * Bottom half work queue access functions
1020 /* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1023 static int mgsl_bh_action(struct mgsl_struct
*info
)
1025 unsigned long flags
;
1028 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1030 if (info
->pending_bh
& BH_RECEIVE
) {
1031 info
->pending_bh
&= ~BH_RECEIVE
;
1033 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1034 info
->pending_bh
&= ~BH_TRANSMIT
;
1036 } else if (info
->pending_bh
& BH_STATUS
) {
1037 info
->pending_bh
&= ~BH_STATUS
;
1042 /* Mark BH routine as complete */
1043 info
->bh_running
= false;
1044 info
->bh_requested
= false;
1047 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1053 * Perform bottom half processing of work items queued by ISR.
1055 static void mgsl_bh_handler(struct work_struct
*work
)
1057 struct mgsl_struct
*info
=
1058 container_of(work
, struct mgsl_struct
, task
);
1061 if ( debug_level
>= DEBUG_LEVEL_BH
)
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__
,__LINE__
,info
->device_name
);
1065 info
->bh_running
= true;
1067 while((action
= mgsl_bh_action(info
)) != 0) {
1069 /* Process work item */
1070 if ( debug_level
>= DEBUG_LEVEL_BH
)
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__
,__LINE__
,action
);
1077 mgsl_bh_receive(info
);
1080 mgsl_bh_transmit(info
);
1083 mgsl_bh_status(info
);
1086 /* unknown work item ID */
1087 printk("Unknown work item ID=%08X!\n", action
);
1092 if ( debug_level
>= DEBUG_LEVEL_BH
)
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__
,__LINE__
,info
->device_name
);
1097 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1099 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1100 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1102 if ( debug_level
>= DEBUG_LEVEL_BH
)
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__
,__LINE__
,info
->device_name
);
1108 if (info
->rx_rcc_underrun
) {
1109 unsigned long flags
;
1110 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1111 usc_start_receiver(info
);
1112 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1115 } while(get_rx_frame(info
));
1118 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1120 struct tty_struct
*tty
= info
->port
.tty
;
1121 unsigned long flags
;
1123 if ( debug_level
>= DEBUG_LEVEL_BH
)
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__
,__LINE__
,info
->device_name
);
1130 /* if transmitter idle and loopmode_send_done_requested
1131 * then start echoing RxD to TxD
1133 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1134 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1135 usc_loopmode_send_done( info
);
1136 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1139 static void mgsl_bh_status(struct mgsl_struct
*info
)
1141 if ( debug_level
>= DEBUG_LEVEL_BH
)
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__
,__LINE__
,info
->device_name
);
1145 info
->ri_chkcount
= 0;
1146 info
->dsr_chkcount
= 0;
1147 info
->dcd_chkcount
= 0;
1148 info
->cts_chkcount
= 0;
1151 /* mgsl_isr_receive_status()
1153 * Service a receive status interrupt. The type of status
1154 * interrupt is indicated by the state of the RCSR.
1155 * This is only used for HDLC mode.
1157 * Arguments: info pointer to device instance data
1158 * Return Value: None
1160 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1162 u16 status
= usc_InReg( info
, RCSR
);
1164 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__
,__LINE__
,status
);
1168 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1169 info
->loopmode_insert_requested
&&
1170 usc_loopmode_active(info
) )
1172 ++info
->icount
.rxabort
;
1173 info
->loopmode_insert_requested
= false;
1175 /* clear CMR:13 to start echoing RxD to TxD */
1176 info
->cmr_value
&= ~BIT13
;
1177 usc_OutReg(info
, CMR
, info
->cmr_value
);
1179 /* disable received abort irq (no longer required) */
1180 usc_OutReg(info
, RICR
,
1181 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1184 if (status
& (RXSTATUS_EXITED_HUNT
| RXSTATUS_IDLE_RECEIVED
)) {
1185 if (status
& RXSTATUS_EXITED_HUNT
)
1186 info
->icount
.exithunt
++;
1187 if (status
& RXSTATUS_IDLE_RECEIVED
)
1188 info
->icount
.rxidle
++;
1189 wake_up_interruptible(&info
->event_wait_q
);
1192 if (status
& RXSTATUS_OVERRUN
){
1193 info
->icount
.rxover
++;
1194 usc_process_rxoverrun_sync( info
);
1197 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1198 usc_UnlatchRxstatusBits( info
, status
);
1200 } /* end of mgsl_isr_receive_status() */
1202 /* mgsl_isr_transmit_status()
1204 * Service a transmit status interrupt
1205 * HDLC mode :end of transmit frame
1206 * Async mode:all data is sent
1207 * transmit status is indicated by bits in the TCSR.
1209 * Arguments: info pointer to device instance data
1210 * Return Value: None
1212 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1214 u16 status
= usc_InReg( info
, TCSR
);
1216 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__
,__LINE__
,status
);
1220 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1221 usc_UnlatchTxstatusBits( info
, status
);
1223 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1225 /* finished sending HDLC abort. This may leave */
1226 /* the TxFifo with data from the aborted frame */
1227 /* so purge the TxFifo. Also shutdown the DMA */
1228 /* channel in case there is data remaining in */
1229 /* the DMA buffer */
1230 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1231 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1234 if ( status
& TXSTATUS_EOF_SENT
)
1235 info
->icount
.txok
++;
1236 else if ( status
& TXSTATUS_UNDERRUN
)
1237 info
->icount
.txunder
++;
1238 else if ( status
& TXSTATUS_ABORT_SENT
)
1239 info
->icount
.txabort
++;
1241 info
->icount
.txunder
++;
1243 info
->tx_active
= false;
1244 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1245 del_timer(&info
->tx_timer
);
1247 if ( info
->drop_rts_on_tx_done
) {
1248 usc_get_serial_signals( info
);
1249 if ( info
->serial_signals
& SerialSignal_RTS
) {
1250 info
->serial_signals
&= ~SerialSignal_RTS
;
1251 usc_set_serial_signals( info
);
1253 info
->drop_rts_on_tx_done
= false;
1256 #if SYNCLINK_GENERIC_HDLC
1258 hdlcdev_tx_done(info
);
1262 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1263 usc_stop_transmitter(info
);
1266 info
->pending_bh
|= BH_TRANSMIT
;
1269 } /* end of mgsl_isr_transmit_status() */
1271 /* mgsl_isr_io_pin()
1273 * Service an Input/Output pin interrupt. The type of
1274 * interrupt is indicated by bits in the MISR
1276 * Arguments: info pointer to device instance data
1277 * Return Value: None
1279 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1281 struct mgsl_icount
*icount
;
1282 u16 status
= usc_InReg( info
, MISR
);
1284 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__
,__LINE__
,status
);
1288 usc_ClearIrqPendingBits( info
, IO_PIN
);
1289 usc_UnlatchIostatusBits( info
, status
);
1291 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1292 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1293 icount
= &info
->icount
;
1294 /* update input line counters */
1295 if (status
& MISCSTATUS_RI_LATCHED
) {
1296 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1297 usc_DisablestatusIrqs(info
,SICR_RI
);
1299 if ( status
& MISCSTATUS_RI
)
1300 info
->input_signal_events
.ri_up
++;
1302 info
->input_signal_events
.ri_down
++;
1304 if (status
& MISCSTATUS_DSR_LATCHED
) {
1305 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1306 usc_DisablestatusIrqs(info
,SICR_DSR
);
1308 if ( status
& MISCSTATUS_DSR
)
1309 info
->input_signal_events
.dsr_up
++;
1311 info
->input_signal_events
.dsr_down
++;
1313 if (status
& MISCSTATUS_DCD_LATCHED
) {
1314 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1315 usc_DisablestatusIrqs(info
,SICR_DCD
);
1317 if (status
& MISCSTATUS_DCD
) {
1318 info
->input_signal_events
.dcd_up
++;
1320 info
->input_signal_events
.dcd_down
++;
1321 #if SYNCLINK_GENERIC_HDLC
1322 if (info
->netcount
) {
1323 if (status
& MISCSTATUS_DCD
)
1324 netif_carrier_on(info
->netdev
);
1326 netif_carrier_off(info
->netdev
);
1330 if (status
& MISCSTATUS_CTS_LATCHED
)
1332 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1333 usc_DisablestatusIrqs(info
,SICR_CTS
);
1335 if ( status
& MISCSTATUS_CTS
)
1336 info
->input_signal_events
.cts_up
++;
1338 info
->input_signal_events
.cts_down
++;
1340 wake_up_interruptible(&info
->status_event_wait_q
);
1341 wake_up_interruptible(&info
->event_wait_q
);
1343 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
1344 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1345 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1346 printk("%s CD now %s...", info
->device_name
,
1347 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1348 if (status
& MISCSTATUS_DCD
)
1349 wake_up_interruptible(&info
->port
.open_wait
);
1351 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1352 printk("doing serial hangup...");
1354 tty_hangup(info
->port
.tty
);
1358 if (tty_port_cts_enabled(&info
->port
) &&
1359 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1360 if (info
->port
.tty
->hw_stopped
) {
1361 if (status
& MISCSTATUS_CTS
) {
1362 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1363 printk("CTS tx start...");
1365 info
->port
.tty
->hw_stopped
= 0;
1366 usc_start_transmitter(info
);
1367 info
->pending_bh
|= BH_TRANSMIT
;
1371 if (!(status
& MISCSTATUS_CTS
)) {
1372 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1373 printk("CTS tx stop...");
1375 info
->port
.tty
->hw_stopped
= 1;
1376 usc_stop_transmitter(info
);
1382 info
->pending_bh
|= BH_STATUS
;
1384 /* for diagnostics set IRQ flag */
1385 if ( status
& MISCSTATUS_TXC_LATCHED
){
1386 usc_OutReg( info
, SICR
,
1387 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1388 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1389 info
->irq_occurred
= true;
1392 } /* end of mgsl_isr_io_pin() */
1394 /* mgsl_isr_transmit_data()
1396 * Service a transmit data interrupt (async mode only).
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1401 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1403 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__
,__LINE__
,info
->xmit_cnt
);
1407 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1409 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1410 usc_stop_transmitter(info
);
1414 if ( info
->xmit_cnt
)
1415 usc_load_txfifo( info
);
1417 info
->tx_active
= false;
1419 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1420 info
->pending_bh
|= BH_TRANSMIT
;
1422 } /* end of mgsl_isr_transmit_data() */
1424 /* mgsl_isr_receive_data()
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1433 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1438 unsigned char DataByte
;
1439 struct mgsl_icount
*icount
= &info
->icount
;
1441 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1445 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1454 /* flush the receive FIFO */
1456 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1459 /* read one byte from RxFIFO */
1460 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1461 info
->io_base
+ CCAR
);
1462 DataByte
= inb( info
->io_base
+ CCAR
);
1464 /* get the status of the received byte */
1465 status
= usc_InReg(info
, RCSR
);
1466 if ( status
& (RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
|
1467 RXSTATUS_OVERRUN
| RXSTATUS_BREAK_RECEIVED
) )
1468 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1473 if ( status
& (RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
|
1474 RXSTATUS_OVERRUN
| RXSTATUS_BREAK_RECEIVED
) ) {
1475 printk("rxerr=%04X\n",status
);
1476 /* update error statistics */
1477 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1478 status
&= ~(RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
);
1480 } else if (status
& RXSTATUS_PARITY_ERROR
)
1482 else if (status
& RXSTATUS_FRAMING_ERROR
)
1484 else if (status
& RXSTATUS_OVERRUN
) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1491 /* discard char if tty control flags say so */
1492 if (status
& info
->ignore_status_mask
)
1495 status
&= info
->read_status_mask
;
1497 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1499 if (info
->port
.flags
& ASYNC_SAK
)
1500 do_SAK(info
->port
.tty
);
1501 } else if (status
& RXSTATUS_PARITY_ERROR
)
1503 else if (status
& RXSTATUS_FRAMING_ERROR
)
1505 } /* end of if (error) */
1506 tty_insert_flip_char(&info
->port
, DataByte
, flag
);
1507 if (status
& RXSTATUS_OVERRUN
) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1512 work
+= tty_insert_flip_char(&info
->port
, 0, TTY_OVERRUN
);
1516 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1519 icount
->parity
,icount
->frame
,icount
->overrun
);
1523 tty_flip_buffer_push(&info
->port
);
1528 * Service a miscellaneous interrupt source.
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1533 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1535 u16 status
= usc_InReg( info
, MISR
);
1537 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__
,__LINE__
,status
);
1541 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1542 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1546 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1547 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1548 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
1549 usc_DisableInterrupts(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
1551 /* schedule BH handler to restart receiver */
1552 info
->pending_bh
|= BH_RECEIVE
;
1553 info
->rx_rcc_underrun
= true;
1556 usc_ClearIrqPendingBits( info
, MISC
);
1557 usc_UnlatchMiscstatusBits( info
, status
);
1559 } /* end of mgsl_isr_misc() */
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1569 static void mgsl_isr_null( struct mgsl_struct
*info
)
1572 } /* end of mgsl_isr_null() */
1574 /* mgsl_isr_receive_dma()
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1593 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1598 usc_OutDmaReg( info
, CDIR
, BIT9
| BIT1
);
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status
= usc_InDmaReg( info
, RDMR
);
1604 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__
,__LINE__
,info
->device_name
,status
);
1608 info
->pending_bh
|= BH_RECEIVE
;
1610 if ( status
& BIT3
) {
1611 info
->rx_overflow
= true;
1612 info
->icount
.buf_overrun
++;
1615 } /* end of mgsl_isr_receive_dma() */
1617 /* mgsl_isr_transmit_dma()
1619 * This function services a transmit DMA channel interrupt.
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1637 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1642 usc_OutDmaReg(info
, CDIR
, BIT8
| BIT0
);
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1647 status
= usc_InDmaReg( info
, TDMR
);
1649 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__
,__LINE__
,info
->device_name
,status
);
1653 if ( status
& BIT2
) {
1654 --info
->tx_dma_buffers_used
;
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1659 if ( load_next_tx_holding_buffer(info
) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1663 info
->pending_bh
|= BH_TRANSMIT
;
1667 } /* end of mgsl_isr_transmit_dma() */
1671 * Interrupt service routine entry point.
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1678 * Return Value: None
1680 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1682 struct mgsl_struct
*info
= dev_id
;
1686 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1687 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__
, __LINE__
, info
->irq_level
);
1690 spin_lock(&info
->irq_spinlock
);
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector
= usc_InReg(info
, IVR
) >> 9;
1695 DmaVector
= usc_InDmaReg(info
, DIVR
);
1697 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1701 if ( !UscVector
&& !DmaVector
)
1704 /* Dispatch interrupt vector */
1706 (*UscIsrTable
[UscVector
])(info
);
1707 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1708 mgsl_isr_transmit_dma(info
);
1710 mgsl_isr_receive_dma(info
);
1712 if ( info
->isr_overflow
) {
1713 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1715 usc_DisableMasterIrqBit(info
);
1716 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1725 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1726 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__
,__LINE__
,info
->device_name
);
1729 schedule_work(&info
->task
);
1730 info
->bh_requested
= true;
1733 spin_unlock(&info
->irq_spinlock
);
1735 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1736 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__
, __LINE__
, info
->irq_level
);
1740 } /* end of mgsl_interrupt() */
1744 * Initialize and start device.
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1749 static int startup(struct mgsl_struct
* info
)
1753 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1756 if (info
->port
.flags
& ASYNC_INITIALIZED
)
1759 if (!info
->xmit_buf
) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1762 if (!info
->xmit_buf
) {
1763 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__
,__LINE__
,info
->device_name
);
1769 info
->pending_bh
= 0;
1771 memset(&info
->icount
, 0, sizeof(info
->icount
));
1773 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1775 /* Allocate and claim adapter resources */
1776 retval
= mgsl_claim_resources(info
);
1778 /* perform existence check and diagnostics */
1780 retval
= mgsl_adapter_test(info
);
1783 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1784 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1785 mgsl_release_resources(info
);
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info
);
1793 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1795 info
->port
.flags
|= ASYNC_INITIALIZED
;
1799 } /* end of startup() */
1803 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1805 * Arguments: info pointer to device instance data
1806 * Return Value: None
1808 static void shutdown(struct mgsl_struct
* info
)
1810 unsigned long flags
;
1812 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1815 if (debug_level
>= DEBUG_LEVEL_INFO
)
1816 printk("%s(%d):mgsl_shutdown(%s)\n",
1817 __FILE__
,__LINE__
, info
->device_name
);
1819 /* clear status wait queue because status changes */
1820 /* can't happen after shutting down the hardware */
1821 wake_up_interruptible(&info
->status_event_wait_q
);
1822 wake_up_interruptible(&info
->event_wait_q
);
1824 del_timer_sync(&info
->tx_timer
);
1826 if (info
->xmit_buf
) {
1827 free_page((unsigned long) info
->xmit_buf
);
1828 info
->xmit_buf
= NULL
;
1831 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1832 usc_DisableMasterIrqBit(info
);
1833 usc_stop_receiver(info
);
1834 usc_stop_transmitter(info
);
1835 usc_DisableInterrupts(info
,RECEIVE_DATA
| RECEIVE_STATUS
|
1836 TRANSMIT_DATA
| TRANSMIT_STATUS
| IO_PIN
| MISC
);
1837 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1839 /* Disable DMAEN (Port 7, Bit 14) */
1840 /* This disconnects the DMA request signal from the ISA bus */
1841 /* on the ISA adapter. This has no effect for the PCI adapter */
1842 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1844 /* Disable INTEN (Port 6, Bit12) */
1845 /* This disconnects the IRQ request signal to the ISA bus */
1846 /* on the ISA adapter. This has no effect for the PCI adapter */
1847 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1849 if (!info
->port
.tty
|| info
->port
.tty
->termios
.c_cflag
& HUPCL
) {
1850 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1851 usc_set_serial_signals(info
);
1854 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1856 mgsl_release_resources(info
);
1859 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1861 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
1863 } /* end of shutdown() */
1865 static void mgsl_program_hw(struct mgsl_struct
*info
)
1867 unsigned long flags
;
1869 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1871 usc_stop_receiver(info
);
1872 usc_stop_transmitter(info
);
1873 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1875 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1876 info
->params
.mode
== MGSL_MODE_RAW
||
1878 usc_set_sync_mode(info
);
1880 usc_set_async_mode(info
);
1882 usc_set_serial_signals(info
);
1884 info
->dcd_chkcount
= 0;
1885 info
->cts_chkcount
= 0;
1886 info
->ri_chkcount
= 0;
1887 info
->dsr_chkcount
= 0;
1889 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1890 usc_EnableInterrupts(info
, IO_PIN
);
1891 usc_get_serial_signals(info
);
1893 if (info
->netcount
|| info
->port
.tty
->termios
.c_cflag
& CREAD
)
1894 usc_start_receiver(info
);
1896 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1899 /* Reconfigure adapter based on new parameters
1901 static void mgsl_change_params(struct mgsl_struct
*info
)
1906 if (!info
->port
.tty
)
1909 if (debug_level
>= DEBUG_LEVEL_INFO
)
1910 printk("%s(%d):mgsl_change_params(%s)\n",
1911 __FILE__
,__LINE__
, info
->device_name
);
1913 cflag
= info
->port
.tty
->termios
.c_cflag
;
1915 /* if B0 rate (hangup) specified then negate RTS and DTR */
1916 /* otherwise assert RTS and DTR */
1918 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
1920 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1922 /* byte size and parity */
1924 switch (cflag
& CSIZE
) {
1925 case CS5
: info
->params
.data_bits
= 5; break;
1926 case CS6
: info
->params
.data_bits
= 6; break;
1927 case CS7
: info
->params
.data_bits
= 7; break;
1928 case CS8
: info
->params
.data_bits
= 8; break;
1929 /* Never happens, but GCC is too dumb to figure it out */
1930 default: info
->params
.data_bits
= 7; break;
1934 info
->params
.stop_bits
= 2;
1936 info
->params
.stop_bits
= 1;
1938 info
->params
.parity
= ASYNC_PARITY_NONE
;
1939 if (cflag
& PARENB
) {
1941 info
->params
.parity
= ASYNC_PARITY_ODD
;
1943 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1946 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1950 /* calculate number of jiffies to transmit a full
1951 * FIFO (32 bytes) at specified data rate
1953 bits_per_char
= info
->params
.data_bits
+
1954 info
->params
.stop_bits
+ 1;
1956 /* if port data rate is set to 460800 or less then
1957 * allow tty settings to override, otherwise keep the
1958 * current data rate.
1960 if (info
->params
.data_rate
<= 460800)
1961 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1963 if ( info
->params
.data_rate
) {
1964 info
->timeout
= (32*HZ
*bits_per_char
) /
1965 info
->params
.data_rate
;
1967 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1969 tty_port_set_cts_flow(&info
->port
, cflag
& CRTSCTS
);
1972 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
1974 info
->port
.flags
|= ASYNC_CHECK_CD
;
1976 /* process tty input control flags */
1978 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1979 if (I_INPCK(info
->port
.tty
))
1980 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1981 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1982 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1984 if (I_IGNPAR(info
->port
.tty
))
1985 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1986 if (I_IGNBRK(info
->port
.tty
)) {
1987 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1988 /* If ignoring parity and break indicators, ignore
1989 * overruns too. (For real raw support).
1991 if (I_IGNPAR(info
->port
.tty
))
1992 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
1995 mgsl_program_hw(info
);
1997 } /* end of mgsl_change_params() */
2001 * Add a character to the transmit buffer.
2003 * Arguments: tty pointer to tty information structure
2004 * ch character to add to transmit buffer
2006 * Return Value: None
2008 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2010 struct mgsl_struct
*info
= tty
->driver_data
;
2011 unsigned long flags
;
2014 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2015 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2016 __FILE__
, __LINE__
, ch
, info
->device_name
);
2019 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2022 if (!info
->xmit_buf
)
2025 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2027 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2028 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2029 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2030 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2035 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2038 } /* end of mgsl_put_char() */
2040 /* mgsl_flush_chars()
2042 * Enable transmitter so remaining characters in the
2043 * transmit buffer are sent.
2045 * Arguments: tty pointer to tty information structure
2046 * Return Value: None
2048 static void mgsl_flush_chars(struct tty_struct
*tty
)
2050 struct mgsl_struct
*info
= tty
->driver_data
;
2051 unsigned long flags
;
2053 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2054 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2055 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2057 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2060 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2064 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2065 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2066 __FILE__
,__LINE__
,info
->device_name
);
2068 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2070 if (!info
->tx_active
) {
2071 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2072 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2073 /* operating in synchronous (frame oriented) mode */
2074 /* copy data from circular xmit_buf to */
2075 /* transmit DMA buffer. */
2076 mgsl_load_tx_dma_buffer(info
,
2077 info
->xmit_buf
,info
->xmit_cnt
);
2079 usc_start_transmitter(info
);
2082 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2084 } /* end of mgsl_flush_chars() */
2088 * Send a block of data
2092 * tty pointer to tty information structure
2093 * buf pointer to buffer containing send data
2094 * count size of send data in bytes
2096 * Return Value: number of characters written
2098 static int mgsl_write(struct tty_struct
* tty
,
2099 const unsigned char *buf
, int count
)
2102 struct mgsl_struct
*info
= tty
->driver_data
;
2103 unsigned long flags
;
2105 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2106 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2107 __FILE__
,__LINE__
,info
->device_name
,count
);
2109 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2112 if (!info
->xmit_buf
)
2115 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2116 info
->params
.mode
== MGSL_MODE_RAW
) {
2117 /* operating in synchronous (frame oriented) mode */
2118 if (info
->tx_active
) {
2120 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2124 /* transmitter is actively sending data -
2125 * if we have multiple transmit dma and
2126 * holding buffers, attempt to queue this
2127 * frame for transmission at a later time.
2129 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2130 /* no tx holding buffers available */
2135 /* queue transmit frame request */
2137 save_tx_buffer_request(info
,buf
,count
);
2139 /* if we have sufficient tx dma buffers,
2140 * load the next buffered tx request
2142 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2143 load_next_tx_holding_buffer(info
);
2144 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2148 /* if operating in HDLC LoopMode and the adapter */
2149 /* has yet to be inserted into the loop, we can't */
2152 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2153 !usc_loopmode_active(info
) )
2159 if ( info
->xmit_cnt
) {
2160 /* Send accumulated from send_char() calls */
2161 /* as frame and wait before accepting more data. */
2164 /* copy data from circular xmit_buf to */
2165 /* transmit DMA buffer. */
2166 mgsl_load_tx_dma_buffer(info
,
2167 info
->xmit_buf
,info
->xmit_cnt
);
2168 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2169 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2170 __FILE__
,__LINE__
,info
->device_name
);
2172 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2173 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2174 __FILE__
,__LINE__
,info
->device_name
);
2176 info
->xmit_cnt
= count
;
2177 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2181 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2182 c
= min_t(int, count
,
2183 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2184 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2186 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2189 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2190 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2191 (SERIAL_XMIT_SIZE
-1));
2192 info
->xmit_cnt
+= c
;
2193 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2200 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2201 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2202 if (!info
->tx_active
)
2203 usc_start_transmitter(info
);
2204 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2207 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2208 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2209 __FILE__
,__LINE__
,info
->device_name
,ret
);
2213 } /* end of mgsl_write() */
2215 /* mgsl_write_room()
2217 * Return the count of free bytes in transmit buffer
2219 * Arguments: tty pointer to tty info structure
2220 * Return Value: None
2222 static int mgsl_write_room(struct tty_struct
*tty
)
2224 struct mgsl_struct
*info
= tty
->driver_data
;
2227 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2229 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2233 if (debug_level
>= DEBUG_LEVEL_INFO
)
2234 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2235 __FILE__
,__LINE__
, info
->device_name
,ret
);
2237 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2238 info
->params
.mode
== MGSL_MODE_RAW
) {
2239 /* operating in synchronous (frame oriented) mode */
2240 if ( info
->tx_active
)
2243 return HDLC_MAX_FRAME_SIZE
;
2248 } /* end of mgsl_write_room() */
2250 /* mgsl_chars_in_buffer()
2252 * Return the count of bytes in transmit buffer
2254 * Arguments: tty pointer to tty info structure
2255 * Return Value: None
2257 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2259 struct mgsl_struct
*info
= tty
->driver_data
;
2261 if (debug_level
>= DEBUG_LEVEL_INFO
)
2262 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2263 __FILE__
,__LINE__
, info
->device_name
);
2265 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2268 if (debug_level
>= DEBUG_LEVEL_INFO
)
2269 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2270 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2272 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2273 info
->params
.mode
== MGSL_MODE_RAW
) {
2274 /* operating in synchronous (frame oriented) mode */
2275 if ( info
->tx_active
)
2276 return info
->max_frame_size
;
2281 return info
->xmit_cnt
;
2282 } /* end of mgsl_chars_in_buffer() */
2284 /* mgsl_flush_buffer()
2286 * Discard all data in the send buffer
2288 * Arguments: tty pointer to tty info structure
2289 * Return Value: None
2291 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2293 struct mgsl_struct
*info
= tty
->driver_data
;
2294 unsigned long flags
;
2296 if (debug_level
>= DEBUG_LEVEL_INFO
)
2297 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2298 __FILE__
,__LINE__
, info
->device_name
);
2300 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2303 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2304 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2305 del_timer(&info
->tx_timer
);
2306 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2311 /* mgsl_send_xchar()
2313 * Send a high-priority XON/XOFF character
2315 * Arguments: tty pointer to tty info structure
2316 * ch character to send
2317 * Return Value: None
2319 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2321 struct mgsl_struct
*info
= tty
->driver_data
;
2322 unsigned long flags
;
2324 if (debug_level
>= DEBUG_LEVEL_INFO
)
2325 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2326 __FILE__
,__LINE__
, info
->device_name
, ch
);
2328 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2333 /* Make sure transmit interrupts are on */
2334 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2335 if (!info
->tx_enabled
)
2336 usc_start_transmitter(info
);
2337 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2339 } /* end of mgsl_send_xchar() */
2343 * Signal remote device to throttle send data (our receive data)
2345 * Arguments: tty pointer to tty info structure
2346 * Return Value: None
2348 static void mgsl_throttle(struct tty_struct
* tty
)
2350 struct mgsl_struct
*info
= tty
->driver_data
;
2351 unsigned long flags
;
2353 if (debug_level
>= DEBUG_LEVEL_INFO
)
2354 printk("%s(%d):mgsl_throttle(%s) entry\n",
2355 __FILE__
,__LINE__
, info
->device_name
);
2357 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2361 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2363 if (C_CRTSCTS(tty
)) {
2364 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2365 info
->serial_signals
&= ~SerialSignal_RTS
;
2366 usc_set_serial_signals(info
);
2367 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2369 } /* end of mgsl_throttle() */
2371 /* mgsl_unthrottle()
2373 * Signal remote device to stop throttling send data (our receive data)
2375 * Arguments: tty pointer to tty info structure
2376 * Return Value: None
2378 static void mgsl_unthrottle(struct tty_struct
* tty
)
2380 struct mgsl_struct
*info
= tty
->driver_data
;
2381 unsigned long flags
;
2383 if (debug_level
>= DEBUG_LEVEL_INFO
)
2384 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2385 __FILE__
,__LINE__
, info
->device_name
);
2387 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2394 mgsl_send_xchar(tty
, START_CHAR(tty
));
2397 if (C_CRTSCTS(tty
)) {
2398 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2399 info
->serial_signals
|= SerialSignal_RTS
;
2400 usc_set_serial_signals(info
);
2401 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2404 } /* end of mgsl_unthrottle() */
2408 * get the current serial parameters information
2410 * Arguments: info pointer to device instance data
2411 * user_icount pointer to buffer to hold returned stats
2413 * Return Value: 0 if success, otherwise error code
2415 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2419 if (debug_level
>= DEBUG_LEVEL_INFO
)
2420 printk("%s(%d):mgsl_get_params(%s)\n",
2421 __FILE__
,__LINE__
, info
->device_name
);
2424 memset(&info
->icount
, 0, sizeof(info
->icount
));
2426 mutex_lock(&info
->port
.mutex
);
2427 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2428 mutex_unlock(&info
->port
.mutex
);
2435 } /* end of mgsl_get_stats() */
2437 /* mgsl_get_params()
2439 * get the current serial parameters information
2441 * Arguments: info pointer to device instance data
2442 * user_params pointer to buffer to hold returned params
2444 * Return Value: 0 if success, otherwise error code
2446 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2449 if (debug_level
>= DEBUG_LEVEL_INFO
)
2450 printk("%s(%d):mgsl_get_params(%s)\n",
2451 __FILE__
,__LINE__
, info
->device_name
);
2453 mutex_lock(&info
->port
.mutex
);
2454 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2455 mutex_unlock(&info
->port
.mutex
);
2457 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2458 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2459 __FILE__
,__LINE__
,info
->device_name
);
2465 } /* end of mgsl_get_params() */
2467 /* mgsl_set_params()
2469 * set the serial parameters
2473 * info pointer to device instance data
2474 * new_params user buffer containing new serial params
2476 * Return Value: 0 if success, otherwise error code
2478 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2480 unsigned long flags
;
2481 MGSL_PARAMS tmp_params
;
2484 if (debug_level
>= DEBUG_LEVEL_INFO
)
2485 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2486 info
->device_name
);
2487 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2489 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2490 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2491 __FILE__
,__LINE__
,info
->device_name
);
2495 mutex_lock(&info
->port
.mutex
);
2496 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2497 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2498 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2500 mgsl_change_params(info
);
2501 mutex_unlock(&info
->port
.mutex
);
2505 } /* end of mgsl_set_params() */
2507 /* mgsl_get_txidle()
2509 * get the current transmit idle mode
2511 * Arguments: info pointer to device instance data
2512 * idle_mode pointer to buffer to hold returned idle mode
2514 * Return Value: 0 if success, otherwise error code
2516 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2520 if (debug_level
>= DEBUG_LEVEL_INFO
)
2521 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2522 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2524 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2526 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2527 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2528 __FILE__
,__LINE__
,info
->device_name
);
2534 } /* end of mgsl_get_txidle() */
2536 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2538 * Arguments: info pointer to device instance data
2539 * idle_mode new idle mode
2541 * Return Value: 0 if success, otherwise error code
2543 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2545 unsigned long flags
;
2547 if (debug_level
>= DEBUG_LEVEL_INFO
)
2548 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2549 info
->device_name
, idle_mode
);
2551 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2552 info
->idle_mode
= idle_mode
;
2553 usc_set_txidle( info
);
2554 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2557 } /* end of mgsl_set_txidle() */
2561 * enable or disable the transmitter
2565 * info pointer to device instance data
2566 * enable 1 = enable, 0 = disable
2568 * Return Value: 0 if success, otherwise error code
2570 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2572 unsigned long flags
;
2574 if (debug_level
>= DEBUG_LEVEL_INFO
)
2575 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2576 info
->device_name
, enable
);
2578 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2580 if ( !info
->tx_enabled
) {
2582 usc_start_transmitter(info
);
2583 /*--------------------------------------------------
2584 * if HDLC/SDLC Loop mode, attempt to insert the
2585 * station in the 'loop' by setting CMR:13. Upon
2586 * receipt of the next GoAhead (RxAbort) sequence,
2587 * the OnLoop indicator (CCSR:7) should go active
2588 * to indicate that we are on the loop
2589 *--------------------------------------------------*/
2590 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2591 usc_loopmode_insert_request( info
);
2594 if ( info
->tx_enabled
)
2595 usc_stop_transmitter(info
);
2597 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2600 } /* end of mgsl_txenable() */
2602 /* mgsl_txabort() abort send HDLC frame
2604 * Arguments: info pointer to device instance data
2605 * Return Value: 0 if success, otherwise error code
2607 static int mgsl_txabort(struct mgsl_struct
* info
)
2609 unsigned long flags
;
2611 if (debug_level
>= DEBUG_LEVEL_INFO
)
2612 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2615 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2616 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2618 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2619 usc_loopmode_cancel_transmit( info
);
2621 usc_TCmd(info
,TCmd_SendAbort
);
2623 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2626 } /* end of mgsl_txabort() */
2628 /* mgsl_rxenable() enable or disable the receiver
2630 * Arguments: info pointer to device instance data
2631 * enable 1 = enable, 0 = disable
2632 * Return Value: 0 if success, otherwise error code
2634 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2636 unsigned long flags
;
2638 if (debug_level
>= DEBUG_LEVEL_INFO
)
2639 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2640 info
->device_name
, enable
);
2642 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2644 if ( !info
->rx_enabled
)
2645 usc_start_receiver(info
);
2647 if ( info
->rx_enabled
)
2648 usc_stop_receiver(info
);
2650 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2653 } /* end of mgsl_rxenable() */
2655 /* mgsl_wait_event() wait for specified event to occur
2657 * Arguments: info pointer to device instance data
2658 * mask pointer to bitmask of events to wait for
2659 * Return Value: 0 if successful and bit mask updated with
2660 * of events triggerred,
2661 * otherwise error code
2663 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2665 unsigned long flags
;
2668 struct mgsl_icount cprev
, cnow
;
2671 struct _input_signal_events oldsigs
, newsigs
;
2672 DECLARE_WAITQUEUE(wait
, current
);
2674 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2679 if (debug_level
>= DEBUG_LEVEL_INFO
)
2680 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2681 info
->device_name
, mask
);
2683 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2685 /* return immediately if state matches requested events */
2686 usc_get_serial_signals(info
);
2687 s
= info
->serial_signals
;
2689 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2690 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2691 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2692 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2694 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2698 /* save current irq counts */
2699 cprev
= info
->icount
;
2700 oldsigs
= info
->input_signal_events
;
2702 /* enable hunt and idle irqs if needed */
2703 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2704 u16 oldreg
= usc_InReg(info
,RICR
);
2705 u16 newreg
= oldreg
+
2706 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2707 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2708 if (oldreg
!= newreg
)
2709 usc_OutReg(info
, RICR
, newreg
);
2712 set_current_state(TASK_INTERRUPTIBLE
);
2713 add_wait_queue(&info
->event_wait_q
, &wait
);
2715 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2720 if (signal_pending(current
)) {
2725 /* get current irq counts */
2726 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2727 cnow
= info
->icount
;
2728 newsigs
= info
->input_signal_events
;
2729 set_current_state(TASK_INTERRUPTIBLE
);
2730 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2732 /* if no change, wait aborted for some reason */
2733 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2734 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2735 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2736 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2737 newsigs
.cts_up
== oldsigs
.cts_up
&&
2738 newsigs
.cts_down
== oldsigs
.cts_down
&&
2739 newsigs
.ri_up
== oldsigs
.ri_up
&&
2740 newsigs
.ri_down
== oldsigs
.ri_down
&&
2741 cnow
.exithunt
== cprev
.exithunt
&&
2742 cnow
.rxidle
== cprev
.rxidle
) {
2748 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2749 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2750 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2751 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2752 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2753 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2754 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2755 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2756 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2757 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2765 remove_wait_queue(&info
->event_wait_q
, &wait
);
2766 set_current_state(TASK_RUNNING
);
2768 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2769 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2770 if (!waitqueue_active(&info
->event_wait_q
)) {
2771 /* disable enable exit hunt mode/idle rcvd IRQs */
2772 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2773 ~(RXSTATUS_EXITED_HUNT
| RXSTATUS_IDLE_RECEIVED
));
2775 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2779 PUT_USER(rc
, events
, mask_ptr
);
2783 } /* end of mgsl_wait_event() */
2785 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2787 unsigned long flags
;
2789 struct mgsl_icount cprev
, cnow
;
2790 DECLARE_WAITQUEUE(wait
, current
);
2792 /* save current irq counts */
2793 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2794 cprev
= info
->icount
;
2795 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2796 set_current_state(TASK_INTERRUPTIBLE
);
2797 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2801 if (signal_pending(current
)) {
2806 /* get new irq counts */
2807 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2808 cnow
= info
->icount
;
2809 set_current_state(TASK_INTERRUPTIBLE
);
2810 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2812 /* if no change, wait aborted for some reason */
2813 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2814 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2819 /* check for change in caller specified modem input */
2820 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2821 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2822 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2823 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2830 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2831 set_current_state(TASK_RUNNING
);
2835 /* return the state of the serial control and status signals
2837 static int tiocmget(struct tty_struct
*tty
)
2839 struct mgsl_struct
*info
= tty
->driver_data
;
2840 unsigned int result
;
2841 unsigned long flags
;
2843 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2844 usc_get_serial_signals(info
);
2845 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2847 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2848 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2849 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2850 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2851 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2852 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2854 if (debug_level
>= DEBUG_LEVEL_INFO
)
2855 printk("%s(%d):%s tiocmget() value=%08X\n",
2856 __FILE__
,__LINE__
, info
->device_name
, result
);
2860 /* set modem control signals (DTR/RTS)
2862 static int tiocmset(struct tty_struct
*tty
,
2863 unsigned int set
, unsigned int clear
)
2865 struct mgsl_struct
*info
= tty
->driver_data
;
2866 unsigned long flags
;
2868 if (debug_level
>= DEBUG_LEVEL_INFO
)
2869 printk("%s(%d):%s tiocmset(%x,%x)\n",
2870 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2872 if (set
& TIOCM_RTS
)
2873 info
->serial_signals
|= SerialSignal_RTS
;
2874 if (set
& TIOCM_DTR
)
2875 info
->serial_signals
|= SerialSignal_DTR
;
2876 if (clear
& TIOCM_RTS
)
2877 info
->serial_signals
&= ~SerialSignal_RTS
;
2878 if (clear
& TIOCM_DTR
)
2879 info
->serial_signals
&= ~SerialSignal_DTR
;
2881 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2882 usc_set_serial_signals(info
);
2883 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2888 /* mgsl_break() Set or clear transmit break condition
2890 * Arguments: tty pointer to tty instance data
2891 * break_state -1=set break condition, 0=clear
2892 * Return Value: error code
2894 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2896 struct mgsl_struct
* info
= tty
->driver_data
;
2897 unsigned long flags
;
2899 if (debug_level
>= DEBUG_LEVEL_INFO
)
2900 printk("%s(%d):mgsl_break(%s,%d)\n",
2901 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2903 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2906 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2907 if (break_state
== -1)
2908 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2910 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2911 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2914 } /* end of mgsl_break() */
2917 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2918 * Return: write counters to the user passed counter struct
2919 * NB: both 1->0 and 0->1 transitions are counted except for
2920 * RI where only 0->1 is counted.
2922 static int msgl_get_icount(struct tty_struct
*tty
,
2923 struct serial_icounter_struct
*icount
)
2926 struct mgsl_struct
* info
= tty
->driver_data
;
2927 struct mgsl_icount cnow
; /* kernel counter temps */
2928 unsigned long flags
;
2930 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2931 cnow
= info
->icount
;
2932 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2934 icount
->cts
= cnow
.cts
;
2935 icount
->dsr
= cnow
.dsr
;
2936 icount
->rng
= cnow
.rng
;
2937 icount
->dcd
= cnow
.dcd
;
2938 icount
->rx
= cnow
.rx
;
2939 icount
->tx
= cnow
.tx
;
2940 icount
->frame
= cnow
.frame
;
2941 icount
->overrun
= cnow
.overrun
;
2942 icount
->parity
= cnow
.parity
;
2943 icount
->brk
= cnow
.brk
;
2944 icount
->buf_overrun
= cnow
.buf_overrun
;
2948 /* mgsl_ioctl() Service an IOCTL request
2952 * tty pointer to tty instance data
2953 * cmd IOCTL command code
2954 * arg command argument/context
2956 * Return Value: 0 if success, otherwise error code
2958 static int mgsl_ioctl(struct tty_struct
*tty
,
2959 unsigned int cmd
, unsigned long arg
)
2961 struct mgsl_struct
* info
= tty
->driver_data
;
2963 if (debug_level
>= DEBUG_LEVEL_INFO
)
2964 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2965 info
->device_name
, cmd
);
2967 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2970 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2971 (cmd
!= TIOCMIWAIT
)) {
2972 if (tty_io_error(tty
))
2976 return mgsl_ioctl_common(info
, cmd
, arg
);
2979 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2981 void __user
*argp
= (void __user
*)arg
;
2984 case MGSL_IOCGPARAMS
:
2985 return mgsl_get_params(info
, argp
);
2986 case MGSL_IOCSPARAMS
:
2987 return mgsl_set_params(info
, argp
);
2988 case MGSL_IOCGTXIDLE
:
2989 return mgsl_get_txidle(info
, argp
);
2990 case MGSL_IOCSTXIDLE
:
2991 return mgsl_set_txidle(info
,(int)arg
);
2992 case MGSL_IOCTXENABLE
:
2993 return mgsl_txenable(info
,(int)arg
);
2994 case MGSL_IOCRXENABLE
:
2995 return mgsl_rxenable(info
,(int)arg
);
2996 case MGSL_IOCTXABORT
:
2997 return mgsl_txabort(info
);
2998 case MGSL_IOCGSTATS
:
2999 return mgsl_get_stats(info
, argp
);
3000 case MGSL_IOCWAITEVENT
:
3001 return mgsl_wait_event(info
, argp
);
3002 case MGSL_IOCLOOPTXDONE
:
3003 return mgsl_loopmode_send_done(info
);
3004 /* Wait for modem input (DCD,RI,DSR,CTS) change
3005 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3008 return modem_input_wait(info
,(int)arg
);
3011 return -ENOIOCTLCMD
;
3016 /* mgsl_set_termios()
3018 * Set new termios settings
3022 * tty pointer to tty structure
3023 * termios pointer to buffer to hold returned old termios
3025 * Return Value: None
3027 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3029 struct mgsl_struct
*info
= tty
->driver_data
;
3030 unsigned long flags
;
3032 if (debug_level
>= DEBUG_LEVEL_INFO
)
3033 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3034 tty
->driver
->name
);
3036 mgsl_change_params(info
);
3038 /* Handle transition to B0 status */
3039 if ((old_termios
->c_cflag
& CBAUD
) && !C_BAUD(tty
)) {
3040 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3041 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3042 usc_set_serial_signals(info
);
3043 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3046 /* Handle transition away from B0 status */
3047 if (!(old_termios
->c_cflag
& CBAUD
) && C_BAUD(tty
)) {
3048 info
->serial_signals
|= SerialSignal_DTR
;
3049 if (!C_CRTSCTS(tty
) || !tty_throttled(tty
))
3050 info
->serial_signals
|= SerialSignal_RTS
;
3051 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3052 usc_set_serial_signals(info
);
3053 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3056 /* Handle turning off CRTSCTS */
3057 if (old_termios
->c_cflag
& CRTSCTS
&& !C_CRTSCTS(tty
)) {
3058 tty
->hw_stopped
= 0;
3062 } /* end of mgsl_set_termios() */
3066 * Called when port is closed. Wait for remaining data to be
3067 * sent. Disable port and free resources.
3071 * tty pointer to open tty structure
3072 * filp pointer to open file object
3074 * Return Value: None
3076 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3078 struct mgsl_struct
* info
= tty
->driver_data
;
3080 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3083 if (debug_level
>= DEBUG_LEVEL_INFO
)
3084 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3085 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3087 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
3090 mutex_lock(&info
->port
.mutex
);
3091 if (info
->port
.flags
& ASYNC_INITIALIZED
)
3092 mgsl_wait_until_sent(tty
, info
->timeout
);
3093 mgsl_flush_buffer(tty
);
3094 tty_ldisc_flush(tty
);
3096 mutex_unlock(&info
->port
.mutex
);
3098 tty_port_close_end(&info
->port
, tty
);
3099 info
->port
.tty
= NULL
;
3101 if (debug_level
>= DEBUG_LEVEL_INFO
)
3102 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3103 tty
->driver
->name
, info
->port
.count
);
3105 } /* end of mgsl_close() */
3107 /* mgsl_wait_until_sent()
3109 * Wait until the transmitter is empty.
3113 * tty pointer to tty info structure
3114 * timeout time to wait for send completion
3116 * Return Value: None
3118 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3120 struct mgsl_struct
* info
= tty
->driver_data
;
3121 unsigned long orig_jiffies
, char_time
;
3126 if (debug_level
>= DEBUG_LEVEL_INFO
)
3127 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3128 __FILE__
,__LINE__
, info
->device_name
);
3130 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3133 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
3136 orig_jiffies
= jiffies
;
3138 /* Set check interval to 1/5 of estimated time to
3139 * send a character, and make it at least 1. The check
3140 * interval should also be less than the timeout.
3141 * Note: use tight timings here to satisfy the NIST-PCTS.
3144 if ( info
->params
.data_rate
) {
3145 char_time
= info
->timeout
/(32 * 5);
3152 char_time
= min_t(unsigned long, char_time
, timeout
);
3154 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3155 info
->params
.mode
== MGSL_MODE_RAW
) {
3156 while (info
->tx_active
) {
3157 msleep_interruptible(jiffies_to_msecs(char_time
));
3158 if (signal_pending(current
))
3160 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3164 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3166 msleep_interruptible(jiffies_to_msecs(char_time
));
3167 if (signal_pending(current
))
3169 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3175 if (debug_level
>= DEBUG_LEVEL_INFO
)
3176 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3177 __FILE__
,__LINE__
, info
->device_name
);
3179 } /* end of mgsl_wait_until_sent() */
3183 * Called by tty_hangup() when a hangup is signaled.
3184 * This is the same as to closing all open files for the port.
3186 * Arguments: tty pointer to associated tty object
3187 * Return Value: None
3189 static void mgsl_hangup(struct tty_struct
*tty
)
3191 struct mgsl_struct
* info
= tty
->driver_data
;
3193 if (debug_level
>= DEBUG_LEVEL_INFO
)
3194 printk("%s(%d):mgsl_hangup(%s)\n",
3195 __FILE__
,__LINE__
, info
->device_name
);
3197 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3200 mgsl_flush_buffer(tty
);
3203 info
->port
.count
= 0;
3204 tty_port_set_active(&info
->port
, 0);
3205 info
->port
.tty
= NULL
;
3207 wake_up_interruptible(&info
->port
.open_wait
);
3209 } /* end of mgsl_hangup() */
3214 * Return true if carrier is raised
3217 static int carrier_raised(struct tty_port
*port
)
3219 unsigned long flags
;
3220 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3222 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3223 usc_get_serial_signals(info
);
3224 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3225 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3228 static void dtr_rts(struct tty_port
*port
, int on
)
3230 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3231 unsigned long flags
;
3233 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3235 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
3237 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3238 usc_set_serial_signals(info
);
3239 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3243 /* block_til_ready()
3245 * Block the current process until the specified port
3246 * is ready to be opened.
3250 * tty pointer to tty info structure
3251 * filp pointer to open file object
3252 * info pointer to device instance data
3254 * Return Value: 0 if success, otherwise error code
3256 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3257 struct mgsl_struct
*info
)
3259 DECLARE_WAITQUEUE(wait
, current
);
3261 bool do_clocal
= false;
3262 unsigned long flags
;
3264 struct tty_port
*port
= &info
->port
;
3266 if (debug_level
>= DEBUG_LEVEL_INFO
)
3267 printk("%s(%d):block_til_ready on %s\n",
3268 __FILE__
,__LINE__
, tty
->driver
->name
);
3270 if (filp
->f_flags
& O_NONBLOCK
|| tty_io_error(tty
)) {
3271 /* nonblock mode is set or port is not enabled */
3272 tty_port_set_active(port
, 1);
3279 /* Wait for carrier detect and the line to become
3280 * free (i.e., not in use by the callout). While we are in
3281 * this loop, port->count is dropped by one, so that
3282 * mgsl_close() knows when to free things. We restore it upon
3283 * exit, either normal or abnormal.
3287 add_wait_queue(&port
->open_wait
, &wait
);
3289 if (debug_level
>= DEBUG_LEVEL_INFO
)
3290 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3291 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3293 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3295 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3296 port
->blocked_open
++;
3299 if (C_BAUD(tty
) && test_bit(ASYNCB_INITIALIZED
, &port
->flags
))
3300 tty_port_raise_dtr_rts(port
);
3302 set_current_state(TASK_INTERRUPTIBLE
);
3304 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3305 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3306 -EAGAIN
: -ERESTARTSYS
;
3310 dcd
= tty_port_carrier_raised(&info
->port
);
3311 if (do_clocal
|| dcd
)
3314 if (signal_pending(current
)) {
3315 retval
= -ERESTARTSYS
;
3319 if (debug_level
>= DEBUG_LEVEL_INFO
)
3320 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3321 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3328 set_current_state(TASK_RUNNING
);
3329 remove_wait_queue(&port
->open_wait
, &wait
);
3331 /* FIXME: Racy on hangup during close wait */
3332 if (!tty_hung_up_p(filp
))
3334 port
->blocked_open
--;
3336 if (debug_level
>= DEBUG_LEVEL_INFO
)
3337 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3338 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3341 tty_port_set_active(port
, 1);
3345 } /* end of block_til_ready() */
3347 static int mgsl_install(struct tty_driver
*driver
, struct tty_struct
*tty
)
3349 struct mgsl_struct
*info
;
3350 int line
= tty
->index
;
3352 /* verify range of specified line number */
3353 if (line
>= mgsl_device_count
) {
3354 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3355 __FILE__
, __LINE__
, line
);
3359 /* find the info structure for the specified line */
3360 info
= mgsl_device_list
;
3361 while (info
&& info
->line
!= line
)
3362 info
= info
->next_device
;
3363 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3365 tty
->driver_data
= info
;
3367 return tty_port_install(&info
->port
, driver
, tty
);
3372 * Called when a port is opened. Init and enable port.
3373 * Perform serial-specific initialization for the tty structure.
3375 * Arguments: tty pointer to tty info structure
3376 * filp associated file pointer
3378 * Return Value: 0 if success, otherwise error code
3380 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3382 struct mgsl_struct
*info
= tty
->driver_data
;
3383 unsigned long flags
;
3386 info
->port
.tty
= tty
;
3388 if (debug_level
>= DEBUG_LEVEL_INFO
)
3389 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3390 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3392 info
->port
.low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3394 spin_lock_irqsave(&info
->netlock
, flags
);
3395 if (info
->netcount
) {
3397 spin_unlock_irqrestore(&info
->netlock
, flags
);
3401 spin_unlock_irqrestore(&info
->netlock
, flags
);
3403 if (info
->port
.count
== 1) {
3404 /* 1st open on this device, init hardware */
3405 retval
= startup(info
);
3410 retval
= block_til_ready(tty
, filp
, info
);
3412 if (debug_level
>= DEBUG_LEVEL_INFO
)
3413 printk("%s(%d):block_til_ready(%s) returned %d\n",
3414 __FILE__
,__LINE__
, info
->device_name
, retval
);
3418 if (debug_level
>= DEBUG_LEVEL_INFO
)
3419 printk("%s(%d):mgsl_open(%s) success\n",
3420 __FILE__
,__LINE__
, info
->device_name
);
3425 if (tty
->count
== 1)
3426 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3427 if(info
->port
.count
)
3433 } /* end of mgsl_open() */
3436 * /proc fs routines....
3439 static inline void line_info(struct seq_file
*m
, struct mgsl_struct
*info
)
3442 unsigned long flags
;
3444 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3445 seq_printf(m
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3446 info
->device_name
, info
->io_base
, info
->irq_level
,
3447 info
->phys_memory_base
, info
->phys_lcr_base
);
3449 seq_printf(m
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3450 info
->device_name
, info
->io_base
,
3451 info
->irq_level
, info
->dma_level
);
3454 /* output current serial signal states */
3455 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3456 usc_get_serial_signals(info
);
3457 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3461 if (info
->serial_signals
& SerialSignal_RTS
)
3462 strcat(stat_buf
, "|RTS");
3463 if (info
->serial_signals
& SerialSignal_CTS
)
3464 strcat(stat_buf
, "|CTS");
3465 if (info
->serial_signals
& SerialSignal_DTR
)
3466 strcat(stat_buf
, "|DTR");
3467 if (info
->serial_signals
& SerialSignal_DSR
)
3468 strcat(stat_buf
, "|DSR");
3469 if (info
->serial_signals
& SerialSignal_DCD
)
3470 strcat(stat_buf
, "|CD");
3471 if (info
->serial_signals
& SerialSignal_RI
)
3472 strcat(stat_buf
, "|RI");
3474 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3475 info
->params
.mode
== MGSL_MODE_RAW
) {
3476 seq_printf(m
, " HDLC txok:%d rxok:%d",
3477 info
->icount
.txok
, info
->icount
.rxok
);
3478 if (info
->icount
.txunder
)
3479 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
3480 if (info
->icount
.txabort
)
3481 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
3482 if (info
->icount
.rxshort
)
3483 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
3484 if (info
->icount
.rxlong
)
3485 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
3486 if (info
->icount
.rxover
)
3487 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
3488 if (info
->icount
.rxcrc
)
3489 seq_printf(m
, " rxcrc:%d", info
->icount
.rxcrc
);
3491 seq_printf(m
, " ASYNC tx:%d rx:%d",
3492 info
->icount
.tx
, info
->icount
.rx
);
3493 if (info
->icount
.frame
)
3494 seq_printf(m
, " fe:%d", info
->icount
.frame
);
3495 if (info
->icount
.parity
)
3496 seq_printf(m
, " pe:%d", info
->icount
.parity
);
3497 if (info
->icount
.brk
)
3498 seq_printf(m
, " brk:%d", info
->icount
.brk
);
3499 if (info
->icount
.overrun
)
3500 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
3503 /* Append serial signal status to end */
3504 seq_printf(m
, " %s\n", stat_buf
+1);
3506 seq_printf(m
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3507 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3510 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3512 u16 Tcsr
= usc_InReg( info
, TCSR
);
3513 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3514 u16 Ticr
= usc_InReg( info
, TICR
);
3515 u16 Rscr
= usc_InReg( info
, RCSR
);
3516 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3517 u16 Ricr
= usc_InReg( info
, RICR
);
3518 u16 Icr
= usc_InReg( info
, ICR
);
3519 u16 Dccr
= usc_InReg( info
, DCCR
);
3520 u16 Tmr
= usc_InReg( info
, TMR
);
3521 u16 Tccr
= usc_InReg( info
, TCCR
);
3522 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3523 seq_printf(m
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3524 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3525 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3527 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3530 /* Called to print information about devices */
3531 static int mgsl_proc_show(struct seq_file
*m
, void *v
)
3533 struct mgsl_struct
*info
;
3535 seq_printf(m
, "synclink driver:%s\n", driver_version
);
3537 info
= mgsl_device_list
;
3540 info
= info
->next_device
;
3545 static int mgsl_proc_open(struct inode
*inode
, struct file
*file
)
3547 return single_open(file
, mgsl_proc_show
, NULL
);
3550 static const struct file_operations mgsl_proc_fops
= {
3551 .owner
= THIS_MODULE
,
3552 .open
= mgsl_proc_open
,
3554 .llseek
= seq_lseek
,
3555 .release
= single_release
,
3558 /* mgsl_allocate_dma_buffers()
3560 * Allocate and format DMA buffers (ISA adapter)
3561 * or format shared memory buffers (PCI adapter).
3563 * Arguments: info pointer to device instance data
3564 * Return Value: 0 if success, otherwise error
3566 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3568 unsigned short BuffersPerFrame
;
3570 info
->last_mem_alloc
= 0;
3572 /* Calculate the number of DMA buffers necessary to hold the */
3573 /* largest allowable frame size. Note: If the max frame size is */
3574 /* not an even multiple of the DMA buffer size then we need to */
3575 /* round the buffer count per frame up one. */
3577 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3578 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3581 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3583 * The PCI adapter has 256KBytes of shared memory to use.
3584 * This is 64 PAGE_SIZE buffers.
3586 * The first page is used for padding at this time so the
3587 * buffer list does not begin at offset 0 of the PCI
3588 * adapter's shared memory.
3590 * The 2nd page is used for the buffer list. A 4K buffer
3591 * list can hold 128 DMA_BUFFER structures at 32 bytes
3594 * This leaves 62 4K pages.
3596 * The next N pages are used for transmit frame(s). We
3597 * reserve enough 4K page blocks to hold the required
3598 * number of transmit dma buffers (num_tx_dma_buffers),
3599 * each of MaxFrameSize size.
3601 * Of the remaining pages (62-N), determine how many can
3602 * be used to receive full MaxFrameSize inbound frames
3604 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3605 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3607 /* Calculate the number of PAGE_SIZE buffers needed for */
3608 /* receive and transmit DMA buffers. */
3611 /* Calculate the number of DMA buffers necessary to */
3612 /* hold 7 max size receive frames and one max size transmit frame. */
3613 /* The receive buffer count is bumped by one so we avoid an */
3614 /* End of List condition if all receive buffers are used when */
3615 /* using linked list DMA buffers. */
3617 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3618 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3621 * limit total TxBuffers & RxBuffers to 62 4K total
3622 * (ala PCI Allocation)
3625 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3626 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3630 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3631 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3632 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3634 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3635 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3636 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3637 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3638 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3639 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3643 mgsl_reset_rx_dma_buffers( info
);
3644 mgsl_reset_tx_dma_buffers( info
);
3648 } /* end of mgsl_allocate_dma_buffers() */
3651 * mgsl_alloc_buffer_list_memory()
3653 * Allocate a common DMA buffer for use as the
3654 * receive and transmit buffer lists.
3656 * A buffer list is a set of buffer entries where each entry contains
3657 * a pointer to an actual buffer and a pointer to the next buffer entry
3658 * (plus some other info about the buffer).
3660 * The buffer entries for a list are built to form a circular list so
3661 * that when the entire list has been traversed you start back at the
3664 * This function allocates memory for just the buffer entries.
3665 * The links (pointer to next entry) are filled in with the physical
3666 * address of the next entry so the adapter can navigate the list
3667 * using bus master DMA. The pointers to the actual buffers are filled
3668 * out later when the actual buffers are allocated.
3670 * Arguments: info pointer to device instance data
3671 * Return Value: 0 if success, otherwise error
3673 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3677 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3678 /* PCI adapter uses shared memory. */
3679 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3680 info
->buffer_list_phys
= info
->last_mem_alloc
;
3681 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3683 /* ISA adapter uses system memory. */
3684 /* The buffer lists are allocated as a common buffer that both */
3685 /* the processor and adapter can access. This allows the driver to */
3686 /* inspect portions of the buffer while other portions are being */
3687 /* updated by the adapter using Bus Master DMA. */
3689 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3690 if (info
->buffer_list
== NULL
)
3692 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3695 /* We got the memory for the buffer entry lists. */
3696 /* Initialize the memory block to all zeros. */
3697 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3699 /* Save virtual address pointers to the receive and */
3700 /* transmit buffer lists. (Receive 1st). These pointers will */
3701 /* be used by the processor to access the lists. */
3702 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3703 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3704 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3707 * Build the links for the buffer entry lists such that
3708 * two circular lists are built. (Transmit and Receive).
3710 * Note: the links are physical addresses
3711 * which are read by the adapter to determine the next
3712 * buffer entry to use.
3715 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3716 /* calculate and store physical address of this buffer entry */
3717 info
->rx_buffer_list
[i
].phys_entry
=
3718 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3720 /* calculate and store physical address of */
3721 /* next entry in cirular list of entries */
3723 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3725 if ( i
< info
->rx_buffer_count
- 1 )
3726 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3729 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3730 /* calculate and store physical address of this buffer entry */
3731 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3732 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3734 /* calculate and store physical address of */
3735 /* next entry in cirular list of entries */
3737 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3738 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3740 if ( i
< info
->tx_buffer_count
- 1 )
3741 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3746 } /* end of mgsl_alloc_buffer_list_memory() */
3748 /* Free DMA buffers allocated for use as the
3749 * receive and transmit buffer lists.
3752 * The data transfer buffers associated with the buffer list
3753 * MUST be freed before freeing the buffer list itself because
3754 * the buffer list contains the information necessary to free
3755 * the individual buffers!
3757 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3759 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3760 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3762 info
->buffer_list
= NULL
;
3763 info
->rx_buffer_list
= NULL
;
3764 info
->tx_buffer_list
= NULL
;
3766 } /* end of mgsl_free_buffer_list_memory() */
3769 * mgsl_alloc_frame_memory()
3771 * Allocate the frame DMA buffers used by the specified buffer list.
3772 * Each DMA buffer will be one memory page in size. This is necessary
3773 * because memory can fragment enough that it may be impossible
3778 * info pointer to device instance data
3779 * BufferList pointer to list of buffer entries
3780 * Buffercount count of buffer entries in buffer list
3782 * Return Value: 0 if success, otherwise -ENOMEM
3784 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3789 /* Allocate page sized buffers for the receive buffer list */
3791 for ( i
= 0; i
< Buffercount
; i
++ ) {
3792 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3793 /* PCI adapter uses shared memory buffers. */
3794 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3795 phys_addr
= info
->last_mem_alloc
;
3796 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3798 /* ISA adapter uses system memory. */
3799 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3800 if (BufferList
[i
].virt_addr
== NULL
)
3802 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3804 BufferList
[i
].phys_addr
= phys_addr
;
3809 } /* end of mgsl_alloc_frame_memory() */
3812 * mgsl_free_frame_memory()
3814 * Free the buffers associated with
3815 * each buffer entry of a buffer list.
3819 * info pointer to device instance data
3820 * BufferList pointer to list of buffer entries
3821 * Buffercount count of buffer entries in buffer list
3823 * Return Value: None
3825 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3830 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3831 if ( BufferList
[i
].virt_addr
) {
3832 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3833 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3834 BufferList
[i
].virt_addr
= NULL
;
3839 } /* end of mgsl_free_frame_memory() */
3841 /* mgsl_free_dma_buffers()
3845 * Arguments: info pointer to device instance data
3846 * Return Value: None
3848 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3850 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3851 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3852 mgsl_free_buffer_list_memory( info
);
3854 } /* end of mgsl_free_dma_buffers() */
3858 * mgsl_alloc_intermediate_rxbuffer_memory()
3860 * Allocate a buffer large enough to hold max_frame_size. This buffer
3861 * is used to pass an assembled frame to the line discipline.
3865 * info pointer to device instance data
3867 * Return Value: 0 if success, otherwise -ENOMEM
3869 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3871 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3872 if ( info
->intermediate_rxbuffer
== NULL
)
3874 /* unused flag buffer to satisfy receive_buf calling interface */
3875 info
->flag_buf
= kzalloc(info
->max_frame_size
, GFP_KERNEL
);
3876 if (!info
->flag_buf
) {
3877 kfree(info
->intermediate_rxbuffer
);
3878 info
->intermediate_rxbuffer
= NULL
;
3883 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3886 * mgsl_free_intermediate_rxbuffer_memory()
3891 * info pointer to device instance data
3893 * Return Value: None
3895 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3897 kfree(info
->intermediate_rxbuffer
);
3898 info
->intermediate_rxbuffer
= NULL
;
3899 kfree(info
->flag_buf
);
3900 info
->flag_buf
= NULL
;
3902 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3905 * mgsl_alloc_intermediate_txbuffer_memory()
3907 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3908 * This buffer is used to load transmit frames into the adapter's dma transfer
3909 * buffers when there is sufficient space.
3913 * info pointer to device instance data
3915 * Return Value: 0 if success, otherwise -ENOMEM
3917 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3921 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3922 printk("%s %s(%d) allocating %d tx holding buffers\n",
3923 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3925 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3927 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3928 info
->tx_holding_buffers
[i
].buffer
=
3929 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3930 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3931 for (--i
; i
>= 0; i
--) {
3932 kfree(info
->tx_holding_buffers
[i
].buffer
);
3933 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3941 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3944 * mgsl_free_intermediate_txbuffer_memory()
3949 * info pointer to device instance data
3951 * Return Value: None
3953 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3957 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3958 kfree(info
->tx_holding_buffers
[i
].buffer
);
3959 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3962 info
->get_tx_holding_index
= 0;
3963 info
->put_tx_holding_index
= 0;
3964 info
->tx_holding_count
= 0;
3966 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3970 * load_next_tx_holding_buffer()
3972 * attempts to load the next buffered tx request into the
3977 * info pointer to device instance data
3979 * Return Value: true if next buffered tx request loaded
3980 * into adapter's tx dma buffer,
3983 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
3987 if ( info
->tx_holding_count
) {
3988 /* determine if we have enough tx dma buffers
3989 * to accommodate the next tx frame
3991 struct tx_holding_buffer
*ptx
=
3992 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
3993 int num_free
= num_free_tx_dma_buffers(info
);
3994 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
3995 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
3998 if (num_needed
<= num_free
) {
3999 info
->xmit_cnt
= ptx
->buffer_size
;
4000 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4002 --info
->tx_holding_count
;
4003 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4004 info
->get_tx_holding_index
=0;
4006 /* restart transmit timer */
4007 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4017 * save_tx_buffer_request()
4019 * attempt to store transmit frame request for later transmission
4023 * info pointer to device instance data
4024 * Buffer pointer to buffer containing frame to load
4025 * BufferSize size in bytes of frame in Buffer
4027 * Return Value: 1 if able to store, 0 otherwise
4029 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4031 struct tx_holding_buffer
*ptx
;
4033 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4034 return 0; /* all buffers in use */
4037 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4038 ptx
->buffer_size
= BufferSize
;
4039 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4041 ++info
->tx_holding_count
;
4042 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4043 info
->put_tx_holding_index
=0;
4048 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4050 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4051 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4052 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4055 info
->io_addr_requested
= true;
4057 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4058 info
->device_name
, info
) < 0 ) {
4059 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4060 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4063 info
->irq_requested
= true;
4065 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4066 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4067 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4068 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4071 info
->shared_mem_requested
= true;
4072 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4073 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4074 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4077 info
->lcr_mem_requested
= true;
4079 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4081 if (!info
->memory_base
) {
4082 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4083 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4087 if ( !mgsl_memory_test(info
) ) {
4088 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4089 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4093 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4095 if (!info
->lcr_base
) {
4096 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4097 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4100 info
->lcr_base
+= info
->lcr_offset
;
4103 /* claim DMA channel */
4105 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4106 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4107 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4108 mgsl_release_resources( info
);
4111 info
->dma_requested
= true;
4113 /* ISA adapter uses bus master DMA */
4114 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4115 enable_dma(info
->dma_level
);
4118 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4119 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4120 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4126 mgsl_release_resources(info
);
4129 } /* end of mgsl_claim_resources() */
4131 static void mgsl_release_resources(struct mgsl_struct
*info
)
4133 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4134 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4135 __FILE__
,__LINE__
,info
->device_name
);
4137 if ( info
->irq_requested
) {
4138 free_irq(info
->irq_level
, info
);
4139 info
->irq_requested
= false;
4141 if ( info
->dma_requested
) {
4142 disable_dma(info
->dma_level
);
4143 free_dma(info
->dma_level
);
4144 info
->dma_requested
= false;
4146 mgsl_free_dma_buffers(info
);
4147 mgsl_free_intermediate_rxbuffer_memory(info
);
4148 mgsl_free_intermediate_txbuffer_memory(info
);
4150 if ( info
->io_addr_requested
) {
4151 release_region(info
->io_base
,info
->io_addr_size
);
4152 info
->io_addr_requested
= false;
4154 if ( info
->shared_mem_requested
) {
4155 release_mem_region(info
->phys_memory_base
,0x40000);
4156 info
->shared_mem_requested
= false;
4158 if ( info
->lcr_mem_requested
) {
4159 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4160 info
->lcr_mem_requested
= false;
4162 if (info
->memory_base
){
4163 iounmap(info
->memory_base
);
4164 info
->memory_base
= NULL
;
4166 if (info
->lcr_base
){
4167 iounmap(info
->lcr_base
- info
->lcr_offset
);
4168 info
->lcr_base
= NULL
;
4171 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4172 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4173 __FILE__
,__LINE__
,info
->device_name
);
4175 } /* end of mgsl_release_resources() */
4177 /* mgsl_add_device()
4179 * Add the specified device instance data structure to the
4180 * global linked list of devices and increment the device count.
4182 * Arguments: info pointer to device instance data
4183 * Return Value: None
4185 static void mgsl_add_device( struct mgsl_struct
*info
)
4187 info
->next_device
= NULL
;
4188 info
->line
= mgsl_device_count
;
4189 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4191 if (info
->line
< MAX_TOTAL_DEVICES
) {
4192 if (maxframe
[info
->line
])
4193 info
->max_frame_size
= maxframe
[info
->line
];
4195 if (txdmabufs
[info
->line
]) {
4196 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4197 if (info
->num_tx_dma_buffers
< 1)
4198 info
->num_tx_dma_buffers
= 1;
4201 if (txholdbufs
[info
->line
]) {
4202 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4203 if (info
->num_tx_holding_buffers
< 1)
4204 info
->num_tx_holding_buffers
= 1;
4205 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4206 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4210 mgsl_device_count
++;
4212 if ( !mgsl_device_list
)
4213 mgsl_device_list
= info
;
4215 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4216 while( current_dev
->next_device
)
4217 current_dev
= current_dev
->next_device
;
4218 current_dev
->next_device
= info
;
4221 if ( info
->max_frame_size
< 4096 )
4222 info
->max_frame_size
= 4096;
4223 else if ( info
->max_frame_size
> 65535 )
4224 info
->max_frame_size
= 65535;
4226 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4227 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4228 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4229 info
->phys_memory_base
, info
->phys_lcr_base
,
4230 info
->max_frame_size
);
4232 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4233 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4234 info
->max_frame_size
);
4237 #if SYNCLINK_GENERIC_HDLC
4241 } /* end of mgsl_add_device() */
4243 static const struct tty_port_operations mgsl_port_ops
= {
4244 .carrier_raised
= carrier_raised
,
4249 /* mgsl_allocate_device()
4251 * Allocate and initialize a device instance structure
4254 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4256 static struct mgsl_struct
* mgsl_allocate_device(void)
4258 struct mgsl_struct
*info
;
4260 info
= kzalloc(sizeof(struct mgsl_struct
),
4264 printk("Error can't allocate device instance data\n");
4266 tty_port_init(&info
->port
);
4267 info
->port
.ops
= &mgsl_port_ops
;
4268 info
->magic
= MGSL_MAGIC
;
4269 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4270 info
->max_frame_size
= 4096;
4271 info
->port
.close_delay
= 5*HZ
/10;
4272 info
->port
.closing_wait
= 30*HZ
;
4273 init_waitqueue_head(&info
->status_event_wait_q
);
4274 init_waitqueue_head(&info
->event_wait_q
);
4275 spin_lock_init(&info
->irq_spinlock
);
4276 spin_lock_init(&info
->netlock
);
4277 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4278 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4279 info
->num_tx_dma_buffers
= 1;
4280 info
->num_tx_holding_buffers
= 0;
4285 } /* end of mgsl_allocate_device()*/
4287 static const struct tty_operations mgsl_ops
= {
4288 .install
= mgsl_install
,
4290 .close
= mgsl_close
,
4291 .write
= mgsl_write
,
4292 .put_char
= mgsl_put_char
,
4293 .flush_chars
= mgsl_flush_chars
,
4294 .write_room
= mgsl_write_room
,
4295 .chars_in_buffer
= mgsl_chars_in_buffer
,
4296 .flush_buffer
= mgsl_flush_buffer
,
4297 .ioctl
= mgsl_ioctl
,
4298 .throttle
= mgsl_throttle
,
4299 .unthrottle
= mgsl_unthrottle
,
4300 .send_xchar
= mgsl_send_xchar
,
4301 .break_ctl
= mgsl_break
,
4302 .wait_until_sent
= mgsl_wait_until_sent
,
4303 .set_termios
= mgsl_set_termios
,
4305 .start
= mgsl_start
,
4306 .hangup
= mgsl_hangup
,
4307 .tiocmget
= tiocmget
,
4308 .tiocmset
= tiocmset
,
4309 .get_icount
= msgl_get_icount
,
4310 .proc_fops
= &mgsl_proc_fops
,
4314 * perform tty device initialization
4316 static int mgsl_init_tty(void)
4320 serial_driver
= alloc_tty_driver(128);
4324 serial_driver
->driver_name
= "synclink";
4325 serial_driver
->name
= "ttySL";
4326 serial_driver
->major
= ttymajor
;
4327 serial_driver
->minor_start
= 64;
4328 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4329 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4330 serial_driver
->init_termios
= tty_std_termios
;
4331 serial_driver
->init_termios
.c_cflag
=
4332 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4333 serial_driver
->init_termios
.c_ispeed
= 9600;
4334 serial_driver
->init_termios
.c_ospeed
= 9600;
4335 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4336 tty_set_operations(serial_driver
, &mgsl_ops
);
4337 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4338 printk("%s(%d):Couldn't register serial driver\n",
4340 put_tty_driver(serial_driver
);
4341 serial_driver
= NULL
;
4345 printk("%s %s, tty major#%d\n",
4346 driver_name
, driver_version
,
4347 serial_driver
->major
);
4351 /* enumerate user specified ISA adapters
4353 static void mgsl_enum_isa_devices(void)
4355 struct mgsl_struct
*info
;
4358 /* Check for user specified ISA devices */
4360 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4361 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4362 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4363 io
[i
], irq
[i
], dma
[i
] );
4365 info
= mgsl_allocate_device();
4367 /* error allocating device instance data */
4368 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4369 printk( "can't allocate device instance data.\n");
4373 /* Copy user configuration info to device instance data */
4374 info
->io_base
= (unsigned int)io
[i
];
4375 info
->irq_level
= (unsigned int)irq
[i
];
4376 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4377 info
->dma_level
= (unsigned int)dma
[i
];
4378 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4379 info
->io_addr_size
= 16;
4380 info
->irq_flags
= 0;
4382 mgsl_add_device( info
);
4386 static void synclink_cleanup(void)
4389 struct mgsl_struct
*info
;
4390 struct mgsl_struct
*tmp
;
4392 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4394 if (serial_driver
) {
4395 rc
= tty_unregister_driver(serial_driver
);
4397 printk("%s(%d) failed to unregister tty driver err=%d\n",
4398 __FILE__
,__LINE__
,rc
);
4399 put_tty_driver(serial_driver
);
4402 info
= mgsl_device_list
;
4404 #if SYNCLINK_GENERIC_HDLC
4407 mgsl_release_resources(info
);
4409 info
= info
->next_device
;
4410 tty_port_destroy(&tmp
->port
);
4415 pci_unregister_driver(&synclink_pci_driver
);
4418 static int __init
synclink_init(void)
4422 if (break_on_load
) {
4423 mgsl_get_text_ptr();
4427 printk("%s %s\n", driver_name
, driver_version
);
4429 mgsl_enum_isa_devices();
4430 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4431 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4433 pci_registered
= true;
4435 if ((rc
= mgsl_init_tty()) < 0)
4445 static void __exit
synclink_exit(void)
4450 module_init(synclink_init
);
4451 module_exit(synclink_exit
);
4456 * Issue a USC Receive/Transmit command to the
4457 * Channel Command/Address Register (CCAR).
4461 * The command is encoded in the most significant 5 bits <15..11>
4462 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4463 * and Bits <6..0> must be written as zeros.
4467 * info pointer to device information structure
4468 * Cmd command mask (use symbolic macros)
4474 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4476 /* output command to CCAR in bits <15..11> */
4477 /* preserve bits <10..7>, bits <6..0> must be zero */
4479 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4481 /* Read to flush write to CCAR */
4482 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4483 inw( info
->io_base
+ CCAR
);
4485 } /* end of usc_RTCmd() */
4490 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4494 * info pointer to device information structure
4495 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4501 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4503 /* write command mask to DCAR */
4504 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4506 /* Read to flush write to DCAR */
4507 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4508 inw( info
->io_base
);
4510 } /* end of usc_DmaCmd() */
4515 * Write a 16-bit value to a USC DMA register
4519 * info pointer to device info structure
4520 * RegAddr register address (number) for write
4521 * RegValue 16-bit value to write to register
4528 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4530 /* Note: The DCAR is located at the adapter base address */
4531 /* Note: must preserve state of BIT8 in DCAR */
4533 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4534 outw( RegValue
, info
->io_base
);
4536 /* Read to flush write to DCAR */
4537 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4538 inw( info
->io_base
);
4540 } /* end of usc_OutDmaReg() */
4545 * Read a 16-bit value from a DMA register
4549 * info pointer to device info structure
4550 * RegAddr register address (number) to read from
4554 * The 16-bit value read from register
4557 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4559 /* Note: The DCAR is located at the adapter base address */
4560 /* Note: must preserve state of BIT8 in DCAR */
4562 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4563 return inw( info
->io_base
);
4565 } /* end of usc_InDmaReg() */
4571 * Write a 16-bit value to a USC serial channel register
4575 * info pointer to device info structure
4576 * RegAddr register address (number) to write to
4577 * RegValue 16-bit value to write to register
4584 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4586 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4587 outw( RegValue
, info
->io_base
+ CCAR
);
4589 /* Read to flush write to CCAR */
4590 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4591 inw( info
->io_base
+ CCAR
);
4593 } /* end of usc_OutReg() */
4598 * Reads a 16-bit value from a USC serial channel register
4602 * info pointer to device extension
4603 * RegAddr register address (number) to read from
4607 * 16-bit value read from register
4609 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4611 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4612 return inw( info
->io_base
+ CCAR
);
4614 } /* end of usc_InReg() */
4616 /* usc_set_sdlc_mode()
4618 * Set up the adapter for SDLC DMA communications.
4620 * Arguments: info pointer to device instance data
4621 * Return Value: NONE
4623 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4629 * determine if the IUSC on the adapter is pre-SL1660. If
4630 * not, take advantage of the UnderWait feature of more
4631 * modern chips. If an underrun occurs and this bit is set,
4632 * the transmitter will idle the programmed idle pattern
4633 * until the driver has time to service the underrun. Otherwise,
4634 * the dma controller may get the cycles previously requested
4635 * and begin transmitting queued tx data.
4637 usc_OutReg(info
,TMCR
,0x1f);
4638 RegValue
=usc_InReg(info
,TMDR
);
4639 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4641 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4644 ** Channel Mode Register (CMR)
4646 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4647 ** <13> 0 0 = Transmit Disabled (initially)
4648 ** <12> 0 1 = Consecutive Idles share common 0
4649 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4650 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4651 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4653 ** 1000 1110 0000 0110 = 0x8e06
4657 /*--------------------------------------------------
4658 * ignore user options for UnderRun Actions and
4660 *--------------------------------------------------*/
4664 /* Channel mode Register (CMR)
4666 * <15..14> 00 Tx Sub modes, Underrun Action
4667 * <13> 0 1 = Send Preamble before opening flag
4668 * <12> 0 1 = Consecutive Idles share common 0
4669 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4670 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4671 * <3..0> 0110 Receiver mode = HDLC/SDLC
4673 * 0000 0110 0000 0110 = 0x0606
4675 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4676 RegValue
= 0x0001; /* Set Receive mode = external sync */
4678 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4679 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4683 * CMR <15> 0 Don't send CRC on Tx Underrun
4684 * CMR <14> x undefined
4685 * CMR <13> 0 Send preamble before openning sync
4686 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4689 * CMR <11-8) 0100 MonoSync
4691 * 0x00 0100 xxxx xxxx 04xx
4699 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4701 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4703 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4704 RegValue
|= BIT15
| BIT14
;
4707 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4711 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4712 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4715 if ( info
->params
.addr_filter
!= 0xff )
4717 /* set up receive address filtering */
4718 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4722 usc_OutReg( info
, CMR
, RegValue
);
4723 info
->cmr_value
= RegValue
;
4725 /* Receiver mode Register (RMR)
4727 * <15..13> 000 encoding
4728 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4729 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4730 * <9> 0 1 = Include Receive chars in CRC
4731 * <8> 1 1 = Use Abort/PE bit as abort indicator
4732 * <7..6> 00 Even parity
4733 * <5> 0 parity disabled
4734 * <4..2> 000 Receive Char Length = 8 bits
4735 * <1..0> 00 Disable Receiver
4737 * 0000 0101 0000 0000 = 0x0500
4742 switch ( info
->params
.encoding
) {
4743 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4744 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4745 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
| BIT13
; break;
4746 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4747 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
| BIT13
; break;
4748 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
; break;
4749 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
| BIT13
; break;
4752 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4754 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4755 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4757 usc_OutReg( info
, RMR
, RegValue
);
4759 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4760 /* When an opening flag of an SDLC frame is recognized the */
4761 /* Receive Character count (RCC) is loaded with the value in */
4762 /* RCLR. The RCC is decremented for each received byte. The */
4763 /* value of RCC is stored after the closing flag of the frame */
4764 /* allowing the frame size to be computed. */
4766 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4768 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4770 /* Receive Interrupt Control Register (RICR)
4772 * <15..8> ? RxFIFO DMA Request Level
4773 * <7> 0 Exited Hunt IA (Interrupt Arm)
4774 * <6> 0 Idle Received IA
4775 * <5> 0 Break/Abort IA
4777 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4779 * <1> 1 Rx Overrun IA
4780 * <0> 0 Select TC0 value for readback
4782 * 0000 0000 0000 1000 = 0x000a
4785 /* Carry over the Exit Hunt and Idle Received bits */
4786 /* in case they have been armed by usc_ArmEvents. */
4788 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4790 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4791 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4793 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4795 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4797 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4798 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4800 /* Transmit mode Register (TMR)
4802 * <15..13> 000 encoding
4803 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4804 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4805 * <9> 0 1 = Tx CRC Enabled
4806 * <8> 0 1 = Append CRC to end of transmit frame
4807 * <7..6> 00 Transmit parity Even
4808 * <5> 0 Transmit parity Disabled
4809 * <4..2> 000 Tx Char Length = 8 bits
4810 * <1..0> 00 Disable Transmitter
4812 * 0000 0100 0000 0000 = 0x0400
4817 switch ( info
->params
.encoding
) {
4818 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4819 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4820 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
| BIT13
; break;
4821 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4822 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
| BIT13
; break;
4823 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
; break;
4824 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
| BIT13
; break;
4827 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4828 RegValue
|= BIT9
| BIT8
;
4829 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4830 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4832 usc_OutReg( info
, TMR
, RegValue
);
4834 usc_set_txidle( info
);
4837 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4839 /* Transmit Interrupt Control Register (TICR)
4841 * <15..8> ? Transmit FIFO DMA Level
4842 * <7> 0 Present IA (Interrupt Arm)
4843 * <6> 0 Idle Sent IA
4844 * <5> 1 Abort Sent IA
4845 * <4> 1 EOF/EOM Sent IA
4847 * <2> 1 1 = Wait for SW Trigger to Start Frame
4848 * <1> 1 Tx Underrun IA
4849 * <0> 0 TC0 constant on read back
4851 * 0000 0000 0011 0110 = 0x0036
4854 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4855 usc_OutReg( info
, TICR
, 0x0736 );
4857 usc_OutReg( info
, TICR
, 0x1436 );
4859 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4860 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4863 ** Transmit Command/Status Register (TCSR)
4865 ** <15..12> 0000 TCmd
4866 ** <11> 0/1 UnderWait
4867 ** <10..08> 000 TxIdle
4871 ** <4> x EOF/EOM Sent
4877 ** 0000 0000 0000 0000 = 0x0000
4879 info
->tcsr_value
= 0;
4882 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4884 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4886 /* Clock mode Control Register (CMCR)
4888 * <15..14> 00 counter 1 Source = Disabled
4889 * <13..12> 00 counter 0 Source = Disabled
4890 * <11..10> 11 BRG1 Input is TxC Pin
4891 * <9..8> 11 BRG0 Input is TxC Pin
4892 * <7..6> 01 DPLL Input is BRG1 Output
4893 * <5..3> XXX TxCLK comes from Port 0
4894 * <2..0> XXX RxCLK comes from Port 1
4896 * 0000 1111 0111 0111 = 0x0f77
4901 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4902 RegValue
|= 0x0003; /* RxCLK from DPLL */
4903 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4904 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4905 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4906 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4908 RegValue
|= 0x0007; /* RxCLK from Port1 */
4910 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4911 RegValue
|= 0x0018; /* TxCLK from DPLL */
4912 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4913 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4914 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4915 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4917 RegValue
|= 0x0030; /* TxCLK from Port0 */
4919 usc_OutReg( info
, CMCR
, RegValue
);
4922 /* Hardware Configuration Register (HCR)
4924 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4925 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4926 * <12> 0 CVOK:0=report code violation in biphase
4927 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4928 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4929 * <7..6> 00 reserved
4930 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4932 * <3..2> 00 reserved
4933 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4939 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
| HDLC_FLAG_TXC_DPLL
) ) {
4944 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4945 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4947 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4948 XtalSpeed
= 11059200;
4950 XtalSpeed
= 14745600;
4952 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4956 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4963 /* Tc = (Xtal/Speed) - 1 */
4964 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4965 /* then rounding up gives a more precise time constant. Instead */
4966 /* of rounding up and then subtracting 1 we just don't subtract */
4967 /* the one in this case. */
4969 /*--------------------------------------------------
4970 * ejz: for DPLL mode, application should use the
4971 * same clock speed as the partner system, even
4972 * though clocking is derived from the input RxData.
4973 * In case the user uses a 0 for the clock speed,
4974 * default to 0xffffffff and don't try to divide by
4976 *--------------------------------------------------*/
4977 if ( info
->params
.clock_speed
)
4979 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
4980 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
4981 / info
->params
.clock_speed
) )
4988 /* Write 16-bit Time Constant for BRG1 */
4989 usc_OutReg( info
, TC1R
, Tc
);
4991 RegValue
|= BIT4
; /* enable BRG1 */
4993 switch ( info
->params
.encoding
) {
4994 case HDLC_ENCODING_NRZ
:
4995 case HDLC_ENCODING_NRZB
:
4996 case HDLC_ENCODING_NRZI_MARK
:
4997 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
4998 case HDLC_ENCODING_BIPHASE_MARK
:
4999 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5000 case HDLC_ENCODING_BIPHASE_LEVEL
:
5001 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
| BIT8
; break;
5005 usc_OutReg( info
, HCR
, RegValue
);
5008 /* Channel Control/status Register (CCSR)
5010 * <15> X RCC FIFO Overflow status (RO)
5011 * <14> X RCC FIFO Not Empty status (RO)
5012 * <13> 0 1 = Clear RCC FIFO (WO)
5013 * <12> X DPLL Sync (RW)
5014 * <11> X DPLL 2 Missed Clocks status (RO)
5015 * <10> X DPLL 1 Missed Clock status (RO)
5016 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5017 * <7> X SDLC Loop On status (RO)
5018 * <6> X SDLC Loop Send status (RO)
5019 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5020 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5021 * <1..0> 00 reserved
5023 * 0000 0000 0010 0000 = 0x0020
5026 usc_OutReg( info
, CCSR
, 0x1020 );
5029 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5030 usc_OutReg( info
, SICR
,
5031 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5035 /* enable Master Interrupt Enable bit (MIE) */
5036 usc_EnableMasterIrqBit( info
);
5038 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
| RECEIVE_DATA
|
5039 TRANSMIT_STATUS
| TRANSMIT_DATA
| MISC
);
5041 /* arm RCC underflow interrupt */
5042 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5043 usc_EnableInterrupts(info
, MISC
);
5046 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5047 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5048 info
->mbre_bit
= BIT8
;
5049 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5051 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5052 /* Enable DMAEN (Port 7, Bit 14) */
5053 /* This connects the DMA request signal to the ISA bus */
5054 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5057 /* DMA Control Register (DCR)
5059 * <15..14> 10 Priority mode = Alternating Tx/Rx
5060 * 01 Rx has priority
5061 * 00 Tx has priority
5063 * <13> 1 Enable Priority Preempt per DCR<15..14>
5064 * (WARNING DCR<11..10> must be 00 when this is 1)
5065 * 0 Choose activate channel per DCR<11..10>
5067 * <12> 0 Little Endian for Array/List
5068 * <11..10> 00 Both Channels can use each bus grant
5069 * <9..6> 0000 reserved
5070 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5071 * <4> 0 1 = drive D/C and S/D pins
5072 * <3> 1 1 = Add one wait state to all DMA cycles.
5073 * <2> 0 1 = Strobe /UAS on every transfer.
5074 * <1..0> 11 Addr incrementing only affects LS24 bits
5076 * 0110 0000 0000 1011 = 0x600b
5079 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5080 /* PCI adapter does not need DMA wait state */
5081 usc_OutDmaReg( info
, DCR
, 0xa00b );
5084 usc_OutDmaReg( info
, DCR
, 0x800b );
5087 /* Receive DMA mode Register (RDMR)
5089 * <15..14> 11 DMA mode = Linked List Buffer mode
5090 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5091 * <12> 1 Clear count of List Entry after fetching
5092 * <11..10> 00 Address mode = Increment
5093 * <9> 1 Terminate Buffer on RxBound
5094 * <8> 0 Bus Width = 16bits
5095 * <7..0> ? status Bits (write as 0s)
5097 * 1111 0010 0000 0000 = 0xf200
5100 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5103 /* Transmit DMA mode Register (TDMR)
5105 * <15..14> 11 DMA mode = Linked List Buffer mode
5106 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5107 * <12> 1 Clear count of List Entry after fetching
5108 * <11..10> 00 Address mode = Increment
5109 * <9> 1 Terminate Buffer on end of frame
5110 * <8> 0 Bus Width = 16bits
5111 * <7..0> ? status Bits (Read Only so write as 0)
5113 * 1111 0010 0000 0000 = 0xf200
5116 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5119 /* DMA Interrupt Control Register (DICR)
5121 * <15> 1 DMA Interrupt Enable
5122 * <14> 0 1 = Disable IEO from USC
5123 * <13> 0 1 = Don't provide vector during IntAck
5124 * <12> 1 1 = Include status in Vector
5125 * <10..2> 0 reserved, Must be 0s
5126 * <1> 0 1 = Rx DMA Interrupt Enabled
5127 * <0> 0 1 = Tx DMA Interrupt Enabled
5129 * 1001 0000 0000 0000 = 0x9000
5132 usc_OutDmaReg( info
, DICR
, 0x9000 );
5134 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5135 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5136 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5138 /* Channel Control Register (CCR)
5140 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5141 * <13> 0 Trigger Tx on SW Command Disabled
5142 * <12> 0 Flag Preamble Disabled
5143 * <11..10> 00 Preamble Length
5144 * <9..8> 00 Preamble Pattern
5145 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5146 * <5> 0 Trigger Rx on SW Command Disabled
5149 * 1000 0000 1000 0000 = 0x8080
5154 switch ( info
->params
.preamble_length
) {
5155 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5156 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5157 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
| BIT10
; break;
5160 switch ( info
->params
.preamble
) {
5161 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
| BIT12
; break;
5162 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5163 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5164 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
| BIT8
; break;
5167 usc_OutReg( info
, CCR
, RegValue
);
5171 * Burst/Dwell Control Register
5173 * <15..8> 0x20 Maximum number of transfers per bus grant
5174 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5177 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5178 /* don't limit bus occupancy on PCI adapter */
5179 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5182 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5184 usc_stop_transmitter(info
);
5185 usc_stop_receiver(info
);
5187 } /* end of usc_set_sdlc_mode() */
5189 /* usc_enable_loopback()
5191 * Set the 16C32 for internal loopback mode.
5192 * The TxCLK and RxCLK signals are generated from the BRG0 and
5193 * the TxD is looped back to the RxD internally.
5195 * Arguments: info pointer to device instance data
5196 * enable 1 = enable loopback, 0 = disable
5197 * Return Value: None
5199 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5202 /* blank external TXD output */
5203 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
| BIT6
));
5205 /* Clock mode Control Register (CMCR)
5207 * <15..14> 00 counter 1 Disabled
5208 * <13..12> 00 counter 0 Disabled
5209 * <11..10> 11 BRG1 Input is TxC Pin
5210 * <9..8> 11 BRG0 Input is TxC Pin
5211 * <7..6> 01 DPLL Input is BRG1 Output
5212 * <5..3> 100 TxCLK comes from BRG0
5213 * <2..0> 100 RxCLK comes from BRG0
5215 * 0000 1111 0110 0100 = 0x0f64
5218 usc_OutReg( info
, CMCR
, 0x0f64 );
5220 /* Write 16-bit Time Constant for BRG0 */
5221 /* use clock speed if available, otherwise use 8 for diagnostics */
5222 if (info
->params
.clock_speed
) {
5223 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5224 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5226 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5228 usc_OutReg(info
, TC0R
, (u16
)8);
5230 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5231 mode = Continuous Set Bit 0 to enable BRG0. */
5232 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5234 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5235 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5237 /* set Internal Data loopback mode */
5238 info
->loopback_bits
= 0x300;
5239 outw( 0x0300, info
->io_base
+ CCAR
);
5241 /* enable external TXD output */
5242 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
| BIT6
));
5244 /* clear Internal Data loopback mode */
5245 info
->loopback_bits
= 0;
5246 outw( 0,info
->io_base
+ CCAR
);
5249 } /* end of usc_enable_loopback() */
5251 /* usc_enable_aux_clock()
5253 * Enabled the AUX clock output at the specified frequency.
5257 * info pointer to device extension
5258 * data_rate data rate of clock in bits per second
5259 * A data rate of 0 disables the AUX clock.
5261 * Return Value: None
5263 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5269 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5270 XtalSpeed
= 11059200;
5272 XtalSpeed
= 14745600;
5275 /* Tc = (Xtal/Speed) - 1 */
5276 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5277 /* then rounding up gives a more precise time constant. Instead */
5278 /* of rounding up and then subtracting 1 we just don't subtract */
5279 /* the one in this case. */
5282 Tc
= (u16
)(XtalSpeed
/data_rate
);
5283 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5286 /* Write 16-bit Time Constant for BRG0 */
5287 usc_OutReg( info
, TC0R
, Tc
);
5290 * Hardware Configuration Register (HCR)
5291 * Clear Bit 1, BRG0 mode = Continuous
5292 * Set Bit 0 to enable BRG0.
5295 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5297 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5298 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5300 /* data rate == 0 so turn off BRG0 */
5301 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5304 } /* end of usc_enable_aux_clock() */
5308 * usc_process_rxoverrun_sync()
5310 * This function processes a receive overrun by resetting the
5311 * receive DMA buffers and issuing a Purge Rx FIFO command
5312 * to allow the receiver to continue receiving.
5316 * info pointer to device extension
5318 * Return Value: None
5320 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5324 int frame_start_index
;
5325 bool start_of_frame_found
= false;
5326 bool end_of_frame_found
= false;
5327 bool reprogram_dma
= false;
5329 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5332 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5333 usc_RCmd( info
, RCmd_EnterHuntmode
);
5334 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5336 /* CurrentRxBuffer points to the 1st buffer of the next */
5337 /* possibly available receive frame. */
5339 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5341 /* Search for an unfinished string of buffers. This means */
5342 /* that a receive frame started (at least one buffer with */
5343 /* count set to zero) but there is no terminiting buffer */
5344 /* (status set to non-zero). */
5346 while( !buffer_list
[end_index
].count
)
5348 /* Count field has been reset to zero by 16C32. */
5349 /* This buffer is currently in use. */
5351 if ( !start_of_frame_found
)
5353 start_of_frame_found
= true;
5354 frame_start_index
= end_index
;
5355 end_of_frame_found
= false;
5358 if ( buffer_list
[end_index
].status
)
5360 /* Status field has been set by 16C32. */
5361 /* This is the last buffer of a received frame. */
5363 /* We want to leave the buffers for this frame intact. */
5364 /* Move on to next possible frame. */
5366 start_of_frame_found
= false;
5367 end_of_frame_found
= true;
5370 /* advance to next buffer entry in linked list */
5372 if ( end_index
== info
->rx_buffer_count
)
5375 if ( start_index
== end_index
)
5377 /* The entire list has been searched with all Counts == 0 and */
5378 /* all Status == 0. The receive buffers are */
5379 /* completely screwed, reset all receive buffers! */
5380 mgsl_reset_rx_dma_buffers( info
);
5381 frame_start_index
= 0;
5382 start_of_frame_found
= false;
5383 reprogram_dma
= true;
5388 if ( start_of_frame_found
&& !end_of_frame_found
)
5390 /* There is an unfinished string of receive DMA buffers */
5391 /* as a result of the receiver overrun. */
5393 /* Reset the buffers for the unfinished frame */
5394 /* and reprogram the receive DMA controller to start */
5395 /* at the 1st buffer of unfinished frame. */
5397 start_index
= frame_start_index
;
5401 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5403 /* Adjust index for wrap around. */
5404 if ( start_index
== info
->rx_buffer_count
)
5407 } while( start_index
!= end_index
);
5409 reprogram_dma
= true;
5412 if ( reprogram_dma
)
5414 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5415 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5416 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5418 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5420 /* This empties the receive FIFO and loads the RCC with RCLR */
5421 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5423 /* program 16C32 with physical address of 1st DMA buffer entry */
5424 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5425 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5426 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5428 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5429 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5430 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5432 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5433 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5435 usc_OutDmaReg( info
, RDIAR
, BIT3
| BIT2
);
5436 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5437 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5438 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5439 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5441 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5445 /* This empties the receive FIFO and loads the RCC with RCLR */
5446 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5447 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5450 } /* end of usc_process_rxoverrun_sync() */
5452 /* usc_stop_receiver()
5454 * Disable USC receiver
5456 * Arguments: info pointer to device instance data
5457 * Return Value: None
5459 static void usc_stop_receiver( struct mgsl_struct
*info
)
5461 if (debug_level
>= DEBUG_LEVEL_ISR
)
5462 printk("%s(%d):usc_stop_receiver(%s)\n",
5463 __FILE__
,__LINE__
, info
->device_name
);
5465 /* Disable receive DMA channel. */
5466 /* This also disables receive DMA channel interrupts */
5467 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5469 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5470 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5471 usc_DisableInterrupts( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5473 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5475 /* This empties the receive FIFO and loads the RCC with RCLR */
5476 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5477 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5479 info
->rx_enabled
= false;
5480 info
->rx_overflow
= false;
5481 info
->rx_rcc_underrun
= false;
5483 } /* end of stop_receiver() */
5485 /* usc_start_receiver()
5487 * Enable the USC receiver
5489 * Arguments: info pointer to device instance data
5490 * Return Value: None
5492 static void usc_start_receiver( struct mgsl_struct
*info
)
5496 if (debug_level
>= DEBUG_LEVEL_ISR
)
5497 printk("%s(%d):usc_start_receiver(%s)\n",
5498 __FILE__
,__LINE__
, info
->device_name
);
5500 mgsl_reset_rx_dma_buffers( info
);
5501 usc_stop_receiver( info
);
5503 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5504 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5506 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5507 info
->params
.mode
== MGSL_MODE_RAW
) {
5508 /* DMA mode Transfers */
5509 /* Program the DMA controller. */
5510 /* Enable the DMA controller end of buffer interrupt. */
5512 /* program 16C32 with physical address of 1st DMA buffer entry */
5513 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5514 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5515 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5517 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5518 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5519 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5521 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5522 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5524 usc_OutDmaReg( info
, RDIAR
, BIT3
| BIT2
);
5525 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5526 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5527 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5528 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5530 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5532 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5533 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5534 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5536 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5537 usc_RCmd( info
, RCmd_EnterHuntmode
);
5539 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5542 usc_OutReg( info
, CCSR
, 0x1020 );
5544 info
->rx_enabled
= true;
5546 } /* end of usc_start_receiver() */
5548 /* usc_start_transmitter()
5550 * Enable the USC transmitter and send a transmit frame if
5551 * one is loaded in the DMA buffers.
5553 * Arguments: info pointer to device instance data
5554 * Return Value: None
5556 static void usc_start_transmitter( struct mgsl_struct
*info
)
5559 unsigned int FrameSize
;
5561 if (debug_level
>= DEBUG_LEVEL_ISR
)
5562 printk("%s(%d):usc_start_transmitter(%s)\n",
5563 __FILE__
,__LINE__
, info
->device_name
);
5565 if ( info
->xmit_cnt
) {
5567 /* If auto RTS enabled and RTS is inactive, then assert */
5568 /* RTS and set a flag indicating that the driver should */
5569 /* negate RTS when the transmission completes. */
5571 info
->drop_rts_on_tx_done
= false;
5573 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5574 usc_get_serial_signals( info
);
5575 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5576 info
->serial_signals
|= SerialSignal_RTS
;
5577 usc_set_serial_signals( info
);
5578 info
->drop_rts_on_tx_done
= true;
5583 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5584 if ( !info
->tx_active
) {
5585 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5586 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5587 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5588 usc_load_txfifo(info
);
5591 /* Disable transmit DMA controller while programming. */
5592 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5594 /* Transmit DMA buffer is loaded, so program USC */
5595 /* to send the frame contained in the buffers. */
5597 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5599 /* if operating in Raw sync mode, reset the rcc component
5600 * of the tx dma buffer entry, otherwise, the serial controller
5601 * will send a closing sync char after this count.
5603 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5604 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5606 /* Program the Transmit Character Length Register (TCLR) */
5607 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5608 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5610 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5612 /* Program the address of the 1st DMA Buffer Entry in linked list */
5613 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5614 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5615 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5617 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5618 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5619 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5621 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5622 info
->num_tx_dma_buffers
> 1 ) {
5623 /* When running external sync mode, attempt to 'stream' transmit */
5624 /* by filling tx dma buffers as they become available. To do this */
5625 /* we need to enable Tx DMA EOB Status interrupts : */
5627 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5628 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5630 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5631 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5634 /* Initialize Transmit DMA Channel */
5635 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5637 usc_TCmd( info
, TCmd_SendFrame
);
5639 mod_timer(&info
->tx_timer
, jiffies
+
5640 msecs_to_jiffies(5000));
5642 info
->tx_active
= true;
5645 if ( !info
->tx_enabled
) {
5646 info
->tx_enabled
= true;
5647 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5648 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5650 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5653 } /* end of usc_start_transmitter() */
5655 /* usc_stop_transmitter()
5657 * Stops the transmitter and DMA
5659 * Arguments: info pointer to device isntance data
5660 * Return Value: None
5662 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5664 if (debug_level
>= DEBUG_LEVEL_ISR
)
5665 printk("%s(%d):usc_stop_transmitter(%s)\n",
5666 __FILE__
,__LINE__
, info
->device_name
);
5668 del_timer(&info
->tx_timer
);
5670 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5671 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5672 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5674 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5675 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5676 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5678 info
->tx_enabled
= false;
5679 info
->tx_active
= false;
5681 } /* end of usc_stop_transmitter() */
5683 /* usc_load_txfifo()
5685 * Fill the transmit FIFO until the FIFO is full or
5686 * there is no more data to load.
5688 * Arguments: info pointer to device extension (instance data)
5689 * Return Value: None
5691 static void usc_load_txfifo( struct mgsl_struct
*info
)
5696 if ( !info
->xmit_cnt
&& !info
->x_char
)
5699 /* Select transmit FIFO status readback in TICR */
5700 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5702 /* load the Transmit FIFO until FIFOs full or all data sent */
5704 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5705 /* there is more space in the transmit FIFO and */
5706 /* there is more data in transmit buffer */
5708 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5709 /* write a 16-bit word from transmit buffer to 16C32 */
5711 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5712 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5713 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5714 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5716 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5718 info
->xmit_cnt
-= 2;
5719 info
->icount
.tx
+= 2;
5721 /* only 1 byte left to transmit or 1 FIFO slot left */
5723 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5724 info
->io_base
+ CCAR
);
5727 /* transmit pending high priority char */
5728 outw( info
->x_char
,info
->io_base
+ CCAR
);
5731 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5732 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5739 } /* end of usc_load_txfifo() */
5743 * Reset the adapter to a known state and prepare it for further use.
5745 * Arguments: info pointer to device instance data
5746 * Return Value: None
5748 static void usc_reset( struct mgsl_struct
*info
)
5750 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5754 /* Set BIT30 of Misc Control Register */
5755 /* (Local Control Register 0x50) to force reset of USC. */
5757 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5758 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5760 info
->misc_ctrl_value
|= BIT30
;
5761 *MiscCtrl
= info
->misc_ctrl_value
;
5764 * Force at least 170ns delay before clearing
5765 * reset bit. Each read from LCR takes at least
5766 * 30ns so 10 times for 300ns to be safe.
5769 readval
= *MiscCtrl
;
5771 info
->misc_ctrl_value
&= ~BIT30
;
5772 *MiscCtrl
= info
->misc_ctrl_value
;
5774 *LCR0BRDR
= BUS_DESCRIPTOR(
5775 1, // Write Strobe Hold (0-3)
5776 2, // Write Strobe Delay (0-3)
5777 2, // Read Strobe Delay (0-3)
5778 0, // NWDD (Write data-data) (0-3)
5779 4, // NWAD (Write Addr-data) (0-31)
5780 0, // NXDA (Read/Write Data-Addr) (0-3)
5781 0, // NRDD (Read Data-Data) (0-3)
5782 5 // NRAD (Read Addr-Data) (0-31)
5786 outb( 0,info
->io_base
+ 8 );
5790 info
->loopback_bits
= 0;
5791 info
->usc_idle_mode
= 0;
5794 * Program the Bus Configuration Register (BCR)
5796 * <15> 0 Don't use separate address
5797 * <14..6> 0 reserved
5798 * <5..4> 00 IAckmode = Default, don't care
5799 * <3> 1 Bus Request Totem Pole output
5800 * <2> 1 Use 16 Bit data bus
5801 * <1> 0 IRQ Totem Pole output
5802 * <0> 0 Don't Shift Right Addr
5804 * 0000 0000 0000 1100 = 0x000c
5806 * By writing to io_base + SDPIN the Wait/Ack pin is
5807 * programmed to work as a Wait pin.
5810 outw( 0x000c,info
->io_base
+ SDPIN
);
5813 outw( 0,info
->io_base
);
5814 outw( 0,info
->io_base
+ CCAR
);
5816 /* select little endian byte ordering */
5817 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5820 /* Port Control Register (PCR)
5822 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5823 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5824 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5825 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5826 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5827 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5828 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5829 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5831 * 1111 0000 1111 0101 = 0xf0f5
5834 usc_OutReg( info
, PCR
, 0xf0f5 );
5838 * Input/Output Control Register
5840 * <15..14> 00 CTS is active low input
5841 * <13..12> 00 DCD is active low input
5842 * <11..10> 00 TxREQ pin is input (DSR)
5843 * <9..8> 00 RxREQ pin is input (RI)
5844 * <7..6> 00 TxD is output (Transmit Data)
5845 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5846 * <2..0> 100 RxC is Output (drive with BRG0)
5848 * 0000 0000 0000 0100 = 0x0004
5851 usc_OutReg( info
, IOCR
, 0x0004 );
5853 } /* end of usc_reset() */
5855 /* usc_set_async_mode()
5857 * Program adapter for asynchronous communications.
5859 * Arguments: info pointer to device instance data
5860 * Return Value: None
5862 static void usc_set_async_mode( struct mgsl_struct
*info
)
5866 /* disable interrupts while programming USC */
5867 usc_DisableMasterIrqBit( info
);
5869 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5870 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5872 usc_loopback_frame( info
);
5874 /* Channel mode Register (CMR)
5876 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5877 * <13..12> 00 00 = 16X Clock
5878 * <11..8> 0000 Transmitter mode = Asynchronous
5879 * <7..6> 00 reserved?
5880 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5881 * <3..0> 0000 Receiver mode = Asynchronous
5883 * 0000 0000 0000 0000 = 0x0
5887 if ( info
->params
.stop_bits
!= 1 )
5889 usc_OutReg( info
, CMR
, RegValue
);
5892 /* Receiver mode Register (RMR)
5894 * <15..13> 000 encoding = None
5895 * <12..08> 00000 reserved (Sync Only)
5896 * <7..6> 00 Even parity
5897 * <5> 0 parity disabled
5898 * <4..2> 000 Receive Char Length = 8 bits
5899 * <1..0> 00 Disable Receiver
5901 * 0000 0000 0000 0000 = 0x0
5906 if ( info
->params
.data_bits
!= 8 )
5907 RegValue
|= BIT4
| BIT3
| BIT2
;
5909 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5911 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5915 usc_OutReg( info
, RMR
, RegValue
);
5918 /* Set IRQ trigger level */
5920 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5923 /* Receive Interrupt Control Register (RICR)
5925 * <15..8> ? RxFIFO IRQ Request Level
5927 * Note: For async mode the receive FIFO level must be set
5928 * to 0 to avoid the situation where the FIFO contains fewer bytes
5929 * than the trigger level and no more data is expected.
5931 * <7> 0 Exited Hunt IA (Interrupt Arm)
5932 * <6> 0 Idle Received IA
5933 * <5> 0 Break/Abort IA
5935 * <3> 0 Queued status reflects oldest byte in FIFO
5937 * <1> 0 Rx Overrun IA
5938 * <0> 0 Select TC0 value for readback
5940 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5943 usc_OutReg( info
, RICR
, 0x0000 );
5945 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5946 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5949 /* Transmit mode Register (TMR)
5951 * <15..13> 000 encoding = None
5952 * <12..08> 00000 reserved (Sync Only)
5953 * <7..6> 00 Transmit parity Even
5954 * <5> 0 Transmit parity Disabled
5955 * <4..2> 000 Tx Char Length = 8 bits
5956 * <1..0> 00 Disable Transmitter
5958 * 0000 0000 0000 0000 = 0x0
5963 if ( info
->params
.data_bits
!= 8 )
5964 RegValue
|= BIT4
| BIT3
| BIT2
;
5966 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5968 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5972 usc_OutReg( info
, TMR
, RegValue
);
5974 usc_set_txidle( info
);
5977 /* Set IRQ trigger level */
5979 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
5982 /* Transmit Interrupt Control Register (TICR)
5984 * <15..8> ? Transmit FIFO IRQ Level
5985 * <7> 0 Present IA (Interrupt Arm)
5986 * <6> 1 Idle Sent IA
5987 * <5> 0 Abort Sent IA
5988 * <4> 0 EOF/EOM Sent IA
5990 * <2> 0 1 = Wait for SW Trigger to Start Frame
5991 * <1> 0 Tx Underrun IA
5992 * <0> 0 TC0 constant on read back
5994 * 0000 0000 0100 0000 = 0x0040
5997 usc_OutReg( info
, TICR
, 0x1f40 );
5999 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6000 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6002 usc_enable_async_clock( info
, info
->params
.data_rate
);
6005 /* Channel Control/status Register (CCSR)
6007 * <15> X RCC FIFO Overflow status (RO)
6008 * <14> X RCC FIFO Not Empty status (RO)
6009 * <13> 0 1 = Clear RCC FIFO (WO)
6010 * <12> X DPLL in Sync status (RO)
6011 * <11> X DPLL 2 Missed Clocks status (RO)
6012 * <10> X DPLL 1 Missed Clock status (RO)
6013 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6014 * <7> X SDLC Loop On status (RO)
6015 * <6> X SDLC Loop Send status (RO)
6016 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6017 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6018 * <1..0> 00 reserved
6020 * 0000 0000 0010 0000 = 0x0020
6023 usc_OutReg( info
, CCSR
, 0x0020 );
6025 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6026 RECEIVE_DATA
+ RECEIVE_STATUS
);
6028 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6029 RECEIVE_DATA
+ RECEIVE_STATUS
);
6031 usc_EnableMasterIrqBit( info
);
6033 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6034 /* Enable INTEN (Port 6, Bit12) */
6035 /* This connects the IRQ request signal to the ISA bus */
6036 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6039 if (info
->params
.loopback
) {
6040 info
->loopback_bits
= 0x300;
6041 outw(0x0300, info
->io_base
+ CCAR
);
6044 } /* end of usc_set_async_mode() */
6046 /* usc_loopback_frame()
6048 * Loop back a small (2 byte) dummy SDLC frame.
6049 * Interrupts and DMA are NOT used. The purpose of this is to
6050 * clear any 'stale' status info left over from running in async mode.
6052 * The 16C32 shows the strange behaviour of marking the 1st
6053 * received SDLC frame with a CRC error even when there is no
6054 * CRC error. To get around this a small dummy from of 2 bytes
6055 * is looped back when switching from async to sync mode.
6057 * Arguments: info pointer to device instance data
6058 * Return Value: None
6060 static void usc_loopback_frame( struct mgsl_struct
*info
)
6063 unsigned long oldmode
= info
->params
.mode
;
6065 info
->params
.mode
= MGSL_MODE_HDLC
;
6067 usc_DisableMasterIrqBit( info
);
6069 usc_set_sdlc_mode( info
);
6070 usc_enable_loopback( info
, 1 );
6072 /* Write 16-bit Time Constant for BRG0 */
6073 usc_OutReg( info
, TC0R
, 0 );
6075 /* Channel Control Register (CCR)
6077 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6078 * <13> 0 Trigger Tx on SW Command Disabled
6079 * <12> 0 Flag Preamble Disabled
6080 * <11..10> 00 Preamble Length = 8-Bits
6081 * <9..8> 01 Preamble Pattern = flags
6082 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6083 * <5> 0 Trigger Rx on SW Command Disabled
6086 * 0000 0001 0000 0000 = 0x0100
6089 usc_OutReg( info
, CCR
, 0x0100 );
6091 /* SETUP RECEIVER */
6092 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6093 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6095 /* SETUP TRANSMITTER */
6096 /* Program the Transmit Character Length Register (TCLR) */
6097 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6098 usc_OutReg( info
, TCLR
, 2 );
6099 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6101 /* unlatch Tx status bits, and start transmit channel. */
6102 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6103 outw(0,info
->io_base
+ DATAREG
);
6105 /* ENABLE TRANSMITTER */
6106 usc_TCmd( info
, TCmd_SendFrame
);
6107 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6109 /* WAIT FOR RECEIVE COMPLETE */
6110 for (i
=0 ; i
<1000 ; i
++)
6111 if (usc_InReg( info
, RCSR
) & (BIT8
| BIT4
| BIT3
| BIT1
))
6114 /* clear Internal Data loopback mode */
6115 usc_enable_loopback(info
, 0);
6117 usc_EnableMasterIrqBit(info
);
6119 info
->params
.mode
= oldmode
;
6121 } /* end of usc_loopback_frame() */
6123 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6125 * Arguments: info pointer to adapter info structure
6126 * Return Value: None
6128 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6130 usc_loopback_frame( info
);
6131 usc_set_sdlc_mode( info
);
6133 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6134 /* Enable INTEN (Port 6, Bit12) */
6135 /* This connects the IRQ request signal to the ISA bus */
6136 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6139 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6141 if (info
->params
.loopback
)
6142 usc_enable_loopback(info
,1);
6144 } /* end of mgsl_set_sync_mode() */
6146 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6148 * Arguments: info pointer to device instance data
6149 * Return Value: None
6151 static void usc_set_txidle( struct mgsl_struct
*info
)
6153 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6155 /* Map API idle mode to USC register bits */
6157 switch( info
->idle_mode
){
6158 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6159 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6160 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6161 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6162 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6163 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6164 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6167 info
->usc_idle_mode
= usc_idle_mode
;
6168 //usc_OutReg(info, TCSR, usc_idle_mode);
6169 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6170 info
->tcsr_value
+= usc_idle_mode
;
6171 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6174 * if SyncLink WAN adapter is running in external sync mode, the
6175 * transmitter has been set to Monosync in order to try to mimic
6176 * a true raw outbound bit stream. Monosync still sends an open/close
6177 * sync char at the start/end of a frame. Try to match those sync
6178 * patterns to the idle mode set here
6180 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6181 unsigned char syncpat
= 0;
6182 switch( info
->idle_mode
) {
6183 case HDLC_TXIDLE_FLAGS
:
6186 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6189 case HDLC_TXIDLE_ZEROS
:
6190 case HDLC_TXIDLE_SPACE
:
6193 case HDLC_TXIDLE_ONES
:
6194 case HDLC_TXIDLE_MARK
:
6197 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6202 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6205 } /* end of usc_set_txidle() */
6207 /* usc_get_serial_signals()
6209 * Query the adapter for the state of the V24 status (input) signals.
6211 * Arguments: info pointer to device instance data
6212 * Return Value: None
6214 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6218 /* clear all serial signals except RTS and DTR */
6219 info
->serial_signals
&= SerialSignal_RTS
| SerialSignal_DTR
;
6221 /* Read the Misc Interrupt status Register (MISR) to get */
6222 /* the V24 status signals. */
6224 status
= usc_InReg( info
, MISR
);
6226 /* set serial signal bits to reflect MISR */
6228 if ( status
& MISCSTATUS_CTS
)
6229 info
->serial_signals
|= SerialSignal_CTS
;
6231 if ( status
& MISCSTATUS_DCD
)
6232 info
->serial_signals
|= SerialSignal_DCD
;
6234 if ( status
& MISCSTATUS_RI
)
6235 info
->serial_signals
|= SerialSignal_RI
;
6237 if ( status
& MISCSTATUS_DSR
)
6238 info
->serial_signals
|= SerialSignal_DSR
;
6240 } /* end of usc_get_serial_signals() */
6242 /* usc_set_serial_signals()
6244 * Set the state of RTS and DTR based on contents of
6245 * serial_signals member of device extension.
6247 * Arguments: info pointer to device instance data
6248 * Return Value: None
6250 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6253 unsigned char V24Out
= info
->serial_signals
;
6255 /* get the current value of the Port Control Register (PCR) */
6257 Control
= usc_InReg( info
, PCR
);
6259 if ( V24Out
& SerialSignal_RTS
)
6264 if ( V24Out
& SerialSignal_DTR
)
6269 usc_OutReg( info
, PCR
, Control
);
6271 } /* end of usc_set_serial_signals() */
6273 /* usc_enable_async_clock()
6275 * Enable the async clock at the specified frequency.
6277 * Arguments: info pointer to device instance data
6278 * data_rate data rate of clock in bps
6279 * 0 disables the AUX clock.
6280 * Return Value: None
6282 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6286 * Clock mode Control Register (CMCR)
6288 * <15..14> 00 counter 1 Disabled
6289 * <13..12> 00 counter 0 Disabled
6290 * <11..10> 11 BRG1 Input is TxC Pin
6291 * <9..8> 11 BRG0 Input is TxC Pin
6292 * <7..6> 01 DPLL Input is BRG1 Output
6293 * <5..3> 100 TxCLK comes from BRG0
6294 * <2..0> 100 RxCLK comes from BRG0
6296 * 0000 1111 0110 0100 = 0x0f64
6299 usc_OutReg( info
, CMCR
, 0x0f64 );
6303 * Write 16-bit Time Constant for BRG0
6304 * Time Constant = (ClkSpeed / data_rate) - 1
6305 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6308 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6309 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6311 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6315 * Hardware Configuration Register (HCR)
6316 * Clear Bit 1, BRG0 mode = Continuous
6317 * Set Bit 0 to enable BRG0.
6320 usc_OutReg( info
, HCR
,
6321 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6324 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6326 usc_OutReg( info
, IOCR
,
6327 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6329 /* data rate == 0 so turn off BRG0 */
6330 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6333 } /* end of usc_enable_async_clock() */
6336 * Buffer Structures:
6338 * Normal memory access uses virtual addresses that can make discontiguous
6339 * physical memory pages appear to be contiguous in the virtual address
6340 * space (the processors memory mapping handles the conversions).
6342 * DMA transfers require physically contiguous memory. This is because
6343 * the DMA system controller and DMA bus masters deal with memory using
6344 * only physical addresses.
6346 * This causes a problem under Windows NT when large DMA buffers are
6347 * needed. Fragmentation of the nonpaged pool prevents allocations of
6348 * physically contiguous buffers larger than the PAGE_SIZE.
6350 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6351 * allows DMA transfers to physically discontiguous buffers. Information
6352 * about each data transfer buffer is contained in a memory structure
6353 * called a 'buffer entry'. A list of buffer entries is maintained
6354 * to track and control the use of the data transfer buffers.
6356 * To support this strategy we will allocate sufficient PAGE_SIZE
6357 * contiguous memory buffers to allow for the total required buffer
6360 * The 16C32 accesses the list of buffer entries using Bus Master
6361 * DMA. Control information is read from the buffer entries by the
6362 * 16C32 to control data transfers. status information is written to
6363 * the buffer entries by the 16C32 to indicate the status of completed
6366 * The CPU writes control information to the buffer entries to control
6367 * the 16C32 and reads status information from the buffer entries to
6368 * determine information about received and transmitted frames.
6370 * Because the CPU and 16C32 (adapter) both need simultaneous access
6371 * to the buffer entries, the buffer entry memory is allocated with
6372 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6373 * entry list to PAGE_SIZE.
6375 * The actual data buffers on the other hand will only be accessed
6376 * by the CPU or the adapter but not by both simultaneously. This allows
6377 * Scatter/Gather packet based DMA procedures for using physically
6378 * discontiguous pages.
6382 * mgsl_reset_tx_dma_buffers()
6384 * Set the count for all transmit buffers to 0 to indicate the
6385 * buffer is available for use and set the current buffer to the
6386 * first buffer. This effectively makes all buffers free and
6387 * discards any data in buffers.
6389 * Arguments: info pointer to device instance data
6390 * Return Value: None
6392 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6396 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6397 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6400 info
->current_tx_buffer
= 0;
6401 info
->start_tx_dma_buffer
= 0;
6402 info
->tx_dma_buffers_used
= 0;
6404 info
->get_tx_holding_index
= 0;
6405 info
->put_tx_holding_index
= 0;
6406 info
->tx_holding_count
= 0;
6408 } /* end of mgsl_reset_tx_dma_buffers() */
6411 * num_free_tx_dma_buffers()
6413 * returns the number of free tx dma buffers available
6415 * Arguments: info pointer to device instance data
6416 * Return Value: number of free tx dma buffers
6418 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6420 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6424 * mgsl_reset_rx_dma_buffers()
6426 * Set the count for all receive buffers to DMABUFFERSIZE
6427 * and set the current buffer to the first buffer. This effectively
6428 * makes all buffers free and discards any data in buffers.
6430 * Arguments: info pointer to device instance data
6431 * Return Value: None
6433 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6437 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6438 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6439 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6440 // info->rx_buffer_list[i].status = 0;
6443 info
->current_rx_buffer
= 0;
6445 } /* end of mgsl_reset_rx_dma_buffers() */
6448 * mgsl_free_rx_frame_buffers()
6450 * Free the receive buffers used by a received SDLC
6451 * frame such that the buffers can be reused.
6455 * info pointer to device instance data
6456 * StartIndex index of 1st receive buffer of frame
6457 * EndIndex index of last receive buffer of frame
6459 * Return Value: None
6461 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6464 DMABUFFERENTRY
*pBufEntry
;
6467 /* Starting with 1st buffer entry of the frame clear the status */
6468 /* field and set the count field to DMA Buffer Size. */
6473 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6475 if ( Index
== EndIndex
) {
6476 /* This is the last buffer of the frame! */
6480 /* reset current buffer for reuse */
6481 // pBufEntry->status = 0;
6482 // pBufEntry->count = DMABUFFERSIZE;
6483 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6485 /* advance to next buffer entry in linked list */
6487 if ( Index
== info
->rx_buffer_count
)
6491 /* set current buffer to next buffer after last buffer of frame */
6492 info
->current_rx_buffer
= Index
;
6494 } /* end of free_rx_frame_buffers() */
6496 /* mgsl_get_rx_frame()
6498 * This function attempts to return a received SDLC frame from the
6499 * receive DMA buffers. Only frames received without errors are returned.
6501 * Arguments: info pointer to device extension
6502 * Return Value: true if frame returned, otherwise false
6504 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6506 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6507 unsigned short status
;
6508 DMABUFFERENTRY
*pBufEntry
;
6509 unsigned int framesize
= 0;
6510 bool ReturnCode
= false;
6511 unsigned long flags
;
6512 struct tty_struct
*tty
= info
->port
.tty
;
6513 bool return_frame
= false;
6516 * current_rx_buffer points to the 1st buffer of the next available
6517 * receive frame. To find the last buffer of the frame look for
6518 * a non-zero status field in the buffer entries. (The status
6519 * field is set by the 16C32 after completing a receive frame.
6522 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6524 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6526 * If the count field of the buffer entry is non-zero then
6527 * this buffer has not been used. (The 16C32 clears the count
6528 * field when it starts using the buffer.) If an unused buffer
6529 * is encountered then there are no frames available.
6532 if ( info
->rx_buffer_list
[EndIndex
].count
)
6535 /* advance to next buffer entry in linked list */
6537 if ( EndIndex
== info
->rx_buffer_count
)
6540 /* if entire list searched then no frame available */
6541 if ( EndIndex
== StartIndex
) {
6542 /* If this occurs then something bad happened,
6543 * all buffers have been 'used' but none mark
6544 * the end of a frame. Reset buffers and receiver.
6547 if ( info
->rx_enabled
){
6548 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6549 usc_start_receiver(info
);
6550 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6557 /* check status of receive frame */
6559 status
= info
->rx_buffer_list
[EndIndex
].status
;
6561 if ( status
& (RXSTATUS_SHORT_FRAME
| RXSTATUS_OVERRUN
|
6562 RXSTATUS_CRC_ERROR
| RXSTATUS_ABORT
) ) {
6563 if ( status
& RXSTATUS_SHORT_FRAME
)
6564 info
->icount
.rxshort
++;
6565 else if ( status
& RXSTATUS_ABORT
)
6566 info
->icount
.rxabort
++;
6567 else if ( status
& RXSTATUS_OVERRUN
)
6568 info
->icount
.rxover
++;
6570 info
->icount
.rxcrc
++;
6571 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6572 return_frame
= true;
6575 #if SYNCLINK_GENERIC_HDLC
6577 info
->netdev
->stats
.rx_errors
++;
6578 info
->netdev
->stats
.rx_frame_errors
++;
6582 return_frame
= true;
6584 if ( return_frame
) {
6585 /* receive frame has no errors, get frame size.
6586 * The frame size is the starting value of the RCC (which was
6587 * set to 0xffff) minus the ending value of the RCC (decremented
6588 * once for each receive character) minus 2 for the 16-bit CRC.
6591 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6593 /* adjust frame size for CRC if any */
6594 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6596 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6600 if ( debug_level
>= DEBUG_LEVEL_BH
)
6601 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6602 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6604 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6605 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6606 min_t(int, framesize
, DMABUFFERSIZE
),0);
6609 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6610 ((framesize
+1) > info
->max_frame_size
) ) ||
6611 (framesize
> info
->max_frame_size
) )
6612 info
->icount
.rxlong
++;
6614 /* copy dma buffer(s) to contiguous intermediate buffer */
6615 int copy_count
= framesize
;
6616 int index
= StartIndex
;
6617 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6619 if ( !(status
& RXSTATUS_CRC_ERROR
))
6620 info
->icount
.rxok
++;
6624 if ( copy_count
> DMABUFFERSIZE
)
6625 partial_count
= DMABUFFERSIZE
;
6627 partial_count
= copy_count
;
6629 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6630 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6631 ptmp
+= partial_count
;
6632 copy_count
-= partial_count
;
6634 if ( ++index
== info
->rx_buffer_count
)
6638 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6640 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6644 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6645 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6646 __FILE__
,__LINE__
,info
->device_name
,
6650 #if SYNCLINK_GENERIC_HDLC
6652 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6655 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6658 /* Free the buffers used by this frame. */
6659 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6665 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6666 /* The receiver needs to restarted because of
6667 * a receive overflow (buffer or FIFO). If the
6668 * receive buffers are now empty, then restart receiver.
6671 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6672 info
->rx_buffer_list
[EndIndex
].count
) {
6673 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6674 usc_start_receiver(info
);
6675 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6681 } /* end of mgsl_get_rx_frame() */
6683 /* mgsl_get_raw_rx_frame()
6685 * This function attempts to return a received frame from the
6686 * receive DMA buffers when running in external loop mode. In this mode,
6687 * we will return at most one DMABUFFERSIZE frame to the application.
6688 * The USC receiver is triggering off of DCD going active to start a new
6689 * frame, and DCD going inactive to terminate the frame (similar to
6690 * processing a closing flag character).
6692 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6693 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6694 * status field and the RCC field will indicate the length of the
6695 * entire received frame. We take this RCC field and get the modulus
6696 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6697 * last Rx DMA buffer and return that last portion of the frame.
6699 * Arguments: info pointer to device extension
6700 * Return Value: true if frame returned, otherwise false
6702 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6704 unsigned int CurrentIndex
, NextIndex
;
6705 unsigned short status
;
6706 DMABUFFERENTRY
*pBufEntry
;
6707 unsigned int framesize
= 0;
6708 bool ReturnCode
= false;
6709 unsigned long flags
;
6710 struct tty_struct
*tty
= info
->port
.tty
;
6713 * current_rx_buffer points to the 1st buffer of the next available
6714 * receive frame. The status field is set by the 16C32 after
6715 * completing a receive frame. If the status field of this buffer
6716 * is zero, either the USC is still filling this buffer or this
6717 * is one of a series of buffers making up a received frame.
6719 * If the count field of this buffer is zero, the USC is either
6720 * using this buffer or has used this buffer. Look at the count
6721 * field of the next buffer. If that next buffer's count is
6722 * non-zero, the USC is still actively using the current buffer.
6723 * Otherwise, if the next buffer's count field is zero, the
6724 * current buffer is complete and the USC is using the next
6727 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6729 if ( NextIndex
== info
->rx_buffer_count
)
6732 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6733 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6734 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6736 * Either the status field of this dma buffer is non-zero
6737 * (indicating the last buffer of a receive frame) or the next
6738 * buffer is marked as in use -- implying this buffer is complete
6739 * and an intermediate buffer for this received frame.
6742 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6744 if ( status
& (RXSTATUS_SHORT_FRAME
| RXSTATUS_OVERRUN
|
6745 RXSTATUS_CRC_ERROR
| RXSTATUS_ABORT
) ) {
6746 if ( status
& RXSTATUS_SHORT_FRAME
)
6747 info
->icount
.rxshort
++;
6748 else if ( status
& RXSTATUS_ABORT
)
6749 info
->icount
.rxabort
++;
6750 else if ( status
& RXSTATUS_OVERRUN
)
6751 info
->icount
.rxover
++;
6753 info
->icount
.rxcrc
++;
6757 * A receive frame is available, get frame size and status.
6759 * The frame size is the starting value of the RCC (which was
6760 * set to 0xffff) minus the ending value of the RCC (decremented
6761 * once for each receive character) minus 2 or 4 for the 16-bit
6764 * If the status field is zero, this is an intermediate buffer.
6767 * If the DMA Buffer Entry's Status field is non-zero, the
6768 * receive operation completed normally (ie: DCD dropped). The
6769 * RCC field is valid and holds the received frame size.
6770 * It is possible that the RCC field will be zero on a DMA buffer
6771 * entry with a non-zero status. This can occur if the total
6772 * frame size (number of bytes between the time DCD goes active
6773 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6774 * case the 16C32 has underrun on the RCC count and appears to
6775 * stop updating this counter to let us know the actual received
6776 * frame size. If this happens (non-zero status and zero RCC),
6777 * simply return the entire RxDMA Buffer
6781 * In the event that the final RxDMA Buffer is
6782 * terminated with a non-zero status and the RCC
6783 * field is zero, we interpret this as the RCC
6784 * having underflowed (received frame > 65535 bytes).
6786 * Signal the event to the user by passing back
6787 * a status of RxStatus_CrcError returning the full
6788 * buffer and let the app figure out what data is
6791 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6792 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6794 framesize
= DMABUFFERSIZE
;
6797 framesize
= DMABUFFERSIZE
;
6800 if ( framesize
> DMABUFFERSIZE
) {
6802 * if running in raw sync mode, ISR handler for
6803 * End Of Buffer events terminates all buffers at 4K.
6804 * If this frame size is said to be >4K, get the
6805 * actual number of bytes of the frame in this buffer.
6807 framesize
= framesize
% DMABUFFERSIZE
;
6811 if ( debug_level
>= DEBUG_LEVEL_BH
)
6812 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6813 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6815 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6816 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6817 min_t(int, framesize
, DMABUFFERSIZE
),0);
6820 /* copy dma buffer(s) to contiguous intermediate buffer */
6821 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6823 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6824 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6825 info
->icount
.rxok
++;
6827 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6830 /* Free the buffers used by this frame. */
6831 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6837 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6838 /* The receiver needs to restarted because of
6839 * a receive overflow (buffer or FIFO). If the
6840 * receive buffers are now empty, then restart receiver.
6843 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6844 info
->rx_buffer_list
[CurrentIndex
].count
) {
6845 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6846 usc_start_receiver(info
);
6847 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6853 } /* end of mgsl_get_raw_rx_frame() */
6855 /* mgsl_load_tx_dma_buffer()
6857 * Load the transmit DMA buffer with the specified data.
6861 * info pointer to device extension
6862 * Buffer pointer to buffer containing frame to load
6863 * BufferSize size in bytes of frame in Buffer
6865 * Return Value: None
6867 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6868 const char *Buffer
, unsigned int BufferSize
)
6870 unsigned short Copycount
;
6872 DMABUFFERENTRY
*pBufEntry
;
6874 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6875 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6877 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6878 /* set CMR:13 to start transmit when
6879 * next GoAhead (abort) is received
6881 info
->cmr_value
|= BIT13
;
6884 /* begin loading the frame in the next available tx dma
6885 * buffer, remember it's starting location for setting
6886 * up tx dma operation
6888 i
= info
->current_tx_buffer
;
6889 info
->start_tx_dma_buffer
= i
;
6891 /* Setup the status and RCC (Frame Size) fields of the 1st */
6892 /* buffer entry in the transmit DMA buffer list. */
6894 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6895 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6896 info
->tx_buffer_list
[i
].count
= BufferSize
;
6898 /* Copy frame data from 1st source buffer to the DMA buffers. */
6899 /* The frame data may span multiple DMA buffers. */
6901 while( BufferSize
){
6902 /* Get a pointer to next DMA buffer entry. */
6903 pBufEntry
= &info
->tx_buffer_list
[i
++];
6905 if ( i
== info
->tx_buffer_count
)
6908 /* Calculate the number of bytes that can be copied from */
6909 /* the source buffer to this DMA buffer. */
6910 if ( BufferSize
> DMABUFFERSIZE
)
6911 Copycount
= DMABUFFERSIZE
;
6913 Copycount
= BufferSize
;
6915 /* Actually copy data from source buffer to DMA buffer. */
6916 /* Also set the data count for this individual DMA buffer. */
6917 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6918 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6920 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6922 pBufEntry
->count
= Copycount
;
6924 /* Advance source pointer and reduce remaining data count. */
6925 Buffer
+= Copycount
;
6926 BufferSize
-= Copycount
;
6928 ++info
->tx_dma_buffers_used
;
6931 /* remember next available tx dma buffer */
6932 info
->current_tx_buffer
= i
;
6934 } /* end of mgsl_load_tx_dma_buffer() */
6937 * mgsl_register_test()
6939 * Performs a register test of the 16C32.
6941 * Arguments: info pointer to device instance data
6942 * Return Value: true if test passed, otherwise false
6944 static bool mgsl_register_test( struct mgsl_struct
*info
)
6946 static unsigned short BitPatterns
[] =
6947 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6948 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
6951 unsigned long flags
;
6953 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6956 /* Verify the reset state of some registers. */
6958 if ( (usc_InReg( info
, SICR
) != 0) ||
6959 (usc_InReg( info
, IVR
) != 0) ||
6960 (usc_InDmaReg( info
, DIVR
) != 0) ){
6965 /* Write bit patterns to various registers but do it out of */
6966 /* sync, then read back and verify values. */
6968 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6969 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6970 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6971 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6972 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6973 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6974 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6976 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6977 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6978 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
6979 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
6980 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
6981 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
6989 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6993 } /* end of mgsl_register_test() */
6995 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6997 * Arguments: info pointer to device instance data
6998 * Return Value: true if test passed, otherwise false
7000 static bool mgsl_irq_test( struct mgsl_struct
*info
)
7002 unsigned long EndTime
;
7003 unsigned long flags
;
7005 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7009 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7010 * The ISR sets irq_occurred to true.
7013 info
->irq_occurred
= false;
7015 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7016 /* Enable INTEN (Port 6, Bit12) */
7017 /* This connects the IRQ request signal to the ISA bus */
7018 /* on the ISA adapter. This has no effect for the PCI adapter */
7019 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7021 usc_EnableMasterIrqBit(info
);
7022 usc_EnableInterrupts(info
, IO_PIN
);
7023 usc_ClearIrqPendingBits(info
, IO_PIN
);
7025 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7026 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7028 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7031 while( EndTime
-- && !info
->irq_occurred
) {
7032 msleep_interruptible(10);
7035 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7037 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7039 return info
->irq_occurred
;
7041 } /* end of mgsl_irq_test() */
7045 * Perform a DMA test of the 16C32. A small frame is
7046 * transmitted via DMA from a transmit buffer to a receive buffer
7047 * using single buffer DMA mode.
7049 * Arguments: info pointer to device instance data
7050 * Return Value: true if test passed, otherwise false
7052 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7054 unsigned short FifoLevel
;
7055 unsigned long phys_addr
;
7056 unsigned int FrameSize
;
7060 unsigned short status
=0;
7061 unsigned long EndTime
;
7062 unsigned long flags
;
7063 MGSL_PARAMS tmp_params
;
7065 /* save current port options */
7066 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7067 /* load default port options */
7068 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7070 #define TESTFRAMESIZE 40
7072 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7074 /* setup 16C32 for SDLC DMA transfer mode */
7077 usc_set_sdlc_mode(info
);
7078 usc_enable_loopback(info
,1);
7080 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7081 * field of the buffer entry after fetching buffer address. This
7082 * way we can detect a DMA failure for a DMA read (which should be
7083 * non-destructive to system memory) before we try and write to
7084 * memory (where a failure could corrupt system memory).
7087 /* Receive DMA mode Register (RDMR)
7089 * <15..14> 11 DMA mode = Linked List Buffer mode
7090 * <13> 1 RSBinA/L = store Rx status Block in List entry
7091 * <12> 0 1 = Clear count of List Entry after fetching
7092 * <11..10> 00 Address mode = Increment
7093 * <9> 1 Terminate Buffer on RxBound
7094 * <8> 0 Bus Width = 16bits
7095 * <7..0> ? status Bits (write as 0s)
7097 * 1110 0010 0000 0000 = 0xe200
7100 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7102 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7105 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7107 FrameSize
= TESTFRAMESIZE
;
7109 /* setup 1st transmit buffer entry: */
7110 /* with frame size and transmit control word */
7112 info
->tx_buffer_list
[0].count
= FrameSize
;
7113 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7114 info
->tx_buffer_list
[0].status
= 0x4000;
7116 /* build a transmit frame in 1st transmit DMA buffer */
7118 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7119 for (i
= 0; i
< FrameSize
; i
++ )
7122 /* setup 1st receive buffer entry: */
7123 /* clear status, set max receive buffer size */
7125 info
->rx_buffer_list
[0].status
= 0;
7126 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7128 /* zero out the 1st receive buffer */
7130 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7132 /* Set count field of next buffer entries to prevent */
7133 /* 16C32 from using buffers after the 1st one. */
7135 info
->tx_buffer_list
[1].count
= 0;
7136 info
->rx_buffer_list
[1].count
= 0;
7139 /***************************/
7140 /* Program 16C32 receiver. */
7141 /***************************/
7143 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7145 /* setup DMA transfers */
7146 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7148 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7149 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7150 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7151 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7153 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7154 usc_InDmaReg( info
, RDMR
);
7155 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7157 /* Enable Receiver (RMR <1..0> = 10) */
7158 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7160 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7163 /*************************************************************/
7164 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7165 /*************************************************************/
7167 /* Wait 100ms for interrupt. */
7168 EndTime
= jiffies
+ msecs_to_jiffies(100);
7171 if (time_after(jiffies
, EndTime
)) {
7176 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7177 status
= usc_InDmaReg( info
, RDMR
);
7178 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7180 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7181 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7182 /* BUSY (BIT 5) is active (channel still active). */
7183 /* This means the buffer entry read has completed. */
7189 /******************************/
7190 /* Program 16C32 transmitter. */
7191 /******************************/
7193 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7195 /* Program the Transmit Character Length Register (TCLR) */
7196 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7198 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7199 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7201 /* Program the address of the 1st DMA Buffer Entry in linked list */
7203 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7204 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7205 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7207 /* unlatch Tx status bits, and start transmit channel. */
7209 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7210 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7212 /* wait for DMA controller to fill transmit FIFO */
7214 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7216 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7219 /**********************************/
7220 /* WAIT FOR TRANSMIT FIFO TO FILL */
7221 /**********************************/
7224 EndTime
= jiffies
+ msecs_to_jiffies(100);
7227 if (time_after(jiffies
, EndTime
)) {
7232 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7233 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7234 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7236 if ( FifoLevel
< 16 )
7239 if ( FrameSize
< 32 ) {
7240 /* This frame is smaller than the entire transmit FIFO */
7241 /* so wait for the entire frame to be loaded. */
7242 if ( FifoLevel
<= (32 - FrameSize
) )
7250 /* Enable 16C32 transmitter. */
7252 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7254 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7255 usc_TCmd( info
, TCmd_SendFrame
);
7256 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7258 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7261 /******************************/
7262 /* WAIT FOR TRANSMIT COMPLETE */
7263 /******************************/
7266 EndTime
= jiffies
+ msecs_to_jiffies(100);
7268 /* While timer not expired wait for transmit complete */
7270 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7271 status
= usc_InReg( info
, TCSR
);
7272 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7274 while ( !(status
& (BIT6
| BIT5
| BIT4
| BIT2
| BIT1
)) ) {
7275 if (time_after(jiffies
, EndTime
)) {
7280 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7281 status
= usc_InReg( info
, TCSR
);
7282 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7288 /* CHECK FOR TRANSMIT ERRORS */
7289 if ( status
& (BIT5
| BIT1
) )
7294 /* WAIT FOR RECEIVE COMPLETE */
7297 EndTime
= jiffies
+ msecs_to_jiffies(100);
7299 /* Wait for 16C32 to write receive status to buffer entry. */
7300 status
=info
->rx_buffer_list
[0].status
;
7301 while ( status
== 0 ) {
7302 if (time_after(jiffies
, EndTime
)) {
7306 status
=info
->rx_buffer_list
[0].status
;
7312 /* CHECK FOR RECEIVE ERRORS */
7313 status
= info
->rx_buffer_list
[0].status
;
7315 if ( status
& (BIT8
| BIT3
| BIT1
) ) {
7316 /* receive error has occurred */
7319 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7320 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7326 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7328 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7330 /* restore current port options */
7331 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7335 } /* end of mgsl_dma_test() */
7337 /* mgsl_adapter_test()
7339 * Perform the register, IRQ, and DMA tests for the 16C32.
7341 * Arguments: info pointer to device instance data
7342 * Return Value: 0 if success, otherwise -ENODEV
7344 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7346 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7347 printk( "%s(%d):Testing device %s\n",
7348 __FILE__
,__LINE__
,info
->device_name
);
7350 if ( !mgsl_register_test( info
) ) {
7351 info
->init_error
= DiagStatus_AddressFailure
;
7352 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7353 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7357 if ( !mgsl_irq_test( info
) ) {
7358 info
->init_error
= DiagStatus_IrqFailure
;
7359 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7360 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7364 if ( !mgsl_dma_test( info
) ) {
7365 info
->init_error
= DiagStatus_DmaFailure
;
7366 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7367 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7371 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7372 printk( "%s(%d):device %s passed diagnostics\n",
7373 __FILE__
,__LINE__
,info
->device_name
);
7377 } /* end of mgsl_adapter_test() */
7379 /* mgsl_memory_test()
7381 * Test the shared memory on a PCI adapter.
7383 * Arguments: info pointer to device instance data
7384 * Return Value: true if test passed, otherwise false
7386 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7388 static unsigned long BitPatterns
[] =
7389 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7390 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7392 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7393 unsigned long * TestAddr
;
7395 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7398 TestAddr
= (unsigned long *)info
->memory_base
;
7400 /* Test data lines with test pattern at one location. */
7402 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7403 *TestAddr
= BitPatterns
[i
];
7404 if ( *TestAddr
!= BitPatterns
[i
] )
7408 /* Test address lines with incrementing pattern over */
7409 /* entire address range. */
7411 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7416 TestAddr
= (unsigned long *)info
->memory_base
;
7418 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7419 if ( *TestAddr
!= i
* 4 )
7424 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7428 } /* End Of mgsl_memory_test() */
7431 /* mgsl_load_pci_memory()
7433 * Load a large block of data into the PCI shared memory.
7434 * Use this instead of memcpy() or memmove() to move data
7435 * into the PCI shared memory.
7439 * This function prevents the PCI9050 interface chip from hogging
7440 * the adapter local bus, which can starve the 16C32 by preventing
7441 * 16C32 bus master cycles.
7443 * The PCI9050 documentation says that the 9050 will always release
7444 * control of the local bus after completing the current read
7445 * or write operation.
7447 * It appears that as long as the PCI9050 write FIFO is full, the
7448 * PCI9050 treats all of the writes as a single burst transaction
7449 * and will not release the bus. This causes DMA latency problems
7450 * at high speeds when copying large data blocks to the shared
7453 * This function in effect, breaks the a large shared memory write
7454 * into multiple transations by interleaving a shared memory read
7455 * which will flush the write FIFO and 'complete' the write
7456 * transation. This allows any pending DMA request to gain control
7457 * of the local bus in a timely fasion.
7461 * TargetPtr pointer to target address in PCI shared memory
7462 * SourcePtr pointer to source buffer for data
7463 * count count in bytes of data to copy
7465 * Return Value: None
7467 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7468 unsigned short count
)
7470 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7471 #define PCI_LOAD_INTERVAL 64
7473 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7474 unsigned short Index
;
7475 unsigned long Dummy
;
7477 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7479 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7480 Dummy
= *((volatile unsigned long *)TargetPtr
);
7481 TargetPtr
+= PCI_LOAD_INTERVAL
;
7482 SourcePtr
+= PCI_LOAD_INTERVAL
;
7485 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7487 } /* End Of mgsl_load_pci_memory() */
7489 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7494 printk("%s tx data:\n",info
->device_name
);
7496 printk("%s rx data:\n",info
->device_name
);
7504 for(i
=0;i
<linecount
;i
++)
7505 printk("%02X ",(unsigned char)data
[i
]);
7508 for(i
=0;i
<linecount
;i
++) {
7509 if (data
[i
]>=040 && data
[i
]<=0176)
7510 printk("%c",data
[i
]);
7519 } /* end of mgsl_trace_block() */
7521 /* mgsl_tx_timeout()
7523 * called when HDLC frame times out
7524 * update stats and do tx completion processing
7526 * Arguments: context pointer to device instance data
7527 * Return Value: None
7529 static void mgsl_tx_timeout(unsigned long context
)
7531 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7532 unsigned long flags
;
7534 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7535 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7536 __FILE__
,__LINE__
,info
->device_name
);
7537 if(info
->tx_active
&&
7538 (info
->params
.mode
== MGSL_MODE_HDLC
||
7539 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7540 info
->icount
.txtimeout
++;
7542 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7543 info
->tx_active
= false;
7544 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7546 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7547 usc_loopmode_cancel_transmit( info
);
7549 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7551 #if SYNCLINK_GENERIC_HDLC
7553 hdlcdev_tx_done(info
);
7556 mgsl_bh_transmit(info
);
7558 } /* end of mgsl_tx_timeout() */
7560 /* signal that there are no more frames to send, so that
7561 * line is 'released' by echoing RxD to TxD when current
7562 * transmission is complete (or immediately if no tx in progress).
7564 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7566 unsigned long flags
;
7568 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7569 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7570 if (info
->tx_active
)
7571 info
->loopmode_send_done_requested
= true;
7573 usc_loopmode_send_done(info
);
7575 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7580 /* release the line by echoing RxD to TxD
7581 * upon completion of a transmit frame
7583 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7585 info
->loopmode_send_done_requested
= false;
7586 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7587 info
->cmr_value
&= ~BIT13
;
7588 usc_OutReg(info
, CMR
, info
->cmr_value
);
7591 /* abort a transmit in progress while in HDLC LoopMode
7593 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7595 /* reset tx dma channel and purge TxFifo */
7596 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7597 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7598 usc_loopmode_send_done( info
);
7601 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7602 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7603 * we must clear CMR:13 to begin repeating TxData to RxData
7605 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7607 info
->loopmode_insert_requested
= true;
7609 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7610 * begin repeating TxData on RxData (complete insertion)
7612 usc_OutReg( info
, RICR
,
7613 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7615 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7616 info
->cmr_value
|= BIT13
;
7617 usc_OutReg(info
, CMR
, info
->cmr_value
);
7620 /* return 1 if station is inserted into the loop, otherwise 0
7622 static int usc_loopmode_active( struct mgsl_struct
* info
)
7624 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7627 #if SYNCLINK_GENERIC_HDLC
7630 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7631 * set encoding and frame check sequence (FCS) options
7633 * dev pointer to network device structure
7634 * encoding serial encoding setting
7635 * parity FCS setting
7637 * returns 0 if success, otherwise error code
7639 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7640 unsigned short parity
)
7642 struct mgsl_struct
*info
= dev_to_port(dev
);
7643 unsigned char new_encoding
;
7644 unsigned short new_crctype
;
7646 /* return error if TTY interface open */
7647 if (info
->port
.count
)
7652 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7653 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7654 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7655 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7656 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7657 default: return -EINVAL
;
7662 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7663 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7664 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7665 default: return -EINVAL
;
7668 info
->params
.encoding
= new_encoding
;
7669 info
->params
.crc_type
= new_crctype
;
7671 /* if network interface up, reprogram hardware */
7673 mgsl_program_hw(info
);
7679 * called by generic HDLC layer to send frame
7681 * skb socket buffer containing HDLC frame
7682 * dev pointer to network device structure
7684 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
7685 struct net_device
*dev
)
7687 struct mgsl_struct
*info
= dev_to_port(dev
);
7688 unsigned long flags
;
7690 if (debug_level
>= DEBUG_LEVEL_INFO
)
7691 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7693 /* stop sending until this frame completes */
7694 netif_stop_queue(dev
);
7696 /* copy data to device buffers */
7697 info
->xmit_cnt
= skb
->len
;
7698 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7700 /* update network statistics */
7701 dev
->stats
.tx_packets
++;
7702 dev
->stats
.tx_bytes
+= skb
->len
;
7704 /* done with socket buffer, so free it */
7707 /* save start time for transmit timeout detection */
7708 dev
->trans_start
= jiffies
;
7710 /* start hardware transmitter if necessary */
7711 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7712 if (!info
->tx_active
)
7713 usc_start_transmitter(info
);
7714 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7716 return NETDEV_TX_OK
;
7720 * called by network layer when interface enabled
7721 * claim resources and initialize hardware
7723 * dev pointer to network device structure
7725 * returns 0 if success, otherwise error code
7727 static int hdlcdev_open(struct net_device
*dev
)
7729 struct mgsl_struct
*info
= dev_to_port(dev
);
7731 unsigned long flags
;
7733 if (debug_level
>= DEBUG_LEVEL_INFO
)
7734 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7736 /* generic HDLC layer open processing */
7737 rc
= hdlc_open(dev
);
7741 /* arbitrate between network and tty opens */
7742 spin_lock_irqsave(&info
->netlock
, flags
);
7743 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7744 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7745 spin_unlock_irqrestore(&info
->netlock
, flags
);
7749 spin_unlock_irqrestore(&info
->netlock
, flags
);
7751 /* claim resources and init adapter */
7752 if ((rc
= startup(info
)) != 0) {
7753 spin_lock_irqsave(&info
->netlock
, flags
);
7755 spin_unlock_irqrestore(&info
->netlock
, flags
);
7759 /* assert RTS and DTR, apply hardware settings */
7760 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
7761 mgsl_program_hw(info
);
7763 /* enable network layer transmit */
7764 dev
->trans_start
= jiffies
;
7765 netif_start_queue(dev
);
7767 /* inform generic HDLC layer of current DCD status */
7768 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7769 usc_get_serial_signals(info
);
7770 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7771 if (info
->serial_signals
& SerialSignal_DCD
)
7772 netif_carrier_on(dev
);
7774 netif_carrier_off(dev
);
7779 * called by network layer when interface is disabled
7780 * shutdown hardware and release resources
7782 * dev pointer to network device structure
7784 * returns 0 if success, otherwise error code
7786 static int hdlcdev_close(struct net_device
*dev
)
7788 struct mgsl_struct
*info
= dev_to_port(dev
);
7789 unsigned long flags
;
7791 if (debug_level
>= DEBUG_LEVEL_INFO
)
7792 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7794 netif_stop_queue(dev
);
7796 /* shutdown adapter and release resources */
7801 spin_lock_irqsave(&info
->netlock
, flags
);
7803 spin_unlock_irqrestore(&info
->netlock
, flags
);
7809 * called by network layer to process IOCTL call to network device
7811 * dev pointer to network device structure
7812 * ifr pointer to network interface request structure
7813 * cmd IOCTL command code
7815 * returns 0 if success, otherwise error code
7817 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7819 const size_t size
= sizeof(sync_serial_settings
);
7820 sync_serial_settings new_line
;
7821 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7822 struct mgsl_struct
*info
= dev_to_port(dev
);
7825 if (debug_level
>= DEBUG_LEVEL_INFO
)
7826 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7828 /* return error if TTY interface open */
7829 if (info
->port
.count
)
7832 if (cmd
!= SIOCWANDEV
)
7833 return hdlc_ioctl(dev
, ifr
, cmd
);
7835 switch(ifr
->ifr_settings
.type
) {
7836 case IF_GET_IFACE
: /* return current sync_serial_settings */
7838 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7839 if (ifr
->ifr_settings
.size
< size
) {
7840 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7844 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7845 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7846 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7847 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7849 memset(&new_line
, 0, sizeof(new_line
));
7851 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7852 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7853 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7854 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7855 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7858 new_line
.clock_rate
= info
->params
.clock_speed
;
7859 new_line
.loopback
= info
->params
.loopback
? 1:0;
7861 if (copy_to_user(line
, &new_line
, size
))
7865 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7867 if(!capable(CAP_NET_ADMIN
))
7869 if (copy_from_user(&new_line
, line
, size
))
7872 switch (new_line
.clock_type
)
7874 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7875 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7876 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7877 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7878 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7879 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7880 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7881 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7882 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7883 default: return -EINVAL
;
7886 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7889 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7890 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7891 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7892 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7893 info
->params
.flags
|= flags
;
7895 info
->params
.loopback
= new_line
.loopback
;
7897 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7898 info
->params
.clock_speed
= new_line
.clock_rate
;
7900 info
->params
.clock_speed
= 0;
7902 /* if network interface up, reprogram hardware */
7904 mgsl_program_hw(info
);
7908 return hdlc_ioctl(dev
, ifr
, cmd
);
7913 * called by network layer when transmit timeout is detected
7915 * dev pointer to network device structure
7917 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7919 struct mgsl_struct
*info
= dev_to_port(dev
);
7920 unsigned long flags
;
7922 if (debug_level
>= DEBUG_LEVEL_INFO
)
7923 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7925 dev
->stats
.tx_errors
++;
7926 dev
->stats
.tx_aborted_errors
++;
7928 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7929 usc_stop_transmitter(info
);
7930 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7932 netif_wake_queue(dev
);
7936 * called by device driver when transmit completes
7937 * reenable network layer transmit if stopped
7939 * info pointer to device instance information
7941 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
7943 if (netif_queue_stopped(info
->netdev
))
7944 netif_wake_queue(info
->netdev
);
7948 * called by device driver when frame received
7949 * pass frame to network layer
7951 * info pointer to device instance information
7952 * buf pointer to buffer contianing frame data
7953 * size count of data bytes in buf
7955 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
7957 struct sk_buff
*skb
= dev_alloc_skb(size
);
7958 struct net_device
*dev
= info
->netdev
;
7960 if (debug_level
>= DEBUG_LEVEL_INFO
)
7961 printk("hdlcdev_rx(%s)\n", dev
->name
);
7964 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
7966 dev
->stats
.rx_dropped
++;
7970 memcpy(skb_put(skb
, size
), buf
, size
);
7972 skb
->protocol
= hdlc_type_trans(skb
, dev
);
7974 dev
->stats
.rx_packets
++;
7975 dev
->stats
.rx_bytes
+= size
;
7980 static const struct net_device_ops hdlcdev_ops
= {
7981 .ndo_open
= hdlcdev_open
,
7982 .ndo_stop
= hdlcdev_close
,
7983 .ndo_change_mtu
= hdlc_change_mtu
,
7984 .ndo_start_xmit
= hdlc_start_xmit
,
7985 .ndo_do_ioctl
= hdlcdev_ioctl
,
7986 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
7990 * called by device driver when adding device instance
7991 * do generic HDLC initialization
7993 * info pointer to device instance information
7995 * returns 0 if success, otherwise error code
7997 static int hdlcdev_init(struct mgsl_struct
*info
)
8000 struct net_device
*dev
;
8003 /* allocate and initialize network and HDLC layer objects */
8005 dev
= alloc_hdlcdev(info
);
8007 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8011 /* for network layer reporting purposes only */
8012 dev
->base_addr
= info
->io_base
;
8013 dev
->irq
= info
->irq_level
;
8014 dev
->dma
= info
->dma_level
;
8016 /* network layer callbacks and settings */
8017 dev
->netdev_ops
= &hdlcdev_ops
;
8018 dev
->watchdog_timeo
= 10 * HZ
;
8019 dev
->tx_queue_len
= 50;
8021 /* generic HDLC layer callbacks and settings */
8022 hdlc
= dev_to_hdlc(dev
);
8023 hdlc
->attach
= hdlcdev_attach
;
8024 hdlc
->xmit
= hdlcdev_xmit
;
8026 /* register objects with HDLC layer */
8027 rc
= register_hdlc_device(dev
);
8029 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8039 * called by device driver when removing device instance
8040 * do generic HDLC cleanup
8042 * info pointer to device instance information
8044 static void hdlcdev_exit(struct mgsl_struct
*info
)
8046 unregister_hdlc_device(info
->netdev
);
8047 free_netdev(info
->netdev
);
8048 info
->netdev
= NULL
;
8051 #endif /* CONFIG_HDLC */
8054 static int synclink_init_one (struct pci_dev
*dev
,
8055 const struct pci_device_id
*ent
)
8057 struct mgsl_struct
*info
;
8059 if (pci_enable_device(dev
)) {
8060 printk("error enabling pci device %p\n", dev
);
8064 info
= mgsl_allocate_device();
8066 printk("can't allocate device instance data.\n");
8070 /* Copy user configuration info to device instance data */
8072 info
->io_base
= pci_resource_start(dev
, 2);
8073 info
->irq_level
= dev
->irq
;
8074 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8076 /* Because veremap only works on page boundaries we must map
8077 * a larger area than is actually implemented for the LCR
8078 * memory range. We map a full page starting at the page boundary.
8080 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8081 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8082 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8084 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8085 info
->io_addr_size
= 8;
8086 info
->irq_flags
= IRQF_SHARED
;
8088 if (dev
->device
== 0x0210) {
8089 /* Version 1 PCI9030 based universal PCI adapter */
8090 info
->misc_ctrl_value
= 0x007c4080;
8091 info
->hw_version
= 1;
8093 /* Version 0 PCI9050 based 5V PCI adapter
8094 * A PCI9050 bug prevents reading LCR registers if
8095 * LCR base address bit 7 is set. Maintain shadow
8096 * value so we can write to LCR misc control reg.
8098 info
->misc_ctrl_value
= 0x087e4546;
8099 info
->hw_version
= 0;
8102 mgsl_add_device(info
);
8107 static void synclink_remove_one (struct pci_dev
*dev
)