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tty: synclink_gt: Rename tty_driver_name
[deliverable/linux.git] / drivers / tty / synclink_gt.c
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/dma.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
81
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
84 #else
85 #define SYNCLINK_GENERIC_HDLC 0
86 #endif
87
88 /*
89 * module identification
90 */
91 static char *driver_name = "SyncLink GT";
92 static char *slgt_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
97
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
104 };
105 MODULE_DEVICE_TABLE(pci, pci_table);
106
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
112 .probe = init_one,
113 .remove = remove_one,
114 };
115
116 static bool pci_registered;
117
118 /*
119 * module configuration and status
120 */
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
123
124 static int ttymajor;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
127
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
131
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135
136 /*
137 * tty support and callbacks
138 */
139 static struct tty_driver *serial_driver;
140
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
155
156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
161
162 /*
163 * generic HDLC support and callbacks
164 */
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
171 #endif
172
173
174 /*
175 * device specific structures, macros and functions
176 */
177
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE 256
180
181 /*
182 * conditional wait facility
183 */
184 struct cond_wait {
185 struct cond_wait *next;
186 wait_queue_head_t q;
187 wait_queue_t wait;
188 unsigned int data;
189 };
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
194
195 /*
196 * DMA buffer descriptor and access macros
197 */
198 struct slgt_desc
199 {
200 __le16 count;
201 __le16 status;
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
204
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
210 };
211
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225 struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234 };
235
236 /*
237 * device instance data structure
238 */
239 struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int rx_pio;
301 unsigned int if_mode;
302 unsigned int base_clock;
303 unsigned int xsync;
304 unsigned int xctrl;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char *flag_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
323
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
327 int ri_chkcount;
328
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
338
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
343
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
346
347 /* SPPP/Cisco HDLC device parts */
348
349 int netcount;
350 spinlock_t netlock;
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
353 #endif
354
355 };
356
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
359 .loopback = 0,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
362 .clock_speed = 0,
363 .addr_filter = 0xff,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
367 .data_rate = 9600,
368 .data_bits = 8,
369 .stop_bits = 1,
370 .parity = ASYNC_PARITY_NONE
371 };
372
373
374 #define BH_RECEIVE 1
375 #define BH_TRANSMIT 2
376 #define BH_STATUS 4
377 #define IO_PIN_SHUTDOWN_LIMIT 100
378
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
381
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
386
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR 0x40 /* extended sync pattern */
409 #define XCR 0x44 /* extended control */
410
411 #define RXIDLE BIT14
412 #define RXBREAK BIT14
413 #define IRQ_TXDATA BIT13
414 #define IRQ_TXIDLE BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA BIT10
417 #define IRQ_RXIDLE BIT9 /* HDLC */
418 #define IRQ_RXBREAK BIT9 /* async */
419 #define IRQ_RXOVER BIT8
420 #define IRQ_DSR BIT7
421 #define IRQ_CTS BIT6
422 #define IRQ_DCD BIT5
423 #define IRQ_RI BIT4
424 #define IRQ_ALL 0x3ff0
425 #define IRQ_MASTER BIT0
426
427 #define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
431
432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
438
439 static void msc_set_vcr(struct slgt_info *info);
440
441 static int startup(struct slgt_info *info);
442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
446
447 static int register_test(struct slgt_info *info);
448 static int irq_test(struct slgt_info *info);
449 static int loopback_test(struct slgt_info *info);
450 static int adapter_test(struct slgt_info *info);
451
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
456
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
464
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
473
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
478
479 static int bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
486
487 static int alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493
494 static int alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
496
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
499
500 /*
501 * ioctl handlers
502 */
503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int set_txidle(struct slgt_info *info, int idle_mode);
508 static int tx_enable(struct slgt_info *info, int enable);
509 static int tx_abort(struct slgt_info *info);
510 static int rx_enable(struct slgt_info *info, int enable);
511 static int modem_input_wait(struct slgt_info *info,int arg);
512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int tiocmget(struct tty_struct *tty);
514 static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int get_interface(struct slgt_info *info, int __user *if_mode);
518 static int set_interface(struct slgt_info *info, int if_mode);
519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int set_xsync(struct slgt_info *info, int if_mode);
524 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int set_xctrl(struct slgt_info *info, int if_mode);
526
527 /*
528 * driver functions
529 */
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
534
535 /*
536 * DEBUG OUTPUT CODE
537 */
538 #ifndef DBGINFO
539 #define DBGINFO(fmt)
540 #endif
541 #ifndef DBGERR
542 #define DBGERR(fmt)
543 #endif
544 #ifndef DBGBH
545 #define DBGBH(fmt)
546 #endif
547 #ifndef DBGISR
548 #define DBGISR(fmt)
549 #endif
550
551 #ifdef DBGDATA
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
553 {
554 int i;
555 int linecount;
556 printk("%s %s data:\n",info->device_name, label);
557 while(count) {
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
561 for(;i<17;i++)
562 printk(" ");
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
566 else
567 printk(".");
568 }
569 printk("\n");
570 data += linecount;
571 count -= linecount;
572 }
573 }
574 #else
575 #define DBGDATA(info, buf, size, label)
576 #endif
577
578 #ifdef DBGTBUF
579 static void dump_tbufs(struct slgt_info *info)
580 {
581 int i;
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
586 }
587 }
588 #else
589 #define DBGTBUF(info)
590 #endif
591
592 #ifdef DBGRBUF
593 static void dump_rbufs(struct slgt_info *info)
594 {
595 int i;
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
600 }
601 }
602 #else
603 #define DBGRBUF(info)
604 #endif
605
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
607 {
608 #ifdef SANITY_CHECK
609 if (!info) {
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
611 return 1;
612 }
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
615 return 1;
616 }
617 #else
618 if (!info)
619 return 1;
620 #endif
621 return 0;
622 }
623
624 /**
625 * line discipline callback wrappers
626 *
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
629 *
630 * ldisc_receive_buf - pass receive data to line discipline
631 */
632 static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
634 {
635 struct tty_ldisc *ld;
636 if (!tty)
637 return;
638 ld = tty_ldisc_ref(tty);
639 if (ld) {
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
642 tty_ldisc_deref(ld);
643 }
644 }
645
646 /* tty callbacks */
647
648 static int open(struct tty_struct *tty, struct file *filp)
649 {
650 struct slgt_info *info;
651 int retval, line;
652 unsigned long flags;
653
654 line = tty->index;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
657 return -ENODEV;
658 }
659
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
664 return -ENODEV;
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
667 return -ENODEV;
668 }
669
670 tty->driver_data = info;
671 info->port.tty = tty;
672
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
674
675 mutex_lock(&info->port.mutex);
676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
677
678 spin_lock_irqsave(&info->netlock, flags);
679 if (info->netcount) {
680 retval = -EBUSY;
681 spin_unlock_irqrestore(&info->netlock, flags);
682 mutex_unlock(&info->port.mutex);
683 goto cleanup;
684 }
685 info->port.count++;
686 spin_unlock_irqrestore(&info->netlock, flags);
687
688 if (info->port.count == 1) {
689 /* 1st open on this device, init hardware */
690 retval = startup(info);
691 if (retval < 0) {
692 mutex_unlock(&info->port.mutex);
693 goto cleanup;
694 }
695 }
696 mutex_unlock(&info->port.mutex);
697 retval = block_til_ready(tty, filp, info);
698 if (retval) {
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
700 goto cleanup;
701 }
702
703 retval = 0;
704
705 cleanup:
706 if (retval) {
707 if (tty->count == 1)
708 info->port.tty = NULL; /* tty layer will release tty struct */
709 if(info->port.count)
710 info->port.count--;
711 }
712
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
714 return retval;
715 }
716
717 static void close(struct tty_struct *tty, struct file *filp)
718 {
719 struct slgt_info *info = tty->driver_data;
720
721 if (sanity_check(info, tty->name, "close"))
722 return;
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
724
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
726 goto cleanup;
727
728 mutex_lock(&info->port.mutex);
729 if (info->port.flags & ASYNC_INITIALIZED)
730 wait_until_sent(tty, info->timeout);
731 flush_buffer(tty);
732 tty_ldisc_flush(tty);
733
734 shutdown(info);
735 mutex_unlock(&info->port.mutex);
736
737 tty_port_close_end(&info->port, tty);
738 info->port.tty = NULL;
739 cleanup:
740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
741 }
742
743 static void hangup(struct tty_struct *tty)
744 {
745 struct slgt_info *info = tty->driver_data;
746 unsigned long flags;
747
748 if (sanity_check(info, tty->name, "hangup"))
749 return;
750 DBGINFO(("%s hangup\n", info->device_name));
751
752 flush_buffer(tty);
753
754 mutex_lock(&info->port.mutex);
755 shutdown(info);
756
757 spin_lock_irqsave(&info->port.lock, flags);
758 info->port.count = 0;
759 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
760 info->port.tty = NULL;
761 spin_unlock_irqrestore(&info->port.lock, flags);
762 mutex_unlock(&info->port.mutex);
763
764 wake_up_interruptible(&info->port.open_wait);
765 }
766
767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
768 {
769 struct slgt_info *info = tty->driver_data;
770 unsigned long flags;
771
772 DBGINFO(("%s set_termios\n", tty->driver->name));
773
774 change_params(info);
775
776 /* Handle transition to B0 status */
777 if (old_termios->c_cflag & CBAUD &&
778 !(tty->termios.c_cflag & CBAUD)) {
779 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
780 spin_lock_irqsave(&info->lock,flags);
781 set_signals(info);
782 spin_unlock_irqrestore(&info->lock,flags);
783 }
784
785 /* Handle transition away from B0 status */
786 if (!(old_termios->c_cflag & CBAUD) &&
787 tty->termios.c_cflag & CBAUD) {
788 info->signals |= SerialSignal_DTR;
789 if (!(tty->termios.c_cflag & CRTSCTS) ||
790 !test_bit(TTY_THROTTLED, &tty->flags)) {
791 info->signals |= SerialSignal_RTS;
792 }
793 spin_lock_irqsave(&info->lock,flags);
794 set_signals(info);
795 spin_unlock_irqrestore(&info->lock,flags);
796 }
797
798 /* Handle turning off CRTSCTS */
799 if (old_termios->c_cflag & CRTSCTS &&
800 !(tty->termios.c_cflag & CRTSCTS)) {
801 tty->hw_stopped = 0;
802 tx_release(tty);
803 }
804 }
805
806 static void update_tx_timer(struct slgt_info *info)
807 {
808 /*
809 * use worst case speed of 1200bps to calculate transmit timeout
810 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
811 */
812 if (info->params.mode == MGSL_MODE_HDLC) {
813 int timeout = (tbuf_bytes(info) * 7) + 1000;
814 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
815 }
816 }
817
818 static int write(struct tty_struct *tty,
819 const unsigned char *buf, int count)
820 {
821 int ret = 0;
822 struct slgt_info *info = tty->driver_data;
823 unsigned long flags;
824
825 if (sanity_check(info, tty->name, "write"))
826 return -EIO;
827
828 DBGINFO(("%s write count=%d\n", info->device_name, count));
829
830 if (!info->tx_buf || (count > info->max_frame_size))
831 return -EIO;
832
833 if (!count || tty->stopped || tty->hw_stopped)
834 return 0;
835
836 spin_lock_irqsave(&info->lock, flags);
837
838 if (info->tx_count) {
839 /* send accumulated data from send_char() */
840 if (!tx_load(info, info->tx_buf, info->tx_count))
841 goto cleanup;
842 info->tx_count = 0;
843 }
844
845 if (tx_load(info, buf, count))
846 ret = count;
847
848 cleanup:
849 spin_unlock_irqrestore(&info->lock, flags);
850 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
851 return ret;
852 }
853
854 static int put_char(struct tty_struct *tty, unsigned char ch)
855 {
856 struct slgt_info *info = tty->driver_data;
857 unsigned long flags;
858 int ret = 0;
859
860 if (sanity_check(info, tty->name, "put_char"))
861 return 0;
862 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
863 if (!info->tx_buf)
864 return 0;
865 spin_lock_irqsave(&info->lock,flags);
866 if (info->tx_count < info->max_frame_size) {
867 info->tx_buf[info->tx_count++] = ch;
868 ret = 1;
869 }
870 spin_unlock_irqrestore(&info->lock,flags);
871 return ret;
872 }
873
874 static void send_xchar(struct tty_struct *tty, char ch)
875 {
876 struct slgt_info *info = tty->driver_data;
877 unsigned long flags;
878
879 if (sanity_check(info, tty->name, "send_xchar"))
880 return;
881 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
882 info->x_char = ch;
883 if (ch) {
884 spin_lock_irqsave(&info->lock,flags);
885 if (!info->tx_enabled)
886 tx_start(info);
887 spin_unlock_irqrestore(&info->lock,flags);
888 }
889 }
890
891 static void wait_until_sent(struct tty_struct *tty, int timeout)
892 {
893 struct slgt_info *info = tty->driver_data;
894 unsigned long orig_jiffies, char_time;
895
896 if (!info )
897 return;
898 if (sanity_check(info, tty->name, "wait_until_sent"))
899 return;
900 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
901 if (!(info->port.flags & ASYNC_INITIALIZED))
902 goto exit;
903
904 orig_jiffies = jiffies;
905
906 /* Set check interval to 1/5 of estimated time to
907 * send a character, and make it at least 1. The check
908 * interval should also be less than the timeout.
909 * Note: use tight timings here to satisfy the NIST-PCTS.
910 */
911
912 if (info->params.data_rate) {
913 char_time = info->timeout/(32 * 5);
914 if (!char_time)
915 char_time++;
916 } else
917 char_time = 1;
918
919 if (timeout)
920 char_time = min_t(unsigned long, char_time, timeout);
921
922 while (info->tx_active) {
923 msleep_interruptible(jiffies_to_msecs(char_time));
924 if (signal_pending(current))
925 break;
926 if (timeout && time_after(jiffies, orig_jiffies + timeout))
927 break;
928 }
929 exit:
930 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
931 }
932
933 static int write_room(struct tty_struct *tty)
934 {
935 struct slgt_info *info = tty->driver_data;
936 int ret;
937
938 if (sanity_check(info, tty->name, "write_room"))
939 return 0;
940 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
941 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
942 return ret;
943 }
944
945 static void flush_chars(struct tty_struct *tty)
946 {
947 struct slgt_info *info = tty->driver_data;
948 unsigned long flags;
949
950 if (sanity_check(info, tty->name, "flush_chars"))
951 return;
952 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
953
954 if (info->tx_count <= 0 || tty->stopped ||
955 tty->hw_stopped || !info->tx_buf)
956 return;
957
958 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
959
960 spin_lock_irqsave(&info->lock,flags);
961 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
962 info->tx_count = 0;
963 spin_unlock_irqrestore(&info->lock,flags);
964 }
965
966 static void flush_buffer(struct tty_struct *tty)
967 {
968 struct slgt_info *info = tty->driver_data;
969 unsigned long flags;
970
971 if (sanity_check(info, tty->name, "flush_buffer"))
972 return;
973 DBGINFO(("%s flush_buffer\n", info->device_name));
974
975 spin_lock_irqsave(&info->lock, flags);
976 info->tx_count = 0;
977 spin_unlock_irqrestore(&info->lock, flags);
978
979 tty_wakeup(tty);
980 }
981
982 /*
983 * throttle (stop) transmitter
984 */
985 static void tx_hold(struct tty_struct *tty)
986 {
987 struct slgt_info *info = tty->driver_data;
988 unsigned long flags;
989
990 if (sanity_check(info, tty->name, "tx_hold"))
991 return;
992 DBGINFO(("%s tx_hold\n", info->device_name));
993 spin_lock_irqsave(&info->lock,flags);
994 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
995 tx_stop(info);
996 spin_unlock_irqrestore(&info->lock,flags);
997 }
998
999 /*
1000 * release (start) transmitter
1001 */
1002 static void tx_release(struct tty_struct *tty)
1003 {
1004 struct slgt_info *info = tty->driver_data;
1005 unsigned long flags;
1006
1007 if (sanity_check(info, tty->name, "tx_release"))
1008 return;
1009 DBGINFO(("%s tx_release\n", info->device_name));
1010 spin_lock_irqsave(&info->lock, flags);
1011 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1012 info->tx_count = 0;
1013 spin_unlock_irqrestore(&info->lock, flags);
1014 }
1015
1016 /*
1017 * Service an IOCTL request
1018 *
1019 * Arguments
1020 *
1021 * tty pointer to tty instance data
1022 * cmd IOCTL command code
1023 * arg command argument/context
1024 *
1025 * Return 0 if success, otherwise error code
1026 */
1027 static int ioctl(struct tty_struct *tty,
1028 unsigned int cmd, unsigned long arg)
1029 {
1030 struct slgt_info *info = tty->driver_data;
1031 void __user *argp = (void __user *)arg;
1032 int ret;
1033
1034 if (sanity_check(info, tty->name, "ioctl"))
1035 return -ENODEV;
1036 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1037
1038 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1039 (cmd != TIOCMIWAIT)) {
1040 if (tty->flags & (1 << TTY_IO_ERROR))
1041 return -EIO;
1042 }
1043
1044 switch (cmd) {
1045 case MGSL_IOCWAITEVENT:
1046 return wait_mgsl_event(info, argp);
1047 case TIOCMIWAIT:
1048 return modem_input_wait(info,(int)arg);
1049 case MGSL_IOCSGPIO:
1050 return set_gpio(info, argp);
1051 case MGSL_IOCGGPIO:
1052 return get_gpio(info, argp);
1053 case MGSL_IOCWAITGPIO:
1054 return wait_gpio(info, argp);
1055 case MGSL_IOCGXSYNC:
1056 return get_xsync(info, argp);
1057 case MGSL_IOCSXSYNC:
1058 return set_xsync(info, (int)arg);
1059 case MGSL_IOCGXCTRL:
1060 return get_xctrl(info, argp);
1061 case MGSL_IOCSXCTRL:
1062 return set_xctrl(info, (int)arg);
1063 }
1064 mutex_lock(&info->port.mutex);
1065 switch (cmd) {
1066 case MGSL_IOCGPARAMS:
1067 ret = get_params(info, argp);
1068 break;
1069 case MGSL_IOCSPARAMS:
1070 ret = set_params(info, argp);
1071 break;
1072 case MGSL_IOCGTXIDLE:
1073 ret = get_txidle(info, argp);
1074 break;
1075 case MGSL_IOCSTXIDLE:
1076 ret = set_txidle(info, (int)arg);
1077 break;
1078 case MGSL_IOCTXENABLE:
1079 ret = tx_enable(info, (int)arg);
1080 break;
1081 case MGSL_IOCRXENABLE:
1082 ret = rx_enable(info, (int)arg);
1083 break;
1084 case MGSL_IOCTXABORT:
1085 ret = tx_abort(info);
1086 break;
1087 case MGSL_IOCGSTATS:
1088 ret = get_stats(info, argp);
1089 break;
1090 case MGSL_IOCGIF:
1091 ret = get_interface(info, argp);
1092 break;
1093 case MGSL_IOCSIF:
1094 ret = set_interface(info,(int)arg);
1095 break;
1096 default:
1097 ret = -ENOIOCTLCMD;
1098 }
1099 mutex_unlock(&info->port.mutex);
1100 return ret;
1101 }
1102
1103 static int get_icount(struct tty_struct *tty,
1104 struct serial_icounter_struct *icount)
1105
1106 {
1107 struct slgt_info *info = tty->driver_data;
1108 struct mgsl_icount cnow; /* kernel counter temps */
1109 unsigned long flags;
1110
1111 spin_lock_irqsave(&info->lock,flags);
1112 cnow = info->icount;
1113 spin_unlock_irqrestore(&info->lock,flags);
1114
1115 icount->cts = cnow.cts;
1116 icount->dsr = cnow.dsr;
1117 icount->rng = cnow.rng;
1118 icount->dcd = cnow.dcd;
1119 icount->rx = cnow.rx;
1120 icount->tx = cnow.tx;
1121 icount->frame = cnow.frame;
1122 icount->overrun = cnow.overrun;
1123 icount->parity = cnow.parity;
1124 icount->brk = cnow.brk;
1125 icount->buf_overrun = cnow.buf_overrun;
1126
1127 return 0;
1128 }
1129
1130 /*
1131 * support for 32 bit ioctl calls on 64 bit systems
1132 */
1133 #ifdef CONFIG_COMPAT
1134 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1135 {
1136 struct MGSL_PARAMS32 tmp_params;
1137
1138 DBGINFO(("%s get_params32\n", info->device_name));
1139 memset(&tmp_params, 0, sizeof(tmp_params));
1140 tmp_params.mode = (compat_ulong_t)info->params.mode;
1141 tmp_params.loopback = info->params.loopback;
1142 tmp_params.flags = info->params.flags;
1143 tmp_params.encoding = info->params.encoding;
1144 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1145 tmp_params.addr_filter = info->params.addr_filter;
1146 tmp_params.crc_type = info->params.crc_type;
1147 tmp_params.preamble_length = info->params.preamble_length;
1148 tmp_params.preamble = info->params.preamble;
1149 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1150 tmp_params.data_bits = info->params.data_bits;
1151 tmp_params.stop_bits = info->params.stop_bits;
1152 tmp_params.parity = info->params.parity;
1153 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1154 return -EFAULT;
1155 return 0;
1156 }
1157
1158 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1159 {
1160 struct MGSL_PARAMS32 tmp_params;
1161
1162 DBGINFO(("%s set_params32\n", info->device_name));
1163 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1164 return -EFAULT;
1165
1166 spin_lock(&info->lock);
1167 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1168 info->base_clock = tmp_params.clock_speed;
1169 } else {
1170 info->params.mode = tmp_params.mode;
1171 info->params.loopback = tmp_params.loopback;
1172 info->params.flags = tmp_params.flags;
1173 info->params.encoding = tmp_params.encoding;
1174 info->params.clock_speed = tmp_params.clock_speed;
1175 info->params.addr_filter = tmp_params.addr_filter;
1176 info->params.crc_type = tmp_params.crc_type;
1177 info->params.preamble_length = tmp_params.preamble_length;
1178 info->params.preamble = tmp_params.preamble;
1179 info->params.data_rate = tmp_params.data_rate;
1180 info->params.data_bits = tmp_params.data_bits;
1181 info->params.stop_bits = tmp_params.stop_bits;
1182 info->params.parity = tmp_params.parity;
1183 }
1184 spin_unlock(&info->lock);
1185
1186 program_hw(info);
1187
1188 return 0;
1189 }
1190
1191 static long slgt_compat_ioctl(struct tty_struct *tty,
1192 unsigned int cmd, unsigned long arg)
1193 {
1194 struct slgt_info *info = tty->driver_data;
1195 int rc = -ENOIOCTLCMD;
1196
1197 if (sanity_check(info, tty->name, "compat_ioctl"))
1198 return -ENODEV;
1199 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1200
1201 switch (cmd) {
1202
1203 case MGSL_IOCSPARAMS32:
1204 rc = set_params32(info, compat_ptr(arg));
1205 break;
1206
1207 case MGSL_IOCGPARAMS32:
1208 rc = get_params32(info, compat_ptr(arg));
1209 break;
1210
1211 case MGSL_IOCGPARAMS:
1212 case MGSL_IOCSPARAMS:
1213 case MGSL_IOCGTXIDLE:
1214 case MGSL_IOCGSTATS:
1215 case MGSL_IOCWAITEVENT:
1216 case MGSL_IOCGIF:
1217 case MGSL_IOCSGPIO:
1218 case MGSL_IOCGGPIO:
1219 case MGSL_IOCWAITGPIO:
1220 case MGSL_IOCGXSYNC:
1221 case MGSL_IOCGXCTRL:
1222 case MGSL_IOCSTXIDLE:
1223 case MGSL_IOCTXENABLE:
1224 case MGSL_IOCRXENABLE:
1225 case MGSL_IOCTXABORT:
1226 case TIOCMIWAIT:
1227 case MGSL_IOCSIF:
1228 case MGSL_IOCSXSYNC:
1229 case MGSL_IOCSXCTRL:
1230 rc = ioctl(tty, cmd, arg);
1231 break;
1232 }
1233
1234 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1235 return rc;
1236 }
1237 #else
1238 #define slgt_compat_ioctl NULL
1239 #endif /* ifdef CONFIG_COMPAT */
1240
1241 /*
1242 * proc fs support
1243 */
1244 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1245 {
1246 char stat_buf[30];
1247 unsigned long flags;
1248
1249 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1250 info->device_name, info->phys_reg_addr,
1251 info->irq_level, info->max_frame_size);
1252
1253 /* output current serial signal states */
1254 spin_lock_irqsave(&info->lock,flags);
1255 get_signals(info);
1256 spin_unlock_irqrestore(&info->lock,flags);
1257
1258 stat_buf[0] = 0;
1259 stat_buf[1] = 0;
1260 if (info->signals & SerialSignal_RTS)
1261 strcat(stat_buf, "|RTS");
1262 if (info->signals & SerialSignal_CTS)
1263 strcat(stat_buf, "|CTS");
1264 if (info->signals & SerialSignal_DTR)
1265 strcat(stat_buf, "|DTR");
1266 if (info->signals & SerialSignal_DSR)
1267 strcat(stat_buf, "|DSR");
1268 if (info->signals & SerialSignal_DCD)
1269 strcat(stat_buf, "|CD");
1270 if (info->signals & SerialSignal_RI)
1271 strcat(stat_buf, "|RI");
1272
1273 if (info->params.mode != MGSL_MODE_ASYNC) {
1274 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1275 info->icount.txok, info->icount.rxok);
1276 if (info->icount.txunder)
1277 seq_printf(m, " txunder:%d", info->icount.txunder);
1278 if (info->icount.txabort)
1279 seq_printf(m, " txabort:%d", info->icount.txabort);
1280 if (info->icount.rxshort)
1281 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1282 if (info->icount.rxlong)
1283 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1284 if (info->icount.rxover)
1285 seq_printf(m, " rxover:%d", info->icount.rxover);
1286 if (info->icount.rxcrc)
1287 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1288 } else {
1289 seq_printf(m, "\tASYNC tx:%d rx:%d",
1290 info->icount.tx, info->icount.rx);
1291 if (info->icount.frame)
1292 seq_printf(m, " fe:%d", info->icount.frame);
1293 if (info->icount.parity)
1294 seq_printf(m, " pe:%d", info->icount.parity);
1295 if (info->icount.brk)
1296 seq_printf(m, " brk:%d", info->icount.brk);
1297 if (info->icount.overrun)
1298 seq_printf(m, " oe:%d", info->icount.overrun);
1299 }
1300
1301 /* Append serial signal status to end */
1302 seq_printf(m, " %s\n", stat_buf+1);
1303
1304 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1305 info->tx_active,info->bh_requested,info->bh_running,
1306 info->pending_bh);
1307 }
1308
1309 /* Called to print information about devices
1310 */
1311 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1312 {
1313 struct slgt_info *info;
1314
1315 seq_puts(m, "synclink_gt driver\n");
1316
1317 info = slgt_device_list;
1318 while( info ) {
1319 line_info(m, info);
1320 info = info->next_device;
1321 }
1322 return 0;
1323 }
1324
1325 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1326 {
1327 return single_open(file, synclink_gt_proc_show, NULL);
1328 }
1329
1330 static const struct file_operations synclink_gt_proc_fops = {
1331 .owner = THIS_MODULE,
1332 .open = synclink_gt_proc_open,
1333 .read = seq_read,
1334 .llseek = seq_lseek,
1335 .release = single_release,
1336 };
1337
1338 /*
1339 * return count of bytes in transmit buffer
1340 */
1341 static int chars_in_buffer(struct tty_struct *tty)
1342 {
1343 struct slgt_info *info = tty->driver_data;
1344 int count;
1345 if (sanity_check(info, tty->name, "chars_in_buffer"))
1346 return 0;
1347 count = tbuf_bytes(info);
1348 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1349 return count;
1350 }
1351
1352 /*
1353 * signal remote device to throttle send data (our receive data)
1354 */
1355 static void throttle(struct tty_struct * tty)
1356 {
1357 struct slgt_info *info = tty->driver_data;
1358 unsigned long flags;
1359
1360 if (sanity_check(info, tty->name, "throttle"))
1361 return;
1362 DBGINFO(("%s throttle\n", info->device_name));
1363 if (I_IXOFF(tty))
1364 send_xchar(tty, STOP_CHAR(tty));
1365 if (tty->termios.c_cflag & CRTSCTS) {
1366 spin_lock_irqsave(&info->lock,flags);
1367 info->signals &= ~SerialSignal_RTS;
1368 set_signals(info);
1369 spin_unlock_irqrestore(&info->lock,flags);
1370 }
1371 }
1372
1373 /*
1374 * signal remote device to stop throttling send data (our receive data)
1375 */
1376 static void unthrottle(struct tty_struct * tty)
1377 {
1378 struct slgt_info *info = tty->driver_data;
1379 unsigned long flags;
1380
1381 if (sanity_check(info, tty->name, "unthrottle"))
1382 return;
1383 DBGINFO(("%s unthrottle\n", info->device_name));
1384 if (I_IXOFF(tty)) {
1385 if (info->x_char)
1386 info->x_char = 0;
1387 else
1388 send_xchar(tty, START_CHAR(tty));
1389 }
1390 if (tty->termios.c_cflag & CRTSCTS) {
1391 spin_lock_irqsave(&info->lock,flags);
1392 info->signals |= SerialSignal_RTS;
1393 set_signals(info);
1394 spin_unlock_irqrestore(&info->lock,flags);
1395 }
1396 }
1397
1398 /*
1399 * set or clear transmit break condition
1400 * break_state -1=set break condition, 0=clear
1401 */
1402 static int set_break(struct tty_struct *tty, int break_state)
1403 {
1404 struct slgt_info *info = tty->driver_data;
1405 unsigned short value;
1406 unsigned long flags;
1407
1408 if (sanity_check(info, tty->name, "set_break"))
1409 return -EINVAL;
1410 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1411
1412 spin_lock_irqsave(&info->lock,flags);
1413 value = rd_reg16(info, TCR);
1414 if (break_state == -1)
1415 value |= BIT6;
1416 else
1417 value &= ~BIT6;
1418 wr_reg16(info, TCR, value);
1419 spin_unlock_irqrestore(&info->lock,flags);
1420 return 0;
1421 }
1422
1423 #if SYNCLINK_GENERIC_HDLC
1424
1425 /**
1426 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1427 * set encoding and frame check sequence (FCS) options
1428 *
1429 * dev pointer to network device structure
1430 * encoding serial encoding setting
1431 * parity FCS setting
1432 *
1433 * returns 0 if success, otherwise error code
1434 */
1435 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1436 unsigned short parity)
1437 {
1438 struct slgt_info *info = dev_to_port(dev);
1439 unsigned char new_encoding;
1440 unsigned short new_crctype;
1441
1442 /* return error if TTY interface open */
1443 if (info->port.count)
1444 return -EBUSY;
1445
1446 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1447
1448 switch (encoding)
1449 {
1450 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1451 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1452 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1453 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1454 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1455 default: return -EINVAL;
1456 }
1457
1458 switch (parity)
1459 {
1460 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1461 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1462 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1463 default: return -EINVAL;
1464 }
1465
1466 info->params.encoding = new_encoding;
1467 info->params.crc_type = new_crctype;
1468
1469 /* if network interface up, reprogram hardware */
1470 if (info->netcount)
1471 program_hw(info);
1472
1473 return 0;
1474 }
1475
1476 /**
1477 * called by generic HDLC layer to send frame
1478 *
1479 * skb socket buffer containing HDLC frame
1480 * dev pointer to network device structure
1481 */
1482 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1483 struct net_device *dev)
1484 {
1485 struct slgt_info *info = dev_to_port(dev);
1486 unsigned long flags;
1487
1488 DBGINFO(("%s hdlc_xmit\n", dev->name));
1489
1490 if (!skb->len)
1491 return NETDEV_TX_OK;
1492
1493 /* stop sending until this frame completes */
1494 netif_stop_queue(dev);
1495
1496 /* update network statistics */
1497 dev->stats.tx_packets++;
1498 dev->stats.tx_bytes += skb->len;
1499
1500 /* save start time for transmit timeout detection */
1501 dev->trans_start = jiffies;
1502
1503 spin_lock_irqsave(&info->lock, flags);
1504 tx_load(info, skb->data, skb->len);
1505 spin_unlock_irqrestore(&info->lock, flags);
1506
1507 /* done with socket buffer, so free it */
1508 dev_kfree_skb(skb);
1509
1510 return NETDEV_TX_OK;
1511 }
1512
1513 /**
1514 * called by network layer when interface enabled
1515 * claim resources and initialize hardware
1516 *
1517 * dev pointer to network device structure
1518 *
1519 * returns 0 if success, otherwise error code
1520 */
1521 static int hdlcdev_open(struct net_device *dev)
1522 {
1523 struct slgt_info *info = dev_to_port(dev);
1524 int rc;
1525 unsigned long flags;
1526
1527 if (!try_module_get(THIS_MODULE))
1528 return -EBUSY;
1529
1530 DBGINFO(("%s hdlcdev_open\n", dev->name));
1531
1532 /* generic HDLC layer open processing */
1533 rc = hdlc_open(dev);
1534 if (rc)
1535 return rc;
1536
1537 /* arbitrate between network and tty opens */
1538 spin_lock_irqsave(&info->netlock, flags);
1539 if (info->port.count != 0 || info->netcount != 0) {
1540 DBGINFO(("%s hdlc_open busy\n", dev->name));
1541 spin_unlock_irqrestore(&info->netlock, flags);
1542 return -EBUSY;
1543 }
1544 info->netcount=1;
1545 spin_unlock_irqrestore(&info->netlock, flags);
1546
1547 /* claim resources and init adapter */
1548 if ((rc = startup(info)) != 0) {
1549 spin_lock_irqsave(&info->netlock, flags);
1550 info->netcount=0;
1551 spin_unlock_irqrestore(&info->netlock, flags);
1552 return rc;
1553 }
1554
1555 /* assert RTS and DTR, apply hardware settings */
1556 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1557 program_hw(info);
1558
1559 /* enable network layer transmit */
1560 dev->trans_start = jiffies;
1561 netif_start_queue(dev);
1562
1563 /* inform generic HDLC layer of current DCD status */
1564 spin_lock_irqsave(&info->lock, flags);
1565 get_signals(info);
1566 spin_unlock_irqrestore(&info->lock, flags);
1567 if (info->signals & SerialSignal_DCD)
1568 netif_carrier_on(dev);
1569 else
1570 netif_carrier_off(dev);
1571 return 0;
1572 }
1573
1574 /**
1575 * called by network layer when interface is disabled
1576 * shutdown hardware and release resources
1577 *
1578 * dev pointer to network device structure
1579 *
1580 * returns 0 if success, otherwise error code
1581 */
1582 static int hdlcdev_close(struct net_device *dev)
1583 {
1584 struct slgt_info *info = dev_to_port(dev);
1585 unsigned long flags;
1586
1587 DBGINFO(("%s hdlcdev_close\n", dev->name));
1588
1589 netif_stop_queue(dev);
1590
1591 /* shutdown adapter and release resources */
1592 shutdown(info);
1593
1594 hdlc_close(dev);
1595
1596 spin_lock_irqsave(&info->netlock, flags);
1597 info->netcount=0;
1598 spin_unlock_irqrestore(&info->netlock, flags);
1599
1600 module_put(THIS_MODULE);
1601 return 0;
1602 }
1603
1604 /**
1605 * called by network layer to process IOCTL call to network device
1606 *
1607 * dev pointer to network device structure
1608 * ifr pointer to network interface request structure
1609 * cmd IOCTL command code
1610 *
1611 * returns 0 if success, otherwise error code
1612 */
1613 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1614 {
1615 const size_t size = sizeof(sync_serial_settings);
1616 sync_serial_settings new_line;
1617 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1618 struct slgt_info *info = dev_to_port(dev);
1619 unsigned int flags;
1620
1621 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1622
1623 /* return error if TTY interface open */
1624 if (info->port.count)
1625 return -EBUSY;
1626
1627 if (cmd != SIOCWANDEV)
1628 return hdlc_ioctl(dev, ifr, cmd);
1629
1630 memset(&new_line, 0, sizeof(new_line));
1631
1632 switch(ifr->ifr_settings.type) {
1633 case IF_GET_IFACE: /* return current sync_serial_settings */
1634
1635 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1636 if (ifr->ifr_settings.size < size) {
1637 ifr->ifr_settings.size = size; /* data size wanted */
1638 return -ENOBUFS;
1639 }
1640
1641 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1642 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1643 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1644 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1645
1646 switch (flags){
1647 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1648 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1649 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1650 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1651 default: new_line.clock_type = CLOCK_DEFAULT;
1652 }
1653
1654 new_line.clock_rate = info->params.clock_speed;
1655 new_line.loopback = info->params.loopback ? 1:0;
1656
1657 if (copy_to_user(line, &new_line, size))
1658 return -EFAULT;
1659 return 0;
1660
1661 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1662
1663 if(!capable(CAP_NET_ADMIN))
1664 return -EPERM;
1665 if (copy_from_user(&new_line, line, size))
1666 return -EFAULT;
1667
1668 switch (new_line.clock_type)
1669 {
1670 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1671 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1672 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1673 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1674 case CLOCK_DEFAULT: flags = info->params.flags &
1675 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1676 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1677 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1678 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1679 default: return -EINVAL;
1680 }
1681
1682 if (new_line.loopback != 0 && new_line.loopback != 1)
1683 return -EINVAL;
1684
1685 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1686 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1687 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1688 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1689 info->params.flags |= flags;
1690
1691 info->params.loopback = new_line.loopback;
1692
1693 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1694 info->params.clock_speed = new_line.clock_rate;
1695 else
1696 info->params.clock_speed = 0;
1697
1698 /* if network interface up, reprogram hardware */
1699 if (info->netcount)
1700 program_hw(info);
1701 return 0;
1702
1703 default:
1704 return hdlc_ioctl(dev, ifr, cmd);
1705 }
1706 }
1707
1708 /**
1709 * called by network layer when transmit timeout is detected
1710 *
1711 * dev pointer to network device structure
1712 */
1713 static void hdlcdev_tx_timeout(struct net_device *dev)
1714 {
1715 struct slgt_info *info = dev_to_port(dev);
1716 unsigned long flags;
1717
1718 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1719
1720 dev->stats.tx_errors++;
1721 dev->stats.tx_aborted_errors++;
1722
1723 spin_lock_irqsave(&info->lock,flags);
1724 tx_stop(info);
1725 spin_unlock_irqrestore(&info->lock,flags);
1726
1727 netif_wake_queue(dev);
1728 }
1729
1730 /**
1731 * called by device driver when transmit completes
1732 * reenable network layer transmit if stopped
1733 *
1734 * info pointer to device instance information
1735 */
1736 static void hdlcdev_tx_done(struct slgt_info *info)
1737 {
1738 if (netif_queue_stopped(info->netdev))
1739 netif_wake_queue(info->netdev);
1740 }
1741
1742 /**
1743 * called by device driver when frame received
1744 * pass frame to network layer
1745 *
1746 * info pointer to device instance information
1747 * buf pointer to buffer contianing frame data
1748 * size count of data bytes in buf
1749 */
1750 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1751 {
1752 struct sk_buff *skb = dev_alloc_skb(size);
1753 struct net_device *dev = info->netdev;
1754
1755 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1756
1757 if (skb == NULL) {
1758 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1759 dev->stats.rx_dropped++;
1760 return;
1761 }
1762
1763 memcpy(skb_put(skb, size), buf, size);
1764
1765 skb->protocol = hdlc_type_trans(skb, dev);
1766
1767 dev->stats.rx_packets++;
1768 dev->stats.rx_bytes += size;
1769
1770 netif_rx(skb);
1771 }
1772
1773 static const struct net_device_ops hdlcdev_ops = {
1774 .ndo_open = hdlcdev_open,
1775 .ndo_stop = hdlcdev_close,
1776 .ndo_change_mtu = hdlc_change_mtu,
1777 .ndo_start_xmit = hdlc_start_xmit,
1778 .ndo_do_ioctl = hdlcdev_ioctl,
1779 .ndo_tx_timeout = hdlcdev_tx_timeout,
1780 };
1781
1782 /**
1783 * called by device driver when adding device instance
1784 * do generic HDLC initialization
1785 *
1786 * info pointer to device instance information
1787 *
1788 * returns 0 if success, otherwise error code
1789 */
1790 static int hdlcdev_init(struct slgt_info *info)
1791 {
1792 int rc;
1793 struct net_device *dev;
1794 hdlc_device *hdlc;
1795
1796 /* allocate and initialize network and HDLC layer objects */
1797
1798 dev = alloc_hdlcdev(info);
1799 if (!dev) {
1800 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1801 return -ENOMEM;
1802 }
1803
1804 /* for network layer reporting purposes only */
1805 dev->mem_start = info->phys_reg_addr;
1806 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1807 dev->irq = info->irq_level;
1808
1809 /* network layer callbacks and settings */
1810 dev->netdev_ops = &hdlcdev_ops;
1811 dev->watchdog_timeo = 10 * HZ;
1812 dev->tx_queue_len = 50;
1813
1814 /* generic HDLC layer callbacks and settings */
1815 hdlc = dev_to_hdlc(dev);
1816 hdlc->attach = hdlcdev_attach;
1817 hdlc->xmit = hdlcdev_xmit;
1818
1819 /* register objects with HDLC layer */
1820 rc = register_hdlc_device(dev);
1821 if (rc) {
1822 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1823 free_netdev(dev);
1824 return rc;
1825 }
1826
1827 info->netdev = dev;
1828 return 0;
1829 }
1830
1831 /**
1832 * called by device driver when removing device instance
1833 * do generic HDLC cleanup
1834 *
1835 * info pointer to device instance information
1836 */
1837 static void hdlcdev_exit(struct slgt_info *info)
1838 {
1839 unregister_hdlc_device(info->netdev);
1840 free_netdev(info->netdev);
1841 info->netdev = NULL;
1842 }
1843
1844 #endif /* ifdef CONFIG_HDLC */
1845
1846 /*
1847 * get async data from rx DMA buffers
1848 */
1849 static void rx_async(struct slgt_info *info)
1850 {
1851 struct mgsl_icount *icount = &info->icount;
1852 unsigned int start, end;
1853 unsigned char *p;
1854 unsigned char status;
1855 struct slgt_desc *bufs = info->rbufs;
1856 int i, count;
1857 int chars = 0;
1858 int stat;
1859 unsigned char ch;
1860
1861 start = end = info->rbuf_current;
1862
1863 while(desc_complete(bufs[end])) {
1864 count = desc_count(bufs[end]) - info->rbuf_index;
1865 p = bufs[end].buf + info->rbuf_index;
1866
1867 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1868 DBGDATA(info, p, count, "rx");
1869
1870 for(i=0 ; i < count; i+=2, p+=2) {
1871 ch = *p;
1872 icount->rx++;
1873
1874 stat = 0;
1875
1876 status = *(p + 1) & (BIT1 + BIT0);
1877 if (status) {
1878 if (status & BIT1)
1879 icount->parity++;
1880 else if (status & BIT0)
1881 icount->frame++;
1882 /* discard char if tty control flags say so */
1883 if (status & info->ignore_status_mask)
1884 continue;
1885 if (status & BIT1)
1886 stat = TTY_PARITY;
1887 else if (status & BIT0)
1888 stat = TTY_FRAME;
1889 }
1890 tty_insert_flip_char(&info->port, ch, stat);
1891 chars++;
1892 }
1893
1894 if (i < count) {
1895 /* receive buffer not completed */
1896 info->rbuf_index += i;
1897 mod_timer(&info->rx_timer, jiffies + 1);
1898 break;
1899 }
1900
1901 info->rbuf_index = 0;
1902 free_rbufs(info, end, end);
1903
1904 if (++end == info->rbuf_count)
1905 end = 0;
1906
1907 /* if entire list searched then no frame available */
1908 if (end == start)
1909 break;
1910 }
1911
1912 if (chars)
1913 tty_flip_buffer_push(&info->port);
1914 }
1915
1916 /*
1917 * return next bottom half action to perform
1918 */
1919 static int bh_action(struct slgt_info *info)
1920 {
1921 unsigned long flags;
1922 int rc;
1923
1924 spin_lock_irqsave(&info->lock,flags);
1925
1926 if (info->pending_bh & BH_RECEIVE) {
1927 info->pending_bh &= ~BH_RECEIVE;
1928 rc = BH_RECEIVE;
1929 } else if (info->pending_bh & BH_TRANSMIT) {
1930 info->pending_bh &= ~BH_TRANSMIT;
1931 rc = BH_TRANSMIT;
1932 } else if (info->pending_bh & BH_STATUS) {
1933 info->pending_bh &= ~BH_STATUS;
1934 rc = BH_STATUS;
1935 } else {
1936 /* Mark BH routine as complete */
1937 info->bh_running = false;
1938 info->bh_requested = false;
1939 rc = 0;
1940 }
1941
1942 spin_unlock_irqrestore(&info->lock,flags);
1943
1944 return rc;
1945 }
1946
1947 /*
1948 * perform bottom half processing
1949 */
1950 static void bh_handler(struct work_struct *work)
1951 {
1952 struct slgt_info *info = container_of(work, struct slgt_info, task);
1953 int action;
1954
1955 info->bh_running = true;
1956
1957 while((action = bh_action(info))) {
1958 switch (action) {
1959 case BH_RECEIVE:
1960 DBGBH(("%s bh receive\n", info->device_name));
1961 switch(info->params.mode) {
1962 case MGSL_MODE_ASYNC:
1963 rx_async(info);
1964 break;
1965 case MGSL_MODE_HDLC:
1966 while(rx_get_frame(info));
1967 break;
1968 case MGSL_MODE_RAW:
1969 case MGSL_MODE_MONOSYNC:
1970 case MGSL_MODE_BISYNC:
1971 case MGSL_MODE_XSYNC:
1972 while(rx_get_buf(info));
1973 break;
1974 }
1975 /* restart receiver if rx DMA buffers exhausted */
1976 if (info->rx_restart)
1977 rx_start(info);
1978 break;
1979 case BH_TRANSMIT:
1980 bh_transmit(info);
1981 break;
1982 case BH_STATUS:
1983 DBGBH(("%s bh status\n", info->device_name));
1984 info->ri_chkcount = 0;
1985 info->dsr_chkcount = 0;
1986 info->dcd_chkcount = 0;
1987 info->cts_chkcount = 0;
1988 break;
1989 default:
1990 DBGBH(("%s unknown action\n", info->device_name));
1991 break;
1992 }
1993 }
1994 DBGBH(("%s bh_handler exit\n", info->device_name));
1995 }
1996
1997 static void bh_transmit(struct slgt_info *info)
1998 {
1999 struct tty_struct *tty = info->port.tty;
2000
2001 DBGBH(("%s bh_transmit\n", info->device_name));
2002 if (tty)
2003 tty_wakeup(tty);
2004 }
2005
2006 static void dsr_change(struct slgt_info *info, unsigned short status)
2007 {
2008 if (status & BIT3) {
2009 info->signals |= SerialSignal_DSR;
2010 info->input_signal_events.dsr_up++;
2011 } else {
2012 info->signals &= ~SerialSignal_DSR;
2013 info->input_signal_events.dsr_down++;
2014 }
2015 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2016 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2017 slgt_irq_off(info, IRQ_DSR);
2018 return;
2019 }
2020 info->icount.dsr++;
2021 wake_up_interruptible(&info->status_event_wait_q);
2022 wake_up_interruptible(&info->event_wait_q);
2023 info->pending_bh |= BH_STATUS;
2024 }
2025
2026 static void cts_change(struct slgt_info *info, unsigned short status)
2027 {
2028 if (status & BIT2) {
2029 info->signals |= SerialSignal_CTS;
2030 info->input_signal_events.cts_up++;
2031 } else {
2032 info->signals &= ~SerialSignal_CTS;
2033 info->input_signal_events.cts_down++;
2034 }
2035 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2036 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2037 slgt_irq_off(info, IRQ_CTS);
2038 return;
2039 }
2040 info->icount.cts++;
2041 wake_up_interruptible(&info->status_event_wait_q);
2042 wake_up_interruptible(&info->event_wait_q);
2043 info->pending_bh |= BH_STATUS;
2044
2045 if (tty_port_cts_enabled(&info->port)) {
2046 if (info->port.tty) {
2047 if (info->port.tty->hw_stopped) {
2048 if (info->signals & SerialSignal_CTS) {
2049 info->port.tty->hw_stopped = 0;
2050 info->pending_bh |= BH_TRANSMIT;
2051 return;
2052 }
2053 } else {
2054 if (!(info->signals & SerialSignal_CTS))
2055 info->port.tty->hw_stopped = 1;
2056 }
2057 }
2058 }
2059 }
2060
2061 static void dcd_change(struct slgt_info *info, unsigned short status)
2062 {
2063 if (status & BIT1) {
2064 info->signals |= SerialSignal_DCD;
2065 info->input_signal_events.dcd_up++;
2066 } else {
2067 info->signals &= ~SerialSignal_DCD;
2068 info->input_signal_events.dcd_down++;
2069 }
2070 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2071 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2072 slgt_irq_off(info, IRQ_DCD);
2073 return;
2074 }
2075 info->icount.dcd++;
2076 #if SYNCLINK_GENERIC_HDLC
2077 if (info->netcount) {
2078 if (info->signals & SerialSignal_DCD)
2079 netif_carrier_on(info->netdev);
2080 else
2081 netif_carrier_off(info->netdev);
2082 }
2083 #endif
2084 wake_up_interruptible(&info->status_event_wait_q);
2085 wake_up_interruptible(&info->event_wait_q);
2086 info->pending_bh |= BH_STATUS;
2087
2088 if (info->port.flags & ASYNC_CHECK_CD) {
2089 if (info->signals & SerialSignal_DCD)
2090 wake_up_interruptible(&info->port.open_wait);
2091 else {
2092 if (info->port.tty)
2093 tty_hangup(info->port.tty);
2094 }
2095 }
2096 }
2097
2098 static void ri_change(struct slgt_info *info, unsigned short status)
2099 {
2100 if (status & BIT0) {
2101 info->signals |= SerialSignal_RI;
2102 info->input_signal_events.ri_up++;
2103 } else {
2104 info->signals &= ~SerialSignal_RI;
2105 info->input_signal_events.ri_down++;
2106 }
2107 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2108 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2109 slgt_irq_off(info, IRQ_RI);
2110 return;
2111 }
2112 info->icount.rng++;
2113 wake_up_interruptible(&info->status_event_wait_q);
2114 wake_up_interruptible(&info->event_wait_q);
2115 info->pending_bh |= BH_STATUS;
2116 }
2117
2118 static void isr_rxdata(struct slgt_info *info)
2119 {
2120 unsigned int count = info->rbuf_fill_count;
2121 unsigned int i = info->rbuf_fill_index;
2122 unsigned short reg;
2123
2124 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2125 reg = rd_reg16(info, RDR);
2126 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2127 if (desc_complete(info->rbufs[i])) {
2128 /* all buffers full */
2129 rx_stop(info);
2130 info->rx_restart = 1;
2131 continue;
2132 }
2133 info->rbufs[i].buf[count++] = (unsigned char)reg;
2134 /* async mode saves status byte to buffer for each data byte */
2135 if (info->params.mode == MGSL_MODE_ASYNC)
2136 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2137 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2138 /* buffer full or end of frame */
2139 set_desc_count(info->rbufs[i], count);
2140 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2141 info->rbuf_fill_count = count = 0;
2142 if (++i == info->rbuf_count)
2143 i = 0;
2144 info->pending_bh |= BH_RECEIVE;
2145 }
2146 }
2147
2148 info->rbuf_fill_index = i;
2149 info->rbuf_fill_count = count;
2150 }
2151
2152 static void isr_serial(struct slgt_info *info)
2153 {
2154 unsigned short status = rd_reg16(info, SSR);
2155
2156 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2157
2158 wr_reg16(info, SSR, status); /* clear pending */
2159
2160 info->irq_occurred = true;
2161
2162 if (info->params.mode == MGSL_MODE_ASYNC) {
2163 if (status & IRQ_TXIDLE) {
2164 if (info->tx_active)
2165 isr_txeom(info, status);
2166 }
2167 if (info->rx_pio && (status & IRQ_RXDATA))
2168 isr_rxdata(info);
2169 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2170 info->icount.brk++;
2171 /* process break detection if tty control allows */
2172 if (info->port.tty) {
2173 if (!(status & info->ignore_status_mask)) {
2174 if (info->read_status_mask & MASK_BREAK) {
2175 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2176 if (info->port.flags & ASYNC_SAK)
2177 do_SAK(info->port.tty);
2178 }
2179 }
2180 }
2181 }
2182 } else {
2183 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2184 isr_txeom(info, status);
2185 if (info->rx_pio && (status & IRQ_RXDATA))
2186 isr_rxdata(info);
2187 if (status & IRQ_RXIDLE) {
2188 if (status & RXIDLE)
2189 info->icount.rxidle++;
2190 else
2191 info->icount.exithunt++;
2192 wake_up_interruptible(&info->event_wait_q);
2193 }
2194
2195 if (status & IRQ_RXOVER)
2196 rx_start(info);
2197 }
2198
2199 if (status & IRQ_DSR)
2200 dsr_change(info, status);
2201 if (status & IRQ_CTS)
2202 cts_change(info, status);
2203 if (status & IRQ_DCD)
2204 dcd_change(info, status);
2205 if (status & IRQ_RI)
2206 ri_change(info, status);
2207 }
2208
2209 static void isr_rdma(struct slgt_info *info)
2210 {
2211 unsigned int status = rd_reg32(info, RDCSR);
2212
2213 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2214
2215 /* RDCSR (rx DMA control/status)
2216 *
2217 * 31..07 reserved
2218 * 06 save status byte to DMA buffer
2219 * 05 error
2220 * 04 eol (end of list)
2221 * 03 eob (end of buffer)
2222 * 02 IRQ enable
2223 * 01 reset
2224 * 00 enable
2225 */
2226 wr_reg32(info, RDCSR, status); /* clear pending */
2227
2228 if (status & (BIT5 + BIT4)) {
2229 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2230 info->rx_restart = true;
2231 }
2232 info->pending_bh |= BH_RECEIVE;
2233 }
2234
2235 static void isr_tdma(struct slgt_info *info)
2236 {
2237 unsigned int status = rd_reg32(info, TDCSR);
2238
2239 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2240
2241 /* TDCSR (tx DMA control/status)
2242 *
2243 * 31..06 reserved
2244 * 05 error
2245 * 04 eol (end of list)
2246 * 03 eob (end of buffer)
2247 * 02 IRQ enable
2248 * 01 reset
2249 * 00 enable
2250 */
2251 wr_reg32(info, TDCSR, status); /* clear pending */
2252
2253 if (status & (BIT5 + BIT4 + BIT3)) {
2254 // another transmit buffer has completed
2255 // run bottom half to get more send data from user
2256 info->pending_bh |= BH_TRANSMIT;
2257 }
2258 }
2259
2260 /*
2261 * return true if there are unsent tx DMA buffers, otherwise false
2262 *
2263 * if there are unsent buffers then info->tbuf_start
2264 * is set to index of first unsent buffer
2265 */
2266 static bool unsent_tbufs(struct slgt_info *info)
2267 {
2268 unsigned int i = info->tbuf_current;
2269 bool rc = false;
2270
2271 /*
2272 * search backwards from last loaded buffer (precedes tbuf_current)
2273 * for first unsent buffer (desc_count > 0)
2274 */
2275
2276 do {
2277 if (i)
2278 i--;
2279 else
2280 i = info->tbuf_count - 1;
2281 if (!desc_count(info->tbufs[i]))
2282 break;
2283 info->tbuf_start = i;
2284 rc = true;
2285 } while (i != info->tbuf_current);
2286
2287 return rc;
2288 }
2289
2290 static void isr_txeom(struct slgt_info *info, unsigned short status)
2291 {
2292 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2293
2294 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2295 tdma_reset(info);
2296 if (status & IRQ_TXUNDER) {
2297 unsigned short val = rd_reg16(info, TCR);
2298 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2299 wr_reg16(info, TCR, val); /* clear reset bit */
2300 }
2301
2302 if (info->tx_active) {
2303 if (info->params.mode != MGSL_MODE_ASYNC) {
2304 if (status & IRQ_TXUNDER)
2305 info->icount.txunder++;
2306 else if (status & IRQ_TXIDLE)
2307 info->icount.txok++;
2308 }
2309
2310 if (unsent_tbufs(info)) {
2311 tx_start(info);
2312 update_tx_timer(info);
2313 return;
2314 }
2315 info->tx_active = false;
2316
2317 del_timer(&info->tx_timer);
2318
2319 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2320 info->signals &= ~SerialSignal_RTS;
2321 info->drop_rts_on_tx_done = false;
2322 set_signals(info);
2323 }
2324
2325 #if SYNCLINK_GENERIC_HDLC
2326 if (info->netcount)
2327 hdlcdev_tx_done(info);
2328 else
2329 #endif
2330 {
2331 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2332 tx_stop(info);
2333 return;
2334 }
2335 info->pending_bh |= BH_TRANSMIT;
2336 }
2337 }
2338 }
2339
2340 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2341 {
2342 struct cond_wait *w, *prev;
2343
2344 /* wake processes waiting for specific transitions */
2345 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2346 if (w->data & changed) {
2347 w->data = state;
2348 wake_up_interruptible(&w->q);
2349 if (prev != NULL)
2350 prev->next = w->next;
2351 else
2352 info->gpio_wait_q = w->next;
2353 } else
2354 prev = w;
2355 }
2356 }
2357
2358 /* interrupt service routine
2359 *
2360 * irq interrupt number
2361 * dev_id device ID supplied during interrupt registration
2362 */
2363 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2364 {
2365 struct slgt_info *info = dev_id;
2366 unsigned int gsr;
2367 unsigned int i;
2368
2369 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2370
2371 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2372 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2373 info->irq_occurred = true;
2374 for(i=0; i < info->port_count ; i++) {
2375 if (info->port_array[i] == NULL)
2376 continue;
2377 spin_lock(&info->port_array[i]->lock);
2378 if (gsr & (BIT8 << i))
2379 isr_serial(info->port_array[i]);
2380 if (gsr & (BIT16 << (i*2)))
2381 isr_rdma(info->port_array[i]);
2382 if (gsr & (BIT17 << (i*2)))
2383 isr_tdma(info->port_array[i]);
2384 spin_unlock(&info->port_array[i]->lock);
2385 }
2386 }
2387
2388 if (info->gpio_present) {
2389 unsigned int state;
2390 unsigned int changed;
2391 spin_lock(&info->lock);
2392 while ((changed = rd_reg32(info, IOSR)) != 0) {
2393 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2394 /* read latched state of GPIO signals */
2395 state = rd_reg32(info, IOVR);
2396 /* clear pending GPIO interrupt bits */
2397 wr_reg32(info, IOSR, changed);
2398 for (i=0 ; i < info->port_count ; i++) {
2399 if (info->port_array[i] != NULL)
2400 isr_gpio(info->port_array[i], changed, state);
2401 }
2402 }
2403 spin_unlock(&info->lock);
2404 }
2405
2406 for(i=0; i < info->port_count ; i++) {
2407 struct slgt_info *port = info->port_array[i];
2408 if (port == NULL)
2409 continue;
2410 spin_lock(&port->lock);
2411 if ((port->port.count || port->netcount) &&
2412 port->pending_bh && !port->bh_running &&
2413 !port->bh_requested) {
2414 DBGISR(("%s bh queued\n", port->device_name));
2415 schedule_work(&port->task);
2416 port->bh_requested = true;
2417 }
2418 spin_unlock(&port->lock);
2419 }
2420
2421 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2422 return IRQ_HANDLED;
2423 }
2424
2425 static int startup(struct slgt_info *info)
2426 {
2427 DBGINFO(("%s startup\n", info->device_name));
2428
2429 if (info->port.flags & ASYNC_INITIALIZED)
2430 return 0;
2431
2432 if (!info->tx_buf) {
2433 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2434 if (!info->tx_buf) {
2435 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2436 return -ENOMEM;
2437 }
2438 }
2439
2440 info->pending_bh = 0;
2441
2442 memset(&info->icount, 0, sizeof(info->icount));
2443
2444 /* program hardware for current parameters */
2445 change_params(info);
2446
2447 if (info->port.tty)
2448 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2449
2450 info->port.flags |= ASYNC_INITIALIZED;
2451
2452 return 0;
2453 }
2454
2455 /*
2456 * called by close() and hangup() to shutdown hardware
2457 */
2458 static void shutdown(struct slgt_info *info)
2459 {
2460 unsigned long flags;
2461
2462 if (!(info->port.flags & ASYNC_INITIALIZED))
2463 return;
2464
2465 DBGINFO(("%s shutdown\n", info->device_name));
2466
2467 /* clear status wait queue because status changes */
2468 /* can't happen after shutting down the hardware */
2469 wake_up_interruptible(&info->status_event_wait_q);
2470 wake_up_interruptible(&info->event_wait_q);
2471
2472 del_timer_sync(&info->tx_timer);
2473 del_timer_sync(&info->rx_timer);
2474
2475 kfree(info->tx_buf);
2476 info->tx_buf = NULL;
2477
2478 spin_lock_irqsave(&info->lock,flags);
2479
2480 tx_stop(info);
2481 rx_stop(info);
2482
2483 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2484
2485 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2486 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2487 set_signals(info);
2488 }
2489
2490 flush_cond_wait(&info->gpio_wait_q);
2491
2492 spin_unlock_irqrestore(&info->lock,flags);
2493
2494 if (info->port.tty)
2495 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2496
2497 info->port.flags &= ~ASYNC_INITIALIZED;
2498 }
2499
2500 static void program_hw(struct slgt_info *info)
2501 {
2502 unsigned long flags;
2503
2504 spin_lock_irqsave(&info->lock,flags);
2505
2506 rx_stop(info);
2507 tx_stop(info);
2508
2509 if (info->params.mode != MGSL_MODE_ASYNC ||
2510 info->netcount)
2511 sync_mode(info);
2512 else
2513 async_mode(info);
2514
2515 set_signals(info);
2516
2517 info->dcd_chkcount = 0;
2518 info->cts_chkcount = 0;
2519 info->ri_chkcount = 0;
2520 info->dsr_chkcount = 0;
2521
2522 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2523 get_signals(info);
2524
2525 if (info->netcount ||
2526 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2527 rx_start(info);
2528
2529 spin_unlock_irqrestore(&info->lock,flags);
2530 }
2531
2532 /*
2533 * reconfigure adapter based on new parameters
2534 */
2535 static void change_params(struct slgt_info *info)
2536 {
2537 unsigned cflag;
2538 int bits_per_char;
2539
2540 if (!info->port.tty)
2541 return;
2542 DBGINFO(("%s change_params\n", info->device_name));
2543
2544 cflag = info->port.tty->termios.c_cflag;
2545
2546 /* if B0 rate (hangup) specified then negate RTS and DTR */
2547 /* otherwise assert RTS and DTR */
2548 if (cflag & CBAUD)
2549 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2550 else
2551 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2552
2553 /* byte size and parity */
2554
2555 switch (cflag & CSIZE) {
2556 case CS5: info->params.data_bits = 5; break;
2557 case CS6: info->params.data_bits = 6; break;
2558 case CS7: info->params.data_bits = 7; break;
2559 case CS8: info->params.data_bits = 8; break;
2560 default: info->params.data_bits = 7; break;
2561 }
2562
2563 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2564
2565 if (cflag & PARENB)
2566 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2567 else
2568 info->params.parity = ASYNC_PARITY_NONE;
2569
2570 /* calculate number of jiffies to transmit a full
2571 * FIFO (32 bytes) at specified data rate
2572 */
2573 bits_per_char = info->params.data_bits +
2574 info->params.stop_bits + 1;
2575
2576 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2577
2578 if (info->params.data_rate) {
2579 info->timeout = (32*HZ*bits_per_char) /
2580 info->params.data_rate;
2581 }
2582 info->timeout += HZ/50; /* Add .02 seconds of slop */
2583
2584 if (cflag & CRTSCTS)
2585 info->port.flags |= ASYNC_CTS_FLOW;
2586 else
2587 info->port.flags &= ~ASYNC_CTS_FLOW;
2588
2589 if (cflag & CLOCAL)
2590 info->port.flags &= ~ASYNC_CHECK_CD;
2591 else
2592 info->port.flags |= ASYNC_CHECK_CD;
2593
2594 /* process tty input control flags */
2595
2596 info->read_status_mask = IRQ_RXOVER;
2597 if (I_INPCK(info->port.tty))
2598 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2599 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2600 info->read_status_mask |= MASK_BREAK;
2601 if (I_IGNPAR(info->port.tty))
2602 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2603 if (I_IGNBRK(info->port.tty)) {
2604 info->ignore_status_mask |= MASK_BREAK;
2605 /* If ignoring parity and break indicators, ignore
2606 * overruns too. (For real raw support).
2607 */
2608 if (I_IGNPAR(info->port.tty))
2609 info->ignore_status_mask |= MASK_OVERRUN;
2610 }
2611
2612 program_hw(info);
2613 }
2614
2615 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2616 {
2617 DBGINFO(("%s get_stats\n", info->device_name));
2618 if (!user_icount) {
2619 memset(&info->icount, 0, sizeof(info->icount));
2620 } else {
2621 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2622 return -EFAULT;
2623 }
2624 return 0;
2625 }
2626
2627 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2628 {
2629 DBGINFO(("%s get_params\n", info->device_name));
2630 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2631 return -EFAULT;
2632 return 0;
2633 }
2634
2635 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2636 {
2637 unsigned long flags;
2638 MGSL_PARAMS tmp_params;
2639
2640 DBGINFO(("%s set_params\n", info->device_name));
2641 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2642 return -EFAULT;
2643
2644 spin_lock_irqsave(&info->lock, flags);
2645 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2646 info->base_clock = tmp_params.clock_speed;
2647 else
2648 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2649 spin_unlock_irqrestore(&info->lock, flags);
2650
2651 program_hw(info);
2652
2653 return 0;
2654 }
2655
2656 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2657 {
2658 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2659 if (put_user(info->idle_mode, idle_mode))
2660 return -EFAULT;
2661 return 0;
2662 }
2663
2664 static int set_txidle(struct slgt_info *info, int idle_mode)
2665 {
2666 unsigned long flags;
2667 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2668 spin_lock_irqsave(&info->lock,flags);
2669 info->idle_mode = idle_mode;
2670 if (info->params.mode != MGSL_MODE_ASYNC)
2671 tx_set_idle(info);
2672 spin_unlock_irqrestore(&info->lock,flags);
2673 return 0;
2674 }
2675
2676 static int tx_enable(struct slgt_info *info, int enable)
2677 {
2678 unsigned long flags;
2679 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2680 spin_lock_irqsave(&info->lock,flags);
2681 if (enable) {
2682 if (!info->tx_enabled)
2683 tx_start(info);
2684 } else {
2685 if (info->tx_enabled)
2686 tx_stop(info);
2687 }
2688 spin_unlock_irqrestore(&info->lock,flags);
2689 return 0;
2690 }
2691
2692 /*
2693 * abort transmit HDLC frame
2694 */
2695 static int tx_abort(struct slgt_info *info)
2696 {
2697 unsigned long flags;
2698 DBGINFO(("%s tx_abort\n", info->device_name));
2699 spin_lock_irqsave(&info->lock,flags);
2700 tdma_reset(info);
2701 spin_unlock_irqrestore(&info->lock,flags);
2702 return 0;
2703 }
2704
2705 static int rx_enable(struct slgt_info *info, int enable)
2706 {
2707 unsigned long flags;
2708 unsigned int rbuf_fill_level;
2709 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2710 spin_lock_irqsave(&info->lock,flags);
2711 /*
2712 * enable[31..16] = receive DMA buffer fill level
2713 * 0 = noop (leave fill level unchanged)
2714 * fill level must be multiple of 4 and <= buffer size
2715 */
2716 rbuf_fill_level = ((unsigned int)enable) >> 16;
2717 if (rbuf_fill_level) {
2718 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2719 spin_unlock_irqrestore(&info->lock, flags);
2720 return -EINVAL;
2721 }
2722 info->rbuf_fill_level = rbuf_fill_level;
2723 if (rbuf_fill_level < 128)
2724 info->rx_pio = 1; /* PIO mode */
2725 else
2726 info->rx_pio = 0; /* DMA mode */
2727 rx_stop(info); /* restart receiver to use new fill level */
2728 }
2729
2730 /*
2731 * enable[1..0] = receiver enable command
2732 * 0 = disable
2733 * 1 = enable
2734 * 2 = enable or force hunt mode if already enabled
2735 */
2736 enable &= 3;
2737 if (enable) {
2738 if (!info->rx_enabled)
2739 rx_start(info);
2740 else if (enable == 2) {
2741 /* force hunt mode (write 1 to RCR[3]) */
2742 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2743 }
2744 } else {
2745 if (info->rx_enabled)
2746 rx_stop(info);
2747 }
2748 spin_unlock_irqrestore(&info->lock,flags);
2749 return 0;
2750 }
2751
2752 /*
2753 * wait for specified event to occur
2754 */
2755 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2756 {
2757 unsigned long flags;
2758 int s;
2759 int rc=0;
2760 struct mgsl_icount cprev, cnow;
2761 int events;
2762 int mask;
2763 struct _input_signal_events oldsigs, newsigs;
2764 DECLARE_WAITQUEUE(wait, current);
2765
2766 if (get_user(mask, mask_ptr))
2767 return -EFAULT;
2768
2769 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2770
2771 spin_lock_irqsave(&info->lock,flags);
2772
2773 /* return immediately if state matches requested events */
2774 get_signals(info);
2775 s = info->signals;
2776
2777 events = mask &
2778 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2779 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2780 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2781 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2782 if (events) {
2783 spin_unlock_irqrestore(&info->lock,flags);
2784 goto exit;
2785 }
2786
2787 /* save current irq counts */
2788 cprev = info->icount;
2789 oldsigs = info->input_signal_events;
2790
2791 /* enable hunt and idle irqs if needed */
2792 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2793 unsigned short val = rd_reg16(info, SCR);
2794 if (!(val & IRQ_RXIDLE))
2795 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2796 }
2797
2798 set_current_state(TASK_INTERRUPTIBLE);
2799 add_wait_queue(&info->event_wait_q, &wait);
2800
2801 spin_unlock_irqrestore(&info->lock,flags);
2802
2803 for(;;) {
2804 schedule();
2805 if (signal_pending(current)) {
2806 rc = -ERESTARTSYS;
2807 break;
2808 }
2809
2810 /* get current irq counts */
2811 spin_lock_irqsave(&info->lock,flags);
2812 cnow = info->icount;
2813 newsigs = info->input_signal_events;
2814 set_current_state(TASK_INTERRUPTIBLE);
2815 spin_unlock_irqrestore(&info->lock,flags);
2816
2817 /* if no change, wait aborted for some reason */
2818 if (newsigs.dsr_up == oldsigs.dsr_up &&
2819 newsigs.dsr_down == oldsigs.dsr_down &&
2820 newsigs.dcd_up == oldsigs.dcd_up &&
2821 newsigs.dcd_down == oldsigs.dcd_down &&
2822 newsigs.cts_up == oldsigs.cts_up &&
2823 newsigs.cts_down == oldsigs.cts_down &&
2824 newsigs.ri_up == oldsigs.ri_up &&
2825 newsigs.ri_down == oldsigs.ri_down &&
2826 cnow.exithunt == cprev.exithunt &&
2827 cnow.rxidle == cprev.rxidle) {
2828 rc = -EIO;
2829 break;
2830 }
2831
2832 events = mask &
2833 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2834 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2835 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2836 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2837 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2838 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2839 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2840 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2841 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2842 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2843 if (events)
2844 break;
2845
2846 cprev = cnow;
2847 oldsigs = newsigs;
2848 }
2849
2850 remove_wait_queue(&info->event_wait_q, &wait);
2851 set_current_state(TASK_RUNNING);
2852
2853
2854 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2855 spin_lock_irqsave(&info->lock,flags);
2856 if (!waitqueue_active(&info->event_wait_q)) {
2857 /* disable enable exit hunt mode/idle rcvd IRQs */
2858 wr_reg16(info, SCR,
2859 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2860 }
2861 spin_unlock_irqrestore(&info->lock,flags);
2862 }
2863 exit:
2864 if (rc == 0)
2865 rc = put_user(events, mask_ptr);
2866 return rc;
2867 }
2868
2869 static int get_interface(struct slgt_info *info, int __user *if_mode)
2870 {
2871 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2872 if (put_user(info->if_mode, if_mode))
2873 return -EFAULT;
2874 return 0;
2875 }
2876
2877 static int set_interface(struct slgt_info *info, int if_mode)
2878 {
2879 unsigned long flags;
2880 unsigned short val;
2881
2882 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2883 spin_lock_irqsave(&info->lock,flags);
2884 info->if_mode = if_mode;
2885
2886 msc_set_vcr(info);
2887
2888 /* TCR (tx control) 07 1=RTS driver control */
2889 val = rd_reg16(info, TCR);
2890 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2891 val |= BIT7;
2892 else
2893 val &= ~BIT7;
2894 wr_reg16(info, TCR, val);
2895
2896 spin_unlock_irqrestore(&info->lock,flags);
2897 return 0;
2898 }
2899
2900 static int get_xsync(struct slgt_info *info, int __user *xsync)
2901 {
2902 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2903 if (put_user(info->xsync, xsync))
2904 return -EFAULT;
2905 return 0;
2906 }
2907
2908 /*
2909 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2910 *
2911 * sync pattern is contained in least significant bytes of value
2912 * most significant byte of sync pattern is oldest (1st sent/detected)
2913 */
2914 static int set_xsync(struct slgt_info *info, int xsync)
2915 {
2916 unsigned long flags;
2917
2918 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2919 spin_lock_irqsave(&info->lock, flags);
2920 info->xsync = xsync;
2921 wr_reg32(info, XSR, xsync);
2922 spin_unlock_irqrestore(&info->lock, flags);
2923 return 0;
2924 }
2925
2926 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2927 {
2928 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2929 if (put_user(info->xctrl, xctrl))
2930 return -EFAULT;
2931 return 0;
2932 }
2933
2934 /*
2935 * set extended control options
2936 *
2937 * xctrl[31:19] reserved, must be zero
2938 * xctrl[18:17] extended sync pattern length in bytes
2939 * 00 = 1 byte in xsr[7:0]
2940 * 01 = 2 bytes in xsr[15:0]
2941 * 10 = 3 bytes in xsr[23:0]
2942 * 11 = 4 bytes in xsr[31:0]
2943 * xctrl[16] 1 = enable terminal count, 0=disabled
2944 * xctrl[15:0] receive terminal count for fixed length packets
2945 * value is count minus one (0 = 1 byte packet)
2946 * when terminal count is reached, receiver
2947 * automatically returns to hunt mode and receive
2948 * FIFO contents are flushed to DMA buffers with
2949 * end of frame (EOF) status
2950 */
2951 static int set_xctrl(struct slgt_info *info, int xctrl)
2952 {
2953 unsigned long flags;
2954
2955 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2956 spin_lock_irqsave(&info->lock, flags);
2957 info->xctrl = xctrl;
2958 wr_reg32(info, XCR, xctrl);
2959 spin_unlock_irqrestore(&info->lock, flags);
2960 return 0;
2961 }
2962
2963 /*
2964 * set general purpose IO pin state and direction
2965 *
2966 * user_gpio fields:
2967 * state each bit indicates a pin state
2968 * smask set bit indicates pin state to set
2969 * dir each bit indicates a pin direction (0=input, 1=output)
2970 * dmask set bit indicates pin direction to set
2971 */
2972 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973 {
2974 unsigned long flags;
2975 struct gpio_desc gpio;
2976 __u32 data;
2977
2978 if (!info->gpio_present)
2979 return -EINVAL;
2980 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2981 return -EFAULT;
2982 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2983 info->device_name, gpio.state, gpio.smask,
2984 gpio.dir, gpio.dmask));
2985
2986 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2987 if (gpio.dmask) {
2988 data = rd_reg32(info, IODR);
2989 data |= gpio.dmask & gpio.dir;
2990 data &= ~(gpio.dmask & ~gpio.dir);
2991 wr_reg32(info, IODR, data);
2992 }
2993 if (gpio.smask) {
2994 data = rd_reg32(info, IOVR);
2995 data |= gpio.smask & gpio.state;
2996 data &= ~(gpio.smask & ~gpio.state);
2997 wr_reg32(info, IOVR, data);
2998 }
2999 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3000
3001 return 0;
3002 }
3003
3004 /*
3005 * get general purpose IO pin state and direction
3006 */
3007 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3008 {
3009 struct gpio_desc gpio;
3010 if (!info->gpio_present)
3011 return -EINVAL;
3012 gpio.state = rd_reg32(info, IOVR);
3013 gpio.smask = 0xffffffff;
3014 gpio.dir = rd_reg32(info, IODR);
3015 gpio.dmask = 0xffffffff;
3016 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3017 return -EFAULT;
3018 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3019 info->device_name, gpio.state, gpio.dir));
3020 return 0;
3021 }
3022
3023 /*
3024 * conditional wait facility
3025 */
3026 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3027 {
3028 init_waitqueue_head(&w->q);
3029 init_waitqueue_entry(&w->wait, current);
3030 w->data = data;
3031 }
3032
3033 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3034 {
3035 set_current_state(TASK_INTERRUPTIBLE);
3036 add_wait_queue(&w->q, &w->wait);
3037 w->next = *head;
3038 *head = w;
3039 }
3040
3041 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3042 {
3043 struct cond_wait *w, *prev;
3044 remove_wait_queue(&cw->q, &cw->wait);
3045 set_current_state(TASK_RUNNING);
3046 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3047 if (w == cw) {
3048 if (prev != NULL)
3049 prev->next = w->next;
3050 else
3051 *head = w->next;
3052 break;
3053 }
3054 }
3055 }
3056
3057 static void flush_cond_wait(struct cond_wait **head)
3058 {
3059 while (*head != NULL) {
3060 wake_up_interruptible(&(*head)->q);
3061 *head = (*head)->next;
3062 }
3063 }
3064
3065 /*
3066 * wait for general purpose I/O pin(s) to enter specified state
3067 *
3068 * user_gpio fields:
3069 * state - bit indicates target pin state
3070 * smask - set bit indicates watched pin
3071 *
3072 * The wait ends when at least one watched pin enters the specified
3073 * state. When 0 (no error) is returned, user_gpio->state is set to the
3074 * state of all GPIO pins when the wait ends.
3075 *
3076 * Note: Each pin may be a dedicated input, dedicated output, or
3077 * configurable input/output. The number and configuration of pins
3078 * varies with the specific adapter model. Only input pins (dedicated
3079 * or configured) can be monitored with this function.
3080 */
3081 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3082 {
3083 unsigned long flags;
3084 int rc = 0;
3085 struct gpio_desc gpio;
3086 struct cond_wait wait;
3087 u32 state;
3088
3089 if (!info->gpio_present)
3090 return -EINVAL;
3091 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3092 return -EFAULT;
3093 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3094 info->device_name, gpio.state, gpio.smask));
3095 /* ignore output pins identified by set IODR bit */
3096 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3097 return -EINVAL;
3098 init_cond_wait(&wait, gpio.smask);
3099
3100 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3101 /* enable interrupts for watched pins */
3102 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3103 /* get current pin states */
3104 state = rd_reg32(info, IOVR);
3105
3106 if (gpio.smask & ~(state ^ gpio.state)) {
3107 /* already in target state */
3108 gpio.state = state;
3109 } else {
3110 /* wait for target state */
3111 add_cond_wait(&info->gpio_wait_q, &wait);
3112 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3113 schedule();
3114 if (signal_pending(current))
3115 rc = -ERESTARTSYS;
3116 else
3117 gpio.state = wait.data;
3118 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3119 remove_cond_wait(&info->gpio_wait_q, &wait);
3120 }
3121
3122 /* disable all GPIO interrupts if no waiting processes */
3123 if (info->gpio_wait_q == NULL)
3124 wr_reg32(info, IOER, 0);
3125 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3126
3127 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3128 rc = -EFAULT;
3129 return rc;
3130 }
3131
3132 static int modem_input_wait(struct slgt_info *info,int arg)
3133 {
3134 unsigned long flags;
3135 int rc;
3136 struct mgsl_icount cprev, cnow;
3137 DECLARE_WAITQUEUE(wait, current);
3138
3139 /* save current irq counts */
3140 spin_lock_irqsave(&info->lock,flags);
3141 cprev = info->icount;
3142 add_wait_queue(&info->status_event_wait_q, &wait);
3143 set_current_state(TASK_INTERRUPTIBLE);
3144 spin_unlock_irqrestore(&info->lock,flags);
3145
3146 for(;;) {
3147 schedule();
3148 if (signal_pending(current)) {
3149 rc = -ERESTARTSYS;
3150 break;
3151 }
3152
3153 /* get new irq counts */
3154 spin_lock_irqsave(&info->lock,flags);
3155 cnow = info->icount;
3156 set_current_state(TASK_INTERRUPTIBLE);
3157 spin_unlock_irqrestore(&info->lock,flags);
3158
3159 /* if no change, wait aborted for some reason */
3160 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3161 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3162 rc = -EIO;
3163 break;
3164 }
3165
3166 /* check for change in caller specified modem input */
3167 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3168 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3169 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3170 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3171 rc = 0;
3172 break;
3173 }
3174
3175 cprev = cnow;
3176 }
3177 remove_wait_queue(&info->status_event_wait_q, &wait);
3178 set_current_state(TASK_RUNNING);
3179 return rc;
3180 }
3181
3182 /*
3183 * return state of serial control and status signals
3184 */
3185 static int tiocmget(struct tty_struct *tty)
3186 {
3187 struct slgt_info *info = tty->driver_data;
3188 unsigned int result;
3189 unsigned long flags;
3190
3191 spin_lock_irqsave(&info->lock,flags);
3192 get_signals(info);
3193 spin_unlock_irqrestore(&info->lock,flags);
3194
3195 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3196 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3197 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3198 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3199 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3200 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3201
3202 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3203 return result;
3204 }
3205
3206 /*
3207 * set modem control signals (DTR/RTS)
3208 *
3209 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3210 * TIOCMSET = set/clear signal values
3211 * value bit mask for command
3212 */
3213 static int tiocmset(struct tty_struct *tty,
3214 unsigned int set, unsigned int clear)
3215 {
3216 struct slgt_info *info = tty->driver_data;
3217 unsigned long flags;
3218
3219 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3220
3221 if (set & TIOCM_RTS)
3222 info->signals |= SerialSignal_RTS;
3223 if (set & TIOCM_DTR)
3224 info->signals |= SerialSignal_DTR;
3225 if (clear & TIOCM_RTS)
3226 info->signals &= ~SerialSignal_RTS;
3227 if (clear & TIOCM_DTR)
3228 info->signals &= ~SerialSignal_DTR;
3229
3230 spin_lock_irqsave(&info->lock,flags);
3231 set_signals(info);
3232 spin_unlock_irqrestore(&info->lock,flags);
3233 return 0;
3234 }
3235
3236 static int carrier_raised(struct tty_port *port)
3237 {
3238 unsigned long flags;
3239 struct slgt_info *info = container_of(port, struct slgt_info, port);
3240
3241 spin_lock_irqsave(&info->lock,flags);
3242 get_signals(info);
3243 spin_unlock_irqrestore(&info->lock,flags);
3244 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3245 }
3246
3247 static void dtr_rts(struct tty_port *port, int on)
3248 {
3249 unsigned long flags;
3250 struct slgt_info *info = container_of(port, struct slgt_info, port);
3251
3252 spin_lock_irqsave(&info->lock,flags);
3253 if (on)
3254 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3255 else
3256 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3257 set_signals(info);
3258 spin_unlock_irqrestore(&info->lock,flags);
3259 }
3260
3261
3262 /*
3263 * block current process until the device is ready to open
3264 */
3265 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3266 struct slgt_info *info)
3267 {
3268 DECLARE_WAITQUEUE(wait, current);
3269 int retval;
3270 bool do_clocal = false;
3271 unsigned long flags;
3272 int cd;
3273 struct tty_port *port = &info->port;
3274
3275 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3276
3277 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3278 /* nonblock mode is set or port is not enabled */
3279 port->flags |= ASYNC_NORMAL_ACTIVE;
3280 return 0;
3281 }
3282
3283 if (tty->termios.c_cflag & CLOCAL)
3284 do_clocal = true;
3285
3286 /* Wait for carrier detect and the line to become
3287 * free (i.e., not in use by the callout). While we are in
3288 * this loop, port->count is dropped by one, so that
3289 * close() knows when to free things. We restore it upon
3290 * exit, either normal or abnormal.
3291 */
3292
3293 retval = 0;
3294 add_wait_queue(&port->open_wait, &wait);
3295
3296 spin_lock_irqsave(&info->lock, flags);
3297 port->count--;
3298 spin_unlock_irqrestore(&info->lock, flags);
3299 port->blocked_open++;
3300
3301 while (1) {
3302 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3303 tty_port_raise_dtr_rts(port);
3304
3305 set_current_state(TASK_INTERRUPTIBLE);
3306
3307 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3308 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3309 -EAGAIN : -ERESTARTSYS;
3310 break;
3311 }
3312
3313 cd = tty_port_carrier_raised(port);
3314 if (do_clocal || cd)
3315 break;
3316
3317 if (signal_pending(current)) {
3318 retval = -ERESTARTSYS;
3319 break;
3320 }
3321
3322 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3323 tty_unlock(tty);
3324 schedule();
3325 tty_lock(tty);
3326 }
3327
3328 set_current_state(TASK_RUNNING);
3329 remove_wait_queue(&port->open_wait, &wait);
3330
3331 if (!tty_hung_up_p(filp))
3332 port->count++;
3333 port->blocked_open--;
3334
3335 if (!retval)
3336 port->flags |= ASYNC_NORMAL_ACTIVE;
3337
3338 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3339 return retval;
3340 }
3341
3342 /*
3343 * allocate buffers used for calling line discipline receive_buf
3344 * directly in synchronous mode
3345 * note: add 5 bytes to max frame size to allow appending
3346 * 32-bit CRC and status byte when configured to do so
3347 */
3348 static int alloc_tmp_rbuf(struct slgt_info *info)
3349 {
3350 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3351 if (info->tmp_rbuf == NULL)
3352 return -ENOMEM;
3353 /* unused flag buffer to satisfy receive_buf calling interface */
3354 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3355 if (!info->flag_buf) {
3356 kfree(info->tmp_rbuf);
3357 info->tmp_rbuf = NULL;
3358 return -ENOMEM;
3359 }
3360 return 0;
3361 }
3362
3363 static void free_tmp_rbuf(struct slgt_info *info)
3364 {
3365 kfree(info->tmp_rbuf);
3366 info->tmp_rbuf = NULL;
3367 kfree(info->flag_buf);
3368 info->flag_buf = NULL;
3369 }
3370
3371 /*
3372 * allocate DMA descriptor lists.
3373 */
3374 static int alloc_desc(struct slgt_info *info)
3375 {
3376 unsigned int i;
3377 unsigned int pbufs;
3378
3379 /* allocate memory to hold descriptor lists */
3380 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3381 &info->bufs_dma_addr);
3382 if (info->bufs == NULL)
3383 return -ENOMEM;
3384
3385 info->rbufs = (struct slgt_desc*)info->bufs;
3386 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3387
3388 pbufs = (unsigned int)info->bufs_dma_addr;
3389
3390 /*
3391 * Build circular lists of descriptors
3392 */
3393
3394 for (i=0; i < info->rbuf_count; i++) {
3395 /* physical address of this descriptor */
3396 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3397
3398 /* physical address of next descriptor */
3399 if (i == info->rbuf_count - 1)
3400 info->rbufs[i].next = cpu_to_le32(pbufs);
3401 else
3402 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3403 set_desc_count(info->rbufs[i], DMABUFSIZE);
3404 }
3405
3406 for (i=0; i < info->tbuf_count; i++) {
3407 /* physical address of this descriptor */
3408 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3409
3410 /* physical address of next descriptor */
3411 if (i == info->tbuf_count - 1)
3412 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3413 else
3414 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3415 }
3416
3417 return 0;
3418 }
3419
3420 static void free_desc(struct slgt_info *info)
3421 {
3422 if (info->bufs != NULL) {
3423 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3424 info->bufs = NULL;
3425 info->rbufs = NULL;
3426 info->tbufs = NULL;
3427 }
3428 }
3429
3430 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3431 {
3432 int i;
3433 for (i=0; i < count; i++) {
3434 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3435 return -ENOMEM;
3436 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3437 }
3438 return 0;
3439 }
3440
3441 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3442 {
3443 int i;
3444 for (i=0; i < count; i++) {
3445 if (bufs[i].buf == NULL)
3446 continue;
3447 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3448 bufs[i].buf = NULL;
3449 }
3450 }
3451
3452 static int alloc_dma_bufs(struct slgt_info *info)
3453 {
3454 info->rbuf_count = 32;
3455 info->tbuf_count = 32;
3456
3457 if (alloc_desc(info) < 0 ||
3458 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3459 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3460 alloc_tmp_rbuf(info) < 0) {
3461 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3462 return -ENOMEM;
3463 }
3464 reset_rbufs(info);
3465 return 0;
3466 }
3467
3468 static void free_dma_bufs(struct slgt_info *info)
3469 {
3470 if (info->bufs) {
3471 free_bufs(info, info->rbufs, info->rbuf_count);
3472 free_bufs(info, info->tbufs, info->tbuf_count);
3473 free_desc(info);
3474 }
3475 free_tmp_rbuf(info);
3476 }
3477
3478 static int claim_resources(struct slgt_info *info)
3479 {
3480 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3481 DBGERR(("%s reg addr conflict, addr=%08X\n",
3482 info->device_name, info->phys_reg_addr));
3483 info->init_error = DiagStatus_AddressConflict;
3484 goto errout;
3485 }
3486 else
3487 info->reg_addr_requested = true;
3488
3489 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3490 if (!info->reg_addr) {
3491 DBGERR(("%s can't map device registers, addr=%08X\n",
3492 info->device_name, info->phys_reg_addr));
3493 info->init_error = DiagStatus_CantAssignPciResources;
3494 goto errout;
3495 }
3496 return 0;
3497
3498 errout:
3499 release_resources(info);
3500 return -ENODEV;
3501 }
3502
3503 static void release_resources(struct slgt_info *info)
3504 {
3505 if (info->irq_requested) {
3506 free_irq(info->irq_level, info);
3507 info->irq_requested = false;
3508 }
3509
3510 if (info->reg_addr_requested) {
3511 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3512 info->reg_addr_requested = false;
3513 }
3514
3515 if (info->reg_addr) {
3516 iounmap(info->reg_addr);
3517 info->reg_addr = NULL;
3518 }
3519 }
3520
3521 /* Add the specified device instance data structure to the
3522 * global linked list of devices and increment the device count.
3523 */
3524 static void add_device(struct slgt_info *info)
3525 {
3526 char *devstr;
3527
3528 info->next_device = NULL;
3529 info->line = slgt_device_count;
3530 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3531
3532 if (info->line < MAX_DEVICES) {
3533 if (maxframe[info->line])
3534 info->max_frame_size = maxframe[info->line];
3535 }
3536
3537 slgt_device_count++;
3538
3539 if (!slgt_device_list)
3540 slgt_device_list = info;
3541 else {
3542 struct slgt_info *current_dev = slgt_device_list;
3543 while(current_dev->next_device)
3544 current_dev = current_dev->next_device;
3545 current_dev->next_device = info;
3546 }
3547
3548 if (info->max_frame_size < 4096)
3549 info->max_frame_size = 4096;
3550 else if (info->max_frame_size > 65535)
3551 info->max_frame_size = 65535;
3552
3553 switch(info->pdev->device) {
3554 case SYNCLINK_GT_DEVICE_ID:
3555 devstr = "GT";
3556 break;
3557 case SYNCLINK_GT2_DEVICE_ID:
3558 devstr = "GT2";
3559 break;
3560 case SYNCLINK_GT4_DEVICE_ID:
3561 devstr = "GT4";
3562 break;
3563 case SYNCLINK_AC_DEVICE_ID:
3564 devstr = "AC";
3565 info->params.mode = MGSL_MODE_ASYNC;
3566 break;
3567 default:
3568 devstr = "(unknown model)";
3569 }
3570 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3571 devstr, info->device_name, info->phys_reg_addr,
3572 info->irq_level, info->max_frame_size);
3573
3574 #if SYNCLINK_GENERIC_HDLC
3575 hdlcdev_init(info);
3576 #endif
3577 }
3578
3579 static const struct tty_port_operations slgt_port_ops = {
3580 .carrier_raised = carrier_raised,
3581 .dtr_rts = dtr_rts,
3582 };
3583
3584 /*
3585 * allocate device instance structure, return NULL on failure
3586 */
3587 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3588 {
3589 struct slgt_info *info;
3590
3591 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3592
3593 if (!info) {
3594 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3595 driver_name, adapter_num, port_num));
3596 } else {
3597 tty_port_init(&info->port);
3598 info->port.ops = &slgt_port_ops;
3599 info->magic = MGSL_MAGIC;
3600 INIT_WORK(&info->task, bh_handler);
3601 info->max_frame_size = 4096;
3602 info->base_clock = 14745600;
3603 info->rbuf_fill_level = DMABUFSIZE;
3604 info->port.close_delay = 5*HZ/10;
3605 info->port.closing_wait = 30*HZ;
3606 init_waitqueue_head(&info->status_event_wait_q);
3607 init_waitqueue_head(&info->event_wait_q);
3608 spin_lock_init(&info->netlock);
3609 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3610 info->idle_mode = HDLC_TXIDLE_FLAGS;
3611 info->adapter_num = adapter_num;
3612 info->port_num = port_num;
3613
3614 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3615 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3616
3617 /* Copy configuration info to device instance data */
3618 info->pdev = pdev;
3619 info->irq_level = pdev->irq;
3620 info->phys_reg_addr = pci_resource_start(pdev,0);
3621
3622 info->bus_type = MGSL_BUS_TYPE_PCI;
3623 info->irq_flags = IRQF_SHARED;
3624
3625 info->init_error = -1; /* assume error, set to 0 on successful init */
3626 }
3627
3628 return info;
3629 }
3630
3631 static void device_init(int adapter_num, struct pci_dev *pdev)
3632 {
3633 struct slgt_info *port_array[SLGT_MAX_PORTS];
3634 int i;
3635 int port_count = 1;
3636
3637 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3638 port_count = 2;
3639 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3640 port_count = 4;
3641
3642 /* allocate device instances for all ports */
3643 for (i=0; i < port_count; ++i) {
3644 port_array[i] = alloc_dev(adapter_num, i, pdev);
3645 if (port_array[i] == NULL) {
3646 for (--i; i >= 0; --i) {
3647 tty_port_destroy(&port_array[i]->port);
3648 kfree(port_array[i]);
3649 }
3650 return;
3651 }
3652 }
3653
3654 /* give copy of port_array to all ports and add to device list */
3655 for (i=0; i < port_count; ++i) {
3656 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3657 add_device(port_array[i]);
3658 port_array[i]->port_count = port_count;
3659 spin_lock_init(&port_array[i]->lock);
3660 }
3661
3662 /* Allocate and claim adapter resources */
3663 if (!claim_resources(port_array[0])) {
3664
3665 alloc_dma_bufs(port_array[0]);
3666
3667 /* copy resource information from first port to others */
3668 for (i = 1; i < port_count; ++i) {
3669 port_array[i]->irq_level = port_array[0]->irq_level;
3670 port_array[i]->reg_addr = port_array[0]->reg_addr;
3671 alloc_dma_bufs(port_array[i]);
3672 }
3673
3674 if (request_irq(port_array[0]->irq_level,
3675 slgt_interrupt,
3676 port_array[0]->irq_flags,
3677 port_array[0]->device_name,
3678 port_array[0]) < 0) {
3679 DBGERR(("%s request_irq failed IRQ=%d\n",
3680 port_array[0]->device_name,
3681 port_array[0]->irq_level));
3682 } else {
3683 port_array[0]->irq_requested = true;
3684 adapter_test(port_array[0]);
3685 for (i=1 ; i < port_count ; i++) {
3686 port_array[i]->init_error = port_array[0]->init_error;
3687 port_array[i]->gpio_present = port_array[0]->gpio_present;
3688 }
3689 }
3690 }
3691
3692 for (i = 0; i < port_count; ++i) {
3693 struct slgt_info *info = port_array[i];
3694 tty_port_register_device(&info->port, serial_driver, info->line,
3695 &info->pdev->dev);
3696 }
3697 }
3698
3699 static int init_one(struct pci_dev *dev,
3700 const struct pci_device_id *ent)
3701 {
3702 if (pci_enable_device(dev)) {
3703 printk("error enabling pci device %p\n", dev);
3704 return -EIO;
3705 }
3706 pci_set_master(dev);
3707 device_init(slgt_device_count, dev);
3708 return 0;
3709 }
3710
3711 static void remove_one(struct pci_dev *dev)
3712 {
3713 }
3714
3715 static const struct tty_operations ops = {
3716 .open = open,
3717 .close = close,
3718 .write = write,
3719 .put_char = put_char,
3720 .flush_chars = flush_chars,
3721 .write_room = write_room,
3722 .chars_in_buffer = chars_in_buffer,
3723 .flush_buffer = flush_buffer,
3724 .ioctl = ioctl,
3725 .compat_ioctl = slgt_compat_ioctl,
3726 .throttle = throttle,
3727 .unthrottle = unthrottle,
3728 .send_xchar = send_xchar,
3729 .break_ctl = set_break,
3730 .wait_until_sent = wait_until_sent,
3731 .set_termios = set_termios,
3732 .stop = tx_hold,
3733 .start = tx_release,
3734 .hangup = hangup,
3735 .tiocmget = tiocmget,
3736 .tiocmset = tiocmset,
3737 .get_icount = get_icount,
3738 .proc_fops = &synclink_gt_proc_fops,
3739 };
3740
3741 static void slgt_cleanup(void)
3742 {
3743 int rc;
3744 struct slgt_info *info;
3745 struct slgt_info *tmp;
3746
3747 printk(KERN_INFO "unload %s\n", driver_name);
3748
3749 if (serial_driver) {
3750 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3751 tty_unregister_device(serial_driver, info->line);
3752 rc = tty_unregister_driver(serial_driver);
3753 if (rc)
3754 DBGERR(("tty_unregister_driver error=%d\n", rc));
3755 put_tty_driver(serial_driver);
3756 }
3757
3758 /* reset devices */
3759 info = slgt_device_list;
3760 while(info) {
3761 reset_port(info);
3762 info = info->next_device;
3763 }
3764
3765 /* release devices */
3766 info = slgt_device_list;
3767 while(info) {
3768 #if SYNCLINK_GENERIC_HDLC
3769 hdlcdev_exit(info);
3770 #endif
3771 free_dma_bufs(info);
3772 free_tmp_rbuf(info);
3773 if (info->port_num == 0)
3774 release_resources(info);
3775 tmp = info;
3776 info = info->next_device;
3777 tty_port_destroy(&tmp->port);
3778 kfree(tmp);
3779 }
3780
3781 if (pci_registered)
3782 pci_unregister_driver(&pci_driver);
3783 }
3784
3785 /*
3786 * Driver initialization entry point.
3787 */
3788 static int __init slgt_init(void)
3789 {
3790 int rc;
3791
3792 printk(KERN_INFO "%s\n", driver_name);
3793
3794 serial_driver = alloc_tty_driver(MAX_DEVICES);
3795 if (!serial_driver) {
3796 printk("%s can't allocate tty driver\n", driver_name);
3797 return -ENOMEM;
3798 }
3799
3800 /* Initialize the tty_driver structure */
3801
3802 serial_driver->driver_name = slgt_driver_name;
3803 serial_driver->name = tty_dev_prefix;
3804 serial_driver->major = ttymajor;
3805 serial_driver->minor_start = 64;
3806 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3807 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3808 serial_driver->init_termios = tty_std_termios;
3809 serial_driver->init_termios.c_cflag =
3810 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3811 serial_driver->init_termios.c_ispeed = 9600;
3812 serial_driver->init_termios.c_ospeed = 9600;
3813 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3814 tty_set_operations(serial_driver, &ops);
3815 if ((rc = tty_register_driver(serial_driver)) < 0) {
3816 DBGERR(("%s can't register serial driver\n", driver_name));
3817 put_tty_driver(serial_driver);
3818 serial_driver = NULL;
3819 goto error;
3820 }
3821
3822 printk(KERN_INFO "%s, tty major#%d\n",
3823 driver_name, serial_driver->major);
3824
3825 slgt_device_count = 0;
3826 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3827 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3828 goto error;
3829 }
3830 pci_registered = true;
3831
3832 if (!slgt_device_list)
3833 printk("%s no devices found\n",driver_name);
3834
3835 return 0;
3836
3837 error:
3838 slgt_cleanup();
3839 return rc;
3840 }
3841
3842 static void __exit slgt_exit(void)
3843 {
3844 slgt_cleanup();
3845 }
3846
3847 module_init(slgt_init);
3848 module_exit(slgt_exit);
3849
3850 /*
3851 * register access routines
3852 */
3853
3854 #define CALC_REGADDR() \
3855 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3856 if (addr >= 0x80) \
3857 reg_addr += (info->port_num) * 32; \
3858 else if (addr >= 0x40) \
3859 reg_addr += (info->port_num) * 16;
3860
3861 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3862 {
3863 CALC_REGADDR();
3864 return readb((void __iomem *)reg_addr);
3865 }
3866
3867 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3868 {
3869 CALC_REGADDR();
3870 writeb(value, (void __iomem *)reg_addr);
3871 }
3872
3873 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3874 {
3875 CALC_REGADDR();
3876 return readw((void __iomem *)reg_addr);
3877 }
3878
3879 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3880 {
3881 CALC_REGADDR();
3882 writew(value, (void __iomem *)reg_addr);
3883 }
3884
3885 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3886 {
3887 CALC_REGADDR();
3888 return readl((void __iomem *)reg_addr);
3889 }
3890
3891 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3892 {
3893 CALC_REGADDR();
3894 writel(value, (void __iomem *)reg_addr);
3895 }
3896
3897 static void rdma_reset(struct slgt_info *info)
3898 {
3899 unsigned int i;
3900
3901 /* set reset bit */
3902 wr_reg32(info, RDCSR, BIT1);
3903
3904 /* wait for enable bit cleared */
3905 for(i=0 ; i < 1000 ; i++)
3906 if (!(rd_reg32(info, RDCSR) & BIT0))
3907 break;
3908 }
3909
3910 static void tdma_reset(struct slgt_info *info)
3911 {
3912 unsigned int i;
3913
3914 /* set reset bit */
3915 wr_reg32(info, TDCSR, BIT1);
3916
3917 /* wait for enable bit cleared */
3918 for(i=0 ; i < 1000 ; i++)
3919 if (!(rd_reg32(info, TDCSR) & BIT0))
3920 break;
3921 }
3922
3923 /*
3924 * enable internal loopback
3925 * TxCLK and RxCLK are generated from BRG
3926 * and TxD is looped back to RxD internally.
3927 */
3928 static void enable_loopback(struct slgt_info *info)
3929 {
3930 /* SCR (serial control) BIT2=loopback enable */
3931 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3932
3933 if (info->params.mode != MGSL_MODE_ASYNC) {
3934 /* CCR (clock control)
3935 * 07..05 tx clock source (010 = BRG)
3936 * 04..02 rx clock source (010 = BRG)
3937 * 01 auxclk enable (0 = disable)
3938 * 00 BRG enable (1 = enable)
3939 *
3940 * 0100 1001
3941 */
3942 wr_reg8(info, CCR, 0x49);
3943
3944 /* set speed if available, otherwise use default */
3945 if (info->params.clock_speed)
3946 set_rate(info, info->params.clock_speed);
3947 else
3948 set_rate(info, 3686400);
3949 }
3950 }
3951
3952 /*
3953 * set baud rate generator to specified rate
3954 */
3955 static void set_rate(struct slgt_info *info, u32 rate)
3956 {
3957 unsigned int div;
3958 unsigned int osc = info->base_clock;
3959
3960 /* div = osc/rate - 1
3961 *
3962 * Round div up if osc/rate is not integer to
3963 * force to next slowest rate.
3964 */
3965
3966 if (rate) {
3967 div = osc/rate;
3968 if (!(osc % rate) && div)
3969 div--;
3970 wr_reg16(info, BDR, (unsigned short)div);
3971 }
3972 }
3973
3974 static void rx_stop(struct slgt_info *info)
3975 {
3976 unsigned short val;
3977
3978 /* disable and reset receiver */
3979 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3980 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3981 wr_reg16(info, RCR, val); /* clear reset bit */
3982
3983 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3984
3985 /* clear pending rx interrupts */
3986 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3987
3988 rdma_reset(info);
3989
3990 info->rx_enabled = false;
3991 info->rx_restart = false;
3992 }
3993
3994 static void rx_start(struct slgt_info *info)
3995 {
3996 unsigned short val;
3997
3998 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3999
4000 /* clear pending rx overrun IRQ */
4001 wr_reg16(info, SSR, IRQ_RXOVER);
4002
4003 /* reset and disable receiver */
4004 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4005 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4006 wr_reg16(info, RCR, val); /* clear reset bit */
4007
4008 rdma_reset(info);
4009 reset_rbufs(info);
4010
4011 if (info->rx_pio) {
4012 /* rx request when rx FIFO not empty */
4013 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4014 slgt_irq_on(info, IRQ_RXDATA);
4015 if (info->params.mode == MGSL_MODE_ASYNC) {
4016 /* enable saving of rx status */
4017 wr_reg32(info, RDCSR, BIT6);
4018 }
4019 } else {
4020 /* rx request when rx FIFO half full */
4021 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4022 /* set 1st descriptor address */
4023 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4024
4025 if (info->params.mode != MGSL_MODE_ASYNC) {
4026 /* enable rx DMA and DMA interrupt */
4027 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4028 } else {
4029 /* enable saving of rx status, rx DMA and DMA interrupt */
4030 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4031 }
4032 }
4033
4034 slgt_irq_on(info, IRQ_RXOVER);
4035
4036 /* enable receiver */
4037 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4038
4039 info->rx_restart = false;
4040 info->rx_enabled = true;
4041 }
4042
4043 static void tx_start(struct slgt_info *info)
4044 {
4045 if (!info->tx_enabled) {
4046 wr_reg16(info, TCR,
4047 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4048 info->tx_enabled = true;
4049 }
4050
4051 if (desc_count(info->tbufs[info->tbuf_start])) {
4052 info->drop_rts_on_tx_done = false;
4053
4054 if (info->params.mode != MGSL_MODE_ASYNC) {
4055 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4056 get_signals(info);
4057 if (!(info->signals & SerialSignal_RTS)) {
4058 info->signals |= SerialSignal_RTS;
4059 set_signals(info);
4060 info->drop_rts_on_tx_done = true;
4061 }
4062 }
4063
4064 slgt_irq_off(info, IRQ_TXDATA);
4065 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4066 /* clear tx idle and underrun status bits */
4067 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4068 } else {
4069 slgt_irq_off(info, IRQ_TXDATA);
4070 slgt_irq_on(info, IRQ_TXIDLE);
4071 /* clear tx idle status bit */
4072 wr_reg16(info, SSR, IRQ_TXIDLE);
4073 }
4074 /* set 1st descriptor address and start DMA */
4075 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4076 wr_reg32(info, TDCSR, BIT2 + BIT0);
4077 info->tx_active = true;
4078 }
4079 }
4080
4081 static void tx_stop(struct slgt_info *info)
4082 {
4083 unsigned short val;
4084
4085 del_timer(&info->tx_timer);
4086
4087 tdma_reset(info);
4088
4089 /* reset and disable transmitter */
4090 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4091 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4092
4093 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4094
4095 /* clear tx idle and underrun status bit */
4096 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4097
4098 reset_tbufs(info);
4099
4100 info->tx_enabled = false;
4101 info->tx_active = false;
4102 }
4103
4104 static void reset_port(struct slgt_info *info)
4105 {
4106 if (!info->reg_addr)
4107 return;
4108
4109 tx_stop(info);
4110 rx_stop(info);
4111
4112 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4113 set_signals(info);
4114
4115 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4116 }
4117
4118 static void reset_adapter(struct slgt_info *info)
4119 {
4120 int i;
4121 for (i=0; i < info->port_count; ++i) {
4122 if (info->port_array[i])
4123 reset_port(info->port_array[i]);
4124 }
4125 }
4126
4127 static void async_mode(struct slgt_info *info)
4128 {
4129 unsigned short val;
4130
4131 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4132 tx_stop(info);
4133 rx_stop(info);
4134
4135 /* TCR (tx control)
4136 *
4137 * 15..13 mode, 010=async
4138 * 12..10 encoding, 000=NRZ
4139 * 09 parity enable
4140 * 08 1=odd parity, 0=even parity
4141 * 07 1=RTS driver control
4142 * 06 1=break enable
4143 * 05..04 character length
4144 * 00=5 bits
4145 * 01=6 bits
4146 * 10=7 bits
4147 * 11=8 bits
4148 * 03 0=1 stop bit, 1=2 stop bits
4149 * 02 reset
4150 * 01 enable
4151 * 00 auto-CTS enable
4152 */
4153 val = 0x4000;
4154
4155 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4156 val |= BIT7;
4157
4158 if (info->params.parity != ASYNC_PARITY_NONE) {
4159 val |= BIT9;
4160 if (info->params.parity == ASYNC_PARITY_ODD)
4161 val |= BIT8;
4162 }
4163
4164 switch (info->params.data_bits)
4165 {
4166 case 6: val |= BIT4; break;
4167 case 7: val |= BIT5; break;
4168 case 8: val |= BIT5 + BIT4; break;
4169 }
4170
4171 if (info->params.stop_bits != 1)
4172 val |= BIT3;
4173
4174 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4175 val |= BIT0;
4176
4177 wr_reg16(info, TCR, val);
4178
4179 /* RCR (rx control)
4180 *
4181 * 15..13 mode, 010=async
4182 * 12..10 encoding, 000=NRZ
4183 * 09 parity enable
4184 * 08 1=odd parity, 0=even parity
4185 * 07..06 reserved, must be 0
4186 * 05..04 character length
4187 * 00=5 bits
4188 * 01=6 bits
4189 * 10=7 bits
4190 * 11=8 bits
4191 * 03 reserved, must be zero
4192 * 02 reset
4193 * 01 enable
4194 * 00 auto-DCD enable
4195 */
4196 val = 0x4000;
4197
4198 if (info->params.parity != ASYNC_PARITY_NONE) {
4199 val |= BIT9;
4200 if (info->params.parity == ASYNC_PARITY_ODD)
4201 val |= BIT8;
4202 }
4203
4204 switch (info->params.data_bits)
4205 {
4206 case 6: val |= BIT4; break;
4207 case 7: val |= BIT5; break;
4208 case 8: val |= BIT5 + BIT4; break;
4209 }
4210
4211 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4212 val |= BIT0;
4213
4214 wr_reg16(info, RCR, val);
4215
4216 /* CCR (clock control)
4217 *
4218 * 07..05 011 = tx clock source is BRG/16
4219 * 04..02 010 = rx clock source is BRG
4220 * 01 0 = auxclk disabled
4221 * 00 1 = BRG enabled
4222 *
4223 * 0110 1001
4224 */
4225 wr_reg8(info, CCR, 0x69);
4226
4227 msc_set_vcr(info);
4228
4229 /* SCR (serial control)
4230 *
4231 * 15 1=tx req on FIFO half empty
4232 * 14 1=rx req on FIFO half full
4233 * 13 tx data IRQ enable
4234 * 12 tx idle IRQ enable
4235 * 11 rx break on IRQ enable
4236 * 10 rx data IRQ enable
4237 * 09 rx break off IRQ enable
4238 * 08 overrun IRQ enable
4239 * 07 DSR IRQ enable
4240 * 06 CTS IRQ enable
4241 * 05 DCD IRQ enable
4242 * 04 RI IRQ enable
4243 * 03 0=16x sampling, 1=8x sampling
4244 * 02 1=txd->rxd internal loopback enable
4245 * 01 reserved, must be zero
4246 * 00 1=master IRQ enable
4247 */
4248 val = BIT15 + BIT14 + BIT0;
4249 /* JCR[8] : 1 = x8 async mode feature available */
4250 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4251 ((info->base_clock < (info->params.data_rate * 16)) ||
4252 (info->base_clock % (info->params.data_rate * 16)))) {
4253 /* use 8x sampling */
4254 val |= BIT3;
4255 set_rate(info, info->params.data_rate * 8);
4256 } else {
4257 /* use 16x sampling */
4258 set_rate(info, info->params.data_rate * 16);
4259 }
4260 wr_reg16(info, SCR, val);
4261
4262 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4263
4264 if (info->params.loopback)
4265 enable_loopback(info);
4266 }
4267
4268 static void sync_mode(struct slgt_info *info)
4269 {
4270 unsigned short val;
4271
4272 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4273 tx_stop(info);
4274 rx_stop(info);
4275
4276 /* TCR (tx control)
4277 *
4278 * 15..13 mode
4279 * 000=HDLC/SDLC
4280 * 001=raw bit synchronous
4281 * 010=asynchronous/isochronous
4282 * 011=monosync byte synchronous
4283 * 100=bisync byte synchronous
4284 * 101=xsync byte synchronous
4285 * 12..10 encoding
4286 * 09 CRC enable
4287 * 08 CRC32
4288 * 07 1=RTS driver control
4289 * 06 preamble enable
4290 * 05..04 preamble length
4291 * 03 share open/close flag
4292 * 02 reset
4293 * 01 enable
4294 * 00 auto-CTS enable
4295 */
4296 val = BIT2;
4297
4298 switch(info->params.mode) {
4299 case MGSL_MODE_XSYNC:
4300 val |= BIT15 + BIT13;
4301 break;
4302 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4303 case MGSL_MODE_BISYNC: val |= BIT15; break;
4304 case MGSL_MODE_RAW: val |= BIT13; break;
4305 }
4306 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4307 val |= BIT7;
4308
4309 switch(info->params.encoding)
4310 {
4311 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4312 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4313 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4314 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4315 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4316 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4317 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4318 }
4319
4320 switch (info->params.crc_type & HDLC_CRC_MASK)
4321 {
4322 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4323 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4324 }
4325
4326 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4327 val |= BIT6;
4328
4329 switch (info->params.preamble_length)
4330 {
4331 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4332 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4333 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4334 }
4335
4336 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4337 val |= BIT0;
4338
4339 wr_reg16(info, TCR, val);
4340
4341 /* TPR (transmit preamble) */
4342
4343 switch (info->params.preamble)
4344 {
4345 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4346 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4347 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4348 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4349 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4350 default: val = 0x7e; break;
4351 }
4352 wr_reg8(info, TPR, (unsigned char)val);
4353
4354 /* RCR (rx control)
4355 *
4356 * 15..13 mode
4357 * 000=HDLC/SDLC
4358 * 001=raw bit synchronous
4359 * 010=asynchronous/isochronous
4360 * 011=monosync byte synchronous
4361 * 100=bisync byte synchronous
4362 * 101=xsync byte synchronous
4363 * 12..10 encoding
4364 * 09 CRC enable
4365 * 08 CRC32
4366 * 07..03 reserved, must be 0
4367 * 02 reset
4368 * 01 enable
4369 * 00 auto-DCD enable
4370 */
4371 val = 0;
4372
4373 switch(info->params.mode) {
4374 case MGSL_MODE_XSYNC:
4375 val |= BIT15 + BIT13;
4376 break;
4377 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4378 case MGSL_MODE_BISYNC: val |= BIT15; break;
4379 case MGSL_MODE_RAW: val |= BIT13; break;
4380 }
4381
4382 switch(info->params.encoding)
4383 {
4384 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4385 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4386 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4387 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4388 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4389 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4390 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4391 }
4392
4393 switch (info->params.crc_type & HDLC_CRC_MASK)
4394 {
4395 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4396 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4397 }
4398
4399 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4400 val |= BIT0;
4401
4402 wr_reg16(info, RCR, val);
4403
4404 /* CCR (clock control)
4405 *
4406 * 07..05 tx clock source
4407 * 04..02 rx clock source
4408 * 01 auxclk enable
4409 * 00 BRG enable
4410 */
4411 val = 0;
4412
4413 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4414 {
4415 // when RxC source is DPLL, BRG generates 16X DPLL
4416 // reference clock, so take TxC from BRG/16 to get
4417 // transmit clock at actual data rate
4418 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4419 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4420 else
4421 val |= BIT6; /* 010, txclk = BRG */
4422 }
4423 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4424 val |= BIT7; /* 100, txclk = DPLL Input */
4425 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4426 val |= BIT5; /* 001, txclk = RXC Input */
4427
4428 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4429 val |= BIT3; /* 010, rxclk = BRG */
4430 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4431 val |= BIT4; /* 100, rxclk = DPLL */
4432 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4433 val |= BIT2; /* 001, rxclk = TXC Input */
4434
4435 if (info->params.clock_speed)
4436 val |= BIT1 + BIT0;
4437
4438 wr_reg8(info, CCR, (unsigned char)val);
4439
4440 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4441 {
4442 // program DPLL mode
4443 switch(info->params.encoding)
4444 {
4445 case HDLC_ENCODING_BIPHASE_MARK:
4446 case HDLC_ENCODING_BIPHASE_SPACE:
4447 val = BIT7; break;
4448 case HDLC_ENCODING_BIPHASE_LEVEL:
4449 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4450 val = BIT7 + BIT6; break;
4451 default: val = BIT6; // NRZ encodings
4452 }
4453 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4454
4455 // DPLL requires a 16X reference clock from BRG
4456 set_rate(info, info->params.clock_speed * 16);
4457 }
4458 else
4459 set_rate(info, info->params.clock_speed);
4460
4461 tx_set_idle(info);
4462
4463 msc_set_vcr(info);
4464
4465 /* SCR (serial control)
4466 *
4467 * 15 1=tx req on FIFO half empty
4468 * 14 1=rx req on FIFO half full
4469 * 13 tx data IRQ enable
4470 * 12 tx idle IRQ enable
4471 * 11 underrun IRQ enable
4472 * 10 rx data IRQ enable
4473 * 09 rx idle IRQ enable
4474 * 08 overrun IRQ enable
4475 * 07 DSR IRQ enable
4476 * 06 CTS IRQ enable
4477 * 05 DCD IRQ enable
4478 * 04 RI IRQ enable
4479 * 03 reserved, must be zero
4480 * 02 1=txd->rxd internal loopback enable
4481 * 01 reserved, must be zero
4482 * 00 1=master IRQ enable
4483 */
4484 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4485
4486 if (info->params.loopback)
4487 enable_loopback(info);
4488 }
4489
4490 /*
4491 * set transmit idle mode
4492 */
4493 static void tx_set_idle(struct slgt_info *info)
4494 {
4495 unsigned char val;
4496 unsigned short tcr;
4497
4498 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4499 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4500 */
4501 tcr = rd_reg16(info, TCR);
4502 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4503 /* disable preamble, set idle size to 16 bits */
4504 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4505 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4506 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4507 } else if (!(tcr & BIT6)) {
4508 /* preamble is disabled, set idle size to 8 bits */
4509 tcr &= ~(BIT5 + BIT4);
4510 }
4511 wr_reg16(info, TCR, tcr);
4512
4513 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4514 /* LSB of custom tx idle specified in tx idle register */
4515 val = (unsigned char)(info->idle_mode & 0xff);
4516 } else {
4517 /* standard 8 bit idle patterns */
4518 switch(info->idle_mode)
4519 {
4520 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4521 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4522 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4523 case HDLC_TXIDLE_ZEROS:
4524 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4525 default: val = 0xff;
4526 }
4527 }
4528
4529 wr_reg8(info, TIR, val);
4530 }
4531
4532 /*
4533 * get state of V24 status (input) signals
4534 */
4535 static void get_signals(struct slgt_info *info)
4536 {
4537 unsigned short status = rd_reg16(info, SSR);
4538
4539 /* clear all serial signals except RTS and DTR */
4540 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4541
4542 if (status & BIT3)
4543 info->signals |= SerialSignal_DSR;
4544 if (status & BIT2)
4545 info->signals |= SerialSignal_CTS;
4546 if (status & BIT1)
4547 info->signals |= SerialSignal_DCD;
4548 if (status & BIT0)
4549 info->signals |= SerialSignal_RI;
4550 }
4551
4552 /*
4553 * set V.24 Control Register based on current configuration
4554 */
4555 static void msc_set_vcr(struct slgt_info *info)
4556 {
4557 unsigned char val = 0;
4558
4559 /* VCR (V.24 control)
4560 *
4561 * 07..04 serial IF select
4562 * 03 DTR
4563 * 02 RTS
4564 * 01 LL
4565 * 00 RL
4566 */
4567
4568 switch(info->if_mode & MGSL_INTERFACE_MASK)
4569 {
4570 case MGSL_INTERFACE_RS232:
4571 val |= BIT5; /* 0010 */
4572 break;
4573 case MGSL_INTERFACE_V35:
4574 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4575 break;
4576 case MGSL_INTERFACE_RS422:
4577 val |= BIT6; /* 0100 */
4578 break;
4579 }
4580
4581 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4582 val |= BIT4;
4583 if (info->signals & SerialSignal_DTR)
4584 val |= BIT3;
4585 if (info->signals & SerialSignal_RTS)
4586 val |= BIT2;
4587 if (info->if_mode & MGSL_INTERFACE_LL)
4588 val |= BIT1;
4589 if (info->if_mode & MGSL_INTERFACE_RL)
4590 val |= BIT0;
4591 wr_reg8(info, VCR, val);
4592 }
4593
4594 /*
4595 * set state of V24 control (output) signals
4596 */
4597 static void set_signals(struct slgt_info *info)
4598 {
4599 unsigned char val = rd_reg8(info, VCR);
4600 if (info->signals & SerialSignal_DTR)
4601 val |= BIT3;
4602 else
4603 val &= ~BIT3;
4604 if (info->signals & SerialSignal_RTS)
4605 val |= BIT2;
4606 else
4607 val &= ~BIT2;
4608 wr_reg8(info, VCR, val);
4609 }
4610
4611 /*
4612 * free range of receive DMA buffers (i to last)
4613 */
4614 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4615 {
4616 int done = 0;
4617
4618 while(!done) {
4619 /* reset current buffer for reuse */
4620 info->rbufs[i].status = 0;
4621 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4622 if (i == last)
4623 done = 1;
4624 if (++i == info->rbuf_count)
4625 i = 0;
4626 }
4627 info->rbuf_current = i;
4628 }
4629
4630 /*
4631 * mark all receive DMA buffers as free
4632 */
4633 static void reset_rbufs(struct slgt_info *info)
4634 {
4635 free_rbufs(info, 0, info->rbuf_count - 1);
4636 info->rbuf_fill_index = 0;
4637 info->rbuf_fill_count = 0;
4638 }
4639
4640 /*
4641 * pass receive HDLC frame to upper layer
4642 *
4643 * return true if frame available, otherwise false
4644 */
4645 static bool rx_get_frame(struct slgt_info *info)
4646 {
4647 unsigned int start, end;
4648 unsigned short status;
4649 unsigned int framesize = 0;
4650 unsigned long flags;
4651 struct tty_struct *tty = info->port.tty;
4652 unsigned char addr_field = 0xff;
4653 unsigned int crc_size = 0;
4654
4655 switch (info->params.crc_type & HDLC_CRC_MASK) {
4656 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4657 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4658 }
4659
4660 check_again:
4661
4662 framesize = 0;
4663 addr_field = 0xff;
4664 start = end = info->rbuf_current;
4665
4666 for (;;) {
4667 if (!desc_complete(info->rbufs[end]))
4668 goto cleanup;
4669
4670 if (framesize == 0 && info->params.addr_filter != 0xff)
4671 addr_field = info->rbufs[end].buf[0];
4672
4673 framesize += desc_count(info->rbufs[end]);
4674
4675 if (desc_eof(info->rbufs[end]))
4676 break;
4677
4678 if (++end == info->rbuf_count)
4679 end = 0;
4680
4681 if (end == info->rbuf_current) {
4682 if (info->rx_enabled){
4683 spin_lock_irqsave(&info->lock,flags);
4684 rx_start(info);
4685 spin_unlock_irqrestore(&info->lock,flags);
4686 }
4687 goto cleanup;
4688 }
4689 }
4690
4691 /* status
4692 *
4693 * 15 buffer complete
4694 * 14..06 reserved
4695 * 05..04 residue
4696 * 02 eof (end of frame)
4697 * 01 CRC error
4698 * 00 abort
4699 */
4700 status = desc_status(info->rbufs[end]);
4701
4702 /* ignore CRC bit if not using CRC (bit is undefined) */
4703 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4704 status &= ~BIT1;
4705
4706 if (framesize == 0 ||
4707 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4708 free_rbufs(info, start, end);
4709 goto check_again;
4710 }
4711
4712 if (framesize < (2 + crc_size) || status & BIT0) {
4713 info->icount.rxshort++;
4714 framesize = 0;
4715 } else if (status & BIT1) {
4716 info->icount.rxcrc++;
4717 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4718 framesize = 0;
4719 }
4720
4721 #if SYNCLINK_GENERIC_HDLC
4722 if (framesize == 0) {
4723 info->netdev->stats.rx_errors++;
4724 info->netdev->stats.rx_frame_errors++;
4725 }
4726 #endif
4727
4728 DBGBH(("%s rx frame status=%04X size=%d\n",
4729 info->device_name, status, framesize));
4730 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4731
4732 if (framesize) {
4733 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4734 framesize -= crc_size;
4735 crc_size = 0;
4736 }
4737
4738 if (framesize > info->max_frame_size + crc_size)
4739 info->icount.rxlong++;
4740 else {
4741 /* copy dma buffer(s) to contiguous temp buffer */
4742 int copy_count = framesize;
4743 int i = start;
4744 unsigned char *p = info->tmp_rbuf;
4745 info->tmp_rbuf_count = framesize;
4746
4747 info->icount.rxok++;
4748
4749 while(copy_count) {
4750 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4751 memcpy(p, info->rbufs[i].buf, partial_count);
4752 p += partial_count;
4753 copy_count -= partial_count;
4754 if (++i == info->rbuf_count)
4755 i = 0;
4756 }
4757
4758 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4759 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4760 framesize++;
4761 }
4762
4763 #if SYNCLINK_GENERIC_HDLC
4764 if (info->netcount)
4765 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4766 else
4767 #endif
4768 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4769 }
4770 }
4771 free_rbufs(info, start, end);
4772 return true;
4773
4774 cleanup:
4775 return false;
4776 }
4777
4778 /*
4779 * pass receive buffer (RAW synchronous mode) to tty layer
4780 * return true if buffer available, otherwise false
4781 */
4782 static bool rx_get_buf(struct slgt_info *info)
4783 {
4784 unsigned int i = info->rbuf_current;
4785 unsigned int count;
4786
4787 if (!desc_complete(info->rbufs[i]))
4788 return false;
4789 count = desc_count(info->rbufs[i]);
4790 switch(info->params.mode) {
4791 case MGSL_MODE_MONOSYNC:
4792 case MGSL_MODE_BISYNC:
4793 case MGSL_MODE_XSYNC:
4794 /* ignore residue in byte synchronous modes */
4795 if (desc_residue(info->rbufs[i]))
4796 count--;
4797 break;
4798 }
4799 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4800 DBGINFO(("rx_get_buf size=%d\n", count));
4801 if (count)
4802 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4803 info->flag_buf, count);
4804 free_rbufs(info, i, i);
4805 return true;
4806 }
4807
4808 static void reset_tbufs(struct slgt_info *info)
4809 {
4810 unsigned int i;
4811 info->tbuf_current = 0;
4812 for (i=0 ; i < info->tbuf_count ; i++) {
4813 info->tbufs[i].status = 0;
4814 info->tbufs[i].count = 0;
4815 }
4816 }
4817
4818 /*
4819 * return number of free transmit DMA buffers
4820 */
4821 static unsigned int free_tbuf_count(struct slgt_info *info)
4822 {
4823 unsigned int count = 0;
4824 unsigned int i = info->tbuf_current;
4825
4826 do
4827 {
4828 if (desc_count(info->tbufs[i]))
4829 break; /* buffer in use */
4830 ++count;
4831 if (++i == info->tbuf_count)
4832 i=0;
4833 } while (i != info->tbuf_current);
4834
4835 /* if tx DMA active, last zero count buffer is in use */
4836 if (count && (rd_reg32(info, TDCSR) & BIT0))
4837 --count;
4838
4839 return count;
4840 }
4841
4842 /*
4843 * return number of bytes in unsent transmit DMA buffers
4844 * and the serial controller tx FIFO
4845 */
4846 static unsigned int tbuf_bytes(struct slgt_info *info)
4847 {
4848 unsigned int total_count = 0;
4849 unsigned int i = info->tbuf_current;
4850 unsigned int reg_value;
4851 unsigned int count;
4852 unsigned int active_buf_count = 0;
4853
4854 /*
4855 * Add descriptor counts for all tx DMA buffers.
4856 * If count is zero (cleared by DMA controller after read),
4857 * the buffer is complete or is actively being read from.
4858 *
4859 * Record buf_count of last buffer with zero count starting
4860 * from current ring position. buf_count is mirror
4861 * copy of count and is not cleared by serial controller.
4862 * If DMA controller is active, that buffer is actively
4863 * being read so add to total.
4864 */
4865 do {
4866 count = desc_count(info->tbufs[i]);
4867 if (count)
4868 total_count += count;
4869 else if (!total_count)
4870 active_buf_count = info->tbufs[i].buf_count;
4871 if (++i == info->tbuf_count)
4872 i = 0;
4873 } while (i != info->tbuf_current);
4874
4875 /* read tx DMA status register */
4876 reg_value = rd_reg32(info, TDCSR);
4877
4878 /* if tx DMA active, last zero count buffer is in use */
4879 if (reg_value & BIT0)
4880 total_count += active_buf_count;
4881
4882 /* add tx FIFO count = reg_value[15..8] */
4883 total_count += (reg_value >> 8) & 0xff;
4884
4885 /* if transmitter active add one byte for shift register */
4886 if (info->tx_active)
4887 total_count++;
4888
4889 return total_count;
4890 }
4891
4892 /*
4893 * load data into transmit DMA buffer ring and start transmitter if needed
4894 * return true if data accepted, otherwise false (buffers full)
4895 */
4896 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4897 {
4898 unsigned short count;
4899 unsigned int i;
4900 struct slgt_desc *d;
4901
4902 /* check required buffer space */
4903 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4904 return false;
4905
4906 DBGDATA(info, buf, size, "tx");
4907
4908 /*
4909 * copy data to one or more DMA buffers in circular ring
4910 * tbuf_start = first buffer for this data
4911 * tbuf_current = next free buffer
4912 *
4913 * Copy all data before making data visible to DMA controller by
4914 * setting descriptor count of the first buffer.
4915 * This prevents an active DMA controller from reading the first DMA
4916 * buffers of a frame and stopping before the final buffers are filled.
4917 */
4918
4919 info->tbuf_start = i = info->tbuf_current;
4920
4921 while (size) {
4922 d = &info->tbufs[i];
4923
4924 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4925 memcpy(d->buf, buf, count);
4926
4927 size -= count;
4928 buf += count;
4929
4930 /*
4931 * set EOF bit for last buffer of HDLC frame or
4932 * for every buffer in raw mode
4933 */
4934 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4935 info->params.mode == MGSL_MODE_RAW)
4936 set_desc_eof(*d, 1);
4937 else
4938 set_desc_eof(*d, 0);
4939
4940 /* set descriptor count for all but first buffer */
4941 if (i != info->tbuf_start)
4942 set_desc_count(*d, count);
4943 d->buf_count = count;
4944
4945 if (++i == info->tbuf_count)
4946 i = 0;
4947 }
4948
4949 info->tbuf_current = i;
4950
4951 /* set first buffer count to make new data visible to DMA controller */
4952 d = &info->tbufs[info->tbuf_start];
4953 set_desc_count(*d, d->buf_count);
4954
4955 /* start transmitter if needed and update transmit timeout */
4956 if (!info->tx_active)
4957 tx_start(info);
4958 update_tx_timer(info);
4959
4960 return true;
4961 }
4962
4963 static int register_test(struct slgt_info *info)
4964 {
4965 static unsigned short patterns[] =
4966 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4967 static unsigned int count = ARRAY_SIZE(patterns);
4968 unsigned int i;
4969 int rc = 0;
4970
4971 for (i=0 ; i < count ; i++) {
4972 wr_reg16(info, TIR, patterns[i]);
4973 wr_reg16(info, BDR, patterns[(i+1)%count]);
4974 if ((rd_reg16(info, TIR) != patterns[i]) ||
4975 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4976 rc = -ENODEV;
4977 break;
4978 }
4979 }
4980 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4981 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4982 return rc;
4983 }
4984
4985 static int irq_test(struct slgt_info *info)
4986 {
4987 unsigned long timeout;
4988 unsigned long flags;
4989 struct tty_struct *oldtty = info->port.tty;
4990 u32 speed = info->params.data_rate;
4991
4992 info->params.data_rate = 921600;
4993 info->port.tty = NULL;
4994
4995 spin_lock_irqsave(&info->lock, flags);
4996 async_mode(info);
4997 slgt_irq_on(info, IRQ_TXIDLE);
4998
4999 /* enable transmitter */
5000 wr_reg16(info, TCR,
5001 (unsigned short)(rd_reg16(info, TCR) | BIT1));
5002
5003 /* write one byte and wait for tx idle */
5004 wr_reg16(info, TDR, 0);
5005
5006 /* assume failure */
5007 info->init_error = DiagStatus_IrqFailure;
5008 info->irq_occurred = false;
5009
5010 spin_unlock_irqrestore(&info->lock, flags);
5011
5012 timeout=100;
5013 while(timeout-- && !info->irq_occurred)
5014 msleep_interruptible(10);
5015
5016 spin_lock_irqsave(&info->lock,flags);
5017 reset_port(info);
5018 spin_unlock_irqrestore(&info->lock,flags);
5019
5020 info->params.data_rate = speed;
5021 info->port.tty = oldtty;
5022
5023 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5024 return info->irq_occurred ? 0 : -ENODEV;
5025 }
5026
5027 static int loopback_test_rx(struct slgt_info *info)
5028 {
5029 unsigned char *src, *dest;
5030 int count;
5031
5032 if (desc_complete(info->rbufs[0])) {
5033 count = desc_count(info->rbufs[0]);
5034 src = info->rbufs[0].buf;
5035 dest = info->tmp_rbuf;
5036
5037 for( ; count ; count-=2, src+=2) {
5038 /* src=data byte (src+1)=status byte */
5039 if (!(*(src+1) & (BIT9 + BIT8))) {
5040 *dest = *src;
5041 dest++;
5042 info->tmp_rbuf_count++;
5043 }
5044 }
5045 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5046 return 1;
5047 }
5048 return 0;
5049 }
5050
5051 static int loopback_test(struct slgt_info *info)
5052 {
5053 #define TESTFRAMESIZE 20
5054
5055 unsigned long timeout;
5056 u16 count = TESTFRAMESIZE;
5057 unsigned char buf[TESTFRAMESIZE];
5058 int rc = -ENODEV;
5059 unsigned long flags;
5060
5061 struct tty_struct *oldtty = info->port.tty;
5062 MGSL_PARAMS params;
5063
5064 memcpy(&params, &info->params, sizeof(params));
5065
5066 info->params.mode = MGSL_MODE_ASYNC;
5067 info->params.data_rate = 921600;
5068 info->params.loopback = 1;
5069 info->port.tty = NULL;
5070
5071 /* build and send transmit frame */
5072 for (count = 0; count < TESTFRAMESIZE; ++count)
5073 buf[count] = (unsigned char)count;
5074
5075 info->tmp_rbuf_count = 0;
5076 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5077
5078 /* program hardware for HDLC and enabled receiver */
5079 spin_lock_irqsave(&info->lock,flags);
5080 async_mode(info);
5081 rx_start(info);
5082 tx_load(info, buf, count);
5083 spin_unlock_irqrestore(&info->lock, flags);
5084
5085 /* wait for receive complete */
5086 for (timeout = 100; timeout; --timeout) {
5087 msleep_interruptible(10);
5088 if (loopback_test_rx(info)) {
5089 rc = 0;
5090 break;
5091 }
5092 }
5093
5094 /* verify received frame length and contents */
5095 if (!rc && (info->tmp_rbuf_count != count ||
5096 memcmp(buf, info->tmp_rbuf, count))) {
5097 rc = -ENODEV;
5098 }
5099
5100 spin_lock_irqsave(&info->lock,flags);
5101 reset_adapter(info);
5102 spin_unlock_irqrestore(&info->lock,flags);
5103
5104 memcpy(&info->params, &params, sizeof(info->params));
5105 info->port.tty = oldtty;
5106
5107 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5108 return rc;
5109 }
5110
5111 static int adapter_test(struct slgt_info *info)
5112 {
5113 DBGINFO(("testing %s\n", info->device_name));
5114 if (register_test(info) < 0) {
5115 printk("register test failure %s addr=%08X\n",
5116 info->device_name, info->phys_reg_addr);
5117 } else if (irq_test(info) < 0) {
5118 printk("IRQ test failure %s IRQ=%d\n",
5119 info->device_name, info->irq_level);
5120 } else if (loopback_test(info) < 0) {
5121 printk("loopback test failure %s\n", info->device_name);
5122 }
5123 return info->init_error;
5124 }
5125
5126 /*
5127 * transmit timeout handler
5128 */
5129 static void tx_timeout(unsigned long context)
5130 {
5131 struct slgt_info *info = (struct slgt_info*)context;
5132 unsigned long flags;
5133
5134 DBGINFO(("%s tx_timeout\n", info->device_name));
5135 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5136 info->icount.txtimeout++;
5137 }
5138 spin_lock_irqsave(&info->lock,flags);
5139 tx_stop(info);
5140 spin_unlock_irqrestore(&info->lock,flags);
5141
5142 #if SYNCLINK_GENERIC_HDLC
5143 if (info->netcount)
5144 hdlcdev_tx_done(info);
5145 else
5146 #endif
5147 bh_transmit(info);
5148 }
5149
5150 /*
5151 * receive buffer polling timer
5152 */
5153 static void rx_timeout(unsigned long context)
5154 {
5155 struct slgt_info *info = (struct slgt_info*)context;
5156 unsigned long flags;
5157
5158 DBGINFO(("%s rx_timeout\n", info->device_name));
5159 spin_lock_irqsave(&info->lock, flags);
5160 info->pending_bh |= BH_RECEIVE;
5161 spin_unlock_irqrestore(&info->lock, flags);
5162 bh_handler(&info->task);
5163 }
5164
Linux kernel - Deliverables
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