drivers/usb/chipidea/ci.h

   1 /*
   2  * ci.h - common structures, functions, and macros of the ChipIdea driver
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  14 #define __DRIVERS_USB_CHIPIDEA_CI_H
  15
  16 #include <linux/list.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <linux/usb/otg-fsm.h>
  21
  22 /******************************************************************************
  23  * DEFINE
  24  *****************************************************************************/
  25 #define TD_PAGE_COUNT      5
  26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  27 #define ENDPT_MAX          32
  28
  29 /******************************************************************************
  30  * REGISTERS
  31  *****************************************************************************/
  32 /* register indices */
  33 enum ci_hw_regs {
  34         CAP_CAPLENGTH,
  35         CAP_HCCPARAMS,
  36         CAP_DCCPARAMS,
  37         CAP_TESTMODE,
  38         CAP_LAST = CAP_TESTMODE,
  39         OP_USBCMD,
  40         OP_USBSTS,
  41         OP_USBINTR,
  42         OP_DEVICEADDR,
  43         OP_ENDPTLISTADDR,
  44         OP_PORTSC,
  45         OP_DEVLC,
  46         OP_OTGSC,
  47         OP_USBMODE,
  48         OP_ENDPTSETUPSTAT,
  49         OP_ENDPTPRIME,
  50         OP_ENDPTFLUSH,
  51         OP_ENDPTSTAT,
  52         OP_ENDPTCOMPLETE,
  53         OP_ENDPTCTRL,
  54         /* endptctrl1..15 follow */
  55         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  56 };
  57
  58 /******************************************************************************
  59  * STRUCTURES
  60  *****************************************************************************/
  61 /**
  62  * struct ci_hw_ep - endpoint representation
  63  * @ep: endpoint structure for gadget drivers
  64  * @dir: endpoint direction (TX/RX)
  65  * @num: endpoint number
  66  * @type: endpoint type
  67  * @name: string description of the endpoint
  68  * @qh: queue head for this endpoint
  69  * @wedge: is the endpoint wedged
  70  * @ci: pointer to the controller
  71  * @lock: pointer to controller's spinlock
  72  * @td_pool: pointer to controller's TD pool
  73  */
  74 struct ci_hw_ep {
  75         struct usb_ep                           ep;
  76         u8                                      dir;
  77         u8                                      num;
  78         u8                                      type;
  79         char                                    name[16];
  80         struct {
  81                 struct list_head        queue;
  82                 struct ci_hw_qh         *ptr;
  83                 dma_addr_t              dma;
  84         }                                       qh;
  85         int                                     wedge;
  86
  87         /* global resources */
  88         struct ci_hdrc                          *ci;
  89         spinlock_t                              *lock;
  90         struct dma_pool                         *td_pool;
  91         struct td_node                          *pending_td;
  92 };
  93
  94 enum ci_role {
  95         CI_ROLE_HOST = 0,
  96         CI_ROLE_GADGET,
  97         CI_ROLE_END,
  98 };
  99
 100 /**
 101  * struct ci_role_driver - host/gadget role driver
 102  * @start: start this role
 103  * @stop: stop this role
 104  * @irq: irq handler for this role
 105  * @name: role name string (host/gadget)
 106  */
 107 struct ci_role_driver {
 108         int             (*start)(struct ci_hdrc *);
 109         void            (*stop)(struct ci_hdrc *);
 110         irqreturn_t     (*irq)(struct ci_hdrc *);
 111         const char      *name;
 112 };
 113
 114 /**
 115  * struct hw_bank - hardware register mapping representation
 116  * @lpm: set if the device is LPM capable
 117  * @phys: physical address of the controller's registers
 118  * @abs: absolute address of the beginning of register window
 119  * @cap: capability registers
 120  * @op: operational registers
 121  * @size: size of the register window
 122  * @regmap: register lookup table
 123  */
 124 struct hw_bank {
 125         unsigned        lpm;
 126         resource_size_t phys;
 127         void __iomem    *abs;
 128         void __iomem    *cap;
 129         void __iomem    *op;
 130         size_t          size;
 131         void __iomem    *regmap[OP_LAST + 1];
 132 };
 133
 134 /**
 135  * struct ci_hdrc - chipidea device representation
 136  * @dev: pointer to parent device
 137  * @lock: access synchronization
 138  * @hw_bank: hardware register mapping
 139  * @irq: IRQ number
 140  * @roles: array of supported roles for this controller
 141  * @role: current role
 142  * @is_otg: if the device is otg-capable
 143  * @fsm: otg finite state machine
 144  * @fsm_timer: pointer to timer list of otg fsm
 145  * @work: work for role changing
 146  * @wq: workqueue thread
 147  * @qh_pool: allocation pool for queue heads
 148  * @td_pool: allocation pool for transfer descriptors
 149  * @gadget: device side representation for peripheral controller
 150  * @driver: gadget driver
 151  * @hw_ep_max: total number of endpoints supported by hardware
 152  * @ci_hw_ep: array of endpoints
 153  * @ep0_dir: ep0 direction
 154  * @ep0out: pointer to ep0 OUT endpoint
 155  * @ep0in: pointer to ep0 IN endpoint
 156  * @status: ep0 status request
 157  * @setaddr: if we should set the address on status completion
 158  * @address: usb address received from the host
 159  * @remote_wakeup: host-enabled remote wakeup
 160  * @suspended: suspended by host
 161  * @test_mode: the selected test mode
 162  * @platdata: platform specific information supplied by parent device
 163  * @vbus_active: is VBUS active
 164  * @phy: pointer to PHY, if any
 165  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 166  * @hcd: pointer to usb_hcd for ehci host driver
 167  * @debugfs: root dentry for this controller in debugfs
 168  * @id_event: indicates there is an id event, and handled at ci_otg_work
 169  * @b_sess_valid_event: indicates there is a vbus event, and handled
 170  * at ci_otg_work
 171  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 172  */
 173 struct ci_hdrc {
 174         struct device                   *dev;
 175         spinlock_t                      lock;
 176         struct hw_bank                  hw_bank;
 177         int                             irq;
 178         struct ci_role_driver           *roles[CI_ROLE_END];
 179         enum ci_role                    role;
 180         bool                            is_otg;
 181         struct usb_otg                  otg;
 182         struct otg_fsm                  fsm;
 183         struct ci_otg_fsm_timer_list    *fsm_timer;
 184         struct work_struct              work;
 185         struct workqueue_struct         *wq;
 186
 187         struct dma_pool                 *qh_pool;
 188         struct dma_pool                 *td_pool;
 189
 190         struct usb_gadget               gadget;
 191         struct usb_gadget_driver        *driver;
 192         unsigned                        hw_ep_max;
 193         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 194         u32                             ep0_dir;
 195         struct ci_hw_ep                 *ep0out, *ep0in;
 196
 197         struct usb_request              *status;
 198         bool                            setaddr;
 199         u8                              address;
 200         u8                              remote_wakeup;
 201         u8                              suspended;
 202         u8                              test_mode;
 203
 204         struct ci_hdrc_platform_data    *platdata;
 205         int                             vbus_active;
 206         struct phy                      *phy;
 207         /* old usb_phy interface */
 208         struct usb_phy                  *usb_phy;
 209         struct usb_hcd                  *hcd;
 210         struct dentry                   *debugfs;
 211         bool                            id_event;
 212         bool                            b_sess_valid_event;
 213         bool                            imx28_write_fix;
 214 };
 215
 216 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 217 {
 218         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 219         return ci->roles[ci->role];
 220 }
 221
 222 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 223 {
 224         int ret;
 225
 226         if (role >= CI_ROLE_END)
 227                 return -EINVAL;
 228
 229         if (!ci->roles[role])
 230                 return -ENXIO;
 231
 232         ret = ci->roles[role]->start(ci);
 233         if (!ret)
 234                 ci->role = role;
 235         return ret;
 236 }
 237
 238 static inline void ci_role_stop(struct ci_hdrc *ci)
 239 {
 240         enum ci_role role = ci->role;
 241
 242         if (role == CI_ROLE_END)
 243                 return;
 244
 245         ci->role = CI_ROLE_END;
 246
 247         ci->roles[role]->stop(ci);
 248 }
 249
 250 /**
 251  * hw_read: reads from a hw register
 252  * @ci: the controller
 253  * @reg:  register index
 254  * @mask: bitfield mask
 255  *
 256  * This function returns register contents
 257  */
 258 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 259 {
 260         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 261 }
 262
 263 #ifdef CONFIG_SOC_IMX28
 264 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 265 {
 266         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 267 }
 268 #else
 269 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 270 {
 271 }
 272 #endif
 273
 274 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 275                 void __iomem *addr)
 276 {
 277         if (ci->imx28_write_fix)
 278                 imx28_ci_writel(val, addr);
 279         else
 280                 iowrite32(val, addr);
 281 }
 282
 283 /**
 284  * hw_write: writes to a hw register
 285  * @ci: the controller
 286  * @reg:  register index
 287  * @mask: bitfield mask
 288  * @data: new value
 289  */
 290 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 291                             u32 mask, u32 data)
 292 {
 293         if (~mask)
 294                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 295                         | (data & mask);
 296
 297         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 298 }
 299
 300 /**
 301  * hw_test_and_clear: tests & clears a hw register
 302  * @ci: the controller
 303  * @reg:  register index
 304  * @mask: bitfield mask
 305  *
 306  * This function returns register contents
 307  */
 308 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 309                                     u32 mask)
 310 {
 311         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 312
 313         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 314         return val;
 315 }
 316
 317 /**
 318  * hw_test_and_write: tests & writes a hw register
 319  * @ci: the controller
 320  * @reg:  register index
 321  * @mask: bitfield mask
 322  * @data: new value
 323  *
 324  * This function returns register contents
 325  */
 326 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 327                                     u32 mask, u32 data)
 328 {
 329         u32 val = hw_read(ci, reg, ~0);
 330
 331         hw_write(ci, reg, mask, data);
 332         return (val & mask) >> __ffs(mask);
 333 }
 334
 335 /**
 336  * ci_otg_is_fsm_mode: runtime check if otg controller
 337  * is in otg fsm mode.
 338  *
 339  * @ci: chipidea device
 340  */
 341 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
 342 {
 343 #ifdef CONFIG_USB_OTG_FSM
 344         return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
 345                                         ci->roles[CI_ROLE_GADGET];
 346 #else
 347         return false;
 348 #endif
 349 }
 350
 351 u32 hw_read_intr_enable(struct ci_hdrc *ci);
 352
 353 u32 hw_read_intr_status(struct ci_hdrc *ci);
 354
 355 int hw_device_reset(struct ci_hdrc *ci);
 356
 357 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 358
 359 u8 hw_port_test_get(struct ci_hdrc *ci);
 360
 361 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
 362                                 u32 value, unsigned int timeout_ms);
 363
 364 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */