drivers/usb/chipidea/core.c

   1 /*
   2  * core.c - ChipIdea USB IP core family device controller
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 /*
  14  * Description: ChipIdea USB IP core family device controller
  15  *
  16  * This driver is composed of several blocks:
  17  * - HW:     hardware interface
  18  * - DBG:    debug facilities (optional)
  19  * - UTIL:   utilities
  20  * - ISR:    interrupts handling
  21  * - ENDPT:  endpoint operations (Gadget API)
  22  * - GADGET: gadget operations (Gadget API)
  23  * - BUS:    bus glue code, bus abstraction layer
  24  *
  25  * Compile Options
  26  * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
  28  *              if defined mass storage compliance succeeds but with warnings
  29  *              => case 4: Hi >  Dn
  30  *              => case 5: Hi >  Di
  31  *              => case 8: Hi <> Do
  32  *              if undefined usbtest 13 fails
  33  * - TRACE:     enable function tracing (depends on DEBUG)
  34  *
  35  * Main Features
  36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38  * - Normal & LPM support
  39  *
  40  * USBTEST Report
  41  * - OK: 0-12, 13 (STALL_IN defined) & 14
  42  * - Not Supported: 15 & 16 (ISO)
  43  *
  44  * TODO List
  45  * - OTG
  46  * - Interrupt Traffic
  47  * - GET_STATUS(device) - always reports 0
  48  * - Gadget API (majority of optional features)
  49  * - Suspend & Remote Wakeup
  50  */
  51 #include <linux/delay.h>
  52 #include <linux/device.h>
  53 #include <linux/dma-mapping.h>
  54 #include <linux/platform_device.h>
  55 #include <linux/module.h>
  56 #include <linux/idr.h>
  57 #include <linux/interrupt.h>
  58 #include <linux/io.h>
  59 #include <linux/kernel.h>
  60 #include <linux/slab.h>
  61 #include <linux/pm_runtime.h>
  62 #include <linux/usb/ch9.h>
  63 #include <linux/usb/gadget.h>
  64 #include <linux/usb/otg.h>
  65 #include <linux/usb/chipidea.h>
  66 #include <linux/usb/of.h>
  67 #include <linux/phy.h>
  68 #include <linux/regulator/consumer.h>
  69
  70 #include "ci.h"
  71 #include "udc.h"
  72 #include "bits.h"
  73 #include "host.h"
  74 #include "debug.h"
  75 #include "otg.h"
  76
  77 /* Controller register map */
  78 static uintptr_t ci_regs_nolpm[] = {
  79         [CAP_CAPLENGTH]         = 0x000UL,
  80         [CAP_HCCPARAMS]         = 0x008UL,
  81         [CAP_DCCPARAMS]         = 0x024UL,
  82         [CAP_TESTMODE]          = 0x038UL,
  83         [OP_USBCMD]             = 0x000UL,
  84         [OP_USBSTS]             = 0x004UL,
  85         [OP_USBINTR]            = 0x008UL,
  86         [OP_DEVICEADDR]         = 0x014UL,
  87         [OP_ENDPTLISTADDR]      = 0x018UL,
  88         [OP_PORTSC]             = 0x044UL,
  89         [OP_DEVLC]              = 0x084UL,
  90         [OP_OTGSC]              = 0x064UL,
  91         [OP_USBMODE]            = 0x068UL,
  92         [OP_ENDPTSETUPSTAT]     = 0x06CUL,
  93         [OP_ENDPTPRIME]         = 0x070UL,
  94         [OP_ENDPTFLUSH]         = 0x074UL,
  95         [OP_ENDPTSTAT]          = 0x078UL,
  96         [OP_ENDPTCOMPLETE]      = 0x07CUL,
  97         [OP_ENDPTCTRL]          = 0x080UL,
  98 };
  99
 100 static uintptr_t ci_regs_lpm[] = {
 101         [CAP_CAPLENGTH]         = 0x000UL,
 102         [CAP_HCCPARAMS]         = 0x008UL,
 103         [CAP_DCCPARAMS]         = 0x024UL,
 104         [CAP_TESTMODE]          = 0x0FCUL,
 105         [OP_USBCMD]             = 0x000UL,
 106         [OP_USBSTS]             = 0x004UL,
 107         [OP_USBINTR]            = 0x008UL,
 108         [OP_DEVICEADDR]         = 0x014UL,
 109         [OP_ENDPTLISTADDR]      = 0x018UL,
 110         [OP_PORTSC]             = 0x044UL,
 111         [OP_DEVLC]              = 0x084UL,
 112         [OP_OTGSC]              = 0x0C4UL,
 113         [OP_USBMODE]            = 0x0C8UL,
 114         [OP_ENDPTSETUPSTAT]     = 0x0D8UL,
 115         [OP_ENDPTPRIME]         = 0x0DCUL,
 116         [OP_ENDPTFLUSH]         = 0x0E0UL,
 117         [OP_ENDPTSTAT]          = 0x0E4UL,
 118         [OP_ENDPTCOMPLETE]      = 0x0E8UL,
 119         [OP_ENDPTCTRL]          = 0x0ECUL,
 120 };
 121
 122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
 123 {
 124         int i;
 125
 126         kfree(ci->hw_bank.regmap);
 127
 128         ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
 129                                      GFP_KERNEL);
 130         if (!ci->hw_bank.regmap)
 131                 return -ENOMEM;
 132
 133         for (i = 0; i < OP_ENDPTCTRL; i++)
 134                 ci->hw_bank.regmap[i] =
 135                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 136                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 137
 138         for (; i <= OP_LAST; i++)
 139                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
 140                         4 * (i - OP_ENDPTCTRL) +
 141                         (is_lpm
 142                          ? ci_regs_lpm[OP_ENDPTCTRL]
 143                          : ci_regs_nolpm[OP_ENDPTCTRL]);
 144
 145         return 0;
 146 }
 147
 148 /**
 149  * hw_port_test_set: writes port test mode (execute without interruption)
 150  * @mode: new value
 151  *
 152  * This function returns an error code
 153  */
 154 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 155 {
 156         const u8 TEST_MODE_MAX = 7;
 157
 158         if (mode > TEST_MODE_MAX)
 159                 return -EINVAL;
 160
 161         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 162         return 0;
 163 }
 164
 165 /**
 166  * hw_port_test_get: reads port test mode value
 167  *
 168  * This function returns port test mode value
 169  */
 170 u8 hw_port_test_get(struct ci_hdrc *ci)
 171 {
 172         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 173 }
 174
 175 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 176 {
 177         u32 reg;
 178
 179         /* bank is a module variable */
 180         ci->hw_bank.abs = base;
 181
 182         ci->hw_bank.cap = ci->hw_bank.abs;
 183         ci->hw_bank.cap += ci->platdata->capoffset;
 184         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 185
 186         hw_alloc_regmap(ci, false);
 187         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 188                 __ffs(HCCPARAMS_LEN);
 189         ci->hw_bank.lpm  = reg;
 190         hw_alloc_regmap(ci, !!reg);
 191         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 192         ci->hw_bank.size += OP_LAST;
 193         ci->hw_bank.size /= sizeof(u32);
 194
 195         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 196                 __ffs(DCCPARAMS_DEN);
 197         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 198
 199         if (ci->hw_ep_max > ENDPT_MAX)
 200                 return -ENODEV;
 201
 202         dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
 203                 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 204
 205         /* setup lock mode ? */
 206
 207         /* ENDPTSETUPSTAT is '0' by default */
 208
 209         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 210
 211         return 0;
 212 }
 213
 214 static void hw_phymode_configure(struct ci_hdrc *ci)
 215 {
 216         u32 portsc, lpm, sts;
 217
 218         switch (ci->platdata->phy_mode) {
 219         case USBPHY_INTERFACE_MODE_UTMI:
 220                 portsc = PORTSC_PTS(PTS_UTMI);
 221                 lpm = DEVLC_PTS(PTS_UTMI);
 222                 break;
 223         case USBPHY_INTERFACE_MODE_UTMIW:
 224                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 225                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 226                 break;
 227         case USBPHY_INTERFACE_MODE_ULPI:
 228                 portsc = PORTSC_PTS(PTS_ULPI);
 229                 lpm = DEVLC_PTS(PTS_ULPI);
 230                 break;
 231         case USBPHY_INTERFACE_MODE_SERIAL:
 232                 portsc = PORTSC_PTS(PTS_SERIAL);
 233                 lpm = DEVLC_PTS(PTS_SERIAL);
 234                 sts = 1;
 235                 break;
 236         case USBPHY_INTERFACE_MODE_HSIC:
 237                 portsc = PORTSC_PTS(PTS_HSIC);
 238                 lpm = DEVLC_PTS(PTS_HSIC);
 239                 break;
 240         default:
 241                 return;
 242         }
 243
 244         if (ci->hw_bank.lpm) {
 245                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 246                 hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
 247         } else {
 248                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 249                 hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
 250         }
 251 }
 252
 253 /**
 254  * hw_device_reset: resets chip (execute without interruption)
 255  * @ci: the controller
 256   *
 257  * This function returns an error code
 258  */
 259 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
 260 {
 261         /* should flush & stop before reset */
 262         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 263         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 264
 265         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 266         while (hw_read(ci, OP_USBCMD, USBCMD_RST))
 267                 udelay(10);             /* not RTOS friendly */
 268
 269         if (ci->platdata->notify_event)
 270                 ci->platdata->notify_event(ci,
 271                         CI_HDRC_CONTROLLER_RESET_EVENT);
 272
 273         if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
 274                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 275
 276         /* USBMODE should be configured step by step */
 277         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 278         hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
 279         /* HW >= 2.3 */
 280         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 281
 282         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
 283                 pr_err("cannot enter in %s mode", ci_role(ci)->name);
 284                 pr_err("lpm = %i", ci->hw_bank.lpm);
 285                 return -ENODEV;
 286         }
 287
 288         return 0;
 289 }
 290
 291 /**
 292  * ci_otg_role - pick role based on ID pin state
 293  * @ci: the controller
 294  */
 295 static enum ci_role ci_otg_role(struct ci_hdrc *ci)
 296 {
 297         u32 sts = hw_read(ci, OP_OTGSC, ~0);
 298         enum ci_role role = sts & OTGSC_ID
 299                 ? CI_ROLE_GADGET
 300                 : CI_ROLE_HOST;
 301
 302         return role;
 303 }
 304
 305 /**
 306  * ci_role_work - perform role changing based on ID pin
 307  * @work: work struct
 308  */
 309 static void ci_role_work(struct work_struct *work)
 310 {
 311         struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
 312         enum ci_role role = ci_otg_role(ci);
 313
 314         if (role != ci->role) {
 315                 dev_dbg(ci->dev, "switching from %s to %s\n",
 316                         ci_role(ci)->name, ci->roles[role]->name);
 317
 318                 ci_role_stop(ci);
 319                 ci_role_start(ci, role);
 320         }
 321
 322         enable_irq(ci->irq);
 323 }
 324
 325 static irqreturn_t ci_irq(int irq, void *data)
 326 {
 327         struct ci_hdrc *ci = data;
 328         irqreturn_t ret = IRQ_NONE;
 329         u32 otgsc = 0;
 330
 331         if (ci->is_otg)
 332                 otgsc = hw_read(ci, OP_OTGSC, ~0);
 333
 334         if (ci->role != CI_ROLE_END)
 335                 ret = ci_role(ci)->irq(ci);
 336
 337         if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
 338                 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
 339                 disable_irq_nosync(ci->irq);
 340                 queue_work(ci->wq, &ci->work);
 341                 ret = IRQ_HANDLED;
 342         }
 343
 344         return ret;
 345 }
 346
 347 static int ci_get_platdata(struct device *dev,
 348                 struct ci_hdrc_platform_data *platdata)
 349 {
 350         /* Get the vbus regulator */
 351         platdata->reg_vbus = devm_regulator_get(dev, "vbus");
 352         if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 353                 return -EPROBE_DEFER;
 354         } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 355                 platdata->reg_vbus = NULL; /* no vbus regualator is needed */
 356         } else if (IS_ERR(platdata->reg_vbus)) {
 357                 dev_err(dev, "Getting regulator error: %ld\n",
 358                         PTR_ERR(platdata->reg_vbus));
 359                 return PTR_ERR(platdata->reg_vbus);
 360         }
 361
 362         return 0;
 363 }
 364
 365 static DEFINE_IDA(ci_ida);
 366
 367 struct platform_device *ci_hdrc_add_device(struct device *dev,
 368                         struct resource *res, int nres,
 369                         struct ci_hdrc_platform_data *platdata)
 370 {
 371         struct platform_device *pdev;
 372         int id, ret;
 373
 374         ret = ci_get_platdata(dev, platdata);
 375         if (ret)
 376                 return ERR_PTR(ret);
 377
 378         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 379         if (id < 0)
 380                 return ERR_PTR(id);
 381
 382         pdev = platform_device_alloc("ci_hdrc", id);
 383         if (!pdev) {
 384                 ret = -ENOMEM;
 385                 goto put_id;
 386         }
 387
 388         pdev->dev.parent = dev;
 389         pdev->dev.dma_mask = dev->dma_mask;
 390         pdev->dev.dma_parms = dev->dma_parms;
 391         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
 392
 393         ret = platform_device_add_resources(pdev, res, nres);
 394         if (ret)
 395                 goto err;
 396
 397         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 398         if (ret)
 399                 goto err;
 400
 401         ret = platform_device_add(pdev);
 402         if (ret)
 403                 goto err;
 404
 405         return pdev;
 406
 407 err:
 408         platform_device_put(pdev);
 409 put_id:
 410         ida_simple_remove(&ci_ida, id);
 411         return ERR_PTR(ret);
 412 }
 413 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 414
 415 void ci_hdrc_remove_device(struct platform_device *pdev)
 416 {
 417         int id = pdev->id;
 418         platform_device_unregister(pdev);
 419         ida_simple_remove(&ci_ida, id);
 420 }
 421 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 422
 423 static int ci_hdrc_probe(struct platform_device *pdev)
 424 {
 425         struct device   *dev = &pdev->dev;
 426         struct ci_hdrc  *ci;
 427         struct resource *res;
 428         void __iomem    *base;
 429         int             ret;
 430         enum usb_dr_mode dr_mode;
 431         struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
 432
 433         if (!dev->platform_data) {
 434                 dev_err(dev, "platform data missing\n");
 435                 return -ENODEV;
 436         }
 437
 438         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 439         base = devm_ioremap_resource(dev, res);
 440         if (IS_ERR(base))
 441                 return PTR_ERR(base);
 442
 443         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
 444         if (!ci) {
 445                 dev_err(dev, "can't allocate device\n");
 446                 return -ENOMEM;
 447         }
 448
 449         ci->dev = dev;
 450         ci->platdata = dev->platform_data;
 451         if (ci->platdata->phy)
 452                 ci->transceiver = ci->platdata->phy;
 453         else
 454                 ci->global_phy = true;
 455
 456         ret = hw_device_init(ci, base);
 457         if (ret < 0) {
 458                 dev_err(dev, "can't initialize hardware\n");
 459                 return -ENODEV;
 460         }
 461
 462         ci->hw_bank.phys = res->start;
 463
 464         ci->irq = platform_get_irq(pdev, 0);
 465         if (ci->irq < 0) {
 466                 dev_err(dev, "missing IRQ\n");
 467                 return -ENODEV;
 468         }
 469
 470         INIT_WORK(&ci->work, ci_role_work);
 471         ci->wq = create_singlethread_workqueue("ci_otg");
 472         if (!ci->wq) {
 473                 dev_err(dev, "can't create workqueue\n");
 474                 return -ENODEV;
 475         }
 476
 477         if (!ci->platdata->phy_mode)
 478                 ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
 479
 480         hw_phymode_configure(ci);
 481
 482         if (!ci->platdata->dr_mode)
 483                 ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
 484
 485         if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 486                 ci->platdata->dr_mode = USB_DR_MODE_OTG;
 487
 488         dr_mode = ci->platdata->dr_mode;
 489         /* initialize role(s) before the interrupt is requested */
 490         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
 491                 ret = ci_hdrc_host_init(ci);
 492                 if (ret)
 493                         dev_info(dev, "doesn't support host\n");
 494         }
 495
 496         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
 497                 ret = ci_hdrc_gadget_init(ci);
 498                 if (ret)
 499                         dev_info(dev, "doesn't support gadget\n");
 500         }
 501
 502         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
 503                 dev_err(dev, "no supported roles\n");
 504                 ret = -ENODEV;
 505                 goto rm_wq;
 506         }
 507
 508         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
 509                 ci->is_otg = true;
 510                 /* ID pin needs 1ms debouce time, we delay 2ms for safe */
 511                 mdelay(2);
 512                 ci->role = ci_otg_role(ci);
 513         } else {
 514                 ci->role = ci->roles[CI_ROLE_HOST]
 515                         ? CI_ROLE_HOST
 516                         : CI_ROLE_GADGET;
 517         }
 518
 519         ret = ci_role_start(ci, ci->role);
 520         if (ret) {
 521                 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
 522                 goto rm_wq;
 523         }
 524
 525         platform_set_drvdata(pdev, ci);
 526         ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
 527                           ci);
 528         if (ret)
 529                 goto stop;
 530
 531         if (ci->is_otg)
 532                 ci_hdrc_otg_init(ci);
 533
 534         ret = dbg_create_files(ci);
 535         if (!ret)
 536                 return 0;
 537
 538         free_irq(ci->irq, ci);
 539 stop:
 540         ci_role_stop(ci);
 541 rm_wq:
 542         flush_workqueue(ci->wq);
 543         destroy_workqueue(ci->wq);
 544
 545         return ret;
 546 }
 547
 548 static int ci_hdrc_remove(struct platform_device *pdev)
 549 {
 550         struct ci_hdrc *ci = platform_get_drvdata(pdev);
 551
 552         dbg_remove_files(ci);
 553         flush_workqueue(ci->wq);
 554         destroy_workqueue(ci->wq);
 555         free_irq(ci->irq, ci);
 556         ci_role_stop(ci);
 557
 558         return 0;
 559 }
 560
 561 static struct platform_driver ci_hdrc_driver = {
 562         .probe  = ci_hdrc_probe,
 563         .remove = ci_hdrc_remove,
 564         .driver = {
 565                 .name   = "ci_hdrc",
 566         },
 567 };
 568
 569 module_platform_driver(ci_hdrc_driver);
 570
 571 MODULE_ALIAS("platform:ci_hdrc");
 572 MODULE_LICENSE("GPL v2");
 573 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
 574 MODULE_DESCRIPTION("ChipIdea HDRC Driver");