2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
46 * - Isochronous & Interrupt Traffic
47 * - Handle requests which spawns into several TDs
48 * - GET_STATUS(device) - always reports 0
49 * - Gadget API (majority of optional features)
50 * - Suspend & Remote Wakeup
52 #include <linux/delay.h>
53 #include <linux/device.h>
54 #include <linux/dmapool.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/init.h>
57 #include <linux/platform_device.h>
58 #include <linux/module.h>
59 #include <linux/interrupt.h>
61 #include <linux/irq.h>
62 #include <linux/kernel.h>
63 #include <linux/slab.h>
64 #include <linux/pm_runtime.h>
65 #include <linux/usb/ch9.h>
66 #include <linux/usb/gadget.h>
67 #include <linux/usb/otg.h>
68 #include <linux/usb/chipidea.h>
75 /* Controller register map */
76 static uintptr_t ci_regs_nolpm
[] = {
77 [CAP_CAPLENGTH
] = 0x000UL
,
78 [CAP_HCCPARAMS
] = 0x008UL
,
79 [CAP_DCCPARAMS
] = 0x024UL
,
80 [CAP_TESTMODE
] = 0x038UL
,
81 [OP_USBCMD
] = 0x000UL
,
82 [OP_USBSTS
] = 0x004UL
,
83 [OP_USBINTR
] = 0x008UL
,
84 [OP_DEVICEADDR
] = 0x014UL
,
85 [OP_ENDPTLISTADDR
] = 0x018UL
,
86 [OP_PORTSC
] = 0x044UL
,
89 [OP_USBMODE
] = 0x068UL
,
90 [OP_ENDPTSETUPSTAT
] = 0x06CUL
,
91 [OP_ENDPTPRIME
] = 0x070UL
,
92 [OP_ENDPTFLUSH
] = 0x074UL
,
93 [OP_ENDPTSTAT
] = 0x078UL
,
94 [OP_ENDPTCOMPLETE
] = 0x07CUL
,
95 [OP_ENDPTCTRL
] = 0x080UL
,
98 static uintptr_t ci_regs_lpm
[] = {
99 [CAP_CAPLENGTH
] = 0x000UL
,
100 [CAP_HCCPARAMS
] = 0x008UL
,
101 [CAP_DCCPARAMS
] = 0x024UL
,
102 [CAP_TESTMODE
] = 0x0FCUL
,
103 [OP_USBCMD
] = 0x000UL
,
104 [OP_USBSTS
] = 0x004UL
,
105 [OP_USBINTR
] = 0x008UL
,
106 [OP_DEVICEADDR
] = 0x014UL
,
107 [OP_ENDPTLISTADDR
] = 0x018UL
,
108 [OP_PORTSC
] = 0x044UL
,
109 [OP_DEVLC
] = 0x084UL
,
110 [OP_OTGSC
] = 0x0C4UL
,
111 [OP_USBMODE
] = 0x0C8UL
,
112 [OP_ENDPTSETUPSTAT
] = 0x0D8UL
,
113 [OP_ENDPTPRIME
] = 0x0DCUL
,
114 [OP_ENDPTFLUSH
] = 0x0E0UL
,
115 [OP_ENDPTSTAT
] = 0x0E4UL
,
116 [OP_ENDPTCOMPLETE
] = 0x0E8UL
,
117 [OP_ENDPTCTRL
] = 0x0ECUL
,
120 static int hw_alloc_regmap(struct ci13xxx
*ci
, bool is_lpm
)
124 kfree(ci
->hw_bank
.regmap
);
126 ci
->hw_bank
.regmap
= kzalloc((OP_LAST
+ 1) * sizeof(void *),
128 if (!ci
->hw_bank
.regmap
)
131 for (i
= 0; i
< OP_ENDPTCTRL
; i
++)
132 ci
->hw_bank
.regmap
[i
] =
133 (i
<= CAP_LAST
? ci
->hw_bank
.cap
: ci
->hw_bank
.op
) +
134 (is_lpm
? ci_regs_lpm
[i
] : ci_regs_nolpm
[i
]);
136 for (; i
<= OP_LAST
; i
++)
137 ci
->hw_bank
.regmap
[i
] = ci
->hw_bank
.op
+
138 4 * (i
- OP_ENDPTCTRL
) +
140 ? ci_regs_lpm
[OP_ENDPTCTRL
]
141 : ci_regs_nolpm
[OP_ENDPTCTRL
]);
147 * hw_port_test_set: writes port test mode (execute without interruption)
150 * This function returns an error code
152 int hw_port_test_set(struct ci13xxx
*ci
, u8 mode
)
154 const u8 TEST_MODE_MAX
= 7;
156 if (mode
> TEST_MODE_MAX
)
159 hw_write(ci
, OP_PORTSC
, PORTSC_PTC
, mode
<< ffs_nr(PORTSC_PTC
));
164 * hw_port_test_get: reads port test mode value
166 * This function returns port test mode value
168 u8
hw_port_test_get(struct ci13xxx
*ci
)
170 return hw_read(ci
, OP_PORTSC
, PORTSC_PTC
) >> ffs_nr(PORTSC_PTC
);
173 static int hw_device_init(struct ci13xxx
*ci
, void __iomem
*base
)
177 /* bank is a module variable */
178 ci
->hw_bank
.abs
= base
;
180 ci
->hw_bank
.cap
= ci
->hw_bank
.abs
;
181 ci
->hw_bank
.cap
+= ci
->udc_driver
->capoffset
;
182 ci
->hw_bank
.op
= ci
->hw_bank
.cap
+ ioread8(ci
->hw_bank
.cap
);
184 hw_alloc_regmap(ci
, false);
185 reg
= hw_read(ci
, CAP_HCCPARAMS
, HCCPARAMS_LEN
) >>
186 ffs_nr(HCCPARAMS_LEN
);
187 ci
->hw_bank
.lpm
= reg
;
188 hw_alloc_regmap(ci
, !!reg
);
189 ci
->hw_bank
.size
= ci
->hw_bank
.op
- ci
->hw_bank
.abs
;
190 ci
->hw_bank
.size
+= OP_LAST
;
191 ci
->hw_bank
.size
/= sizeof(u32
);
193 reg
= hw_read(ci
, CAP_DCCPARAMS
, DCCPARAMS_DEN
) >>
194 ffs_nr(DCCPARAMS_DEN
);
195 ci
->hw_ep_max
= reg
* 2; /* cache hw ENDPT_MAX */
197 if (ci
->hw_ep_max
== 0 || ci
->hw_ep_max
> ENDPT_MAX
)
200 dev_dbg(ci
->dev
, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
201 ci
->hw_bank
.lpm
, ci
->hw_bank
.cap
, ci
->hw_bank
.op
);
203 /* setup lock mode ? */
205 /* ENDPTSETUPSTAT is '0' by default */
207 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
213 * hw_device_reset: resets chip (execute without interruption)
214 * @ci: the controller
216 * This function returns an error code
218 int hw_device_reset(struct ci13xxx
*ci
)
220 /* should flush & stop before reset */
221 hw_write(ci
, OP_ENDPTFLUSH
, ~0, ~0);
222 hw_write(ci
, OP_USBCMD
, USBCMD_RS
, 0);
224 hw_write(ci
, OP_USBCMD
, USBCMD_RST
, USBCMD_RST
);
225 while (hw_read(ci
, OP_USBCMD
, USBCMD_RST
))
226 udelay(10); /* not RTOS friendly */
229 if (ci
->udc_driver
->notify_event
)
230 ci
->udc_driver
->notify_event(ci
,
231 CI13XXX_CONTROLLER_RESET_EVENT
);
233 if (ci
->udc_driver
->flags
& CI13XXX_DISABLE_STREAMING
)
234 hw_write(ci
, OP_USBMODE
, USBMODE_SDIS
, USBMODE_SDIS
);
236 /* USBMODE should be configured step by step */
237 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_IDLE
);
238 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_DEVICE
);
240 hw_write(ci
, OP_USBMODE
, USBMODE_SLOM
, USBMODE_SLOM
);
242 if (hw_read(ci
, OP_USBMODE
, USBMODE_CM
) != USBMODE_CM_DEVICE
) {
243 pr_err("cannot enter in device mode");
244 pr_err("lpm = %i", ci
->hw_bank
.lpm
);
252 * ci_otg_role - pick role based on ID pin state
253 * @ci: the controller
255 static enum ci_role
ci_otg_role(struct ci13xxx
*ci
)
257 u32 sts
= hw_read(ci
, OP_OTGSC
, ~0);
258 enum ci_role role
= sts
& OTGSC_ID
266 * ci_role_work - perform role changing based on ID pin
269 static void ci_role_work(struct work_struct
*work
)
271 struct ci13xxx
*ci
= container_of(work
, struct ci13xxx
, work
);
272 enum ci_role role
= ci_otg_role(ci
);
274 hw_write(ci
, OP_OTGSC
, OTGSC_IDIS
, OTGSC_IDIS
);
276 if (role
!= ci
->role
) {
277 dev_dbg(ci
->dev
, "switching from %s to %s\n",
278 ci_role(ci
)->name
, ci
->roles
[role
]->name
);
281 ci_role_start(ci
, role
);
285 static ssize_t
show_role(struct device
*dev
, struct device_attribute
*attr
,
288 struct ci13xxx
*ci
= dev_get_drvdata(dev
);
290 return sprintf(buf
, "%s\n", ci_role(ci
)->name
);
293 static ssize_t
store_role(struct device
*dev
, struct device_attribute
*attr
,
294 const char *buf
, size_t count
)
296 struct ci13xxx
*ci
= dev_get_drvdata(dev
);
300 for (role
= CI_ROLE_HOST
; role
< CI_ROLE_END
; role
++)
301 if (ci
->roles
[role
] && !strcmp(buf
, ci
->roles
[role
]->name
))
304 if (role
== CI_ROLE_END
|| role
== ci
->role
)
308 ret
= ci_role_start(ci
, role
);
315 static DEVICE_ATTR(role
, S_IRUSR
| S_IWUSR
, show_role
, store_role
);
317 static irqreturn_t
ci_irq(int irq
, void *data
)
319 struct ci13xxx
*ci
= data
;
320 irqreturn_t ret
= IRQ_NONE
;
323 u32 sts
= hw_read(ci
, OP_OTGSC
, ~0);
325 if (sts
& OTGSC_IDIS
) {
326 queue_work(ci
->wq
, &ci
->work
);
331 return ci
->role
== CI_ROLE_END
? ret
: ci_role(ci
)->irq(ci
);
334 static int __devinit
ci_hdrc_probe(struct platform_device
*pdev
)
336 struct device
*dev
= &pdev
->dev
;
338 struct resource
*res
;
342 if (!dev
->platform_data
) {
343 dev_err(dev
, "platform data missing\n");
347 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
349 dev_err(dev
, "missing resource\n");
353 base
= devm_request_and_ioremap(dev
, res
);
355 dev_err(dev
, "can't request and ioremap resource\n");
359 ci
= devm_kzalloc(dev
, sizeof(*ci
), GFP_KERNEL
);
361 dev_err(dev
, "can't allocate device\n");
366 ci
->udc_driver
= dev
->platform_data
;
368 ret
= hw_device_init(ci
, base
);
370 dev_err(dev
, "can't initialize hardware\n");
374 ci
->irq
= platform_get_irq(pdev
, 0);
376 dev_err(dev
, "missing IRQ\n");
380 INIT_WORK(&ci
->work
, ci_role_work
);
381 ci
->wq
= create_singlethread_workqueue("ci_otg");
383 dev_err(dev
, "can't create workqueue\n");
387 /* initialize role(s) before the interrupt is requested */
388 ret
= ci_hdrc_gadget_init(ci
);
390 dev_info(dev
, "doesn't support gadget\n");
392 if (!ci
->roles
[CI_ROLE_HOST
] && !ci
->roles
[CI_ROLE_GADGET
]) {
393 dev_err(dev
, "no supported roles\n");
398 if (ci
->roles
[CI_ROLE_HOST
] && ci
->roles
[CI_ROLE_GADGET
]) {
400 ci
->role
= ci_otg_role(ci
);
402 ci
->role
= ci
->roles
[CI_ROLE_HOST
]
407 ret
= ci_role_start(ci
, ci
->role
);
409 dev_err(dev
, "can't start %s role\n", ci_role(ci
)->name
);
414 platform_set_drvdata(pdev
, ci
);
415 ret
= request_irq(ci
->irq
, ci_irq
, IRQF_SHARED
, ci
->udc_driver
->name
,
420 ret
= device_create_file(dev
, &dev_attr_role
);
425 hw_write(ci
, OP_OTGSC
, OTGSC_IDIE
, OTGSC_IDIE
);
430 device_remove_file(dev
, &dev_attr_role
);
434 flush_workqueue(ci
->wq
);
435 destroy_workqueue(ci
->wq
);
440 static int __devexit
ci_hdrc_remove(struct platform_device
*pdev
)
442 struct ci13xxx
*ci
= platform_get_drvdata(pdev
);
444 flush_workqueue(ci
->wq
);
445 destroy_workqueue(ci
->wq
);
446 device_remove_file(ci
->dev
, &dev_attr_role
);
447 free_irq(ci
->irq
, ci
);
453 static struct platform_driver ci_hdrc_driver
= {
454 .probe
= ci_hdrc_probe
,
455 .remove
= __devexit_p(ci_hdrc_remove
),
461 module_platform_driver(ci_hdrc_driver
);
463 MODULE_ALIAS("platform:ci_hdrc");
464 MODULE_ALIAS("platform:ci13xxx");
465 MODULE_LICENSE("GPL v2");
466 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
467 MODULE_DESCRIPTION("ChipIdea HDRC Driver");