2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
67 #include <linux/phy.h>
68 #include <linux/regulator/consumer.h>
77 /* Controller register map */
78 static uintptr_t ci_regs_nolpm
[] = {
79 [CAP_CAPLENGTH
] = 0x000UL
,
80 [CAP_HCCPARAMS
] = 0x008UL
,
81 [CAP_DCCPARAMS
] = 0x024UL
,
82 [CAP_TESTMODE
] = 0x038UL
,
83 [OP_USBCMD
] = 0x000UL
,
84 [OP_USBSTS
] = 0x004UL
,
85 [OP_USBINTR
] = 0x008UL
,
86 [OP_DEVICEADDR
] = 0x014UL
,
87 [OP_ENDPTLISTADDR
] = 0x018UL
,
88 [OP_PORTSC
] = 0x044UL
,
91 [OP_USBMODE
] = 0x068UL
,
92 [OP_ENDPTSETUPSTAT
] = 0x06CUL
,
93 [OP_ENDPTPRIME
] = 0x070UL
,
94 [OP_ENDPTFLUSH
] = 0x074UL
,
95 [OP_ENDPTSTAT
] = 0x078UL
,
96 [OP_ENDPTCOMPLETE
] = 0x07CUL
,
97 [OP_ENDPTCTRL
] = 0x080UL
,
100 static uintptr_t ci_regs_lpm
[] = {
101 [CAP_CAPLENGTH
] = 0x000UL
,
102 [CAP_HCCPARAMS
] = 0x008UL
,
103 [CAP_DCCPARAMS
] = 0x024UL
,
104 [CAP_TESTMODE
] = 0x0FCUL
,
105 [OP_USBCMD
] = 0x000UL
,
106 [OP_USBSTS
] = 0x004UL
,
107 [OP_USBINTR
] = 0x008UL
,
108 [OP_DEVICEADDR
] = 0x014UL
,
109 [OP_ENDPTLISTADDR
] = 0x018UL
,
110 [OP_PORTSC
] = 0x044UL
,
111 [OP_DEVLC
] = 0x084UL
,
112 [OP_OTGSC
] = 0x0C4UL
,
113 [OP_USBMODE
] = 0x0C8UL
,
114 [OP_ENDPTSETUPSTAT
] = 0x0D8UL
,
115 [OP_ENDPTPRIME
] = 0x0DCUL
,
116 [OP_ENDPTFLUSH
] = 0x0E0UL
,
117 [OP_ENDPTSTAT
] = 0x0E4UL
,
118 [OP_ENDPTCOMPLETE
] = 0x0E8UL
,
119 [OP_ENDPTCTRL
] = 0x0ECUL
,
122 static int hw_alloc_regmap(struct ci_hdrc
*ci
, bool is_lpm
)
126 kfree(ci
->hw_bank
.regmap
);
128 ci
->hw_bank
.regmap
= kzalloc((OP_LAST
+ 1) * sizeof(void *),
130 if (!ci
->hw_bank
.regmap
)
133 for (i
= 0; i
< OP_ENDPTCTRL
; i
++)
134 ci
->hw_bank
.regmap
[i
] =
135 (i
<= CAP_LAST
? ci
->hw_bank
.cap
: ci
->hw_bank
.op
) +
136 (is_lpm
? ci_regs_lpm
[i
] : ci_regs_nolpm
[i
]);
138 for (; i
<= OP_LAST
; i
++)
139 ci
->hw_bank
.regmap
[i
] = ci
->hw_bank
.op
+
140 4 * (i
- OP_ENDPTCTRL
) +
142 ? ci_regs_lpm
[OP_ENDPTCTRL
]
143 : ci_regs_nolpm
[OP_ENDPTCTRL
]);
149 * hw_port_test_set: writes port test mode (execute without interruption)
152 * This function returns an error code
154 int hw_port_test_set(struct ci_hdrc
*ci
, u8 mode
)
156 const u8 TEST_MODE_MAX
= 7;
158 if (mode
> TEST_MODE_MAX
)
161 hw_write(ci
, OP_PORTSC
, PORTSC_PTC
, mode
<< __ffs(PORTSC_PTC
));
166 * hw_port_test_get: reads port test mode value
168 * This function returns port test mode value
170 u8
hw_port_test_get(struct ci_hdrc
*ci
)
172 return hw_read(ci
, OP_PORTSC
, PORTSC_PTC
) >> __ffs(PORTSC_PTC
);
175 /* The PHY enters/leaves low power mode */
176 static void ci_hdrc_enter_lpm(struct ci_hdrc
*ci
, bool enable
)
178 enum ci_hw_regs reg
= ci
->hw_bank
.lpm
? OP_DEVLC
: OP_PORTSC
;
179 bool lpm
= !!(hw_read(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
)));
181 if (enable
&& !lpm
) {
182 hw_write(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
),
183 PORTSC_PHCD(ci
->hw_bank
.lpm
));
184 } else if (!enable
&& lpm
) {
185 hw_write(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
),
188 * The controller needs at least 1ms to reflect
189 * PHY's status, the PHY also needs some time (less
190 * than 1ms) to leave low power mode.
192 usleep_range(1500, 2000);
196 static int hw_device_init(struct ci_hdrc
*ci
, void __iomem
*base
)
200 /* bank is a module variable */
201 ci
->hw_bank
.abs
= base
;
203 ci
->hw_bank
.cap
= ci
->hw_bank
.abs
;
204 ci
->hw_bank
.cap
+= ci
->platdata
->capoffset
;
205 ci
->hw_bank
.op
= ci
->hw_bank
.cap
+ (ioread32(ci
->hw_bank
.cap
) & 0xff);
207 hw_alloc_regmap(ci
, false);
208 reg
= hw_read(ci
, CAP_HCCPARAMS
, HCCPARAMS_LEN
) >>
209 __ffs(HCCPARAMS_LEN
);
210 ci
->hw_bank
.lpm
= reg
;
211 hw_alloc_regmap(ci
, !!reg
);
212 ci
->hw_bank
.size
= ci
->hw_bank
.op
- ci
->hw_bank
.abs
;
213 ci
->hw_bank
.size
+= OP_LAST
;
214 ci
->hw_bank
.size
/= sizeof(u32
);
216 reg
= hw_read(ci
, CAP_DCCPARAMS
, DCCPARAMS_DEN
) >>
217 __ffs(DCCPARAMS_DEN
);
218 ci
->hw_ep_max
= reg
* 2; /* cache hw ENDPT_MAX */
220 if (ci
->hw_ep_max
> ENDPT_MAX
)
223 ci_hdrc_enter_lpm(ci
, false);
225 /* Disable all interrupts bits */
226 hw_write(ci
, OP_USBINTR
, 0xffffffff, 0);
228 /* Clear all interrupts status bits*/
229 hw_write(ci
, OP_USBSTS
, 0xffffffff, 0xffffffff);
231 dev_dbg(ci
->dev
, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
232 ci
->hw_bank
.lpm
, ci
->hw_bank
.cap
, ci
->hw_bank
.op
);
234 /* setup lock mode ? */
236 /* ENDPTSETUPSTAT is '0' by default */
238 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
243 static void hw_phymode_configure(struct ci_hdrc
*ci
)
245 u32 portsc
, lpm
, sts
;
247 switch (ci
->platdata
->phy_mode
) {
248 case USBPHY_INTERFACE_MODE_UTMI
:
249 portsc
= PORTSC_PTS(PTS_UTMI
);
250 lpm
= DEVLC_PTS(PTS_UTMI
);
252 case USBPHY_INTERFACE_MODE_UTMIW
:
253 portsc
= PORTSC_PTS(PTS_UTMI
) | PORTSC_PTW
;
254 lpm
= DEVLC_PTS(PTS_UTMI
) | DEVLC_PTW
;
256 case USBPHY_INTERFACE_MODE_ULPI
:
257 portsc
= PORTSC_PTS(PTS_ULPI
);
258 lpm
= DEVLC_PTS(PTS_ULPI
);
260 case USBPHY_INTERFACE_MODE_SERIAL
:
261 portsc
= PORTSC_PTS(PTS_SERIAL
);
262 lpm
= DEVLC_PTS(PTS_SERIAL
);
265 case USBPHY_INTERFACE_MODE_HSIC
:
266 portsc
= PORTSC_PTS(PTS_HSIC
);
267 lpm
= DEVLC_PTS(PTS_HSIC
);
273 if (ci
->hw_bank
.lpm
) {
274 hw_write(ci
, OP_DEVLC
, DEVLC_PTS(7) | DEVLC_PTW
, lpm
);
275 hw_write(ci
, OP_DEVLC
, DEVLC_STS
, sts
);
277 hw_write(ci
, OP_PORTSC
, PORTSC_PTS(7) | PORTSC_PTW
, portsc
);
278 hw_write(ci
, OP_PORTSC
, PORTSC_STS
, sts
);
283 * hw_device_reset: resets chip (execute without interruption)
284 * @ci: the controller
286 * This function returns an error code
288 int hw_device_reset(struct ci_hdrc
*ci
, u32 mode
)
290 /* should flush & stop before reset */
291 hw_write(ci
, OP_ENDPTFLUSH
, ~0, ~0);
292 hw_write(ci
, OP_USBCMD
, USBCMD_RS
, 0);
294 hw_write(ci
, OP_USBCMD
, USBCMD_RST
, USBCMD_RST
);
295 while (hw_read(ci
, OP_USBCMD
, USBCMD_RST
))
296 udelay(10); /* not RTOS friendly */
298 if (ci
->platdata
->notify_event
)
299 ci
->platdata
->notify_event(ci
,
300 CI_HDRC_CONTROLLER_RESET_EVENT
);
302 if (ci
->platdata
->flags
& CI_HDRC_DISABLE_STREAMING
)
303 hw_write(ci
, OP_USBMODE
, USBMODE_CI_SDIS
, USBMODE_CI_SDIS
);
305 /* USBMODE should be configured step by step */
306 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_IDLE
);
307 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, mode
);
309 hw_write(ci
, OP_USBMODE
, USBMODE_SLOM
, USBMODE_SLOM
);
311 if (hw_read(ci
, OP_USBMODE
, USBMODE_CM
) != mode
) {
312 pr_err("cannot enter in %s mode", ci_role(ci
)->name
);
313 pr_err("lpm = %i", ci
->hw_bank
.lpm
);
321 * hw_wait_reg: wait the register value
323 * Sometimes, it needs to wait register value before going on.
324 * Eg, when switch to device mode, the vbus value should be lower
325 * than OTGSC_BSV before connects to host.
327 * @ci: the controller
328 * @reg: register index
330 * @value: the bit value to wait
331 * @timeout_ms: timeout in millisecond
333 * This function returns an error code if timeout
335 int hw_wait_reg(struct ci_hdrc
*ci
, enum ci_hw_regs reg
, u32 mask
,
336 u32 value
, unsigned int timeout_ms
)
338 unsigned long elapse
= jiffies
+ msecs_to_jiffies(timeout_ms
);
340 while (hw_read(ci
, reg
, mask
) != value
) {
341 if (time_after(jiffies
, elapse
)) {
342 dev_err(ci
->dev
, "timeout waiting for %08x in %d\n",
352 static irqreturn_t
ci_irq(int irq
, void *data
)
354 struct ci_hdrc
*ci
= data
;
355 irqreturn_t ret
= IRQ_NONE
;
359 otgsc
= hw_read(ci
, OP_OTGSC
, ~0);
362 * Handle id change interrupt, it indicates device/host function
365 if (ci
->is_otg
&& (otgsc
& OTGSC_IDIE
) && (otgsc
& OTGSC_IDIS
)) {
367 ci_clear_otg_interrupt(ci
, OTGSC_IDIS
);
368 disable_irq_nosync(ci
->irq
);
369 queue_work(ci
->wq
, &ci
->work
);
374 * Handle vbus change interrupt, it indicates device connection
375 * and disconnection events.
377 if (ci
->is_otg
&& (otgsc
& OTGSC_BSVIE
) && (otgsc
& OTGSC_BSVIS
)) {
378 ci
->b_sess_valid_event
= true;
379 ci_clear_otg_interrupt(ci
, OTGSC_BSVIS
);
380 disable_irq_nosync(ci
->irq
);
381 queue_work(ci
->wq
, &ci
->work
);
385 /* Handle device/host interrupt */
386 if (ci
->role
!= CI_ROLE_END
)
387 ret
= ci_role(ci
)->irq(ci
);
392 static int ci_get_platdata(struct device
*dev
,
393 struct ci_hdrc_platform_data
*platdata
)
395 if (!platdata
->phy_mode
)
396 platdata
->phy_mode
= of_usb_get_phy_mode(dev
->of_node
);
398 if (!platdata
->dr_mode
)
399 platdata
->dr_mode
= of_usb_get_dr_mode(dev
->of_node
);
401 if (platdata
->dr_mode
== USB_DR_MODE_UNKNOWN
)
402 platdata
->dr_mode
= USB_DR_MODE_OTG
;
404 if (platdata
->dr_mode
!= USB_DR_MODE_PERIPHERAL
) {
405 /* Get the vbus regulator */
406 platdata
->reg_vbus
= devm_regulator_get(dev
, "vbus");
407 if (PTR_ERR(platdata
->reg_vbus
) == -EPROBE_DEFER
) {
408 return -EPROBE_DEFER
;
409 } else if (PTR_ERR(platdata
->reg_vbus
) == -ENODEV
) {
410 /* no vbus regualator is needed */
411 platdata
->reg_vbus
= NULL
;
412 } else if (IS_ERR(platdata
->reg_vbus
)) {
413 dev_err(dev
, "Getting regulator error: %ld\n",
414 PTR_ERR(platdata
->reg_vbus
));
415 return PTR_ERR(platdata
->reg_vbus
);
422 static DEFINE_IDA(ci_ida
);
424 struct platform_device
*ci_hdrc_add_device(struct device
*dev
,
425 struct resource
*res
, int nres
,
426 struct ci_hdrc_platform_data
*platdata
)
428 struct platform_device
*pdev
;
431 ret
= ci_get_platdata(dev
, platdata
);
435 id
= ida_simple_get(&ci_ida
, 0, 0, GFP_KERNEL
);
439 pdev
= platform_device_alloc("ci_hdrc", id
);
445 pdev
->dev
.parent
= dev
;
446 pdev
->dev
.dma_mask
= dev
->dma_mask
;
447 pdev
->dev
.dma_parms
= dev
->dma_parms
;
448 dma_set_coherent_mask(&pdev
->dev
, dev
->coherent_dma_mask
);
450 ret
= platform_device_add_resources(pdev
, res
, nres
);
454 ret
= platform_device_add_data(pdev
, platdata
, sizeof(*platdata
));
458 ret
= platform_device_add(pdev
);
465 platform_device_put(pdev
);
467 ida_simple_remove(&ci_ida
, id
);
470 EXPORT_SYMBOL_GPL(ci_hdrc_add_device
);
472 void ci_hdrc_remove_device(struct platform_device
*pdev
)
475 platform_device_unregister(pdev
);
476 ida_simple_remove(&ci_ida
, id
);
478 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device
);
480 static inline void ci_role_destroy(struct ci_hdrc
*ci
)
482 ci_hdrc_gadget_destroy(ci
);
483 ci_hdrc_host_destroy(ci
);
485 ci_hdrc_otg_destroy(ci
);
488 static void ci_get_otg_capable(struct ci_hdrc
*ci
)
490 if (ci
->platdata
->flags
& CI_HDRC_DUAL_ROLE_NOT_OTG
)
493 ci
->is_otg
= (hw_read(ci
, CAP_DCCPARAMS
,
494 DCCPARAMS_DC
| DCCPARAMS_HC
)
495 == (DCCPARAMS_DC
| DCCPARAMS_HC
));
497 dev_dbg(ci
->dev
, "It is OTG capable controller\n");
498 ci_disable_otg_interrupt(ci
, OTGSC_INT_EN_BITS
);
499 ci_clear_otg_interrupt(ci
, OTGSC_INT_STATUS_BITS
);
503 static int ci_usb_phy_init(struct ci_hdrc
*ci
)
505 if (ci
->platdata
->phy
) {
506 ci
->transceiver
= ci
->platdata
->phy
;
507 return usb_phy_init(ci
->transceiver
);
509 ci
->global_phy
= true;
510 ci
->transceiver
= usb_get_phy(USB_PHY_TYPE_USB2
);
511 if (IS_ERR(ci
->transceiver
))
512 ci
->transceiver
= NULL
;
518 static void ci_usb_phy_destroy(struct ci_hdrc
*ci
)
520 if (!ci
->transceiver
)
523 otg_set_peripheral(ci
->transceiver
->otg
, NULL
);
525 usb_put_phy(ci
->transceiver
);
527 usb_phy_shutdown(ci
->transceiver
);
530 static int ci_hdrc_probe(struct platform_device
*pdev
)
532 struct device
*dev
= &pdev
->dev
;
534 struct resource
*res
;
537 enum usb_dr_mode dr_mode
;
539 if (!dev
->platform_data
) {
540 dev_err(dev
, "platform data missing\n");
544 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
545 base
= devm_ioremap_resource(dev
, res
);
547 return PTR_ERR(base
);
549 ci
= devm_kzalloc(dev
, sizeof(*ci
), GFP_KERNEL
);
551 dev_err(dev
, "can't allocate device\n");
556 ci
->platdata
= dev
->platform_data
;
558 ret
= hw_device_init(ci
, base
);
560 dev_err(dev
, "can't initialize hardware\n");
564 ret
= ci_usb_phy_init(ci
);
566 dev_err(dev
, "unable to init phy: %d\n", ret
);
570 ci
->hw_bank
.phys
= res
->start
;
572 ci
->irq
= platform_get_irq(pdev
, 0);
574 dev_err(dev
, "missing IRQ\n");
579 ci_get_otg_capable(ci
);
581 hw_phymode_configure(ci
);
583 dr_mode
= ci
->platdata
->dr_mode
;
584 /* initialize role(s) before the interrupt is requested */
585 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_HOST
) {
586 ret
= ci_hdrc_host_init(ci
);
588 dev_info(dev
, "doesn't support host\n");
591 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_PERIPHERAL
) {
592 ret
= ci_hdrc_gadget_init(ci
);
594 dev_info(dev
, "doesn't support gadget\n");
595 if (!ret
&& ci
->transceiver
) {
596 ret
= otg_set_peripheral(ci
->transceiver
->otg
,
599 * If we implement all USB functions using chipidea drivers,
600 * it doesn't need to call above API, meanwhile, if we only
601 * use gadget function, calling above API is useless.
603 if (ret
&& ret
!= -ENOTSUPP
)
608 if (!ci
->roles
[CI_ROLE_HOST
] && !ci
->roles
[CI_ROLE_GADGET
]) {
609 dev_err(dev
, "no supported roles\n");
615 ret
= ci_hdrc_otg_init(ci
);
617 dev_err(dev
, "init otg fails, ret = %d\n", ret
);
622 if (ci
->roles
[CI_ROLE_HOST
] && ci
->roles
[CI_ROLE_GADGET
]) {
625 * ID pin needs 1ms debouce time,
626 * we delay 2ms for safe.
629 ci
->role
= ci_otg_role(ci
);
630 ci_enable_otg_interrupt(ci
, OTGSC_IDIE
);
633 * If the controller is not OTG capable, but support
634 * role switch, the defalt role is gadget, and the
635 * user can switch it through debugfs.
637 ci
->role
= CI_ROLE_GADGET
;
640 ci
->role
= ci
->roles
[CI_ROLE_HOST
]
645 ret
= ci_role_start(ci
, ci
->role
);
647 dev_err(dev
, "can't start %s role\n", ci_role(ci
)->name
);
651 platform_set_drvdata(pdev
, ci
);
652 ret
= request_irq(ci
->irq
, ci_irq
, IRQF_SHARED
, ci
->platdata
->name
,
657 ret
= dbg_create_files(ci
);
661 free_irq(ci
->irq
, ci
);
665 ci_usb_phy_destroy(ci
);
670 static int ci_hdrc_remove(struct platform_device
*pdev
)
672 struct ci_hdrc
*ci
= platform_get_drvdata(pdev
);
674 dbg_remove_files(ci
);
675 free_irq(ci
->irq
, ci
);
677 ci_hdrc_enter_lpm(ci
, true);
678 ci_usb_phy_destroy(ci
);
679 kfree(ci
->hw_bank
.regmap
);
684 static struct platform_driver ci_hdrc_driver
= {
685 .probe
= ci_hdrc_probe
,
686 .remove
= ci_hdrc_remove
,
692 module_platform_driver(ci_hdrc_driver
);
694 MODULE_ALIAS("platform:ci_hdrc");
695 MODULE_LICENSE("GPL v2");
696 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
697 MODULE_DESCRIPTION("ChipIdea HDRC Driver");