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[deliverable/linux.git] / drivers / usb / chipidea / core.c
1 /*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - Suspend & Remote Wakeup
46 */
47 #include <linux/delay.h>
48 #include <linux/device.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
55 #include <linux/io.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
64 #include <linux/of.h>
65 #include <linux/phy.h>
66 #include <linux/regulator/consumer.h>
67
68 #include "ci.h"
69 #include "udc.h"
70 #include "bits.h"
71 #include "host.h"
72 #include "debug.h"
73 #include "otg.h"
74 #include "otg_fsm.h"
75
76 /* Controller register map */
77 static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
82 [OP_USBCMD] = 0x00U,
83 [OP_USBSTS] = 0x04U,
84 [OP_USBINTR] = 0x08U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97 };
98
99 static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_PORTSC] = 0x44U,
110 [OP_DEVLC] = 0x84U,
111 [OP_OTGSC] = 0xC4U,
112 [OP_USBMODE] = 0xC8U,
113 [OP_ENDPTSETUPSTAT] = 0xD8U,
114 [OP_ENDPTPRIME] = 0xDCU,
115 [OP_ENDPTFLUSH] = 0xE0U,
116 [OP_ENDPTSTAT] = 0xE4U,
117 [OP_ENDPTCOMPLETE] = 0xE8U,
118 [OP_ENDPTCTRL] = 0xECU,
119 };
120
121 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
122 {
123 int i;
124
125 for (i = 0; i < OP_ENDPTCTRL; i++)
126 ci->hw_bank.regmap[i] =
127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
129
130 for (; i <= OP_LAST; i++)
131 ci->hw_bank.regmap[i] = ci->hw_bank.op +
132 4 * (i - OP_ENDPTCTRL) +
133 (is_lpm
134 ? ci_regs_lpm[OP_ENDPTCTRL]
135 : ci_regs_nolpm[OP_ENDPTCTRL]);
136
137 return 0;
138 }
139
140 /**
141 * hw_read_intr_enable: returns interrupt enable register
142 *
143 * @ci: the controller
144 *
145 * This function returns register data
146 */
147 u32 hw_read_intr_enable(struct ci_hdrc *ci)
148 {
149 return hw_read(ci, OP_USBINTR, ~0);
150 }
151
152 /**
153 * hw_read_intr_status: returns interrupt status register
154 *
155 * @ci: the controller
156 *
157 * This function returns register data
158 */
159 u32 hw_read_intr_status(struct ci_hdrc *ci)
160 {
161 return hw_read(ci, OP_USBSTS, ~0);
162 }
163
164 /**
165 * hw_port_test_set: writes port test mode (execute without interruption)
166 * @mode: new value
167 *
168 * This function returns an error code
169 */
170 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
171 {
172 const u8 TEST_MODE_MAX = 7;
173
174 if (mode > TEST_MODE_MAX)
175 return -EINVAL;
176
177 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
178 return 0;
179 }
180
181 /**
182 * hw_port_test_get: reads port test mode value
183 *
184 * @ci: the controller
185 *
186 * This function returns port test mode value
187 */
188 u8 hw_port_test_get(struct ci_hdrc *ci)
189 {
190 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
191 }
192
193 /* The PHY enters/leaves low power mode */
194 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
195 {
196 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
197 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
198
199 if (enable && !lpm)
200 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
201 PORTSC_PHCD(ci->hw_bank.lpm));
202 else if (!enable && lpm)
203 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
204 0);
205 }
206
207 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
208 {
209 u32 reg;
210
211 /* bank is a module variable */
212 ci->hw_bank.abs = base;
213
214 ci->hw_bank.cap = ci->hw_bank.abs;
215 ci->hw_bank.cap += ci->platdata->capoffset;
216 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
217
218 hw_alloc_regmap(ci, false);
219 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
220 __ffs(HCCPARAMS_LEN);
221 ci->hw_bank.lpm = reg;
222 if (reg)
223 hw_alloc_regmap(ci, !!reg);
224 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
225 ci->hw_bank.size += OP_LAST;
226 ci->hw_bank.size /= sizeof(u32);
227
228 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
229 __ffs(DCCPARAMS_DEN);
230 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
231
232 if (ci->hw_ep_max > ENDPT_MAX)
233 return -ENODEV;
234
235 ci_hdrc_enter_lpm(ci, false);
236
237 /* Disable all interrupts bits */
238 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
239
240 /* Clear all interrupts status bits*/
241 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
242
243 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
244 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
245
246 /* setup lock mode ? */
247
248 /* ENDPTSETUPSTAT is '0' by default */
249
250 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
251
252 return 0;
253 }
254
255 static void hw_phymode_configure(struct ci_hdrc *ci)
256 {
257 u32 portsc, lpm, sts = 0;
258
259 switch (ci->platdata->phy_mode) {
260 case USBPHY_INTERFACE_MODE_UTMI:
261 portsc = PORTSC_PTS(PTS_UTMI);
262 lpm = DEVLC_PTS(PTS_UTMI);
263 break;
264 case USBPHY_INTERFACE_MODE_UTMIW:
265 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
266 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
267 break;
268 case USBPHY_INTERFACE_MODE_ULPI:
269 portsc = PORTSC_PTS(PTS_ULPI);
270 lpm = DEVLC_PTS(PTS_ULPI);
271 break;
272 case USBPHY_INTERFACE_MODE_SERIAL:
273 portsc = PORTSC_PTS(PTS_SERIAL);
274 lpm = DEVLC_PTS(PTS_SERIAL);
275 sts = 1;
276 break;
277 case USBPHY_INTERFACE_MODE_HSIC:
278 portsc = PORTSC_PTS(PTS_HSIC);
279 lpm = DEVLC_PTS(PTS_HSIC);
280 break;
281 default:
282 return;
283 }
284
285 if (ci->hw_bank.lpm) {
286 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
287 if (sts)
288 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
289 } else {
290 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
291 if (sts)
292 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
293 }
294 }
295
296 /**
297 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
298 * interfaces
299 * @ci: the controller
300 *
301 * This function returns an error code if the phy failed to init
302 */
303 static int _ci_usb_phy_init(struct ci_hdrc *ci)
304 {
305 int ret;
306
307 if (ci->phy) {
308 ret = phy_init(ci->phy);
309 if (ret)
310 return ret;
311
312 ret = phy_power_on(ci->phy);
313 if (ret) {
314 phy_exit(ci->phy);
315 return ret;
316 }
317 } else {
318 ret = usb_phy_init(ci->usb_phy);
319 }
320
321 return ret;
322 }
323
324 /**
325 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
326 * interfaces
327 * @ci: the controller
328 */
329 static void ci_usb_phy_exit(struct ci_hdrc *ci)
330 {
331 if (ci->phy) {
332 phy_power_off(ci->phy);
333 phy_exit(ci->phy);
334 } else {
335 usb_phy_shutdown(ci->usb_phy);
336 }
337 }
338
339 /**
340 * ci_usb_phy_init: initialize phy according to different phy type
341 * @ci: the controller
342 *
343 * This function returns an error code if usb_phy_init has failed
344 */
345 static int ci_usb_phy_init(struct ci_hdrc *ci)
346 {
347 int ret;
348
349 switch (ci->platdata->phy_mode) {
350 case USBPHY_INTERFACE_MODE_UTMI:
351 case USBPHY_INTERFACE_MODE_UTMIW:
352 case USBPHY_INTERFACE_MODE_HSIC:
353 ret = _ci_usb_phy_init(ci);
354 if (ret)
355 return ret;
356 hw_phymode_configure(ci);
357 break;
358 case USBPHY_INTERFACE_MODE_ULPI:
359 case USBPHY_INTERFACE_MODE_SERIAL:
360 hw_phymode_configure(ci);
361 ret = _ci_usb_phy_init(ci);
362 if (ret)
363 return ret;
364 break;
365 default:
366 ret = _ci_usb_phy_init(ci);
367 }
368
369 return ret;
370 }
371
372 /**
373 * hw_device_reset: resets chip (execute without interruption)
374 * @ci: the controller
375 *
376 * This function returns an error code
377 */
378 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
379 {
380 /* should flush & stop before reset */
381 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
382 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
383
384 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
385 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
386 udelay(10); /* not RTOS friendly */
387
388 if (ci->platdata->notify_event)
389 ci->platdata->notify_event(ci,
390 CI_HDRC_CONTROLLER_RESET_EVENT);
391
392 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
393 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
394
395 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
396 if (ci->hw_bank.lpm)
397 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
398 else
399 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
400 }
401
402 /* USBMODE should be configured step by step */
403 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
404 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
405 /* HW >= 2.3 */
406 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
407
408 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
409 pr_err("cannot enter in %s mode", ci_role(ci)->name);
410 pr_err("lpm = %i", ci->hw_bank.lpm);
411 return -ENODEV;
412 }
413
414 return 0;
415 }
416
417 /**
418 * hw_wait_reg: wait the register value
419 *
420 * Sometimes, it needs to wait register value before going on.
421 * Eg, when switch to device mode, the vbus value should be lower
422 * than OTGSC_BSV before connects to host.
423 *
424 * @ci: the controller
425 * @reg: register index
426 * @mask: mast bit
427 * @value: the bit value to wait
428 * @timeout_ms: timeout in millisecond
429 *
430 * This function returns an error code if timeout
431 */
432 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
433 u32 value, unsigned int timeout_ms)
434 {
435 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
436
437 while (hw_read(ci, reg, mask) != value) {
438 if (time_after(jiffies, elapse)) {
439 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
440 mask, reg);
441 return -ETIMEDOUT;
442 }
443 msleep(20);
444 }
445
446 return 0;
447 }
448
449 static irqreturn_t ci_irq(int irq, void *data)
450 {
451 struct ci_hdrc *ci = data;
452 irqreturn_t ret = IRQ_NONE;
453 u32 otgsc = 0;
454
455 if (ci->is_otg) {
456 otgsc = hw_read_otgsc(ci, ~0);
457 if (ci_otg_is_fsm_mode(ci)) {
458 ret = ci_otg_fsm_irq(ci);
459 if (ret == IRQ_HANDLED)
460 return ret;
461 }
462 }
463
464 /*
465 * Handle id change interrupt, it indicates device/host function
466 * switch.
467 */
468 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
469 ci->id_event = true;
470 /* Clear ID change irq status */
471 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
472 ci_otg_queue_work(ci);
473 return IRQ_HANDLED;
474 }
475
476 /*
477 * Handle vbus change interrupt, it indicates device connection
478 * and disconnection events.
479 */
480 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
481 ci->b_sess_valid_event = true;
482 /* Clear BSV irq */
483 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
484 ci_otg_queue_work(ci);
485 return IRQ_HANDLED;
486 }
487
488 /* Handle device/host interrupt */
489 if (ci->role != CI_ROLE_END)
490 ret = ci_role(ci)->irq(ci);
491
492 return ret;
493 }
494
495 static int ci_get_platdata(struct device *dev,
496 struct ci_hdrc_platform_data *platdata)
497 {
498 if (!platdata->phy_mode)
499 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
500
501 if (!platdata->dr_mode)
502 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
503
504 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
505 platdata->dr_mode = USB_DR_MODE_OTG;
506
507 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
508 /* Get the vbus regulator */
509 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
510 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
511 return -EPROBE_DEFER;
512 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
513 /* no vbus regualator is needed */
514 platdata->reg_vbus = NULL;
515 } else if (IS_ERR(platdata->reg_vbus)) {
516 dev_err(dev, "Getting regulator error: %ld\n",
517 PTR_ERR(platdata->reg_vbus));
518 return PTR_ERR(platdata->reg_vbus);
519 }
520 /* Get TPL support */
521 if (!platdata->tpl_support)
522 platdata->tpl_support =
523 of_usb_host_tpl_support(dev->of_node);
524 }
525
526 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
527 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
528
529 return 0;
530 }
531
532 static DEFINE_IDA(ci_ida);
533
534 struct platform_device *ci_hdrc_add_device(struct device *dev,
535 struct resource *res, int nres,
536 struct ci_hdrc_platform_data *platdata)
537 {
538 struct platform_device *pdev;
539 int id, ret;
540
541 ret = ci_get_platdata(dev, platdata);
542 if (ret)
543 return ERR_PTR(ret);
544
545 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
546 if (id < 0)
547 return ERR_PTR(id);
548
549 pdev = platform_device_alloc("ci_hdrc", id);
550 if (!pdev) {
551 ret = -ENOMEM;
552 goto put_id;
553 }
554
555 pdev->dev.parent = dev;
556 pdev->dev.dma_mask = dev->dma_mask;
557 pdev->dev.dma_parms = dev->dma_parms;
558 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
559
560 ret = platform_device_add_resources(pdev, res, nres);
561 if (ret)
562 goto err;
563
564 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
565 if (ret)
566 goto err;
567
568 ret = platform_device_add(pdev);
569 if (ret)
570 goto err;
571
572 return pdev;
573
574 err:
575 platform_device_put(pdev);
576 put_id:
577 ida_simple_remove(&ci_ida, id);
578 return ERR_PTR(ret);
579 }
580 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
581
582 void ci_hdrc_remove_device(struct platform_device *pdev)
583 {
584 int id = pdev->id;
585 platform_device_unregister(pdev);
586 ida_simple_remove(&ci_ida, id);
587 }
588 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
589
590 static inline void ci_role_destroy(struct ci_hdrc *ci)
591 {
592 ci_hdrc_gadget_destroy(ci);
593 ci_hdrc_host_destroy(ci);
594 if (ci->is_otg)
595 ci_hdrc_otg_destroy(ci);
596 }
597
598 static void ci_get_otg_capable(struct ci_hdrc *ci)
599 {
600 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
601 ci->is_otg = false;
602 else
603 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
604 DCCPARAMS_DC | DCCPARAMS_HC)
605 == (DCCPARAMS_DC | DCCPARAMS_HC));
606 if (ci->is_otg)
607 dev_dbg(ci->dev, "It is OTG capable controller\n");
608 }
609
610 static int ci_hdrc_probe(struct platform_device *pdev)
611 {
612 struct device *dev = &pdev->dev;
613 struct ci_hdrc *ci;
614 struct resource *res;
615 void __iomem *base;
616 int ret;
617 enum usb_dr_mode dr_mode;
618
619 if (!dev_get_platdata(dev)) {
620 dev_err(dev, "platform data missing\n");
621 return -ENODEV;
622 }
623
624 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
625 base = devm_ioremap_resource(dev, res);
626 if (IS_ERR(base))
627 return PTR_ERR(base);
628
629 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
630 if (!ci)
631 return -ENOMEM;
632
633 ci->dev = dev;
634 ci->platdata = dev_get_platdata(dev);
635 ci->imx28_write_fix = !!(ci->platdata->flags &
636 CI_HDRC_IMX28_WRITE_FIX);
637
638 ret = hw_device_init(ci, base);
639 if (ret < 0) {
640 dev_err(dev, "can't initialize hardware\n");
641 return -ENODEV;
642 }
643
644 if (ci->platdata->phy) {
645 ci->phy = ci->platdata->phy;
646 } else if (ci->platdata->usb_phy) {
647 ci->usb_phy = ci->platdata->usb_phy;
648 } else {
649 ci->phy = devm_phy_get(dev, "usb-phy");
650 ci->usb_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
651
652 /* if both generic PHY and USB PHY layers aren't enabled */
653 if (PTR_ERR(ci->phy) == -ENOSYS &&
654 PTR_ERR(ci->usb_phy) == -ENXIO)
655 return -ENXIO;
656
657 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
658 return -EPROBE_DEFER;
659
660 if (IS_ERR(ci->phy))
661 ci->phy = NULL;
662 else if (IS_ERR(ci->usb_phy))
663 ci->usb_phy = NULL;
664 }
665
666 ret = ci_usb_phy_init(ci);
667 if (ret) {
668 dev_err(dev, "unable to init phy: %d\n", ret);
669 return ret;
670 } else {
671 /*
672 * The delay to sync PHY's status, the maximum delay is
673 * 2ms since the otgsc uses 1ms timer to debounce the
674 * PHY's input
675 */
676 usleep_range(2000, 2500);
677 }
678
679 ci->hw_bank.phys = res->start;
680
681 ci->irq = platform_get_irq(pdev, 0);
682 if (ci->irq < 0) {
683 dev_err(dev, "missing IRQ\n");
684 ret = ci->irq;
685 goto deinit_phy;
686 }
687
688 ci_get_otg_capable(ci);
689
690 dr_mode = ci->platdata->dr_mode;
691 /* initialize role(s) before the interrupt is requested */
692 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
693 ret = ci_hdrc_host_init(ci);
694 if (ret)
695 dev_info(dev, "doesn't support host\n");
696 }
697
698 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
699 ret = ci_hdrc_gadget_init(ci);
700 if (ret)
701 dev_info(dev, "doesn't support gadget\n");
702 }
703
704 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
705 dev_err(dev, "no supported roles\n");
706 ret = -ENODEV;
707 goto deinit_phy;
708 }
709
710 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
711 /* Disable and clear all OTG irq */
712 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
713 OTGSC_INT_STATUS_BITS);
714 ret = ci_hdrc_otg_init(ci);
715 if (ret) {
716 dev_err(dev, "init otg fails, ret = %d\n", ret);
717 goto stop;
718 }
719 }
720
721 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
722 if (ci->is_otg) {
723 ci->role = ci_otg_role(ci);
724 /* Enable ID change irq */
725 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
726 } else {
727 /*
728 * If the controller is not OTG capable, but support
729 * role switch, the defalt role is gadget, and the
730 * user can switch it through debugfs.
731 */
732 ci->role = CI_ROLE_GADGET;
733 }
734 } else {
735 ci->role = ci->roles[CI_ROLE_HOST]
736 ? CI_ROLE_HOST
737 : CI_ROLE_GADGET;
738 }
739
740 /* only update vbus status for peripheral */
741 if (ci->role == CI_ROLE_GADGET)
742 ci_handle_vbus_change(ci);
743
744 if (!ci_otg_is_fsm_mode(ci)) {
745 ret = ci_role_start(ci, ci->role);
746 if (ret) {
747 dev_err(dev, "can't start %s role\n",
748 ci_role(ci)->name);
749 goto stop;
750 }
751 }
752
753 platform_set_drvdata(pdev, ci);
754 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
755 ci->platdata->name, ci);
756 if (ret)
757 goto stop;
758
759 if (ci_otg_is_fsm_mode(ci))
760 ci_hdrc_otg_fsm_start(ci);
761
762 ret = dbg_create_files(ci);
763 if (!ret)
764 return 0;
765
766 stop:
767 ci_role_destroy(ci);
768 deinit_phy:
769 ci_usb_phy_exit(ci);
770
771 return ret;
772 }
773
774 static int ci_hdrc_remove(struct platform_device *pdev)
775 {
776 struct ci_hdrc *ci = platform_get_drvdata(pdev);
777
778 dbg_remove_files(ci);
779 ci_role_destroy(ci);
780 ci_hdrc_enter_lpm(ci, true);
781 ci_usb_phy_exit(ci);
782
783 return 0;
784 }
785
786 static struct platform_driver ci_hdrc_driver = {
787 .probe = ci_hdrc_probe,
788 .remove = ci_hdrc_remove,
789 .driver = {
790 .name = "ci_hdrc",
791 .owner = THIS_MODULE,
792 },
793 };
794
795 module_platform_driver(ci_hdrc_driver);
796
797 MODULE_ALIAS("platform:ci_hdrc");
798 MODULE_LICENSE("GPL v2");
799 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
800 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Linux kernel - Deliverables
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