drivers/usb/chipidea/core.c

   1 /*
   2  * core.c - ChipIdea USB IP core family device controller
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 /*
  14  * Description: ChipIdea USB IP core family device controller
  15  *
  16  * This driver is composed of several blocks:
  17  * - HW:     hardware interface
  18  * - DBG:    debug facilities (optional)
  19  * - UTIL:   utilities
  20  * - ISR:    interrupts handling
  21  * - ENDPT:  endpoint operations (Gadget API)
  22  * - GADGET: gadget operations (Gadget API)
  23  * - BUS:    bus glue code, bus abstraction layer
  24  *
  25  * Compile Options
  26  * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
  27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
  28  *              if defined mass storage compliance succeeds but with warnings
  29  *              => case 4: Hi >  Dn
  30  *              => case 5: Hi >  Di
  31  *              => case 8: Hi <> Do
  32  *              if undefined usbtest 13 fails
  33  * - TRACE:     enable function tracing (depends on DEBUG)
  34  *
  35  * Main Features
  36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38  * - Normal & LPM support
  39  *
  40  * USBTEST Report
  41  * - OK: 0-12, 13 (STALL_IN defined) & 14
  42  * - Not Supported: 15 & 16 (ISO)
  43  *
  44  * TODO List
  45  * - Suspend & Remote Wakeup
  46  */
  47 #include <linux/delay.h>
  48 #include <linux/device.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/phy/phy.h>
  51 #include <linux/platform_device.h>
  52 #include <linux/module.h>
  53 #include <linux/idr.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/io.h>
  56 #include <linux/kernel.h>
  57 #include <linux/slab.h>
  58 #include <linux/pm_runtime.h>
  59 #include <linux/usb/ch9.h>
  60 #include <linux/usb/gadget.h>
  61 #include <linux/usb/otg.h>
  62 #include <linux/usb/chipidea.h>
  63 #include <linux/usb/of.h>
  64 #include <linux/of.h>
  65 #include <linux/phy.h>
  66 #include <linux/regulator/consumer.h>
  67
  68 #include "ci.h"
  69 #include "udc.h"
  70 #include "bits.h"
  71 #include "host.h"
  72 #include "debug.h"
  73 #include "otg.h"
  74 #include "otg_fsm.h"
  75
  76 /* Controller register map */
  77 static const u8 ci_regs_nolpm[] = {
  78         [CAP_CAPLENGTH]         = 0x00U,
  79         [CAP_HCCPARAMS]         = 0x08U,
  80         [CAP_DCCPARAMS]         = 0x24U,
  81         [CAP_TESTMODE]          = 0x38U,
  82         [OP_USBCMD]             = 0x00U,
  83         [OP_USBSTS]             = 0x04U,
  84         [OP_USBINTR]            = 0x08U,
  85         [OP_DEVICEADDR]         = 0x14U,
  86         [OP_ENDPTLISTADDR]      = 0x18U,
  87         [OP_PORTSC]             = 0x44U,
  88         [OP_DEVLC]              = 0x84U,
  89         [OP_OTGSC]              = 0x64U,
  90         [OP_USBMODE]            = 0x68U,
  91         [OP_ENDPTSETUPSTAT]     = 0x6CU,
  92         [OP_ENDPTPRIME]         = 0x70U,
  93         [OP_ENDPTFLUSH]         = 0x74U,
  94         [OP_ENDPTSTAT]          = 0x78U,
  95         [OP_ENDPTCOMPLETE]      = 0x7CU,
  96         [OP_ENDPTCTRL]          = 0x80U,
  97 };
  98
  99 static const u8 ci_regs_lpm[] = {
 100         [CAP_CAPLENGTH]         = 0x00U,
 101         [CAP_HCCPARAMS]         = 0x08U,
 102         [CAP_DCCPARAMS]         = 0x24U,
 103         [CAP_TESTMODE]          = 0xFCU,
 104         [OP_USBCMD]             = 0x00U,
 105         [OP_USBSTS]             = 0x04U,
 106         [OP_USBINTR]            = 0x08U,
 107         [OP_DEVICEADDR]         = 0x14U,
 108         [OP_ENDPTLISTADDR]      = 0x18U,
 109         [OP_PORTSC]             = 0x44U,
 110         [OP_DEVLC]              = 0x84U,
 111         [OP_OTGSC]              = 0xC4U,
 112         [OP_USBMODE]            = 0xC8U,
 113         [OP_ENDPTSETUPSTAT]     = 0xD8U,
 114         [OP_ENDPTPRIME]         = 0xDCU,
 115         [OP_ENDPTFLUSH]         = 0xE0U,
 116         [OP_ENDPTSTAT]          = 0xE4U,
 117         [OP_ENDPTCOMPLETE]      = 0xE8U,
 118         [OP_ENDPTCTRL]          = 0xECU,
 119 };
 120
 121 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
 122 {
 123         int i;
 124
 125         for (i = 0; i < OP_ENDPTCTRL; i++)
 126                 ci->hw_bank.regmap[i] =
 127                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 128                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 129
 130         for (; i <= OP_LAST; i++)
 131                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
 132                         4 * (i - OP_ENDPTCTRL) +
 133                         (is_lpm
 134                          ? ci_regs_lpm[OP_ENDPTCTRL]
 135                          : ci_regs_nolpm[OP_ENDPTCTRL]);
 136
 137         return 0;
 138 }
 139
 140 /**
 141  * hw_read_intr_enable: returns interrupt enable register
 142  *
 143  * @ci: the controller
 144  *
 145  * This function returns register data
 146  */
 147 u32 hw_read_intr_enable(struct ci_hdrc *ci)
 148 {
 149         return hw_read(ci, OP_USBINTR, ~0);
 150 }
 151
 152 /**
 153  * hw_read_intr_status: returns interrupt status register
 154  *
 155  * @ci: the controller
 156  *
 157  * This function returns register data
 158  */
 159 u32 hw_read_intr_status(struct ci_hdrc *ci)
 160 {
 161         return hw_read(ci, OP_USBSTS, ~0);
 162 }
 163
 164 /**
 165  * hw_port_test_set: writes port test mode (execute without interruption)
 166  * @mode: new value
 167  *
 168  * This function returns an error code
 169  */
 170 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 171 {
 172         const u8 TEST_MODE_MAX = 7;
 173
 174         if (mode > TEST_MODE_MAX)
 175                 return -EINVAL;
 176
 177         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 178         return 0;
 179 }
 180
 181 /**
 182  * hw_port_test_get: reads port test mode value
 183  *
 184  * @ci: the controller
 185  *
 186  * This function returns port test mode value
 187  */
 188 u8 hw_port_test_get(struct ci_hdrc *ci)
 189 {
 190         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 191 }
 192
 193 static void hw_wait_phy_stable(void)
 194 {
 195         /*
 196          * The phy needs some delay to output the stable status from low
 197          * power mode. And for OTGSC, the status inputs are debounced
 198          * using a 1 ms time constant, so, delay 2ms for controller to get
 199          * the stable status, like vbus and id when the phy leaves low power.
 200          */
 201         usleep_range(2000, 2500);
 202 }
 203
 204 /* The PHY enters/leaves low power mode */
 205 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
 206 {
 207         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
 208         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
 209
 210         if (enable && !lpm)
 211                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 212                                 PORTSC_PHCD(ci->hw_bank.lpm));
 213         else if (!enable && lpm)
 214                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 215                                 0);
 216 }
 217
 218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 219 {
 220         u32 reg;
 221
 222         /* bank is a module variable */
 223         ci->hw_bank.abs = base;
 224
 225         ci->hw_bank.cap = ci->hw_bank.abs;
 226         ci->hw_bank.cap += ci->platdata->capoffset;
 227         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 228
 229         hw_alloc_regmap(ci, false);
 230         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 231                 __ffs(HCCPARAMS_LEN);
 232         ci->hw_bank.lpm  = reg;
 233         if (reg)
 234                 hw_alloc_regmap(ci, !!reg);
 235         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 236         ci->hw_bank.size += OP_LAST;
 237         ci->hw_bank.size /= sizeof(u32);
 238
 239         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 240                 __ffs(DCCPARAMS_DEN);
 241         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 242
 243         if (ci->hw_ep_max > ENDPT_MAX)
 244                 return -ENODEV;
 245
 246         ci_hdrc_enter_lpm(ci, false);
 247
 248         /* Disable all interrupts bits */
 249         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
 250
 251         /* Clear all interrupts status bits*/
 252         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
 253
 254         dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
 255                 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 256
 257         /* setup lock mode ? */
 258
 259         /* ENDPTSETUPSTAT is '0' by default */
 260
 261         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 262
 263         return 0;
 264 }
 265
 266 static void hw_phymode_configure(struct ci_hdrc *ci)
 267 {
 268         u32 portsc, lpm, sts = 0;
 269
 270         switch (ci->platdata->phy_mode) {
 271         case USBPHY_INTERFACE_MODE_UTMI:
 272                 portsc = PORTSC_PTS(PTS_UTMI);
 273                 lpm = DEVLC_PTS(PTS_UTMI);
 274                 break;
 275         case USBPHY_INTERFACE_MODE_UTMIW:
 276                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 277                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 278                 break;
 279         case USBPHY_INTERFACE_MODE_ULPI:
 280                 portsc = PORTSC_PTS(PTS_ULPI);
 281                 lpm = DEVLC_PTS(PTS_ULPI);
 282                 break;
 283         case USBPHY_INTERFACE_MODE_SERIAL:
 284                 portsc = PORTSC_PTS(PTS_SERIAL);
 285                 lpm = DEVLC_PTS(PTS_SERIAL);
 286                 sts = 1;
 287                 break;
 288         case USBPHY_INTERFACE_MODE_HSIC:
 289                 portsc = PORTSC_PTS(PTS_HSIC);
 290                 lpm = DEVLC_PTS(PTS_HSIC);
 291                 break;
 292         default:
 293                 return;
 294         }
 295
 296         if (ci->hw_bank.lpm) {
 297                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 298                 if (sts)
 299                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 300         } else {
 301                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 302                 if (sts)
 303                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 304         }
 305 }
 306
 307 /**
 308  * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
 309  * interfaces
 310  * @ci: the controller
 311  *
 312  * This function returns an error code if the phy failed to init
 313  */
 314 static int _ci_usb_phy_init(struct ci_hdrc *ci)
 315 {
 316         int ret;
 317
 318         if (ci->phy) {
 319                 ret = phy_init(ci->phy);
 320                 if (ret)
 321                         return ret;
 322
 323                 ret = phy_power_on(ci->phy);
 324                 if (ret) {
 325                         phy_exit(ci->phy);
 326                         return ret;
 327                 }
 328         } else {
 329                 ret = usb_phy_init(ci->usb_phy);
 330         }
 331
 332         return ret;
 333 }
 334
 335 /**
 336  * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
 337  * interfaces
 338  * @ci: the controller
 339  */
 340 static void ci_usb_phy_exit(struct ci_hdrc *ci)
 341 {
 342         if (ci->phy) {
 343                 phy_power_off(ci->phy);
 344                 phy_exit(ci->phy);
 345         } else {
 346                 usb_phy_shutdown(ci->usb_phy);
 347         }
 348 }
 349
 350 /**
 351  * ci_usb_phy_init: initialize phy according to different phy type
 352  * @ci: the controller
 353  *
 354  * This function returns an error code if usb_phy_init has failed
 355  */
 356 static int ci_usb_phy_init(struct ci_hdrc *ci)
 357 {
 358         int ret;
 359
 360         switch (ci->platdata->phy_mode) {
 361         case USBPHY_INTERFACE_MODE_UTMI:
 362         case USBPHY_INTERFACE_MODE_UTMIW:
 363         case USBPHY_INTERFACE_MODE_HSIC:
 364                 ret = _ci_usb_phy_init(ci);
 365                 if (!ret)
 366                         hw_wait_phy_stable();
 367                 else
 368                         return ret;
 369                 hw_phymode_configure(ci);
 370                 break;
 371         case USBPHY_INTERFACE_MODE_ULPI:
 372         case USBPHY_INTERFACE_MODE_SERIAL:
 373                 hw_phymode_configure(ci);
 374                 ret = _ci_usb_phy_init(ci);
 375                 if (ret)
 376                         return ret;
 377                 break;
 378         default:
 379                 ret = _ci_usb_phy_init(ci);
 380                 if (!ret)
 381                         hw_wait_phy_stable();
 382         }
 383
 384         return ret;
 385 }
 386
 387 /**
 388  * hw_device_reset: resets chip (execute without interruption)
 389  * @ci: the controller
 390   *
 391  * This function returns an error code
 392  */
 393 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
 394 {
 395         /* should flush & stop before reset */
 396         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 397         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 398
 399         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 400         while (hw_read(ci, OP_USBCMD, USBCMD_RST))
 401                 udelay(10);             /* not RTOS friendly */
 402
 403         if (ci->platdata->notify_event)
 404                 ci->platdata->notify_event(ci,
 405                         CI_HDRC_CONTROLLER_RESET_EVENT);
 406
 407         if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
 408                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
 409
 410         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
 411                 if (ci->hw_bank.lpm)
 412                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
 413                 else
 414                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
 415         }
 416
 417         /* USBMODE should be configured step by step */
 418         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 419         hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
 420         /* HW >= 2.3 */
 421         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 422
 423         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
 424                 pr_err("cannot enter in %s mode", ci_role(ci)->name);
 425                 pr_err("lpm = %i", ci->hw_bank.lpm);
 426                 return -ENODEV;
 427         }
 428
 429         return 0;
 430 }
 431
 432 /**
 433  * hw_wait_reg: wait the register value
 434  *
 435  * Sometimes, it needs to wait register value before going on.
 436  * Eg, when switch to device mode, the vbus value should be lower
 437  * than OTGSC_BSV before connects to host.
 438  *
 439  * @ci: the controller
 440  * @reg: register index
 441  * @mask: mast bit
 442  * @value: the bit value to wait
 443  * @timeout_ms: timeout in millisecond
 444  *
 445  * This function returns an error code if timeout
 446  */
 447 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
 448                                 u32 value, unsigned int timeout_ms)
 449 {
 450         unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
 451
 452         while (hw_read(ci, reg, mask) != value) {
 453                 if (time_after(jiffies, elapse)) {
 454                         dev_err(ci->dev, "timeout waiting for %08x in %d\n",
 455                                         mask, reg);
 456                         return -ETIMEDOUT;
 457                 }
 458                 msleep(20);
 459         }
 460
 461         return 0;
 462 }
 463
 464 static irqreturn_t ci_irq(int irq, void *data)
 465 {
 466         struct ci_hdrc *ci = data;
 467         irqreturn_t ret = IRQ_NONE;
 468         u32 otgsc = 0;
 469
 470         if (ci->is_otg) {
 471                 otgsc = hw_read_otgsc(ci, ~0);
 472                 if (ci_otg_is_fsm_mode(ci)) {
 473                         ret = ci_otg_fsm_irq(ci);
 474                         if (ret == IRQ_HANDLED)
 475                                 return ret;
 476                 }
 477         }
 478
 479         /*
 480          * Handle id change interrupt, it indicates device/host function
 481          * switch.
 482          */
 483         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
 484                 ci->id_event = true;
 485                 /* Clear ID change irq status */
 486                 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
 487                 ci_otg_queue_work(ci);
 488                 return IRQ_HANDLED;
 489         }
 490
 491         /*
 492          * Handle vbus change interrupt, it indicates device connection
 493          * and disconnection events.
 494          */
 495         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
 496                 ci->b_sess_valid_event = true;
 497                 /* Clear BSV irq */
 498                 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
 499                 ci_otg_queue_work(ci);
 500                 return IRQ_HANDLED;
 501         }
 502
 503         /* Handle device/host interrupt */
 504         if (ci->role != CI_ROLE_END)
 505                 ret = ci_role(ci)->irq(ci);
 506
 507         return ret;
 508 }
 509
 510 static int ci_get_platdata(struct device *dev,
 511                 struct ci_hdrc_platform_data *platdata)
 512 {
 513         if (!platdata->phy_mode)
 514                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
 515
 516         if (!platdata->dr_mode)
 517                 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
 518
 519         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 520                 platdata->dr_mode = USB_DR_MODE_OTG;
 521
 522         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
 523                 /* Get the vbus regulator */
 524                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
 525                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 526                         return -EPROBE_DEFER;
 527                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 528                         /* no vbus regualator is needed */
 529                         platdata->reg_vbus = NULL;
 530                 } else if (IS_ERR(platdata->reg_vbus)) {
 531                         dev_err(dev, "Getting regulator error: %ld\n",
 532                                 PTR_ERR(platdata->reg_vbus));
 533                         return PTR_ERR(platdata->reg_vbus);
 534                 }
 535                 /* Get TPL support */
 536                 if (!platdata->tpl_support)
 537                         platdata->tpl_support =
 538                                 of_usb_host_tpl_support(dev->of_node);
 539         }
 540
 541         if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
 542                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 543
 544         return 0;
 545 }
 546
 547 static DEFINE_IDA(ci_ida);
 548
 549 struct platform_device *ci_hdrc_add_device(struct device *dev,
 550                         struct resource *res, int nres,
 551                         struct ci_hdrc_platform_data *platdata)
 552 {
 553         struct platform_device *pdev;
 554         int id, ret;
 555
 556         ret = ci_get_platdata(dev, platdata);
 557         if (ret)
 558                 return ERR_PTR(ret);
 559
 560         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 561         if (id < 0)
 562                 return ERR_PTR(id);
 563
 564         pdev = platform_device_alloc("ci_hdrc", id);
 565         if (!pdev) {
 566                 ret = -ENOMEM;
 567                 goto put_id;
 568         }
 569
 570         pdev->dev.parent = dev;
 571         pdev->dev.dma_mask = dev->dma_mask;
 572         pdev->dev.dma_parms = dev->dma_parms;
 573         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
 574
 575         ret = platform_device_add_resources(pdev, res, nres);
 576         if (ret)
 577                 goto err;
 578
 579         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 580         if (ret)
 581                 goto err;
 582
 583         ret = platform_device_add(pdev);
 584         if (ret)
 585                 goto err;
 586
 587         return pdev;
 588
 589 err:
 590         platform_device_put(pdev);
 591 put_id:
 592         ida_simple_remove(&ci_ida, id);
 593         return ERR_PTR(ret);
 594 }
 595 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 596
 597 void ci_hdrc_remove_device(struct platform_device *pdev)
 598 {
 599         int id = pdev->id;
 600         platform_device_unregister(pdev);
 601         ida_simple_remove(&ci_ida, id);
 602 }
 603 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 604
 605 static inline void ci_role_destroy(struct ci_hdrc *ci)
 606 {
 607         ci_hdrc_gadget_destroy(ci);
 608         ci_hdrc_host_destroy(ci);
 609         if (ci->is_otg)
 610                 ci_hdrc_otg_destroy(ci);
 611 }
 612
 613 static void ci_get_otg_capable(struct ci_hdrc *ci)
 614 {
 615         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
 616                 ci->is_otg = false;
 617         else
 618                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
 619                                 DCCPARAMS_DC | DCCPARAMS_HC)
 620                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
 621         if (ci->is_otg)
 622                 dev_dbg(ci->dev, "It is OTG capable controller\n");
 623 }
 624
 625 static int ci_hdrc_probe(struct platform_device *pdev)
 626 {
 627         struct device   *dev = &pdev->dev;
 628         struct ci_hdrc  *ci;
 629         struct resource *res;
 630         void __iomem    *base;
 631         int             ret;
 632         enum usb_dr_mode dr_mode;
 633
 634         if (!dev_get_platdata(dev)) {
 635                 dev_err(dev, "platform data missing\n");
 636                 return -ENODEV;
 637         }
 638
 639         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 640         base = devm_ioremap_resource(dev, res);
 641         if (IS_ERR(base))
 642                 return PTR_ERR(base);
 643
 644         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
 645         if (!ci)
 646                 return -ENOMEM;
 647
 648         ci->dev = dev;
 649         ci->platdata = dev_get_platdata(dev);
 650         ci->imx28_write_fix = !!(ci->platdata->flags &
 651                 CI_HDRC_IMX28_WRITE_FIX);
 652
 653         ret = hw_device_init(ci, base);
 654         if (ret < 0) {
 655                 dev_err(dev, "can't initialize hardware\n");
 656                 return -ENODEV;
 657         }
 658
 659         if (ci->platdata->phy) {
 660                 ci->phy = ci->platdata->phy;
 661         } else if (ci->platdata->usb_phy) {
 662                 ci->usb_phy = ci->platdata->usb_phy;
 663         } else {
 664                 ci->phy = devm_phy_get(dev, "usb-phy");
 665                 ci->usb_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 666
 667                 /* if both generic PHY and USB PHY layers aren't enabled */
 668                 if (PTR_ERR(ci->phy) == -ENOSYS &&
 669                                 PTR_ERR(ci->usb_phy) == -ENXIO)
 670                         return -ENXIO;
 671
 672                 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
 673                         return -EPROBE_DEFER;
 674
 675                 if (IS_ERR(ci->phy))
 676                         ci->phy = NULL;
 677                 else if (IS_ERR(ci->usb_phy))
 678                         ci->usb_phy = NULL;
 679         }
 680
 681         ret = ci_usb_phy_init(ci);
 682         if (ret) {
 683                 dev_err(dev, "unable to init phy: %d\n", ret);
 684                 return ret;
 685         }
 686
 687         ci->hw_bank.phys = res->start;
 688
 689         ci->irq = platform_get_irq(pdev, 0);
 690         if (ci->irq < 0) {
 691                 dev_err(dev, "missing IRQ\n");
 692                 ret = ci->irq;
 693                 goto deinit_phy;
 694         }
 695
 696         ci_get_otg_capable(ci);
 697
 698         dr_mode = ci->platdata->dr_mode;
 699         /* initialize role(s) before the interrupt is requested */
 700         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
 701                 ret = ci_hdrc_host_init(ci);
 702                 if (ret)
 703                         dev_info(dev, "doesn't support host\n");
 704         }
 705
 706         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
 707                 ret = ci_hdrc_gadget_init(ci);
 708                 if (ret)
 709                         dev_info(dev, "doesn't support gadget\n");
 710         }
 711
 712         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
 713                 dev_err(dev, "no supported roles\n");
 714                 ret = -ENODEV;
 715                 goto deinit_phy;
 716         }
 717
 718         if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
 719                 /* Disable and clear all OTG irq */
 720                 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
 721                                                         OTGSC_INT_STATUS_BITS);
 722                 ret = ci_hdrc_otg_init(ci);
 723                 if (ret) {
 724                         dev_err(dev, "init otg fails, ret = %d\n", ret);
 725                         goto stop;
 726                 }
 727         }
 728
 729         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
 730                 if (ci->is_otg) {
 731                         ci->role = ci_otg_role(ci);
 732                         /* Enable ID change irq */
 733                         hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
 734                 } else {
 735                         /*
 736                          * If the controller is not OTG capable, but support
 737                          * role switch, the defalt role is gadget, and the
 738                          * user can switch it through debugfs.
 739                          */
 740                         ci->role = CI_ROLE_GADGET;
 741                 }
 742         } else {
 743                 ci->role = ci->roles[CI_ROLE_HOST]
 744                         ? CI_ROLE_HOST
 745                         : CI_ROLE_GADGET;
 746         }
 747
 748         /* only update vbus status for peripheral */
 749         if (ci->role == CI_ROLE_GADGET)
 750                 ci_handle_vbus_change(ci);
 751
 752         if (!ci_otg_is_fsm_mode(ci)) {
 753                 ret = ci_role_start(ci, ci->role);
 754                 if (ret) {
 755                         dev_err(dev, "can't start %s role\n",
 756                                                 ci_role(ci)->name);
 757                         goto stop;
 758                 }
 759         }
 760
 761         platform_set_drvdata(pdev, ci);
 762         ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
 763                         ci->platdata->name, ci);
 764         if (ret)
 765                 goto stop;
 766
 767         if (ci_otg_is_fsm_mode(ci))
 768                 ci_hdrc_otg_fsm_start(ci);
 769
 770         ret = dbg_create_files(ci);
 771         if (!ret)
 772                 return 0;
 773
 774 stop:
 775         ci_role_destroy(ci);
 776 deinit_phy:
 777         ci_usb_phy_exit(ci);
 778
 779         return ret;
 780 }
 781
 782 static int ci_hdrc_remove(struct platform_device *pdev)
 783 {
 784         struct ci_hdrc *ci = platform_get_drvdata(pdev);
 785
 786         dbg_remove_files(ci);
 787         ci_role_destroy(ci);
 788         ci_hdrc_enter_lpm(ci, true);
 789         ci_usb_phy_exit(ci);
 790
 791         return 0;
 792 }
 793
 794 static struct platform_driver ci_hdrc_driver = {
 795         .probe  = ci_hdrc_probe,
 796         .remove = ci_hdrc_remove,
 797         .driver = {
 798                 .name   = "ci_hdrc",
 799                 .owner  = THIS_MODULE,
 800         },
 801 };
 802
 803 module_platform_driver(ci_hdrc_driver);
 804
 805 MODULE_ALIAS("platform:ci_hdrc");
 806 MODULE_LICENSE("GPL v2");
 807 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
 808 MODULE_DESCRIPTION("ChipIdea HDRC Driver");