2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
67 #include <linux/phy.h>
75 /* Controller register map */
76 static uintptr_t ci_regs_nolpm
[] = {
77 [CAP_CAPLENGTH
] = 0x000UL
,
78 [CAP_HCCPARAMS
] = 0x008UL
,
79 [CAP_DCCPARAMS
] = 0x024UL
,
80 [CAP_TESTMODE
] = 0x038UL
,
81 [OP_USBCMD
] = 0x000UL
,
82 [OP_USBSTS
] = 0x004UL
,
83 [OP_USBINTR
] = 0x008UL
,
84 [OP_DEVICEADDR
] = 0x014UL
,
85 [OP_ENDPTLISTADDR
] = 0x018UL
,
86 [OP_PORTSC
] = 0x044UL
,
89 [OP_USBMODE
] = 0x068UL
,
90 [OP_ENDPTSETUPSTAT
] = 0x06CUL
,
91 [OP_ENDPTPRIME
] = 0x070UL
,
92 [OP_ENDPTFLUSH
] = 0x074UL
,
93 [OP_ENDPTSTAT
] = 0x078UL
,
94 [OP_ENDPTCOMPLETE
] = 0x07CUL
,
95 [OP_ENDPTCTRL
] = 0x080UL
,
98 static uintptr_t ci_regs_lpm
[] = {
99 [CAP_CAPLENGTH
] = 0x000UL
,
100 [CAP_HCCPARAMS
] = 0x008UL
,
101 [CAP_DCCPARAMS
] = 0x024UL
,
102 [CAP_TESTMODE
] = 0x0FCUL
,
103 [OP_USBCMD
] = 0x000UL
,
104 [OP_USBSTS
] = 0x004UL
,
105 [OP_USBINTR
] = 0x008UL
,
106 [OP_DEVICEADDR
] = 0x014UL
,
107 [OP_ENDPTLISTADDR
] = 0x018UL
,
108 [OP_PORTSC
] = 0x044UL
,
109 [OP_DEVLC
] = 0x084UL
,
110 [OP_OTGSC
] = 0x0C4UL
,
111 [OP_USBMODE
] = 0x0C8UL
,
112 [OP_ENDPTSETUPSTAT
] = 0x0D8UL
,
113 [OP_ENDPTPRIME
] = 0x0DCUL
,
114 [OP_ENDPTFLUSH
] = 0x0E0UL
,
115 [OP_ENDPTSTAT
] = 0x0E4UL
,
116 [OP_ENDPTCOMPLETE
] = 0x0E8UL
,
117 [OP_ENDPTCTRL
] = 0x0ECUL
,
120 static int hw_alloc_regmap(struct ci_hdrc
*ci
, bool is_lpm
)
124 kfree(ci
->hw_bank
.regmap
);
126 ci
->hw_bank
.regmap
= kzalloc((OP_LAST
+ 1) * sizeof(void *),
128 if (!ci
->hw_bank
.regmap
)
131 for (i
= 0; i
< OP_ENDPTCTRL
; i
++)
132 ci
->hw_bank
.regmap
[i
] =
133 (i
<= CAP_LAST
? ci
->hw_bank
.cap
: ci
->hw_bank
.op
) +
134 (is_lpm
? ci_regs_lpm
[i
] : ci_regs_nolpm
[i
]);
136 for (; i
<= OP_LAST
; i
++)
137 ci
->hw_bank
.regmap
[i
] = ci
->hw_bank
.op
+
138 4 * (i
- OP_ENDPTCTRL
) +
140 ? ci_regs_lpm
[OP_ENDPTCTRL
]
141 : ci_regs_nolpm
[OP_ENDPTCTRL
]);
147 * hw_port_test_set: writes port test mode (execute without interruption)
150 * This function returns an error code
152 int hw_port_test_set(struct ci_hdrc
*ci
, u8 mode
)
154 const u8 TEST_MODE_MAX
= 7;
156 if (mode
> TEST_MODE_MAX
)
159 hw_write(ci
, OP_PORTSC
, PORTSC_PTC
, mode
<< __ffs(PORTSC_PTC
));
164 * hw_port_test_get: reads port test mode value
166 * This function returns port test mode value
168 u8
hw_port_test_get(struct ci_hdrc
*ci
)
170 return hw_read(ci
, OP_PORTSC
, PORTSC_PTC
) >> __ffs(PORTSC_PTC
);
173 static int hw_device_init(struct ci_hdrc
*ci
, void __iomem
*base
)
177 /* bank is a module variable */
178 ci
->hw_bank
.abs
= base
;
180 ci
->hw_bank
.cap
= ci
->hw_bank
.abs
;
181 ci
->hw_bank
.cap
+= ci
->platdata
->capoffset
;
182 ci
->hw_bank
.op
= ci
->hw_bank
.cap
+ (ioread32(ci
->hw_bank
.cap
) & 0xff);
184 hw_alloc_regmap(ci
, false);
185 reg
= hw_read(ci
, CAP_HCCPARAMS
, HCCPARAMS_LEN
) >>
186 __ffs(HCCPARAMS_LEN
);
187 ci
->hw_bank
.lpm
= reg
;
188 hw_alloc_regmap(ci
, !!reg
);
189 ci
->hw_bank
.size
= ci
->hw_bank
.op
- ci
->hw_bank
.abs
;
190 ci
->hw_bank
.size
+= OP_LAST
;
191 ci
->hw_bank
.size
/= sizeof(u32
);
193 reg
= hw_read(ci
, CAP_DCCPARAMS
, DCCPARAMS_DEN
) >>
194 __ffs(DCCPARAMS_DEN
);
195 ci
->hw_ep_max
= reg
* 2; /* cache hw ENDPT_MAX */
197 if (ci
->hw_ep_max
> ENDPT_MAX
)
200 dev_dbg(ci
->dev
, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
201 ci
->hw_bank
.lpm
, ci
->hw_bank
.cap
, ci
->hw_bank
.op
);
203 /* setup lock mode ? */
205 /* ENDPTSETUPSTAT is '0' by default */
207 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
212 static void hw_phymode_configure(struct ci_hdrc
*ci
)
214 u32 portsc
, lpm
, sts
;
216 switch (ci
->platdata
->phy_mode
) {
217 case USBPHY_INTERFACE_MODE_UTMI
:
218 portsc
= PORTSC_PTS(PTS_UTMI
);
219 lpm
= DEVLC_PTS(PTS_UTMI
);
221 case USBPHY_INTERFACE_MODE_UTMIW
:
222 portsc
= PORTSC_PTS(PTS_UTMI
) | PORTSC_PTW
;
223 lpm
= DEVLC_PTS(PTS_UTMI
) | DEVLC_PTW
;
225 case USBPHY_INTERFACE_MODE_ULPI
:
226 portsc
= PORTSC_PTS(PTS_ULPI
);
227 lpm
= DEVLC_PTS(PTS_ULPI
);
229 case USBPHY_INTERFACE_MODE_SERIAL
:
230 portsc
= PORTSC_PTS(PTS_SERIAL
);
231 lpm
= DEVLC_PTS(PTS_SERIAL
);
234 case USBPHY_INTERFACE_MODE_HSIC
:
235 portsc
= PORTSC_PTS(PTS_HSIC
);
236 lpm
= DEVLC_PTS(PTS_HSIC
);
242 if (ci
->hw_bank
.lpm
) {
243 hw_write(ci
, OP_DEVLC
, DEVLC_PTS(7) | DEVLC_PTW
, lpm
);
244 hw_write(ci
, OP_DEVLC
, DEVLC_STS
, sts
);
246 hw_write(ci
, OP_PORTSC
, PORTSC_PTS(7) | PORTSC_PTW
, portsc
);
247 hw_write(ci
, OP_PORTSC
, PORTSC_STS
, sts
);
252 * hw_device_reset: resets chip (execute without interruption)
253 * @ci: the controller
255 * This function returns an error code
257 int hw_device_reset(struct ci_hdrc
*ci
, u32 mode
)
259 /* should flush & stop before reset */
260 hw_write(ci
, OP_ENDPTFLUSH
, ~0, ~0);
261 hw_write(ci
, OP_USBCMD
, USBCMD_RS
, 0);
263 hw_write(ci
, OP_USBCMD
, USBCMD_RST
, USBCMD_RST
);
264 while (hw_read(ci
, OP_USBCMD
, USBCMD_RST
))
265 udelay(10); /* not RTOS friendly */
267 hw_phymode_configure(ci
);
269 if (ci
->platdata
->notify_event
)
270 ci
->platdata
->notify_event(ci
,
271 CI_HDRC_CONTROLLER_RESET_EVENT
);
273 if (ci
->platdata
->flags
& CI_HDRC_DISABLE_STREAMING
)
274 hw_write(ci
, OP_USBMODE
, USBMODE_CI_SDIS
, USBMODE_CI_SDIS
);
276 /* USBMODE should be configured step by step */
277 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_IDLE
);
278 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, mode
);
280 hw_write(ci
, OP_USBMODE
, USBMODE_SLOM
, USBMODE_SLOM
);
282 if (hw_read(ci
, OP_USBMODE
, USBMODE_CM
) != mode
) {
283 pr_err("cannot enter in %s mode", ci_role(ci
)->name
);
284 pr_err("lpm = %i", ci
->hw_bank
.lpm
);
292 * ci_otg_role - pick role based on ID pin state
293 * @ci: the controller
295 static enum ci_role
ci_otg_role(struct ci_hdrc
*ci
)
297 u32 sts
= hw_read(ci
, OP_OTGSC
, ~0);
298 enum ci_role role
= sts
& OTGSC_ID
306 * ci_role_work - perform role changing based on ID pin
309 static void ci_role_work(struct work_struct
*work
)
311 struct ci_hdrc
*ci
= container_of(work
, struct ci_hdrc
, work
);
312 enum ci_role role
= ci_otg_role(ci
);
314 if (role
!= ci
->role
) {
315 dev_dbg(ci
->dev
, "switching from %s to %s\n",
316 ci_role(ci
)->name
, ci
->roles
[role
]->name
);
319 ci_role_start(ci
, role
);
325 static irqreturn_t
ci_irq(int irq
, void *data
)
327 struct ci_hdrc
*ci
= data
;
328 irqreturn_t ret
= IRQ_NONE
;
332 otgsc
= hw_read(ci
, OP_OTGSC
, ~0);
334 if (ci
->role
!= CI_ROLE_END
)
335 ret
= ci_role(ci
)->irq(ci
);
337 if (ci
->is_otg
&& (otgsc
& OTGSC_IDIS
)) {
338 hw_write(ci
, OP_OTGSC
, OTGSC_IDIS
, OTGSC_IDIS
);
339 disable_irq_nosync(ci
->irq
);
340 queue_work(ci
->wq
, &ci
->work
);
347 static DEFINE_IDA(ci_ida
);
349 struct platform_device
*ci_hdrc_add_device(struct device
*dev
,
350 struct resource
*res
, int nres
,
351 struct ci_hdrc_platform_data
*platdata
)
353 struct platform_device
*pdev
;
356 id
= ida_simple_get(&ci_ida
, 0, 0, GFP_KERNEL
);
360 pdev
= platform_device_alloc("ci_hdrc", id
);
366 pdev
->dev
.parent
= dev
;
367 pdev
->dev
.dma_mask
= dev
->dma_mask
;
368 pdev
->dev
.dma_parms
= dev
->dma_parms
;
369 dma_set_coherent_mask(&pdev
->dev
, dev
->coherent_dma_mask
);
371 ret
= platform_device_add_resources(pdev
, res
, nres
);
375 ret
= platform_device_add_data(pdev
, platdata
, sizeof(*platdata
));
379 ret
= platform_device_add(pdev
);
386 platform_device_put(pdev
);
388 ida_simple_remove(&ci_ida
, id
);
391 EXPORT_SYMBOL_GPL(ci_hdrc_add_device
);
393 void ci_hdrc_remove_device(struct platform_device
*pdev
)
396 platform_device_unregister(pdev
);
397 ida_simple_remove(&ci_ida
, id
);
399 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device
);
401 static int ci_hdrc_probe(struct platform_device
*pdev
)
403 struct device
*dev
= &pdev
->dev
;
405 struct resource
*res
;
408 enum usb_dr_mode dr_mode
;
410 if (!dev
->platform_data
) {
411 dev_err(dev
, "platform data missing\n");
415 if (!dev
->of_node
&& dev
->parent
)
416 dev
->of_node
= dev
->parent
->of_node
;
418 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
419 base
= devm_ioremap_resource(dev
, res
);
421 return PTR_ERR(base
);
423 ci
= devm_kzalloc(dev
, sizeof(*ci
), GFP_KERNEL
);
425 dev_err(dev
, "can't allocate device\n");
430 ci
->platdata
= dev
->platform_data
;
431 if (ci
->platdata
->phy
)
432 ci
->transceiver
= ci
->platdata
->phy
;
434 ci
->global_phy
= true;
436 ret
= hw_device_init(ci
, base
);
438 dev_err(dev
, "can't initialize hardware\n");
442 ci
->hw_bank
.phys
= res
->start
;
444 ci
->irq
= platform_get_irq(pdev
, 0);
446 dev_err(dev
, "missing IRQ\n");
450 INIT_WORK(&ci
->work
, ci_role_work
);
451 ci
->wq
= create_singlethread_workqueue("ci_otg");
453 dev_err(dev
, "can't create workqueue\n");
457 if (!ci
->platdata
->phy_mode
)
458 ci
->platdata
->phy_mode
= of_usb_get_phy_mode(dev
->of_node
);
460 if (!ci
->platdata
->dr_mode
)
461 ci
->platdata
->dr_mode
= of_usb_get_dr_mode(dev
->of_node
);
463 if (ci
->platdata
->dr_mode
== USB_DR_MODE_UNKNOWN
)
464 ci
->platdata
->dr_mode
= USB_DR_MODE_OTG
;
466 dr_mode
= ci
->platdata
->dr_mode
;
467 /* initialize role(s) before the interrupt is requested */
468 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_HOST
) {
469 ret
= ci_hdrc_host_init(ci
);
471 dev_info(dev
, "doesn't support host\n");
474 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_PERIPHERAL
) {
475 ret
= ci_hdrc_gadget_init(ci
);
477 dev_info(dev
, "doesn't support gadget\n");
480 if (!ci
->roles
[CI_ROLE_HOST
] && !ci
->roles
[CI_ROLE_GADGET
]) {
481 dev_err(dev
, "no supported roles\n");
486 if (ci
->roles
[CI_ROLE_HOST
] && ci
->roles
[CI_ROLE_GADGET
]) {
488 /* ID pin needs 1ms debouce time, we delay 2ms for safe */
490 ci
->role
= ci_otg_role(ci
);
492 ci
->role
= ci
->roles
[CI_ROLE_HOST
]
497 ret
= ci_role_start(ci
, ci
->role
);
499 dev_err(dev
, "can't start %s role\n", ci_role(ci
)->name
);
504 platform_set_drvdata(pdev
, ci
);
505 ret
= request_irq(ci
->irq
, ci_irq
, IRQF_SHARED
, ci
->platdata
->name
,
511 hw_write(ci
, OP_OTGSC
, OTGSC_IDIE
, OTGSC_IDIE
);
513 ret
= dbg_create_files(ci
);
517 free_irq(ci
->irq
, ci
);
521 flush_workqueue(ci
->wq
);
522 destroy_workqueue(ci
->wq
);
527 static int ci_hdrc_remove(struct platform_device
*pdev
)
529 struct ci_hdrc
*ci
= platform_get_drvdata(pdev
);
531 dbg_remove_files(ci
);
532 flush_workqueue(ci
->wq
);
533 destroy_workqueue(ci
->wq
);
534 free_irq(ci
->irq
, ci
);
540 static struct platform_driver ci_hdrc_driver
= {
541 .probe
= ci_hdrc_probe
,
542 .remove
= ci_hdrc_remove
,
548 module_platform_driver(ci_hdrc_driver
);
550 MODULE_ALIAS("platform:ci_hdrc");
551 MODULE_ALIAS("platform:ci13xxx");
552 MODULE_LICENSE("GPL v2");
553 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
554 MODULE_DESCRIPTION("ChipIdea HDRC Driver");