2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
41 /* conversion functions */
42 static inline struct dwc2_hsotg_req
*our_req(struct usb_request
*req
)
44 return container_of(req
, struct dwc2_hsotg_req
, req
);
47 static inline struct dwc2_hsotg_ep
*our_ep(struct usb_ep
*ep
)
49 return container_of(ep
, struct dwc2_hsotg_ep
, ep
);
52 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
54 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
57 static inline void __orr32(void __iomem
*ptr
, u32 val
)
59 dwc2_writel(dwc2_readl(ptr
) | val
, ptr
);
62 static inline void __bic32(void __iomem
*ptr
, u32 val
)
64 dwc2_writel(dwc2_readl(ptr
) & ~val
, ptr
);
67 static inline struct dwc2_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
68 u32 ep_index
, u32 dir_in
)
71 return hsotg
->eps_in
[ep_index
];
73 return hsotg
->eps_out
[ep_index
];
76 /* forward declaration of functions */
77 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
);
80 * using_dma - return the DMA status of the driver.
81 * @hsotg: The driver state.
83 * Return true if we're using DMA.
85 * Currently, we have the DMA support code worked into everywhere
86 * that needs it, but the AMBA DMA implementation in the hardware can
87 * only DMA from 32bit aligned addresses. This means that gadgets such
88 * as the CDC Ethernet cannot work as they often pass packets which are
91 * Unfortunately the choice to use DMA or not is global to the controller
92 * and seems to be only settable when the controller is being put through
93 * a core reset. This means we either need to fix the gadgets to take
94 * account of DMA alignment, or add bounce buffers (yuerk).
96 * g_using_dma is set depending on dts flag.
98 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
100 return hsotg
->g_using_dma
;
104 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
105 * @hsotg: The device state
106 * @ints: A bitmask of the interrupts to enable
108 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
110 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
113 new_gsintmsk
= gsintmsk
| ints
;
115 if (new_gsintmsk
!= gsintmsk
) {
116 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
117 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
122 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
123 * @hsotg: The device state
124 * @ints: A bitmask of the interrupts to enable
126 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
128 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
131 new_gsintmsk
= gsintmsk
& ~ints
;
133 if (new_gsintmsk
!= gsintmsk
)
134 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
138 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
139 * @hsotg: The device state
140 * @ep: The endpoint index
141 * @dir_in: True if direction is in.
142 * @en: The enable value, true to enable
144 * Set or clear the mask for an individual endpoint's interrupt
147 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
148 unsigned int ep
, unsigned int dir_in
,
158 local_irq_save(flags
);
159 daint
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
164 dwc2_writel(daint
, hsotg
->regs
+ DAINTMSK
);
165 local_irq_restore(flags
);
169 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
170 * @hsotg: The device instance.
172 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
179 /* Reset fifo map if not correctly cleared during previous session */
180 WARN_ON(hsotg
->fifo_map
);
183 /* set RX/NPTX FIFO sizes */
184 dwc2_writel(hsotg
->g_rx_fifo_sz
, hsotg
->regs
+ GRXFSIZ
);
185 dwc2_writel((hsotg
->g_rx_fifo_sz
<< FIFOSIZE_STARTADDR_SHIFT
) |
186 (hsotg
->g_np_g_tx_fifo_sz
<< FIFOSIZE_DEPTH_SHIFT
),
187 hsotg
->regs
+ GNPTXFSIZ
);
190 * arange all the rest of the TX FIFOs, as some versions of this
191 * block have overlapping default addresses. This also ensures
192 * that if the settings have been changed, then they are set to
196 /* start at the end of the GNPTXFSIZ, rounded up */
197 addr
= hsotg
->g_rx_fifo_sz
+ hsotg
->g_np_g_tx_fifo_sz
;
200 * Configure fifos sizes from provided configuration and assign
201 * them to endpoints dynamically according to maxpacket size value of
204 for (ep
= 1; ep
< MAX_EPS_CHANNELS
; ep
++) {
205 if (!hsotg
->g_tx_fifo_sz
[ep
])
208 val
|= hsotg
->g_tx_fifo_sz
[ep
] << FIFOSIZE_DEPTH_SHIFT
;
209 WARN_ONCE(addr
+ hsotg
->g_tx_fifo_sz
[ep
] > hsotg
->fifo_mem
,
210 "insufficient fifo memory");
211 addr
+= hsotg
->g_tx_fifo_sz
[ep
];
213 dwc2_writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
217 * according to p428 of the design guide, we need to ensure that
218 * all fifos are flushed before continuing
221 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
222 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
224 /* wait until the fifos are both flushed */
227 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
229 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
232 if (--timeout
== 0) {
234 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
242 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
246 * @ep: USB endpoint to allocate request for.
247 * @flags: Allocation flags
249 * Allocate a new USB request structure appropriate for the specified endpoint
251 static struct usb_request
*dwc2_hsotg_ep_alloc_request(struct usb_ep
*ep
,
254 struct dwc2_hsotg_req
*req
;
256 req
= kzalloc(sizeof(struct dwc2_hsotg_req
), flags
);
260 INIT_LIST_HEAD(&req
->queue
);
266 * is_ep_periodic - return true if the endpoint is in periodic mode.
267 * @hs_ep: The endpoint to query.
269 * Returns true if the endpoint is in periodic mode, meaning it is being
270 * used for an Interrupt or ISO transfer.
272 static inline int is_ep_periodic(struct dwc2_hsotg_ep
*hs_ep
)
274 return hs_ep
->periodic
;
278 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
279 * @hsotg: The device state.
280 * @hs_ep: The endpoint for the request
281 * @hs_req: The request being processed.
283 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
284 * of a request to ensure the buffer is ready for access by the caller.
286 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
287 struct dwc2_hsotg_ep
*hs_ep
,
288 struct dwc2_hsotg_req
*hs_req
)
290 struct usb_request
*req
= &hs_req
->req
;
292 /* ignore this if we're not moving any data */
293 if (hs_req
->req
.length
== 0)
296 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
300 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
301 * @hsotg: The controller state.
302 * @hs_ep: The endpoint we're going to write for.
303 * @hs_req: The request to write data for.
305 * This is called when the TxFIFO has some space in it to hold a new
306 * transmission and we have something to give it. The actual setup of
307 * the data size is done elsewhere, so all we have to do is to actually
310 * The return value is zero if there is more space (or nothing was done)
311 * otherwise -ENOSPC is returned if the FIFO space was used up.
313 * This routine is only needed for PIO
315 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
316 struct dwc2_hsotg_ep
*hs_ep
,
317 struct dwc2_hsotg_req
*hs_req
)
319 bool periodic
= is_ep_periodic(hs_ep
);
320 u32 gnptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
321 int buf_pos
= hs_req
->req
.actual
;
322 int to_write
= hs_ep
->size_loaded
;
328 to_write
-= (buf_pos
- hs_ep
->last_load
);
330 /* if there's nothing to write, get out early */
334 if (periodic
&& !hsotg
->dedicated_fifos
) {
335 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
340 * work out how much data was loaded so we can calculate
341 * how much data is left in the fifo.
344 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
347 * if shared fifo, we cannot write anything until the
348 * previous data has been completely sent.
350 if (hs_ep
->fifo_load
!= 0) {
351 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
355 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
357 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
359 /* how much of the data has moved */
360 size_done
= hs_ep
->size_loaded
- size_left
;
362 /* how much data is left in the fifo */
363 can_write
= hs_ep
->fifo_load
- size_done
;
364 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
365 __func__
, can_write
);
367 can_write
= hs_ep
->fifo_size
- can_write
;
368 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
369 __func__
, can_write
);
371 if (can_write
<= 0) {
372 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
375 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
376 can_write
= dwc2_readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
381 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
383 "%s: no queue slots available (0x%08x)\n",
386 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
390 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
391 can_write
*= 4; /* fifo size is in 32bit quantities. */
394 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
396 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
397 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
400 * limit to 512 bytes of data, it seems at least on the non-periodic
401 * FIFO, requests of >512 cause the endpoint to get stuck with a
402 * fragment of the end of the transfer in it.
404 if (can_write
> 512 && !periodic
)
408 * limit the write to one max-packet size worth of data, but allow
409 * the transfer to return that it did not run out of fifo space
412 if (to_write
> max_transfer
) {
413 to_write
= max_transfer
;
415 /* it's needed only when we do not use dedicated fifos */
416 if (!hsotg
->dedicated_fifos
)
417 dwc2_hsotg_en_gsint(hsotg
,
418 periodic
? GINTSTS_PTXFEMP
:
422 /* see if we can write data */
424 if (to_write
> can_write
) {
425 to_write
= can_write
;
426 pkt_round
= to_write
% max_transfer
;
429 * Round the write down to an
430 * exact number of packets.
432 * Note, we do not currently check to see if we can ever
433 * write a full packet or not to the FIFO.
437 to_write
-= pkt_round
;
440 * enable correct FIFO interrupt to alert us when there
444 /* it's needed only when we do not use dedicated fifos */
445 if (!hsotg
->dedicated_fifos
)
446 dwc2_hsotg_en_gsint(hsotg
,
447 periodic
? GINTSTS_PTXFEMP
:
451 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
452 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
457 hs_req
->req
.actual
= buf_pos
+ to_write
;
458 hs_ep
->total_data
+= to_write
;
461 hs_ep
->fifo_load
+= to_write
;
463 to_write
= DIV_ROUND_UP(to_write
, 4);
464 data
= hs_req
->req
.buf
+ buf_pos
;
466 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
468 return (to_write
>= can_write
) ? -ENOSPC
: 0;
472 * get_ep_limit - get the maximum data legnth for this endpoint
473 * @hs_ep: The endpoint
475 * Return the maximum data that can be queued in one go on a given endpoint
476 * so that transfers that are too long can be split.
478 static unsigned get_ep_limit(struct dwc2_hsotg_ep
*hs_ep
)
480 int index
= hs_ep
->index
;
485 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
486 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
490 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
495 /* we made the constant loading easier above by using +1 */
500 * constrain by packet count if maxpkts*pktsize is greater
501 * than the length register size.
504 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
505 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
511 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
512 * @hsotg: The controller state.
513 * @hs_ep: The endpoint to process a request for
514 * @hs_req: The request to start.
515 * @continuing: True if we are doing more for the current request.
517 * Start the given request running by setting the endpoint registers
518 * appropriately, and writing any data to the FIFOs.
520 static void dwc2_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
521 struct dwc2_hsotg_ep
*hs_ep
,
522 struct dwc2_hsotg_req
*hs_req
,
525 struct usb_request
*ureq
= &hs_req
->req
;
526 int index
= hs_ep
->index
;
527 int dir_in
= hs_ep
->dir_in
;
537 if (hs_ep
->req
&& !continuing
) {
538 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
541 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
543 "%s: continue different req\n", __func__
);
549 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
550 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
552 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
553 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
), index
,
554 hs_ep
->dir_in
? "in" : "out");
556 /* If endpoint is stalled, we will restart request later */
557 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
559 if (index
&& ctrl
& DXEPCTL_STALL
) {
560 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
564 length
= ureq
->length
- ureq
->actual
;
565 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
566 ureq
->length
, ureq
->actual
);
568 maxreq
= get_ep_limit(hs_ep
);
569 if (length
> maxreq
) {
570 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
572 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
573 __func__
, length
, maxreq
, round
);
575 /* round down to multiple of packets */
583 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
585 packets
= 1; /* send one packet if length is zero. */
587 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
588 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
592 if (dir_in
&& index
!= 0)
593 if (hs_ep
->isochronous
)
594 epsize
= DXEPTSIZ_MC(packets
);
596 epsize
= DXEPTSIZ_MC(1);
601 * zero length packet should be programmed on its own and should not
602 * be counted in DIEPTSIZ.PktCnt with other packets.
604 if (dir_in
&& ureq
->zero
&& !continuing
) {
605 /* Test if zlp is actually required. */
606 if ((ureq
->length
>= hs_ep
->ep
.maxpacket
) &&
607 !(ureq
->length
% hs_ep
->ep
.maxpacket
))
611 epsize
|= DXEPTSIZ_PKTCNT(packets
);
612 epsize
|= DXEPTSIZ_XFERSIZE(length
);
614 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
615 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
617 /* store the request as the current one we're doing */
620 /* write size / packets */
621 dwc2_writel(epsize
, hsotg
->regs
+ epsize_reg
);
623 if (using_dma(hsotg
) && !continuing
) {
624 unsigned int dma_reg
;
627 * write DMA address to control register, buffer already
628 * synced by dwc2_hsotg_ep_queue().
631 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
632 dwc2_writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
634 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
635 __func__
, &ureq
->dma
, dma_reg
);
638 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
639 ctrl
|= DXEPCTL_USBACTEP
;
641 dev_dbg(hsotg
->dev
, "ep0 state:%d\n", hsotg
->ep0_state
);
643 /* For Setup request do not clear NAK */
644 if (!(index
== 0 && hsotg
->ep0_state
== DWC2_EP0_SETUP
))
645 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
647 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
648 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
651 * set these, it seems that DMA support increments past the end
652 * of the packet buffer so we need to calculate the length from
655 hs_ep
->size_loaded
= length
;
656 hs_ep
->last_load
= ureq
->actual
;
658 if (dir_in
&& !using_dma(hsotg
)) {
659 /* set these anyway, we may need them for non-periodic in */
660 hs_ep
->fifo_load
= 0;
662 dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
666 * clear the INTknTXFEmpMsk when we start request, more as a aide
667 * to debugging to see what is going on.
670 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK
,
671 hsotg
->regs
+ DIEPINT(index
));
674 * Note, trying to clear the NAK here causes problems with transmit
675 * on the S3C6400 ending up with the TXFIFO becoming full.
678 /* check ep is enabled */
679 if (!(dwc2_readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
681 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
682 index
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
684 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
685 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
687 /* enable ep interrupts */
688 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
692 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
693 * @hsotg: The device state.
694 * @hs_ep: The endpoint the request is on.
695 * @req: The request being processed.
697 * We've been asked to queue a request, so ensure that the memory buffer
698 * is correctly setup for DMA. If we've been passed an extant DMA address
699 * then ensure the buffer has been synced to memory. If our buffer has no
700 * DMA memory, then we map the memory and mark our request to allow us to
701 * cleanup on completion.
703 static int dwc2_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
704 struct dwc2_hsotg_ep
*hs_ep
,
705 struct usb_request
*req
)
707 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
710 /* if the length is zero, ignore the DMA data */
711 if (hs_req
->req
.length
== 0)
714 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
721 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
722 __func__
, req
->buf
, req
->length
);
727 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg
*hsotg
,
728 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
730 void *req_buf
= hs_req
->req
.buf
;
732 /* If dma is not being used or buffer is aligned */
733 if (!using_dma(hsotg
) || !((long)req_buf
& 3))
736 WARN_ON(hs_req
->saved_req_buf
);
738 dev_dbg(hsotg
->dev
, "%s: %s: buf=%p length=%d\n", __func__
,
739 hs_ep
->ep
.name
, req_buf
, hs_req
->req
.length
);
741 hs_req
->req
.buf
= kmalloc(hs_req
->req
.length
, GFP_ATOMIC
);
742 if (!hs_req
->req
.buf
) {
743 hs_req
->req
.buf
= req_buf
;
745 "%s: unable to allocate memory for bounce buffer\n",
750 /* Save actual buffer */
751 hs_req
->saved_req_buf
= req_buf
;
754 memcpy(hs_req
->req
.buf
, req_buf
, hs_req
->req
.length
);
758 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg
*hsotg
,
759 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
761 /* If dma is not being used or buffer was aligned */
762 if (!using_dma(hsotg
) || !hs_req
->saved_req_buf
)
765 dev_dbg(hsotg
->dev
, "%s: %s: status=%d actual-length=%d\n", __func__
,
766 hs_ep
->ep
.name
, hs_req
->req
.status
, hs_req
->req
.actual
);
768 /* Copy data from bounce buffer on successful out transfer */
769 if (!hs_ep
->dir_in
&& !hs_req
->req
.status
)
770 memcpy(hs_req
->saved_req_buf
, hs_req
->req
.buf
,
773 /* Free bounce buffer */
774 kfree(hs_req
->req
.buf
);
776 hs_req
->req
.buf
= hs_req
->saved_req_buf
;
777 hs_req
->saved_req_buf
= NULL
;
780 static int dwc2_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
783 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
784 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
785 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
789 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
790 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
791 req
->zero
, req
->short_not_ok
);
793 /* Prevent new request submission when controller is suspended */
794 if (hs
->lx_state
== DWC2_L2
) {
795 dev_dbg(hs
->dev
, "%s: don't submit request while suspended\n",
800 /* initialise status of the request */
801 INIT_LIST_HEAD(&hs_req
->queue
);
803 req
->status
= -EINPROGRESS
;
805 ret
= dwc2_hsotg_handle_unaligned_buf_start(hs
, hs_ep
, hs_req
);
809 /* if we're using DMA, sync the buffers as necessary */
811 ret
= dwc2_hsotg_map_dma(hs
, hs_ep
, req
);
816 first
= list_empty(&hs_ep
->queue
);
817 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
820 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
825 static int dwc2_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
828 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
829 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
830 unsigned long flags
= 0;
833 spin_lock_irqsave(&hs
->lock
, flags
);
834 ret
= dwc2_hsotg_ep_queue(ep
, req
, gfp_flags
);
835 spin_unlock_irqrestore(&hs
->lock
, flags
);
840 static void dwc2_hsotg_ep_free_request(struct usb_ep
*ep
,
841 struct usb_request
*req
)
843 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
849 * dwc2_hsotg_complete_oursetup - setup completion callback
850 * @ep: The endpoint the request was on.
851 * @req: The request completed.
853 * Called on completion of any requests the driver itself
854 * submitted that need cleaning up.
856 static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep
,
857 struct usb_request
*req
)
859 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
860 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
862 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
864 dwc2_hsotg_ep_free_request(ep
, req
);
868 * ep_from_windex - convert control wIndex value to endpoint
869 * @hsotg: The driver state.
870 * @windex: The control request wIndex field (in host order).
872 * Convert the given wIndex into a pointer to an driver endpoint
873 * structure, or return NULL if it is not a valid endpoint.
875 static struct dwc2_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
878 struct dwc2_hsotg_ep
*ep
;
879 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
880 int idx
= windex
& 0x7F;
885 if (idx
> hsotg
->num_of_eps
)
888 ep
= index_to_ep(hsotg
, idx
, dir
);
890 if (idx
&& ep
->dir_in
!= dir
)
897 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
898 * @hsotg: The driver state.
899 * @testmode: requested usb test mode
900 * Enable usb Test Mode requested by the Host.
902 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
)
904 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
906 dctl
&= ~DCTL_TSTCTL_MASK
;
913 dctl
|= testmode
<< DCTL_TSTCTL_SHIFT
;
918 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
923 * dwc2_hsotg_send_reply - send reply to control request
924 * @hsotg: The device state
926 * @buff: Buffer for request
927 * @length: Length of reply.
929 * Create a request and queue it on the given endpoint. This is useful as
930 * an internal method of sending replies to certain control requests, etc.
932 static int dwc2_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
933 struct dwc2_hsotg_ep
*ep
,
937 struct usb_request
*req
;
940 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
942 req
= dwc2_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
943 hsotg
->ep0_reply
= req
;
945 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
949 req
->buf
= hsotg
->ep0_buff
;
950 req
->length
= length
;
952 * zero flag is for sending zlp in DATA IN stage. It has no impact on
956 req
->complete
= dwc2_hsotg_complete_oursetup
;
959 memcpy(req
->buf
, buff
, length
);
961 ret
= dwc2_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
963 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
971 * dwc2_hsotg_process_req_status - process request GET_STATUS
972 * @hsotg: The device state
973 * @ctrl: USB control request
975 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
976 struct usb_ctrlrequest
*ctrl
)
978 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
979 struct dwc2_hsotg_ep
*ep
;
983 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
986 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
990 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
991 case USB_RECIP_DEVICE
:
992 reply
= cpu_to_le16(0); /* bit 0 => self powered,
993 * bit 1 => remote wakeup */
996 case USB_RECIP_INTERFACE
:
997 /* currently, the data result should be zero */
998 reply
= cpu_to_le16(0);
1001 case USB_RECIP_ENDPOINT
:
1002 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1006 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1013 if (le16_to_cpu(ctrl
->wLength
) != 2)
1016 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1018 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1025 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1028 * get_ep_head - return the first request on the endpoint
1029 * @hs_ep: The controller endpoint to get
1031 * Get the first request on the endpoint.
1033 static struct dwc2_hsotg_req
*get_ep_head(struct dwc2_hsotg_ep
*hs_ep
)
1035 if (list_empty(&hs_ep
->queue
))
1038 return list_first_entry(&hs_ep
->queue
, struct dwc2_hsotg_req
, queue
);
1042 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1043 * @hsotg: The device state
1044 * @ctrl: USB control request
1046 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
1047 struct usb_ctrlrequest
*ctrl
)
1049 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1050 struct dwc2_hsotg_req
*hs_req
;
1052 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1053 struct dwc2_hsotg_ep
*ep
;
1060 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1061 __func__
, set
? "SET" : "CLEAR");
1063 wValue
= le16_to_cpu(ctrl
->wValue
);
1064 wIndex
= le16_to_cpu(ctrl
->wIndex
);
1065 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
1068 case USB_RECIP_DEVICE
:
1070 case USB_DEVICE_TEST_MODE
:
1071 if ((wIndex
& 0xff) != 0)
1076 hsotg
->test_mode
= wIndex
>> 8;
1077 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1080 "%s: failed to send reply\n", __func__
);
1089 case USB_RECIP_ENDPOINT
:
1090 ep
= ep_from_windex(hsotg
, wIndex
);
1092 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1098 case USB_ENDPOINT_HALT
:
1099 halted
= ep
->halted
;
1101 dwc2_hsotg_ep_sethalt(&ep
->ep
, set
);
1103 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1106 "%s: failed to send reply\n", __func__
);
1111 * we have to complete all requests for ep if it was
1112 * halted, and the halt was cleared by CLEAR_FEATURE
1115 if (!set
&& halted
) {
1117 * If we have request in progress,
1123 list_del_init(&hs_req
->queue
);
1124 if (hs_req
->req
.complete
) {
1125 spin_unlock(&hsotg
->lock
);
1126 usb_gadget_giveback_request(
1127 &ep
->ep
, &hs_req
->req
);
1128 spin_lock(&hsotg
->lock
);
1132 /* If we have pending request, then start it */
1134 restart
= !list_empty(&ep
->queue
);
1136 hs_req
= get_ep_head(ep
);
1137 dwc2_hsotg_start_req(hsotg
, ep
,
1155 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1158 * dwc2_hsotg_stall_ep0 - stall ep0
1159 * @hsotg: The device state
1161 * Set stall for ep0 as response for setup request.
1163 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1165 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1169 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1170 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1173 * DxEPCTL_Stall will be cleared by EP once it has
1174 * taken effect, so no need to clear later.
1177 ctrl
= dwc2_readl(hsotg
->regs
+ reg
);
1178 ctrl
|= DXEPCTL_STALL
;
1179 ctrl
|= DXEPCTL_CNAK
;
1180 dwc2_writel(ctrl
, hsotg
->regs
+ reg
);
1183 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1184 ctrl
, reg
, dwc2_readl(hsotg
->regs
+ reg
));
1187 * complete won't be called, so we enqueue
1188 * setup request here
1190 dwc2_hsotg_enqueue_setup(hsotg
);
1194 * dwc2_hsotg_process_control - process a control request
1195 * @hsotg: The device state
1196 * @ctrl: The control request received
1198 * The controller has received the SETUP phase of a control request, and
1199 * needs to work out what to do next (and whether to pass it on to the
1202 static void dwc2_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1203 struct usb_ctrlrequest
*ctrl
)
1205 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1210 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1211 ctrl
->bRequestType
, ctrl
->bRequest
, ctrl
->wValue
,
1212 ctrl
->wIndex
, ctrl
->wLength
);
1214 if (ctrl
->wLength
== 0) {
1216 hsotg
->ep0_state
= DWC2_EP0_STATUS_IN
;
1217 } else if (ctrl
->bRequestType
& USB_DIR_IN
) {
1219 hsotg
->ep0_state
= DWC2_EP0_DATA_IN
;
1222 hsotg
->ep0_state
= DWC2_EP0_DATA_OUT
;
1225 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1226 switch (ctrl
->bRequest
) {
1227 case USB_REQ_SET_ADDRESS
:
1228 hsotg
->connected
= 1;
1229 dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
1230 dcfg
&= ~DCFG_DEVADDR_MASK
;
1231 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1232 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1233 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
1235 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1237 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1240 case USB_REQ_GET_STATUS
:
1241 ret
= dwc2_hsotg_process_req_status(hsotg
, ctrl
);
1244 case USB_REQ_CLEAR_FEATURE
:
1245 case USB_REQ_SET_FEATURE
:
1246 ret
= dwc2_hsotg_process_req_feature(hsotg
, ctrl
);
1251 /* as a fallback, try delivering it to the driver to deal with */
1253 if (ret
== 0 && hsotg
->driver
) {
1254 spin_unlock(&hsotg
->lock
);
1255 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1256 spin_lock(&hsotg
->lock
);
1258 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1262 * the request is either unhandlable, or is not formatted correctly
1263 * so respond with a STALL for the status stage to indicate failure.
1267 dwc2_hsotg_stall_ep0(hsotg
);
1271 * dwc2_hsotg_complete_setup - completion of a setup transfer
1272 * @ep: The endpoint the request was on.
1273 * @req: The request completed.
1275 * Called on completion of any requests the driver itself submitted for
1278 static void dwc2_hsotg_complete_setup(struct usb_ep
*ep
,
1279 struct usb_request
*req
)
1281 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1282 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1284 if (req
->status
< 0) {
1285 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1289 spin_lock(&hsotg
->lock
);
1290 if (req
->actual
== 0)
1291 dwc2_hsotg_enqueue_setup(hsotg
);
1293 dwc2_hsotg_process_control(hsotg
, req
->buf
);
1294 spin_unlock(&hsotg
->lock
);
1298 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1299 * @hsotg: The device state.
1301 * Enqueue a request on EP0 if necessary to received any SETUP packets
1302 * received from the host.
1304 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1306 struct usb_request
*req
= hsotg
->ctrl_req
;
1307 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1310 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1314 req
->buf
= hsotg
->ctrl_buff
;
1315 req
->complete
= dwc2_hsotg_complete_setup
;
1317 if (!list_empty(&hs_req
->queue
)) {
1318 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1322 hsotg
->eps_out
[0]->dir_in
= 0;
1323 hsotg
->eps_out
[0]->send_zlp
= 0;
1324 hsotg
->ep0_state
= DWC2_EP0_SETUP
;
1326 ret
= dwc2_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1328 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1330 * Don't think there's much we can do other than watch the
1336 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg
*hsotg
,
1337 struct dwc2_hsotg_ep
*hs_ep
)
1340 u8 index
= hs_ep
->index
;
1341 u32 epctl_reg
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1342 u32 epsiz_reg
= hs_ep
->dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1345 dev_dbg(hsotg
->dev
, "Sending zero-length packet on ep%d\n",
1348 dev_dbg(hsotg
->dev
, "Receiving zero-length packet on ep%d\n",
1351 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1352 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+
1355 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1356 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1357 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1358 ctrl
|= DXEPCTL_USBACTEP
;
1359 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1363 * dwc2_hsotg_complete_request - complete a request given to us
1364 * @hsotg: The device state.
1365 * @hs_ep: The endpoint the request was on.
1366 * @hs_req: The request to complete.
1367 * @result: The result code (0 => Ok, otherwise errno)
1369 * The given request has finished, so call the necessary completion
1370 * if it has one and then look to see if we can start a new request
1373 * Note, expects the ep to already be locked as appropriate.
1375 static void dwc2_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1376 struct dwc2_hsotg_ep
*hs_ep
,
1377 struct dwc2_hsotg_req
*hs_req
,
1383 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1387 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1388 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1391 * only replace the status if we've not already set an error
1392 * from a previous transaction
1395 if (hs_req
->req
.status
== -EINPROGRESS
)
1396 hs_req
->req
.status
= result
;
1398 if (using_dma(hsotg
))
1399 dwc2_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1401 dwc2_hsotg_handle_unaligned_buf_complete(hsotg
, hs_ep
, hs_req
);
1404 list_del_init(&hs_req
->queue
);
1407 * call the complete request with the locks off, just in case the
1408 * request tries to queue more work for this endpoint.
1411 if (hs_req
->req
.complete
) {
1412 spin_unlock(&hsotg
->lock
);
1413 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1414 spin_lock(&hsotg
->lock
);
1418 * Look to see if there is anything else to do. Note, the completion
1419 * of the previous request may have caused a new request to be started
1420 * so be careful when doing this.
1423 if (!hs_ep
->req
&& result
>= 0) {
1424 restart
= !list_empty(&hs_ep
->queue
);
1426 hs_req
= get_ep_head(hs_ep
);
1427 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1433 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1434 * @hsotg: The device state.
1435 * @ep_idx: The endpoint index for the data
1436 * @size: The size of data in the fifo, in bytes
1438 * The FIFO status shows there is data to read from the FIFO for a given
1439 * endpoint, so sort out whether we need to read the data into a request
1440 * that has been made for that endpoint.
1442 static void dwc2_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
1444 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
1445 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1446 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1453 u32 epctl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1457 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1458 __func__
, size
, ep_idx
, epctl
);
1460 /* dump the data from the FIFO, we've nothing we can do */
1461 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1462 (void)dwc2_readl(fifo
);
1468 read_ptr
= hs_req
->req
.actual
;
1469 max_req
= hs_req
->req
.length
- read_ptr
;
1471 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1472 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1474 if (to_read
> max_req
) {
1476 * more data appeared than we where willing
1477 * to deal with in this request.
1480 /* currently we don't deal this */
1484 hs_ep
->total_data
+= to_read
;
1485 hs_req
->req
.actual
+= to_read
;
1486 to_read
= DIV_ROUND_UP(to_read
, 4);
1489 * note, we might over-write the buffer end by 3 bytes depending on
1490 * alignment of the data.
1492 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1496 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1497 * @hsotg: The device instance
1498 * @dir_in: If IN zlp
1500 * Generate a zero-length IN packet request for terminating a SETUP
1503 * Note, since we don't write any data to the TxFIFO, then it is
1504 * currently believed that we do not need to wait for any space in
1507 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg
*hsotg
, bool dir_in
)
1509 /* eps_out[0] is used in both directions */
1510 hsotg
->eps_out
[0]->dir_in
= dir_in
;
1511 hsotg
->ep0_state
= dir_in
? DWC2_EP0_STATUS_IN
: DWC2_EP0_STATUS_OUT
;
1513 dwc2_hsotg_program_zlp(hsotg
, hsotg
->eps_out
[0]);
1516 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg
*hsotg
,
1521 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1522 if (ctrl
& DXEPCTL_EOFRNUM
)
1523 ctrl
|= DXEPCTL_SETEVENFR
;
1525 ctrl
|= DXEPCTL_SETODDFR
;
1526 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1530 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1531 * @hsotg: The device instance
1532 * @epnum: The endpoint received from
1534 * The RXFIFO has delivered an OutDone event, which means that the data
1535 * transfer for an OUT endpoint has been completed, either by a short
1536 * packet or by the finish of a transfer.
1538 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
, int epnum
)
1540 u32 epsize
= dwc2_readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1541 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
1542 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1543 struct usb_request
*req
= &hs_req
->req
;
1544 unsigned size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1548 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1552 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_OUT
) {
1553 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1554 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1555 dwc2_hsotg_enqueue_setup(hsotg
);
1559 if (using_dma(hsotg
)) {
1563 * Calculate the size of the transfer by checking how much
1564 * is left in the endpoint size register and then working it
1565 * out from the amount we loaded for the transfer.
1567 * We need to do this as DMA pointers are always 32bit aligned
1568 * so may overshoot/undershoot the transfer.
1571 size_done
= hs_ep
->size_loaded
- size_left
;
1572 size_done
+= hs_ep
->last_load
;
1574 req
->actual
= size_done
;
1577 /* if there is more request to do, schedule new transfer */
1578 if (req
->actual
< req
->length
&& size_left
== 0) {
1579 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1583 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1584 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1585 __func__
, req
->actual
, req
->length
);
1588 * todo - what should we return here? there's no one else
1589 * even bothering to check the status.
1593 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
) {
1594 /* Move to STATUS IN */
1595 dwc2_hsotg_ep0_zlp(hsotg
, true);
1600 * Slave mode OUT transfers do not go through XferComplete so
1601 * adjust the ISOC parity here.
1603 if (!using_dma(hsotg
)) {
1604 hs_ep
->has_correct_parity
= 1;
1605 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
1606 dwc2_hsotg_change_ep_iso_parity(hsotg
, DOEPCTL(epnum
));
1609 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1613 * dwc2_hsotg_read_frameno - read current frame number
1614 * @hsotg: The device instance
1616 * Return the current frame number
1618 static u32
dwc2_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
1622 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
1623 dsts
&= DSTS_SOFFN_MASK
;
1624 dsts
>>= DSTS_SOFFN_SHIFT
;
1630 * dwc2_hsotg_handle_rx - RX FIFO has data
1631 * @hsotg: The device instance
1633 * The IRQ handler has detected that the RX FIFO has some data in it
1634 * that requires processing, so find out what is in there and do the
1637 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1638 * chunks, so if you have x packets received on an endpoint you'll get x
1639 * FIFO events delivered, each with a packet's worth of data in it.
1641 * When using DMA, we should not be processing events from the RXFIFO
1642 * as the actual data should be sent to the memory directly and we turn
1643 * on the completion interrupts to get notifications of transfer completion.
1645 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
1647 u32 grxstsr
= dwc2_readl(hsotg
->regs
+ GRXSTSP
);
1648 u32 epnum
, status
, size
;
1650 WARN_ON(using_dma(hsotg
));
1652 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
1653 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
1655 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
1656 size
>>= GRXSTS_BYTECNT_SHIFT
;
1658 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1659 __func__
, grxstsr
, size
, epnum
);
1661 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
1662 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
1663 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
1666 case GRXSTS_PKTSTS_OUTDONE
:
1667 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1668 dwc2_hsotg_read_frameno(hsotg
));
1670 if (!using_dma(hsotg
))
1671 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
1674 case GRXSTS_PKTSTS_SETUPDONE
:
1676 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1677 dwc2_hsotg_read_frameno(hsotg
),
1678 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
1680 * Call dwc2_hsotg_handle_outdone here if it was not called from
1681 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1682 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1684 if (hsotg
->ep0_state
== DWC2_EP0_SETUP
)
1685 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
1688 case GRXSTS_PKTSTS_OUTRX
:
1689 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
1692 case GRXSTS_PKTSTS_SETUPRX
:
1694 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1695 dwc2_hsotg_read_frameno(hsotg
),
1696 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
1698 WARN_ON(hsotg
->ep0_state
!= DWC2_EP0_SETUP
);
1700 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
1704 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1707 dwc2_hsotg_dump(hsotg
);
1713 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1714 * @mps: The maximum packet size in bytes.
1716 static u32
dwc2_hsotg_ep0_mps(unsigned int mps
)
1720 return D0EPCTL_MPS_64
;
1722 return D0EPCTL_MPS_32
;
1724 return D0EPCTL_MPS_16
;
1726 return D0EPCTL_MPS_8
;
1729 /* bad max packet size, warn and return invalid result */
1735 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1736 * @hsotg: The driver state.
1737 * @ep: The index number of the endpoint
1738 * @mps: The maximum packet size in bytes
1740 * Configure the maximum packet size for the given endpoint, updating
1741 * the hardware control registers to reflect this.
1743 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
1744 unsigned int ep
, unsigned int mps
, unsigned int dir_in
)
1746 struct dwc2_hsotg_ep
*hs_ep
;
1747 void __iomem
*regs
= hsotg
->regs
;
1752 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
1757 /* EP0 is a special case */
1758 mpsval
= dwc2_hsotg_ep0_mps(mps
);
1761 hs_ep
->ep
.maxpacket
= mps
;
1764 mpsval
= mps
& DXEPCTL_MPS_MASK
;
1767 mcval
= ((mps
>> 11) & 0x3) + 1;
1771 hs_ep
->ep
.maxpacket
= mpsval
;
1775 reg
= dwc2_readl(regs
+ DIEPCTL(ep
));
1776 reg
&= ~DXEPCTL_MPS_MASK
;
1778 dwc2_writel(reg
, regs
+ DIEPCTL(ep
));
1780 reg
= dwc2_readl(regs
+ DOEPCTL(ep
));
1781 reg
&= ~DXEPCTL_MPS_MASK
;
1783 dwc2_writel(reg
, regs
+ DOEPCTL(ep
));
1789 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1793 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1794 * @hsotg: The driver state
1795 * @idx: The index for the endpoint (0..15)
1797 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
1802 dwc2_writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
1803 hsotg
->regs
+ GRSTCTL
);
1805 /* wait until the fifo is flushed */
1809 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
1811 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
1814 if (--timeout
== 0) {
1816 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1826 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1827 * @hsotg: The driver state
1828 * @hs_ep: The driver endpoint to check.
1830 * Check to see if there is a request that has data to send, and if so
1831 * make an attempt to write data into the FIFO.
1833 static int dwc2_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
1834 struct dwc2_hsotg_ep
*hs_ep
)
1836 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1838 if (!hs_ep
->dir_in
|| !hs_req
) {
1840 * if request is not enqueued, we disable interrupts
1841 * for endpoints, excepting ep0
1843 if (hs_ep
->index
!= 0)
1844 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
1849 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1850 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1852 return dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1859 * dwc2_hsotg_complete_in - complete IN transfer
1860 * @hsotg: The device state.
1861 * @hs_ep: The endpoint that has just completed.
1863 * An IN transfer has been completed, update the transfer's state and then
1864 * call the relevant completion routines.
1866 static void dwc2_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
1867 struct dwc2_hsotg_ep
*hs_ep
)
1869 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1870 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1871 int size_left
, size_done
;
1874 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1878 /* Finish ZLP handling for IN EP0 transactions */
1879 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_IN
) {
1880 dev_dbg(hsotg
->dev
, "zlp packet sent\n");
1881 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1882 if (hsotg
->test_mode
) {
1885 ret
= dwc2_hsotg_set_test_mode(hsotg
, hsotg
->test_mode
);
1887 dev_dbg(hsotg
->dev
, "Invalid Test #%d\n",
1889 dwc2_hsotg_stall_ep0(hsotg
);
1893 dwc2_hsotg_enqueue_setup(hsotg
);
1898 * Calculate the size of the transfer by checking how much is left
1899 * in the endpoint size register and then working it out from
1900 * the amount we loaded for the transfer.
1902 * We do this even for DMA, as the transfer may have incremented
1903 * past the end of the buffer (DMA transfers are always 32bit
1907 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1909 size_done
= hs_ep
->size_loaded
- size_left
;
1910 size_done
+= hs_ep
->last_load
;
1912 if (hs_req
->req
.actual
!= size_done
)
1913 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1914 __func__
, hs_req
->req
.actual
, size_done
);
1916 hs_req
->req
.actual
= size_done
;
1917 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1918 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1920 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1921 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1922 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1926 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1927 if (hs_ep
->send_zlp
) {
1928 dwc2_hsotg_program_zlp(hsotg
, hs_ep
);
1929 hs_ep
->send_zlp
= 0;
1930 /* transfer will be completed on next complete interrupt */
1934 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_IN
) {
1935 /* Move to STATUS OUT */
1936 dwc2_hsotg_ep0_zlp(hsotg
, false);
1940 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1944 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1945 * @hsotg: The driver state
1946 * @idx: The index for the endpoint (0..15)
1947 * @dir_in: Set if this is an IN endpoint
1949 * Process and clear any interrupt pending for an individual endpoint
1951 static void dwc2_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
1954 struct dwc2_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
1955 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1956 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1957 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1961 ints
= dwc2_readl(hsotg
->regs
+ epint_reg
);
1962 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1964 /* Clear endpoint interrupts */
1965 dwc2_writel(ints
, hsotg
->regs
+ epint_reg
);
1968 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
1969 __func__
, idx
, dir_in
? "in" : "out");
1973 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1974 __func__
, idx
, dir_in
? "in" : "out", ints
);
1976 /* Don't process XferCompl interrupt if it is a setup packet */
1977 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
1978 ints
&= ~DXEPINT_XFERCOMPL
;
1980 if (ints
& DXEPINT_XFERCOMPL
) {
1981 hs_ep
->has_correct_parity
= 1;
1982 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
1983 dwc2_hsotg_change_ep_iso_parity(hsotg
, epctl_reg
);
1986 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1987 __func__
, dwc2_readl(hsotg
->regs
+ epctl_reg
),
1988 dwc2_readl(hsotg
->regs
+ epsiz_reg
));
1991 * we get OutDone from the FIFO, so we only need to look
1992 * at completing IN requests here
1995 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
1997 if (idx
== 0 && !hs_ep
->req
)
1998 dwc2_hsotg_enqueue_setup(hsotg
);
1999 } else if (using_dma(hsotg
)) {
2001 * We're using DMA, we need to fire an OutDone here
2002 * as we ignore the RXFIFO.
2005 dwc2_hsotg_handle_outdone(hsotg
, idx
);
2009 if (ints
& DXEPINT_EPDISBLD
) {
2010 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
2013 int epctl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2015 dwc2_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
2017 if ((epctl
& DXEPCTL_STALL
) &&
2018 (epctl
& DXEPCTL_EPTYPE_BULK
)) {
2019 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2021 dctl
|= DCTL_CGNPINNAK
;
2022 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2027 if (ints
& DXEPINT_AHBERR
)
2028 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
2030 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
2031 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2033 if (using_dma(hsotg
) && idx
== 0) {
2035 * this is the notification we've received a
2036 * setup packet. In non-DMA mode we'd get this
2037 * from the RXFIFO, instead we need to process
2044 dwc2_hsotg_handle_outdone(hsotg
, 0);
2048 if (ints
& DXEPINT_BACK2BACKSETUP
)
2049 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2051 if (dir_in
&& !hs_ep
->isochronous
) {
2052 /* not sure if this is important, but we'll clear it anyway */
2053 if (ints
& DIEPMSK_INTKNTXFEMPMSK
) {
2054 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2058 /* this probably means something bad is happening */
2059 if (ints
& DIEPMSK_INTKNEPMISMSK
) {
2060 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2064 /* FIFO has space or is empty (see GAHBCFG) */
2065 if (hsotg
->dedicated_fifos
&&
2066 ints
& DIEPMSK_TXFIFOEMPTY
) {
2067 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2069 if (!using_dma(hsotg
))
2070 dwc2_hsotg_trytx(hsotg
, hs_ep
);
2076 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2077 * @hsotg: The device state.
2079 * Handle updating the device settings after the enumeration phase has
2082 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
2084 u32 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2085 int ep0_mps
= 0, ep_mps
= 8;
2088 * This should signal the finish of the enumeration phase
2089 * of the USB handshaking, so we should now know what rate
2093 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2096 * note, since we're limited by the size of transfer on EP0, and
2097 * it seems IN transfers must be a even number of packets we do
2098 * not advertise a 64byte MPS on EP0.
2101 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2102 switch (dsts
& DSTS_ENUMSPD_MASK
) {
2103 case DSTS_ENUMSPD_FS
:
2104 case DSTS_ENUMSPD_FS48
:
2105 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2106 ep0_mps
= EP0_MPS_LIMIT
;
2110 case DSTS_ENUMSPD_HS
:
2111 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2112 ep0_mps
= EP0_MPS_LIMIT
;
2116 case DSTS_ENUMSPD_LS
:
2117 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2119 * note, we don't actually support LS in this driver at the
2120 * moment, and the documentation seems to imply that it isn't
2121 * supported by the PHYs on some of the devices.
2125 dev_info(hsotg
->dev
, "new device is %s\n",
2126 usb_speed_string(hsotg
->gadget
.speed
));
2129 * we should now know the maximum packet size for an
2130 * endpoint, so set the endpoints to a default value.
2135 /* Initialize ep0 for both in and out directions */
2136 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 1);
2137 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0);
2138 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
2139 if (hsotg
->eps_in
[i
])
2140 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 1);
2141 if (hsotg
->eps_out
[i
])
2142 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 0);
2146 /* ensure after enumeration our EP0 is active */
2148 dwc2_hsotg_enqueue_setup(hsotg
);
2150 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2151 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2152 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2156 * kill_all_requests - remove all requests from the endpoint's queue
2157 * @hsotg: The device state.
2158 * @ep: The endpoint the requests may be on.
2159 * @result: The result code to use.
2161 * Go through the requests on the given endpoint and mark them
2162 * completed with the given result code.
2164 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
2165 struct dwc2_hsotg_ep
*ep
,
2168 struct dwc2_hsotg_req
*req
, *treq
;
2173 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
2174 dwc2_hsotg_complete_request(hsotg
, ep
, req
,
2177 if (!hsotg
->dedicated_fifos
)
2179 size
= (dwc2_readl(hsotg
->regs
+ DTXFSTS(ep
->index
)) & 0xffff) * 4;
2180 if (size
< ep
->fifo_size
)
2181 dwc2_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
2185 * dwc2_hsotg_disconnect - disconnect service
2186 * @hsotg: The device state.
2188 * The device has been disconnected. Remove all current
2189 * transactions and signal the gadget driver that this
2192 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
2196 if (!hsotg
->connected
)
2199 hsotg
->connected
= 0;
2200 hsotg
->test_mode
= 0;
2202 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
2203 if (hsotg
->eps_in
[ep
])
2204 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
2206 if (hsotg
->eps_out
[ep
])
2207 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
2211 call_gadget(hsotg
, disconnect
);
2212 hsotg
->lx_state
= DWC2_L3
;
2216 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2217 * @hsotg: The device state:
2218 * @periodic: True if this is a periodic FIFO interrupt
2220 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
2222 struct dwc2_hsotg_ep
*ep
;
2225 /* look through for any more data to transmit */
2226 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2227 ep
= index_to_ep(hsotg
, epno
, 1);
2235 if ((periodic
&& !ep
->periodic
) ||
2236 (!periodic
&& ep
->periodic
))
2239 ret
= dwc2_hsotg_trytx(hsotg
, ep
);
2245 /* IRQ flags which will trigger a retry around the IRQ loop */
2246 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2251 * dwc2_hsotg_corereset - issue softreset to the core
2252 * @hsotg: The device state
2254 * Issue a soft reset to the core, and await the core finishing it.
2256 static int dwc2_hsotg_corereset(struct dwc2_hsotg
*hsotg
)
2261 dev_dbg(hsotg
->dev
, "resetting core\n");
2263 /* issue soft reset */
2264 dwc2_writel(GRSTCTL_CSFTRST
, hsotg
->regs
+ GRSTCTL
);
2268 grstctl
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
2269 } while ((grstctl
& GRSTCTL_CSFTRST
) && timeout
-- > 0);
2271 if (grstctl
& GRSTCTL_CSFTRST
) {
2272 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2279 u32 grstctl
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
2281 if (timeout
-- < 0) {
2282 dev_info(hsotg
->dev
,
2283 "%s: reset failed, GRSTCTL=%08x\n",
2288 if (!(grstctl
& GRSTCTL_AHBIDLE
))
2291 break; /* reset done */
2294 dev_dbg(hsotg
->dev
, "reset successful\n");
2299 * dwc2_hsotg_core_init - issue softreset to the core
2300 * @hsotg: The device state
2302 * Issue a soft reset to the core, and await the core finishing it.
2304 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
,
2310 /* Kill any ep0 requests as controller will be reinitialized */
2311 kill_all_requests(hsotg
, hsotg
->eps_out
[0], -ECONNRESET
);
2314 if (dwc2_hsotg_corereset(hsotg
))
2318 * we must now enable ep0 ready for host detection and then
2319 * set configuration.
2322 /* set the PLL on, remove the HNP/SRP and set the PHY */
2323 val
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
2324 dwc2_writel(hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
2325 (val
<< GUSBCFG_USBTRDTIM_SHIFT
), hsotg
->regs
+ GUSBCFG
);
2327 dwc2_hsotg_init_fifo(hsotg
);
2330 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2332 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS
, hsotg
->regs
+ DCFG
);
2334 /* Clear any pending OTG interrupts */
2335 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2337 /* Clear any pending interrupts */
2338 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2339 intmsk
= GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
2340 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
2341 GINTSTS_USBRST
| GINTSTS_RESETDET
|
2342 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
2343 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
|
2344 GINTSTS_INCOMPL_SOIN
| GINTSTS_INCOMPL_SOOUT
;
2346 if (hsotg
->core_params
->external_id_pin_ctl
<= 0)
2347 intmsk
|= GINTSTS_CONIDSTSCHNG
;
2349 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
2351 if (using_dma(hsotg
))
2352 dwc2_writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
2353 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
2354 hsotg
->regs
+ GAHBCFG
);
2356 dwc2_writel(((hsotg
->dedicated_fifos
) ?
2357 (GAHBCFG_NP_TXF_EMP_LVL
|
2358 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
2359 GAHBCFG_GLBL_INTR_EN
, hsotg
->regs
+ GAHBCFG
);
2362 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2363 * when we have no data to transfer. Otherwise we get being flooded by
2367 dwc2_writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
2368 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
2369 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
2370 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
2371 DIEPMSK_INTKNEPMISMSK
,
2372 hsotg
->regs
+ DIEPMSK
);
2375 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2376 * DMA mode we may need this.
2378 dwc2_writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
2379 DIEPMSK_TIMEOUTMSK
) : 0) |
2380 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
2382 hsotg
->regs
+ DOEPMSK
);
2384 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
2386 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2387 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2388 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2390 /* enable in and out endpoint interrupts */
2391 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
2394 * Enable the RXFIFO when in slave mode, as this is how we collect
2395 * the data. In DMA mode, we get events from the FIFO but also
2396 * things we cannot process, so do not use it.
2398 if (!using_dma(hsotg
))
2399 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
2401 /* Enable interrupts for EP0 in and out */
2402 dwc2_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2403 dwc2_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2405 if (!is_usb_reset
) {
2406 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2407 udelay(10); /* see openiboot */
2408 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2411 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", dwc2_readl(hsotg
->regs
+ DCTL
));
2414 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2415 * writing to the EPCTL register..
2418 /* set to read 1 8byte packet */
2419 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2420 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
2422 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2423 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
2425 hsotg
->regs
+ DOEPCTL0
);
2427 /* enable, but don't activate EP0in */
2428 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2429 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
2431 dwc2_hsotg_enqueue_setup(hsotg
);
2433 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2434 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2435 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2437 /* clear global NAKs */
2438 val
= DCTL_CGOUTNAK
| DCTL_CGNPINNAK
;
2440 val
|= DCTL_SFTDISCON
;
2441 __orr32(hsotg
->regs
+ DCTL
, val
);
2443 /* must be at-least 3ms to allow bus to see disconnect */
2446 hsotg
->lx_state
= DWC2_L0
;
2449 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
2451 /* set the soft-disconnect bit */
2452 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2455 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
2457 /* remove the soft-disconnect and let's go */
2458 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2462 * dwc2_hsotg_irq - handle device interrupt
2463 * @irq: The IRQ number triggered
2464 * @pw: The pw value when registered the handler.
2466 static irqreturn_t
dwc2_hsotg_irq(int irq
, void *pw
)
2468 struct dwc2_hsotg
*hsotg
= pw
;
2469 int retry_count
= 8;
2473 spin_lock(&hsotg
->lock
);
2475 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
2476 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
2478 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2479 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2483 if (gintsts
& GINTSTS_RESETDET
) {
2484 dev_dbg(hsotg
->dev
, "%s: USBRstDet\n", __func__
);
2486 dwc2_writel(GINTSTS_RESETDET
, hsotg
->regs
+ GINTSTS
);
2488 /* This event must be used only if controller is suspended */
2489 if (hsotg
->lx_state
== DWC2_L2
) {
2490 dwc2_exit_hibernation(hsotg
, true);
2491 hsotg
->lx_state
= DWC2_L0
;
2495 if (gintsts
& (GINTSTS_USBRST
| GINTSTS_RESETDET
)) {
2497 u32 usb_status
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
2498 u32 connected
= hsotg
->connected
;
2500 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
2501 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2502 dwc2_readl(hsotg
->regs
+ GNPTXSTS
));
2504 dwc2_writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
2506 /* Report disconnection if it is not already done. */
2507 dwc2_hsotg_disconnect(hsotg
);
2509 if (usb_status
& GOTGCTL_BSESVLD
&& connected
)
2510 dwc2_hsotg_core_init_disconnected(hsotg
, true);
2513 if (gintsts
& GINTSTS_ENUMDONE
) {
2514 dwc2_writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
2516 dwc2_hsotg_irq_enumdone(hsotg
);
2519 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
2520 u32 daint
= dwc2_readl(hsotg
->regs
+ DAINT
);
2521 u32 daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
2522 u32 daint_out
, daint_in
;
2526 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
2527 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
2529 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2531 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_out
;
2532 ep
++, daint_out
>>= 1) {
2534 dwc2_hsotg_epint(hsotg
, ep
, 0);
2537 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_in
;
2538 ep
++, daint_in
>>= 1) {
2540 dwc2_hsotg_epint(hsotg
, ep
, 1);
2544 /* check both FIFOs */
2546 if (gintsts
& GINTSTS_NPTXFEMP
) {
2547 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2550 * Disable the interrupt to stop it happening again
2551 * unless one of these endpoint routines decides that
2552 * it needs re-enabling
2555 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
2556 dwc2_hsotg_irq_fifoempty(hsotg
, false);
2559 if (gintsts
& GINTSTS_PTXFEMP
) {
2560 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2562 /* See note in GINTSTS_NPTxFEmp */
2564 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
2565 dwc2_hsotg_irq_fifoempty(hsotg
, true);
2568 if (gintsts
& GINTSTS_RXFLVL
) {
2570 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2571 * we need to retry dwc2_hsotg_handle_rx if this is still
2575 dwc2_hsotg_handle_rx(hsotg
);
2578 if (gintsts
& GINTSTS_ERLYSUSP
) {
2579 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2580 dwc2_writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
2584 * these next two seem to crop-up occasionally causing the core
2585 * to shutdown the USB transfer, so try clearing them and logging
2589 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
2590 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2592 dwc2_writel(DCTL_CGOUTNAK
, hsotg
->regs
+ DCTL
);
2594 dwc2_hsotg_dump(hsotg
);
2597 if (gintsts
& GINTSTS_GINNAKEFF
) {
2598 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2600 dwc2_writel(DCTL_CGNPINNAK
, hsotg
->regs
+ DCTL
);
2602 dwc2_hsotg_dump(hsotg
);
2605 if (gintsts
& GINTSTS_INCOMPL_SOIN
) {
2607 struct dwc2_hsotg_ep
*hs_ep
;
2609 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOIN\n", __func__
);
2610 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
2611 hs_ep
= hsotg
->eps_in
[idx
];
2613 if (!hs_ep
->isochronous
|| hs_ep
->has_correct_parity
)
2616 epctl_reg
= DIEPCTL(idx
);
2617 dwc2_hsotg_change_ep_iso_parity(hsotg
, epctl_reg
);
2619 dwc2_writel(GINTSTS_INCOMPL_SOIN
, hsotg
->regs
+ GINTSTS
);
2622 if (gintsts
& GINTSTS_INCOMPL_SOOUT
) {
2624 struct dwc2_hsotg_ep
*hs_ep
;
2626 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__
);
2627 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
2628 hs_ep
= hsotg
->eps_out
[idx
];
2630 if (!hs_ep
->isochronous
|| hs_ep
->has_correct_parity
)
2633 epctl_reg
= DOEPCTL(idx
);
2634 dwc2_hsotg_change_ep_iso_parity(hsotg
, epctl_reg
);
2636 dwc2_writel(GINTSTS_INCOMPL_SOOUT
, hsotg
->regs
+ GINTSTS
);
2640 * if we've had fifo events, we should try and go around the
2641 * loop again to see if there's any point in returning yet.
2644 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2647 spin_unlock(&hsotg
->lock
);
2653 * dwc2_hsotg_ep_enable - enable the given endpoint
2654 * @ep: The USB endpint to configure
2655 * @desc: The USB endpoint descriptor to configure with.
2657 * This is called from the USB gadget code's usb_ep_enable().
2659 static int dwc2_hsotg_ep_enable(struct usb_ep
*ep
,
2660 const struct usb_endpoint_descriptor
*desc
)
2662 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
2663 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2664 unsigned long flags
;
2665 unsigned int index
= hs_ep
->index
;
2669 unsigned int dir_in
;
2670 unsigned int i
, val
, size
;
2674 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2675 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2676 desc
->wMaxPacketSize
, desc
->bInterval
);
2678 /* not to be called for EP0 */
2679 WARN_ON(index
== 0);
2681 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2682 if (dir_in
!= hs_ep
->dir_in
) {
2683 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2687 mps
= usb_endpoint_maxp(desc
);
2689 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2691 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2692 epctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
2694 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2695 __func__
, epctrl
, epctrl_reg
);
2697 spin_lock_irqsave(&hsotg
->lock
, flags
);
2699 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
2700 epctrl
|= DXEPCTL_MPS(mps
);
2703 * mark the endpoint as active, otherwise the core may ignore
2704 * transactions entirely for this endpoint
2706 epctrl
|= DXEPCTL_USBACTEP
;
2709 * set the NAK status on the endpoint, otherwise we might try and
2710 * do something with data that we've yet got a request to process
2711 * since the RXFIFO will take data for an endpoint even if the
2712 * size register hasn't been set.
2715 epctrl
|= DXEPCTL_SNAK
;
2717 /* update the endpoint state */
2718 dwc2_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, dir_in
);
2720 /* default, set to non-periodic */
2721 hs_ep
->isochronous
= 0;
2722 hs_ep
->periodic
= 0;
2724 hs_ep
->interval
= desc
->bInterval
;
2725 hs_ep
->has_correct_parity
= 0;
2727 if (hs_ep
->interval
> 1 && hs_ep
->mc
> 1)
2728 dev_err(hsotg
->dev
, "MC > 1 when interval is not 1\n");
2730 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2731 case USB_ENDPOINT_XFER_ISOC
:
2732 epctrl
|= DXEPCTL_EPTYPE_ISO
;
2733 epctrl
|= DXEPCTL_SETEVENFR
;
2734 hs_ep
->isochronous
= 1;
2736 hs_ep
->periodic
= 1;
2739 case USB_ENDPOINT_XFER_BULK
:
2740 epctrl
|= DXEPCTL_EPTYPE_BULK
;
2743 case USB_ENDPOINT_XFER_INT
:
2745 hs_ep
->periodic
= 1;
2747 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
2750 case USB_ENDPOINT_XFER_CONTROL
:
2751 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
2755 /* If fifo is already allocated for this ep */
2756 if (hs_ep
->fifo_index
) {
2757 size
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
2758 /* If bigger fifo is required deallocate current one */
2759 if (size
> hs_ep
->fifo_size
) {
2760 hsotg
->fifo_map
&= ~(1 << hs_ep
->fifo_index
);
2761 hs_ep
->fifo_index
= 0;
2762 hs_ep
->fifo_size
= 0;
2767 * if the hardware has dedicated fifos, we must give each IN EP
2768 * a unique tx-fifo even if it is non-periodic.
2770 if (dir_in
&& hsotg
->dedicated_fifos
&& !hs_ep
->fifo_index
) {
2772 u32 fifo_size
= UINT_MAX
;
2773 size
= hs_ep
->ep
.maxpacket
*hs_ep
->mc
;
2774 for (i
= 1; i
< hsotg
->num_of_eps
; ++i
) {
2775 if (hsotg
->fifo_map
& (1<<i
))
2777 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(i
));
2778 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
)*4;
2781 /* Search for smallest acceptable fifo */
2782 if (val
< fifo_size
) {
2789 "%s: No suitable fifo found\n", __func__
);
2793 hsotg
->fifo_map
|= 1 << fifo_index
;
2794 epctrl
|= DXEPCTL_TXFNUM(fifo_index
);
2795 hs_ep
->fifo_index
= fifo_index
;
2796 hs_ep
->fifo_size
= fifo_size
;
2799 /* for non control endpoints, set PID to D0 */
2801 epctrl
|= DXEPCTL_SETD0PID
;
2803 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2806 dwc2_writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2807 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2808 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
2810 /* enable the endpoint interrupt */
2811 dwc2_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2814 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2819 * dwc2_hsotg_ep_disable - disable given endpoint
2820 * @ep: The endpoint to disable.
2822 static int dwc2_hsotg_ep_disable(struct usb_ep
*ep
)
2824 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
2825 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2826 int dir_in
= hs_ep
->dir_in
;
2827 int index
= hs_ep
->index
;
2828 unsigned long flags
;
2832 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2834 if (ep
== &hsotg
->eps_out
[0]->ep
) {
2835 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2839 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2841 spin_lock_irqsave(&hsotg
->lock
, flags
);
2843 hsotg
->fifo_map
&= ~(1<<hs_ep
->fifo_index
);
2844 hs_ep
->fifo_index
= 0;
2845 hs_ep
->fifo_size
= 0;
2847 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
2848 ctrl
&= ~DXEPCTL_EPENA
;
2849 ctrl
&= ~DXEPCTL_USBACTEP
;
2850 ctrl
|= DXEPCTL_SNAK
;
2852 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2853 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2855 /* disable endpoint interrupts */
2856 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2858 /* terminate all requests with shutdown */
2859 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
2861 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2866 * on_list - check request is on the given endpoint
2867 * @ep: The endpoint to check.
2868 * @test: The request to test if it is on the endpoint.
2870 static bool on_list(struct dwc2_hsotg_ep
*ep
, struct dwc2_hsotg_req
*test
)
2872 struct dwc2_hsotg_req
*req
, *treq
;
2874 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2882 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg
*hs_otg
, u32 reg
,
2883 u32 bit
, u32 timeout
)
2887 for (i
= 0; i
< timeout
; i
++) {
2888 if (dwc2_readl(hs_otg
->regs
+ reg
) & bit
)
2896 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg
*hsotg
,
2897 struct dwc2_hsotg_ep
*hs_ep
)
2902 epctrl_reg
= hs_ep
->dir_in
? DIEPCTL(hs_ep
->index
) :
2903 DOEPCTL(hs_ep
->index
);
2904 epint_reg
= hs_ep
->dir_in
? DIEPINT(hs_ep
->index
) :
2905 DOEPINT(hs_ep
->index
);
2907 dev_dbg(hsotg
->dev
, "%s: stopping transfer on %s\n", __func__
,
2909 if (hs_ep
->dir_in
) {
2910 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_SNAK
);
2911 /* Wait for Nak effect */
2912 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
,
2913 DXEPINT_INEPNAKEFF
, 100))
2914 dev_warn(hsotg
->dev
,
2915 "%s: timeout DIEPINT.NAKEFF\n", __func__
);
2917 /* Clear any pending nak effect interrupt */
2918 dwc2_writel(GINTSTS_GINNAKEFF
, hsotg
->regs
+ GINTSTS
);
2920 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGNPINNAK
);
2922 /* Wait for global nak to take effect */
2923 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
2924 GINTSTS_GINNAKEFF
, 100))
2925 dev_warn(hsotg
->dev
,
2926 "%s: timeout GINTSTS.GINNAKEFF\n", __func__
);
2930 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_EPDIS
| DXEPCTL_SNAK
);
2932 /* Wait for ep to be disabled */
2933 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
, DXEPINT_EPDISBLD
, 100))
2934 dev_warn(hsotg
->dev
,
2935 "%s: timeout DOEPCTL.EPDisable\n", __func__
);
2937 if (hs_ep
->dir_in
) {
2938 if (hsotg
->dedicated_fifos
) {
2939 dwc2_writel(GRSTCTL_TXFNUM(hs_ep
->fifo_index
) |
2940 GRSTCTL_TXFFLSH
, hsotg
->regs
+ GRSTCTL
);
2941 /* Wait for fifo flush */
2942 if (dwc2_hsotg_wait_bit_set(hsotg
, GRSTCTL
,
2943 GRSTCTL_TXFFLSH
, 100))
2944 dev_warn(hsotg
->dev
,
2945 "%s: timeout flushing fifos\n",
2948 /* TODO: Flush shared tx fifo */
2950 /* Remove global NAKs */
2951 __bic32(hsotg
->regs
+ DCTL
, DCTL_SGNPINNAK
);
2956 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2957 * @ep: The endpoint to dequeue.
2958 * @req: The request to be removed from a queue.
2960 static int dwc2_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2962 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
2963 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
2964 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2965 unsigned long flags
;
2967 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2969 spin_lock_irqsave(&hs
->lock
, flags
);
2971 if (!on_list(hs_ep
, hs_req
)) {
2972 spin_unlock_irqrestore(&hs
->lock
, flags
);
2976 /* Dequeue already started request */
2977 if (req
== &hs_ep
->req
->req
)
2978 dwc2_hsotg_ep_stop_xfr(hs
, hs_ep
);
2980 dwc2_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2981 spin_unlock_irqrestore(&hs
->lock
, flags
);
2987 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2988 * @ep: The endpoint to set halt.
2989 * @value: Set or unset the halt.
2991 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2993 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
2994 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2995 int index
= hs_ep
->index
;
3000 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
3004 dwc2_hsotg_stall_ep0(hs
);
3007 "%s: can't clear halt on ep0\n", __func__
);
3011 if (hs_ep
->dir_in
) {
3012 epreg
= DIEPCTL(index
);
3013 epctl
= dwc2_readl(hs
->regs
+ epreg
);
3016 epctl
|= DXEPCTL_STALL
| DXEPCTL_SNAK
;
3017 if (epctl
& DXEPCTL_EPENA
)
3018 epctl
|= DXEPCTL_EPDIS
;
3020 epctl
&= ~DXEPCTL_STALL
;
3021 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
3022 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
3023 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
3024 epctl
|= DXEPCTL_SETD0PID
;
3026 dwc2_writel(epctl
, hs
->regs
+ epreg
);
3029 epreg
= DOEPCTL(index
);
3030 epctl
= dwc2_readl(hs
->regs
+ epreg
);
3033 epctl
|= DXEPCTL_STALL
;
3035 epctl
&= ~DXEPCTL_STALL
;
3036 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
3037 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
3038 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
3039 epctl
|= DXEPCTL_SETD0PID
;
3041 dwc2_writel(epctl
, hs
->regs
+ epreg
);
3044 hs_ep
->halted
= value
;
3050 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3051 * @ep: The endpoint to set halt.
3052 * @value: Set or unset the halt.
3054 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
3056 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3057 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
3058 unsigned long flags
= 0;
3061 spin_lock_irqsave(&hs
->lock
, flags
);
3062 ret
= dwc2_hsotg_ep_sethalt(ep
, value
);
3063 spin_unlock_irqrestore(&hs
->lock
, flags
);
3068 static struct usb_ep_ops dwc2_hsotg_ep_ops
= {
3069 .enable
= dwc2_hsotg_ep_enable
,
3070 .disable
= dwc2_hsotg_ep_disable
,
3071 .alloc_request
= dwc2_hsotg_ep_alloc_request
,
3072 .free_request
= dwc2_hsotg_ep_free_request
,
3073 .queue
= dwc2_hsotg_ep_queue_lock
,
3074 .dequeue
= dwc2_hsotg_ep_dequeue
,
3075 .set_halt
= dwc2_hsotg_ep_sethalt_lock
,
3076 /* note, don't believe we have any call for the fifo routines */
3080 * dwc2_hsotg_phy_enable - enable platform phy dev
3081 * @hsotg: The driver state
3083 * A wrapper for platform code responsible for controlling
3084 * low-level USB code
3086 static void dwc2_hsotg_phy_enable(struct dwc2_hsotg
*hsotg
)
3088 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
3090 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
3093 usb_phy_init(hsotg
->uphy
);
3094 else if (hsotg
->plat
&& hsotg
->plat
->phy_init
)
3095 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
3097 phy_init(hsotg
->phy
);
3098 phy_power_on(hsotg
->phy
);
3103 * dwc2_hsotg_phy_disable - disable platform phy dev
3104 * @hsotg: The driver state
3106 * A wrapper for platform code responsible for controlling
3107 * low-level USB code
3109 static void dwc2_hsotg_phy_disable(struct dwc2_hsotg
*hsotg
)
3111 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
3114 usb_phy_shutdown(hsotg
->uphy
);
3115 else if (hsotg
->plat
&& hsotg
->plat
->phy_exit
)
3116 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
3118 phy_power_off(hsotg
->phy
);
3119 phy_exit(hsotg
->phy
);
3124 * dwc2_hsotg_init - initalize the usb core
3125 * @hsotg: The driver state
3127 static void dwc2_hsotg_init(struct dwc2_hsotg
*hsotg
)
3130 /* unmask subset of endpoint interrupts */
3132 dwc2_writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
3133 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
3134 hsotg
->regs
+ DIEPMSK
);
3136 dwc2_writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
3137 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
3138 hsotg
->regs
+ DOEPMSK
);
3140 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
3142 /* Be in disconnected state until gadget is registered */
3143 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3147 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3148 dwc2_readl(hsotg
->regs
+ GRXFSIZ
),
3149 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
3151 dwc2_hsotg_init_fifo(hsotg
);
3153 /* set the PLL on, remove the HNP/SRP and set the PHY */
3154 trdtim
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
3155 dwc2_writel(hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
3156 (trdtim
<< GUSBCFG_USBTRDTIM_SHIFT
),
3157 hsotg
->regs
+ GUSBCFG
);
3159 if (using_dma(hsotg
))
3160 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
3164 * dwc2_hsotg_udc_start - prepare the udc for work
3165 * @gadget: The usb gadget state
3166 * @driver: The usb gadget driver
3168 * Perform initialization to prepare udc device and driver
3171 static int dwc2_hsotg_udc_start(struct usb_gadget
*gadget
,
3172 struct usb_gadget_driver
*driver
)
3174 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3175 unsigned long flags
;
3179 pr_err("%s: called with no device\n", __func__
);
3184 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
3188 if (driver
->max_speed
< USB_SPEED_FULL
)
3189 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
3191 if (!driver
->setup
) {
3192 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
3196 WARN_ON(hsotg
->driver
);
3198 driver
->driver
.bus
= NULL
;
3199 hsotg
->driver
= driver
;
3200 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
3201 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3203 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3206 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3210 dwc2_hsotg_phy_enable(hsotg
);
3211 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3212 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
3214 spin_lock_irqsave(&hsotg
->lock
, flags
);
3215 dwc2_hsotg_init(hsotg
);
3216 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3218 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3220 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
3225 hsotg
->driver
= NULL
;
3230 * dwc2_hsotg_udc_stop - stop the udc
3231 * @gadget: The usb gadget state
3232 * @driver: The usb gadget driver
3234 * Stop udc hw block and stay tunned for future transmissions
3236 static int dwc2_hsotg_udc_stop(struct usb_gadget
*gadget
)
3238 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3239 unsigned long flags
= 0;
3245 /* all endpoints should be shutdown */
3246 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
3247 if (hsotg
->eps_in
[ep
])
3248 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
3249 if (hsotg
->eps_out
[ep
])
3250 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
3253 spin_lock_irqsave(&hsotg
->lock
, flags
);
3255 hsotg
->driver
= NULL
;
3256 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3259 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3261 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3262 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
3263 dwc2_hsotg_phy_disable(hsotg
);
3265 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3271 * dwc2_hsotg_gadget_getframe - read the frame number
3272 * @gadget: The usb gadget state
3274 * Read the {micro} frame number
3276 static int dwc2_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3278 return dwc2_hsotg_read_frameno(to_hsotg(gadget
));
3282 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3283 * @gadget: The usb gadget state
3284 * @is_on: Current state of the USB PHY
3286 * Connect/Disconnect the USB PHY pullup
3288 static int dwc2_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3290 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3291 unsigned long flags
= 0;
3293 dev_dbg(hsotg
->dev
, "%s: is_on: %d op_state: %d\n", __func__
, is_on
,
3296 /* Don't modify pullup state while in host mode */
3297 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
3298 hsotg
->enabled
= is_on
;
3302 spin_lock_irqsave(&hsotg
->lock
, flags
);
3305 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3306 dwc2_hsotg_core_connect(hsotg
);
3308 dwc2_hsotg_core_disconnect(hsotg
);
3309 dwc2_hsotg_disconnect(hsotg
);
3313 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3314 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3319 static int dwc2_hsotg_vbus_session(struct usb_gadget
*gadget
, int is_active
)
3321 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3322 unsigned long flags
;
3324 dev_dbg(hsotg
->dev
, "%s: is_active: %d\n", __func__
, is_active
);
3325 spin_lock_irqsave(&hsotg
->lock
, flags
);
3328 * If controller is hibernated, it must exit from hibernation
3329 * before being initialized / de-initialized
3331 if (hsotg
->lx_state
== DWC2_L2
)
3332 dwc2_exit_hibernation(hsotg
, false);
3335 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
3337 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3339 dwc2_hsotg_core_connect(hsotg
);
3341 dwc2_hsotg_core_disconnect(hsotg
);
3342 dwc2_hsotg_disconnect(hsotg
);
3345 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3350 * dwc2_hsotg_vbus_draw - report bMaxPower field
3351 * @gadget: The usb gadget state
3352 * @mA: Amount of current
3354 * Report how much power the device may consume to the phy.
3356 static int dwc2_hsotg_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
3358 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3360 if (IS_ERR_OR_NULL(hsotg
->uphy
))
3362 return usb_phy_set_power(hsotg
->uphy
, mA
);
3365 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops
= {
3366 .get_frame
= dwc2_hsotg_gadget_getframe
,
3367 .udc_start
= dwc2_hsotg_udc_start
,
3368 .udc_stop
= dwc2_hsotg_udc_stop
,
3369 .pullup
= dwc2_hsotg_pullup
,
3370 .vbus_session
= dwc2_hsotg_vbus_session
,
3371 .vbus_draw
= dwc2_hsotg_vbus_draw
,
3375 * dwc2_hsotg_initep - initialise a single endpoint
3376 * @hsotg: The device state.
3377 * @hs_ep: The endpoint to be initialised.
3378 * @epnum: The endpoint number
3380 * Initialise the given endpoint (as part of the probe and device state
3381 * creation) to give to the gadget driver. Setup the endpoint name, any
3382 * direction information and other state that may be required.
3384 static void dwc2_hsotg_initep(struct dwc2_hsotg
*hsotg
,
3385 struct dwc2_hsotg_ep
*hs_ep
,
3398 hs_ep
->dir_in
= dir_in
;
3399 hs_ep
->index
= epnum
;
3401 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3403 INIT_LIST_HEAD(&hs_ep
->queue
);
3404 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3406 /* add to the list of endpoints known by the gadget driver */
3408 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3410 hs_ep
->parent
= hsotg
;
3411 hs_ep
->ep
.name
= hs_ep
->name
;
3412 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, epnum
? 1024 : EP0_MPS_LIMIT
);
3413 hs_ep
->ep
.ops
= &dwc2_hsotg_ep_ops
;
3416 hs_ep
->ep
.caps
.type_control
= true;
3418 hs_ep
->ep
.caps
.type_iso
= true;
3419 hs_ep
->ep
.caps
.type_bulk
= true;
3420 hs_ep
->ep
.caps
.type_int
= true;
3424 hs_ep
->ep
.caps
.dir_in
= true;
3426 hs_ep
->ep
.caps
.dir_out
= true;
3429 * if we're using dma, we need to set the next-endpoint pointer
3430 * to be something valid.
3433 if (using_dma(hsotg
)) {
3434 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
3436 dwc2_writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3438 dwc2_writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3443 * dwc2_hsotg_hw_cfg - read HW configuration registers
3444 * @param: The device state
3446 * Read the USB core HW configuration registers
3448 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
3454 /* check hardware configuration */
3456 cfg
= dwc2_readl(hsotg
->regs
+ GHWCFG2
);
3457 hsotg
->num_of_eps
= (cfg
>> GHWCFG2_NUM_DEV_EP_SHIFT
) & 0xF;
3459 hsotg
->num_of_eps
++;
3461 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
, sizeof(struct dwc2_hsotg_ep
),
3463 if (!hsotg
->eps_in
[0])
3465 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3466 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
3468 cfg
= dwc2_readl(hsotg
->regs
+ GHWCFG1
);
3469 for (i
= 1, cfg
>>= 2; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
3471 /* Direction in or both */
3472 if (!(ep_type
& 2)) {
3473 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
3474 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
3475 if (!hsotg
->eps_in
[i
])
3478 /* Direction out or both */
3479 if (!(ep_type
& 1)) {
3480 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
3481 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
3482 if (!hsotg
->eps_out
[i
])
3487 cfg
= dwc2_readl(hsotg
->regs
+ GHWCFG3
);
3488 hsotg
->fifo_mem
= (cfg
>> GHWCFG3_DFIFO_DEPTH_SHIFT
);
3490 cfg
= dwc2_readl(hsotg
->regs
+ GHWCFG4
);
3491 hsotg
->dedicated_fifos
= (cfg
>> GHWCFG4_DED_FIFO_SHIFT
) & 1;
3493 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3495 hsotg
->dedicated_fifos
? "dedicated" : "shared",
3501 * dwc2_hsotg_dump - dump state of the udc
3502 * @param: The device state
3504 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
)
3507 struct device
*dev
= hsotg
->dev
;
3508 void __iomem
*regs
= hsotg
->regs
;
3512 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3513 dwc2_readl(regs
+ DCFG
), dwc2_readl(regs
+ DCTL
),
3514 dwc2_readl(regs
+ DIEPMSK
));
3516 dev_info(dev
, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3517 dwc2_readl(regs
+ GAHBCFG
), dwc2_readl(regs
+ GHWCFG1
));
3519 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3520 dwc2_readl(regs
+ GRXFSIZ
), dwc2_readl(regs
+ GNPTXFSIZ
));
3522 /* show periodic fifo settings */
3524 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
3525 val
= dwc2_readl(regs
+ DPTXFSIZN(idx
));
3526 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3527 val
>> FIFOSIZE_DEPTH_SHIFT
,
3528 val
& FIFOSIZE_STARTADDR_MASK
);
3531 for (idx
= 0; idx
< hsotg
->num_of_eps
; idx
++) {
3533 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3534 dwc2_readl(regs
+ DIEPCTL(idx
)),
3535 dwc2_readl(regs
+ DIEPTSIZ(idx
)),
3536 dwc2_readl(regs
+ DIEPDMA(idx
)));
3538 val
= dwc2_readl(regs
+ DOEPCTL(idx
));
3540 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3541 idx
, dwc2_readl(regs
+ DOEPCTL(idx
)),
3542 dwc2_readl(regs
+ DOEPTSIZ(idx
)),
3543 dwc2_readl(regs
+ DOEPDMA(idx
)));
3547 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3548 dwc2_readl(regs
+ DVBUSDIS
), dwc2_readl(regs
+ DVBUSPULSE
));
3553 static void dwc2_hsotg_of_probe(struct dwc2_hsotg
*hsotg
)
3555 struct device_node
*np
= hsotg
->dev
->of_node
;
3559 /* Enable dma if requested in device tree */
3560 hsotg
->g_using_dma
= of_property_read_bool(np
, "g-use-dma");
3563 * Register TX periodic fifo size per endpoint.
3564 * EP0 is excluded since it has no fifo configuration.
3566 if (!of_find_property(np
, "g-tx-fifo-size", &len
))
3571 /* Read tx fifo sizes other than ep0 */
3572 if (of_property_read_u32_array(np
, "g-tx-fifo-size",
3573 &hsotg
->g_tx_fifo_sz
[1], len
))
3579 /* Make remaining TX fifos unavailable */
3580 if (len
< MAX_EPS_CHANNELS
) {
3581 for (i
= len
; i
< MAX_EPS_CHANNELS
; i
++)
3582 hsotg
->g_tx_fifo_sz
[i
] = 0;
3586 /* Register RX fifo size */
3587 of_property_read_u32(np
, "g-rx-fifo-size", &hsotg
->g_rx_fifo_sz
);
3589 /* Register NPTX fifo size */
3590 of_property_read_u32(np
, "g-np-tx-fifo-size",
3591 &hsotg
->g_np_g_tx_fifo_sz
);
3594 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg
*hsotg
) { }
3598 * dwc2_gadget_init - init function for gadget
3599 * @dwc2: The data structure for the DWC2 driver.
3600 * @irq: The IRQ number for the controller.
3602 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
3604 struct device
*dev
= hsotg
->dev
;
3605 struct dwc2_hsotg_plat
*plat
= dev
->platform_data
;
3609 u32 p_tx_fifo
[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE
;
3611 /* Set default UTMI width */
3612 hsotg
->phyif
= GUSBCFG_PHYIF16
;
3614 /* Initialize to legacy fifo configuration values */
3615 hsotg
->g_rx_fifo_sz
= 2048;
3616 hsotg
->g_np_g_tx_fifo_sz
= 1024;
3617 memcpy(&hsotg
->g_tx_fifo_sz
[1], p_tx_fifo
, sizeof(p_tx_fifo
));
3618 /* Device tree specific probe */
3619 dwc2_hsotg_of_probe(hsotg
);
3620 /* Dump fifo information */
3621 dev_dbg(dev
, "NonPeriodic TXFIFO size: %d\n",
3622 hsotg
->g_np_g_tx_fifo_sz
);
3623 dev_dbg(dev
, "RXFIFO size: %d\n", hsotg
->g_rx_fifo_sz
);
3624 for (i
= 0; i
< MAX_EPS_CHANNELS
; i
++)
3625 dev_dbg(dev
, "Periodic TXFIFO%2d size: %d\n", i
,
3626 hsotg
->g_tx_fifo_sz
[i
]);
3628 * If platform probe couldn't find a generic PHY or an old style
3629 * USB PHY, fall back to pdata
3631 if (IS_ERR_OR_NULL(hsotg
->phy
) && IS_ERR_OR_NULL(hsotg
->uphy
)) {
3632 plat
= dev_get_platdata(dev
);
3635 "no platform data or transceiver defined\n");
3636 return -EPROBE_DEFER
;
3639 } else if (hsotg
->phy
) {
3641 * If using the generic PHY framework, check if the PHY bus
3642 * width is 8-bit and set the phyif appropriately.
3644 if (phy_get_bus_width(hsotg
->phy
) == 8)
3645 hsotg
->phyif
= GUSBCFG_PHYIF8
;
3648 hsotg
->clk
= devm_clk_get(dev
, "otg");
3649 if (IS_ERR(hsotg
->clk
)) {
3651 dev_dbg(dev
, "cannot get otg clock\n");
3654 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3655 hsotg
->gadget
.ops
= &dwc2_hsotg_gadget_ops
;
3656 hsotg
->gadget
.name
= dev_name(dev
);
3657 if (hsotg
->dr_mode
== USB_DR_MODE_OTG
)
3658 hsotg
->gadget
.is_otg
= 1;
3659 else if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
3660 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
3662 /* reset the system */
3664 ret
= clk_prepare_enable(hsotg
->clk
);
3666 dev_err(dev
, "failed to enable otg clk\n");
3673 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3674 hsotg
->supplies
[i
].supply
= dwc2_hsotg_supply_names
[i
];
3676 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3679 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3683 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3687 dev_err(dev
, "failed to enable supplies: %d\n", ret
);
3691 /* usb phy enable */
3692 dwc2_hsotg_phy_enable(hsotg
);
3695 * Force Device mode before initialization.
3696 * This allows correctly configuring fifo for device mode.
3698 __bic32(hsotg
->regs
+ GUSBCFG
, GUSBCFG_FORCEHOSTMODE
);
3699 __orr32(hsotg
->regs
+ GUSBCFG
, GUSBCFG_FORCEDEVMODE
);
3702 * According to Synopsys databook, this sleep is needed for the force
3703 * device mode to take effect.
3707 dwc2_hsotg_corereset(hsotg
);
3708 ret
= dwc2_hsotg_hw_cfg(hsotg
);
3710 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
3714 dwc2_hsotg_init(hsotg
);
3716 /* Switch back to default configuration */
3717 __bic32(hsotg
->regs
+ GUSBCFG
, GUSBCFG_FORCEDEVMODE
);
3719 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
3720 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3721 if (!hsotg
->ctrl_buff
) {
3722 dev_err(dev
, "failed to allocate ctrl request buff\n");
3727 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
3728 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3729 if (!hsotg
->ep0_buff
) {
3730 dev_err(dev
, "failed to allocate ctrl reply buff\n");
3735 ret
= devm_request_irq(hsotg
->dev
, irq
, dwc2_hsotg_irq
, IRQF_SHARED
,
3736 dev_name(hsotg
->dev
), hsotg
);
3738 dwc2_hsotg_phy_disable(hsotg
);
3739 clk_disable_unprepare(hsotg
->clk
);
3740 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3742 dev_err(dev
, "cannot claim IRQ for gadget\n");
3746 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3748 if (hsotg
->num_of_eps
== 0) {
3749 dev_err(dev
, "wrong number of EPs (zero)\n");
3754 /* setup endpoint information */
3756 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3757 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
3759 /* allocate EP0 request */
3761 hsotg
->ctrl_req
= dwc2_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
3763 if (!hsotg
->ctrl_req
) {
3764 dev_err(dev
, "failed to allocate ctrl req\n");
3769 /* initialise the endpoints now the core has been initialised */
3770 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
3771 if (hsotg
->eps_in
[epnum
])
3772 dwc2_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
3774 if (hsotg
->eps_out
[epnum
])
3775 dwc2_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
3779 /* disable power and clock */
3780 dwc2_hsotg_phy_disable(hsotg
);
3782 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3785 dev_err(dev
, "failed to disable supplies: %d\n", ret
);
3789 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
3793 dwc2_hsotg_dump(hsotg
);
3798 dwc2_hsotg_phy_disable(hsotg
);
3800 clk_disable_unprepare(hsotg
->clk
);
3806 * dwc2_hsotg_remove - remove function for hsotg driver
3807 * @pdev: The platform information for the driver
3809 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
)
3811 usb_del_gadget_udc(&hsotg
->gadget
);
3812 clk_disable_unprepare(hsotg
->clk
);
3817 int dwc2_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
3819 unsigned long flags
;
3822 if (hsotg
->lx_state
!= DWC2_L0
)
3825 if (hsotg
->driver
) {
3828 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
3829 hsotg
->driver
->driver
.name
);
3831 spin_lock_irqsave(&hsotg
->lock
, flags
);
3833 dwc2_hsotg_core_disconnect(hsotg
);
3834 dwc2_hsotg_disconnect(hsotg
);
3835 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3836 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3838 dwc2_hsotg_phy_disable(hsotg
);
3840 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3841 if (hsotg
->eps_in
[ep
])
3842 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
3843 if (hsotg
->eps_out
[ep
])
3844 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
3847 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3849 clk_disable(hsotg
->clk
);
3855 int dwc2_hsotg_resume(struct dwc2_hsotg
*hsotg
)
3857 unsigned long flags
;
3860 if (hsotg
->lx_state
== DWC2_L2
)
3863 if (hsotg
->driver
) {
3864 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
3865 hsotg
->driver
->driver
.name
);
3867 clk_enable(hsotg
->clk
);
3868 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3871 dwc2_hsotg_phy_enable(hsotg
);
3873 spin_lock_irqsave(&hsotg
->lock
, flags
);
3874 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3876 dwc2_hsotg_core_connect(hsotg
);
3877 spin_unlock_irqrestore(&hsotg
->lock
, flags
);