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0686acff1e22a839e95727f7e381170430ea4ed1
[deliverable/linux.git] / drivers / usb / dwc3 / core.c
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/io.h>
31 #include <linux/list.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/of.h>
35
36 #include <linux/usb/otg.h>
37 #include <linux/usb/ch9.h>
38 #include <linux/usb/gadget.h>
39 #include <linux/usb/of.h>
40
41 #include "platform_data.h"
42 #include "core.h"
43 #include "gadget.h"
44 #include "io.h"
45
46 #include "debug.h"
47
48 /* -------------------------------------------------------------------------- */
49
50 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
51 {
52 u32 reg;
53
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
56 reg |= DWC3_GCTL_PRTCAPDIR(mode);
57 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
58 }
59
60 /**
61 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
62 * @dwc: pointer to our context structure
63 */
64 static void dwc3_core_soft_reset(struct dwc3 *dwc)
65 {
66 u32 reg;
67
68 /* Before Resetting PHY, put Core in Reset */
69 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
70 reg |= DWC3_GCTL_CORESOFTRESET;
71 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
72
73 /* Assert USB3 PHY reset */
74 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
75 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
76 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
77
78 /* Assert USB2 PHY reset */
79 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
80 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
81 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
82
83 usb_phy_init(dwc->usb2_phy);
84 usb_phy_init(dwc->usb3_phy);
85 mdelay(100);
86
87 /* Clear USB3 PHY reset */
88 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
89 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
90 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
91
92 /* Clear USB2 PHY reset */
93 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
94 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
95 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
96
97 mdelay(100);
98
99 /* After PHYs are stable we can take Core out of reset state */
100 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
101 reg &= ~DWC3_GCTL_CORESOFTRESET;
102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
103 }
104
105 /**
106 * dwc3_free_one_event_buffer - Frees one event buffer
107 * @dwc: Pointer to our controller context structure
108 * @evt: Pointer to event buffer to be freed
109 */
110 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
111 struct dwc3_event_buffer *evt)
112 {
113 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
114 }
115
116 /**
117 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
118 * @dwc: Pointer to our controller context structure
119 * @length: size of the event buffer
120 *
121 * Returns a pointer to the allocated event buffer structure on success
122 * otherwise ERR_PTR(errno).
123 */
124 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
125 unsigned length)
126 {
127 struct dwc3_event_buffer *evt;
128
129 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
130 if (!evt)
131 return ERR_PTR(-ENOMEM);
132
133 evt->dwc = dwc;
134 evt->length = length;
135 evt->buf = dma_alloc_coherent(dwc->dev, length,
136 &evt->dma, GFP_KERNEL);
137 if (!evt->buf)
138 return ERR_PTR(-ENOMEM);
139
140 return evt;
141 }
142
143 /**
144 * dwc3_free_event_buffers - frees all allocated event buffers
145 * @dwc: Pointer to our controller context structure
146 */
147 static void dwc3_free_event_buffers(struct dwc3 *dwc)
148 {
149 struct dwc3_event_buffer *evt;
150 int i;
151
152 for (i = 0; i < dwc->num_event_buffers; i++) {
153 evt = dwc->ev_buffs[i];
154 if (evt)
155 dwc3_free_one_event_buffer(dwc, evt);
156 }
157 }
158
159 /**
160 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
161 * @dwc: pointer to our controller context structure
162 * @length: size of event buffer
163 *
164 * Returns 0 on success otherwise negative errno. In the error case, dwc
165 * may contain some buffers allocated but not all which were requested.
166 */
167 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
168 {
169 int num;
170 int i;
171
172 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
173 dwc->num_event_buffers = num;
174
175 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
176 GFP_KERNEL);
177 if (!dwc->ev_buffs) {
178 dev_err(dwc->dev, "can't allocate event buffers array\n");
179 return -ENOMEM;
180 }
181
182 for (i = 0; i < num; i++) {
183 struct dwc3_event_buffer *evt;
184
185 evt = dwc3_alloc_one_event_buffer(dwc, length);
186 if (IS_ERR(evt)) {
187 dev_err(dwc->dev, "can't allocate event buffer\n");
188 return PTR_ERR(evt);
189 }
190 dwc->ev_buffs[i] = evt;
191 }
192
193 return 0;
194 }
195
196 /**
197 * dwc3_event_buffers_setup - setup our allocated event buffers
198 * @dwc: pointer to our controller context structure
199 *
200 * Returns 0 on success otherwise negative errno.
201 */
202 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
203 {
204 struct dwc3_event_buffer *evt;
205 int n;
206
207 for (n = 0; n < dwc->num_event_buffers; n++) {
208 evt = dwc->ev_buffs[n];
209 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
210 evt->buf, (unsigned long long) evt->dma,
211 evt->length);
212
213 evt->lpos = 0;
214
215 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
216 lower_32_bits(evt->dma));
217 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
218 upper_32_bits(evt->dma));
219 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
220 evt->length & 0xffff);
221 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
222 }
223
224 return 0;
225 }
226
227 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
228 {
229 struct dwc3_event_buffer *evt;
230 int n;
231
232 for (n = 0; n < dwc->num_event_buffers; n++) {
233 evt = dwc->ev_buffs[n];
234
235 evt->lpos = 0;
236
237 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
238 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
239 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
240 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
241 }
242 }
243
244 static void dwc3_core_num_eps(struct dwc3 *dwc)
245 {
246 struct dwc3_hwparams *parms = &dwc->hwparams;
247
248 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
249 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
250
251 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
252 dwc->num_in_eps, dwc->num_out_eps);
253 }
254
255 static void dwc3_cache_hwparams(struct dwc3 *dwc)
256 {
257 struct dwc3_hwparams *parms = &dwc->hwparams;
258
259 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
260 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
261 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
262 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
263 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
264 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
265 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
266 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
267 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
268 }
269
270 /**
271 * dwc3_core_init - Low-level initialization of DWC3 Core
272 * @dwc: Pointer to our controller context structure
273 *
274 * Returns 0 on success otherwise negative errno.
275 */
276 static int dwc3_core_init(struct dwc3 *dwc)
277 {
278 unsigned long timeout;
279 u32 reg;
280 int ret;
281
282 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
283 /* This should read as U3 followed by revision number */
284 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
285 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
286 ret = -ENODEV;
287 goto err0;
288 }
289 dwc->revision = reg;
290
291 /* issue device SoftReset too */
292 timeout = jiffies + msecs_to_jiffies(500);
293 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
294 do {
295 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
296 if (!(reg & DWC3_DCTL_CSFTRST))
297 break;
298
299 if (time_after(jiffies, timeout)) {
300 dev_err(dwc->dev, "Reset Timed Out\n");
301 ret = -ETIMEDOUT;
302 goto err0;
303 }
304
305 cpu_relax();
306 } while (true);
307
308 dwc3_core_soft_reset(dwc);
309
310 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
311 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
312 reg &= ~DWC3_GCTL_DISSCRAMBLE;
313
314 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
315 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
316 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
317 break;
318 default:
319 dev_dbg(dwc->dev, "No power optimization available\n");
320 }
321
322 /*
323 * WORKAROUND: DWC3 revisions <1.90a have a bug
324 * where the device can fail to connect at SuperSpeed
325 * and falls back to high-speed mode which causes
326 * the device to enter a Connect/Disconnect loop
327 */
328 if (dwc->revision < DWC3_REVISION_190A)
329 reg |= DWC3_GCTL_U2RSTECN;
330
331 dwc3_core_num_eps(dwc);
332
333 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
334
335 return 0;
336
337 err0:
338 return ret;
339 }
340
341 static void dwc3_core_exit(struct dwc3 *dwc)
342 {
343 usb_phy_shutdown(dwc->usb2_phy);
344 usb_phy_shutdown(dwc->usb3_phy);
345 }
346
347 #define DWC3_ALIGN_MASK (16 - 1)
348
349 static int dwc3_probe(struct platform_device *pdev)
350 {
351 struct dwc3_platform_data *pdata = pdev->dev.platform_data;
352 struct device_node *node = pdev->dev.of_node;
353 struct resource *res;
354 struct dwc3 *dwc;
355 struct device *dev = &pdev->dev;
356
357 int ret = -ENOMEM;
358
359 void __iomem *regs;
360 void *mem;
361
362 u8 mode;
363
364 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
365 if (!mem) {
366 dev_err(dev, "not enough memory\n");
367 return -ENOMEM;
368 }
369 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
370 dwc->mem = mem;
371
372 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
373 if (!res) {
374 dev_err(dev, "missing IRQ\n");
375 return -ENODEV;
376 }
377 dwc->xhci_resources[1].start = res->start;
378 dwc->xhci_resources[1].end = res->end;
379 dwc->xhci_resources[1].flags = res->flags;
380 dwc->xhci_resources[1].name = res->name;
381
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 if (!res) {
384 dev_err(dev, "missing memory resource\n");
385 return -ENODEV;
386 }
387 dwc->xhci_resources[0].start = res->start;
388 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
389 DWC3_XHCI_REGS_END;
390 dwc->xhci_resources[0].flags = res->flags;
391 dwc->xhci_resources[0].name = res->name;
392
393 /*
394 * Request memory region but exclude xHCI regs,
395 * since it will be requested by the xhci-plat driver.
396 */
397 res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
398 resource_size(res) - DWC3_GLOBALS_REGS_START,
399 dev_name(dev));
400 if (!res) {
401 dev_err(dev, "can't request mem region\n");
402 return -ENOMEM;
403 }
404
405 regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
406 if (!regs) {
407 dev_err(dev, "ioremap failed\n");
408 return -ENOMEM;
409 }
410
411 if (node) {
412 dwc->maximum_speed = of_usb_get_maximum_speed(node);
413
414 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
415 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
416
417 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
418 } else {
419 dwc->maximum_speed = pdata->maximum_speed;
420
421 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
422 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
423
424 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
425 }
426
427 /* default to superspeed if no maximum_speed passed */
428 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
429 dwc->maximum_speed = USB_SPEED_SUPER;
430
431 if (IS_ERR(dwc->usb2_phy)) {
432 ret = PTR_ERR(dwc->usb2_phy);
433
434 /*
435 * if -ENXIO is returned, it means PHY layer wasn't
436 * enabled, so it makes no sense to return -EPROBE_DEFER
437 * in that case, since no PHY driver will ever probe.
438 */
439 if (ret == -ENXIO)
440 return ret;
441
442 dev_err(dev, "no usb2 phy configured\n");
443 return -EPROBE_DEFER;
444 }
445
446 if (IS_ERR(dwc->usb3_phy)) {
447 ret = PTR_ERR(dwc->usb3_phy);
448
449 /*
450 * if -ENXIO is returned, it means PHY layer wasn't
451 * enabled, so it makes no sense to return -EPROBE_DEFER
452 * in that case, since no PHY driver will ever probe.
453 */
454 if (ret == -ENXIO)
455 return ret;
456
457 dev_err(dev, "no usb3 phy configured\n");
458 return -EPROBE_DEFER;
459 }
460
461 usb_phy_set_suspend(dwc->usb2_phy, 0);
462 usb_phy_set_suspend(dwc->usb3_phy, 0);
463
464 spin_lock_init(&dwc->lock);
465 platform_set_drvdata(pdev, dwc);
466
467 dwc->regs = regs;
468 dwc->regs_size = resource_size(res);
469 dwc->dev = dev;
470
471 dev->dma_mask = dev->parent->dma_mask;
472 dev->dma_parms = dev->parent->dma_parms;
473 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
474
475 pm_runtime_enable(dev);
476 pm_runtime_get_sync(dev);
477 pm_runtime_forbid(dev);
478
479 dwc3_cache_hwparams(dwc);
480
481 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
482 if (ret) {
483 dev_err(dwc->dev, "failed to allocate event buffers\n");
484 ret = -ENOMEM;
485 goto err0;
486 }
487
488 ret = dwc3_core_init(dwc);
489 if (ret) {
490 dev_err(dev, "failed to initialize core\n");
491 goto err0;
492 }
493
494 ret = dwc3_event_buffers_setup(dwc);
495 if (ret) {
496 dev_err(dwc->dev, "failed to setup event buffers\n");
497 goto err1;
498 }
499
500 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
501 mode = DWC3_MODE_HOST;
502 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
503 mode = DWC3_MODE_DEVICE;
504 else
505 mode = DWC3_MODE_DRD;
506
507 switch (mode) {
508 case DWC3_MODE_DEVICE:
509 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
510 ret = dwc3_gadget_init(dwc);
511 if (ret) {
512 dev_err(dev, "failed to initialize gadget\n");
513 goto err2;
514 }
515 break;
516 case DWC3_MODE_HOST:
517 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
518 ret = dwc3_host_init(dwc);
519 if (ret) {
520 dev_err(dev, "failed to initialize host\n");
521 goto err2;
522 }
523 break;
524 case DWC3_MODE_DRD:
525 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
526 ret = dwc3_host_init(dwc);
527 if (ret) {
528 dev_err(dev, "failed to initialize host\n");
529 goto err2;
530 }
531
532 ret = dwc3_gadget_init(dwc);
533 if (ret) {
534 dev_err(dev, "failed to initialize gadget\n");
535 goto err2;
536 }
537 break;
538 default:
539 dev_err(dev, "Unsupported mode of operation %d\n", mode);
540 goto err2;
541 }
542 dwc->mode = mode;
543
544 ret = dwc3_debugfs_init(dwc);
545 if (ret) {
546 dev_err(dev, "failed to initialize debugfs\n");
547 goto err3;
548 }
549
550 pm_runtime_allow(dev);
551
552 return 0;
553
554 err3:
555 switch (mode) {
556 case DWC3_MODE_DEVICE:
557 dwc3_gadget_exit(dwc);
558 break;
559 case DWC3_MODE_HOST:
560 dwc3_host_exit(dwc);
561 break;
562 case DWC3_MODE_DRD:
563 dwc3_host_exit(dwc);
564 dwc3_gadget_exit(dwc);
565 break;
566 default:
567 /* do nothing */
568 break;
569 }
570
571 err2:
572 dwc3_event_buffers_cleanup(dwc);
573
574 err1:
575 dwc3_core_exit(dwc);
576
577 err0:
578 dwc3_free_event_buffers(dwc);
579
580 return ret;
581 }
582
583 static int dwc3_remove(struct platform_device *pdev)
584 {
585 struct dwc3 *dwc = platform_get_drvdata(pdev);
586
587 usb_phy_set_suspend(dwc->usb2_phy, 1);
588 usb_phy_set_suspend(dwc->usb3_phy, 1);
589
590 pm_runtime_put(&pdev->dev);
591 pm_runtime_disable(&pdev->dev);
592
593 dwc3_debugfs_exit(dwc);
594
595 switch (dwc->mode) {
596 case DWC3_MODE_DEVICE:
597 dwc3_gadget_exit(dwc);
598 break;
599 case DWC3_MODE_HOST:
600 dwc3_host_exit(dwc);
601 break;
602 case DWC3_MODE_DRD:
603 dwc3_host_exit(dwc);
604 dwc3_gadget_exit(dwc);
605 break;
606 default:
607 /* do nothing */
608 break;
609 }
610
611 dwc3_event_buffers_cleanup(dwc);
612 dwc3_free_event_buffers(dwc);
613 dwc3_core_exit(dwc);
614
615 return 0;
616 }
617
618 #ifdef CONFIG_PM_SLEEP
619 static int dwc3_prepare(struct device *dev)
620 {
621 struct dwc3 *dwc = dev_get_drvdata(dev);
622 unsigned long flags;
623
624 spin_lock_irqsave(&dwc->lock, flags);
625
626 switch (dwc->mode) {
627 case DWC3_MODE_DEVICE:
628 case DWC3_MODE_DRD:
629 dwc3_gadget_prepare(dwc);
630 /* FALLTHROUGH */
631 case DWC3_MODE_HOST:
632 default:
633 dwc3_event_buffers_cleanup(dwc);
634 break;
635 }
636
637 spin_unlock_irqrestore(&dwc->lock, flags);
638
639 return 0;
640 }
641
642 static void dwc3_complete(struct device *dev)
643 {
644 struct dwc3 *dwc = dev_get_drvdata(dev);
645 unsigned long flags;
646
647 spin_lock_irqsave(&dwc->lock, flags);
648
649 switch (dwc->mode) {
650 case DWC3_MODE_DEVICE:
651 case DWC3_MODE_DRD:
652 dwc3_gadget_complete(dwc);
653 /* FALLTHROUGH */
654 case DWC3_MODE_HOST:
655 default:
656 dwc3_event_buffers_setup(dwc);
657 break;
658 }
659
660 spin_unlock_irqrestore(&dwc->lock, flags);
661 }
662
663 static int dwc3_suspend(struct device *dev)
664 {
665 struct dwc3 *dwc = dev_get_drvdata(dev);
666 unsigned long flags;
667
668 spin_lock_irqsave(&dwc->lock, flags);
669
670 switch (dwc->mode) {
671 case DWC3_MODE_DEVICE:
672 case DWC3_MODE_DRD:
673 dwc3_gadget_suspend(dwc);
674 /* FALLTHROUGH */
675 case DWC3_MODE_HOST:
676 default:
677 /* do nothing */
678 break;
679 }
680
681 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
682 spin_unlock_irqrestore(&dwc->lock, flags);
683
684 usb_phy_shutdown(dwc->usb3_phy);
685 usb_phy_shutdown(dwc->usb2_phy);
686
687 return 0;
688 }
689
690 static int dwc3_resume(struct device *dev)
691 {
692 struct dwc3 *dwc = dev_get_drvdata(dev);
693 unsigned long flags;
694
695 usb_phy_init(dwc->usb3_phy);
696 usb_phy_init(dwc->usb2_phy);
697 msleep(100);
698
699 spin_lock_irqsave(&dwc->lock, flags);
700
701 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
702
703 switch (dwc->mode) {
704 case DWC3_MODE_DEVICE:
705 case DWC3_MODE_DRD:
706 dwc3_gadget_resume(dwc);
707 /* FALLTHROUGH */
708 case DWC3_MODE_HOST:
709 default:
710 /* do nothing */
711 break;
712 }
713
714 spin_unlock_irqrestore(&dwc->lock, flags);
715
716 pm_runtime_disable(dev);
717 pm_runtime_set_active(dev);
718 pm_runtime_enable(dev);
719
720 return 0;
721 }
722
723 static const struct dev_pm_ops dwc3_dev_pm_ops = {
724 .prepare = dwc3_prepare,
725 .complete = dwc3_complete,
726
727 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
728 };
729
730 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
731 #else
732 #define DWC3_PM_OPS NULL
733 #endif
734
735 #ifdef CONFIG_OF
736 static const struct of_device_id of_dwc3_match[] = {
737 {
738 .compatible = "synopsys,dwc3"
739 },
740 { },
741 };
742 MODULE_DEVICE_TABLE(of, of_dwc3_match);
743 #endif
744
745 static struct platform_driver dwc3_driver = {
746 .probe = dwc3_probe,
747 .remove = dwc3_remove,
748 .driver = {
749 .name = "dwc3",
750 .of_match_table = of_match_ptr(of_dwc3_match),
751 .pm = DWC3_PM_OPS,
752 },
753 };
754
755 module_platform_driver(dwc3_driver);
756
757 MODULE_ALIAS("platform:dwc3");
758 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
759 MODULE_LICENSE("GPL v2");
760 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux kernel - Deliverables
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