drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/ioport.h>
  47 #include <linux/io.h>
  48 #include <linux/list.h>
  49 #include <linux/delay.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/of.h>
  52
  53 #include <linux/usb/otg.h>
  54 #include <linux/usb/ch9.h>
  55 #include <linux/usb/gadget.h>
  56
  57 #include "core.h"
  58 #include "gadget.h"
  59 #include "io.h"
  60
  61 #include "debug.h"
  62
  63 static char *maximum_speed = "super";
  64 module_param(maximum_speed, charp, 0);
  65 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
  66
  67 /* -------------------------------------------------------------------------- */
  68
  69 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  70 {
  71         u32 reg;
  72
  73         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  74         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  75         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  76         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  77 }
  78
  79 /**
  80  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  81  * @dwc: pointer to our context structure
  82  */
  83 static void dwc3_core_soft_reset(struct dwc3 *dwc)
  84 {
  85         u32             reg;
  86
  87         /* Before Resetting PHY, put Core in Reset */
  88         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  89         reg |= DWC3_GCTL_CORESOFTRESET;
  90         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  91
  92         /* Assert USB3 PHY reset */
  93         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  94         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  95         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  96
  97         /* Assert USB2 PHY reset */
  98         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  99         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
 100         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 101
 102         usb_phy_init(dwc->usb2_phy);
 103         usb_phy_init(dwc->usb3_phy);
 104         mdelay(100);
 105
 106         /* Clear USB3 PHY reset */
 107         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 108         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 109         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 110
 111         /* Clear USB2 PHY reset */
 112         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 113         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 114         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 115
 116         mdelay(100);
 117
 118         /* After PHYs are stable we can take Core out of reset state */
 119         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 120         reg &= ~DWC3_GCTL_CORESOFTRESET;
 121         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 122 }
 123
 124 /**
 125  * dwc3_free_one_event_buffer - Frees one event buffer
 126  * @dwc: Pointer to our controller context structure
 127  * @evt: Pointer to event buffer to be freed
 128  */
 129 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 130                 struct dwc3_event_buffer *evt)
 131 {
 132         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 133 }
 134
 135 /**
 136  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 137  * @dwc: Pointer to our controller context structure
 138  * @length: size of the event buffer
 139  *
 140  * Returns a pointer to the allocated event buffer structure on success
 141  * otherwise ERR_PTR(errno).
 142  */
 143 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 144                 unsigned length)
 145 {
 146         struct dwc3_event_buffer        *evt;
 147
 148         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 149         if (!evt)
 150                 return ERR_PTR(-ENOMEM);
 151
 152         evt->dwc        = dwc;
 153         evt->length     = length;
 154         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 155                         &evt->dma, GFP_KERNEL);
 156         if (!evt->buf)
 157                 return ERR_PTR(-ENOMEM);
 158
 159         return evt;
 160 }
 161
 162 /**
 163  * dwc3_free_event_buffers - frees all allocated event buffers
 164  * @dwc: Pointer to our controller context structure
 165  */
 166 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 167 {
 168         struct dwc3_event_buffer        *evt;
 169         int i;
 170
 171         for (i = 0; i < dwc->num_event_buffers; i++) {
 172                 evt = dwc->ev_buffs[i];
 173                 if (evt)
 174                         dwc3_free_one_event_buffer(dwc, evt);
 175         }
 176 }
 177
 178 /**
 179  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 180  * @dwc: pointer to our controller context structure
 181  * @length: size of event buffer
 182  *
 183  * Returns 0 on success otherwise negative errno. In the error case, dwc
 184  * may contain some buffers allocated but not all which were requested.
 185  */
 186 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 187 {
 188         int                     num;
 189         int                     i;
 190
 191         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 192         dwc->num_event_buffers = num;
 193
 194         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 195                         GFP_KERNEL);
 196         if (!dwc->ev_buffs) {
 197                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 198                 return -ENOMEM;
 199         }
 200
 201         for (i = 0; i < num; i++) {
 202                 struct dwc3_event_buffer        *evt;
 203
 204                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 205                 if (IS_ERR(evt)) {
 206                         dev_err(dwc->dev, "can't allocate event buffer\n");
 207                         return PTR_ERR(evt);
 208                 }
 209                 dwc->ev_buffs[i] = evt;
 210         }
 211
 212         return 0;
 213 }
 214
 215 /**
 216  * dwc3_event_buffers_setup - setup our allocated event buffers
 217  * @dwc: pointer to our controller context structure
 218  *
 219  * Returns 0 on success otherwise negative errno.
 220  */
 221 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 222 {
 223         struct dwc3_event_buffer        *evt;
 224         int                             n;
 225
 226         for (n = 0; n < dwc->num_event_buffers; n++) {
 227                 evt = dwc->ev_buffs[n];
 228                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 229                                 evt->buf, (unsigned long long) evt->dma,
 230                                 evt->length);
 231
 232                 evt->lpos = 0;
 233
 234                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 235                                 lower_32_bits(evt->dma));
 236                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 237                                 upper_32_bits(evt->dma));
 238                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 239                                 evt->length & 0xffff);
 240                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 247 {
 248         struct dwc3_event_buffer        *evt;
 249         int                             n;
 250
 251         for (n = 0; n < dwc->num_event_buffers; n++) {
 252                 evt = dwc->ev_buffs[n];
 253
 254                 evt->lpos = 0;
 255
 256                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 257                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 258                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
 259                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 260         }
 261 }
 262
 263 static void dwc3_core_num_eps(struct dwc3 *dwc)
 264 {
 265         struct dwc3_hwparams    *parms = &dwc->hwparams;
 266
 267         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 268         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 269
 270         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 271                         dwc->num_in_eps, dwc->num_out_eps);
 272 }
 273
 274 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 275 {
 276         struct dwc3_hwparams    *parms = &dwc->hwparams;
 277
 278         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 279         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 280         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 281         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 282         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 283         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 284         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 285         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 286         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 287 }
 288
 289 /**
 290  * dwc3_core_init - Low-level initialization of DWC3 Core
 291  * @dwc: Pointer to our controller context structure
 292  *
 293  * Returns 0 on success otherwise negative errno.
 294  */
 295 static int dwc3_core_init(struct dwc3 *dwc)
 296 {
 297         unsigned long           timeout;
 298         u32                     reg;
 299         int                     ret;
 300
 301         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 302         /* This should read as U3 followed by revision number */
 303         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 304                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 305                 ret = -ENODEV;
 306                 goto err0;
 307         }
 308         dwc->revision = reg;
 309
 310         /* issue device SoftReset too */
 311         timeout = jiffies + msecs_to_jiffies(500);
 312         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 313         do {
 314                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 315                 if (!(reg & DWC3_DCTL_CSFTRST))
 316                         break;
 317
 318                 if (time_after(jiffies, timeout)) {
 319                         dev_err(dwc->dev, "Reset Timed Out\n");
 320                         ret = -ETIMEDOUT;
 321                         goto err0;
 322                 }
 323
 324                 cpu_relax();
 325         } while (true);
 326
 327         dwc3_core_soft_reset(dwc);
 328
 329         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 330         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 331         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 332
 333         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 334         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 335                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 336                 break;
 337         default:
 338                 dev_dbg(dwc->dev, "No power optimization available\n");
 339         }
 340
 341         /*
 342          * WORKAROUND: DWC3 revisions <1.90a have a bug
 343          * where the device can fail to connect at SuperSpeed
 344          * and falls back to high-speed mode which causes
 345          * the device to enter a Connect/Disconnect loop
 346          */
 347         if (dwc->revision < DWC3_REVISION_190A)
 348                 reg |= DWC3_GCTL_U2RSTECN;
 349
 350         dwc3_core_num_eps(dwc);
 351
 352         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 353
 354         return 0;
 355
 356 err0:
 357         return ret;
 358 }
 359
 360 static void dwc3_core_exit(struct dwc3 *dwc)
 361 {
 362         usb_phy_shutdown(dwc->usb2_phy);
 363         usb_phy_shutdown(dwc->usb3_phy);
 364 }
 365
 366 #define DWC3_ALIGN_MASK         (16 - 1)
 367
 368 static int dwc3_probe(struct platform_device *pdev)
 369 {
 370         struct device_node      *node = pdev->dev.of_node;
 371         struct resource         *res;
 372         struct dwc3             *dwc;
 373         struct device           *dev = &pdev->dev;
 374
 375         int                     ret = -ENOMEM;
 376
 377         void __iomem            *regs;
 378         void                    *mem;
 379
 380         u8                      mode;
 381
 382         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 383         if (!mem) {
 384                 dev_err(dev, "not enough memory\n");
 385                 return -ENOMEM;
 386         }
 387         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 388         dwc->mem = mem;
 389
 390         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 391         if (!res) {
 392                 dev_err(dev, "missing IRQ\n");
 393                 return -ENODEV;
 394         }
 395         dwc->xhci_resources[1].start = res->start;
 396         dwc->xhci_resources[1].end = res->end;
 397         dwc->xhci_resources[1].flags = res->flags;
 398         dwc->xhci_resources[1].name = res->name;
 399
 400         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 401         if (!res) {
 402                 dev_err(dev, "missing memory resource\n");
 403                 return -ENODEV;
 404         }
 405         dwc->xhci_resources[0].start = res->start;
 406         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 407                                         DWC3_XHCI_REGS_END;
 408         dwc->xhci_resources[0].flags = res->flags;
 409         dwc->xhci_resources[0].name = res->name;
 410
 411          /*
 412           * Request memory region but exclude xHCI regs,
 413           * since it will be requested by the xhci-plat driver.
 414           */
 415         res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
 416                         resource_size(res) - DWC3_GLOBALS_REGS_START,
 417                         dev_name(dev));
 418         if (!res) {
 419                 dev_err(dev, "can't request mem region\n");
 420                 return -ENOMEM;
 421         }
 422
 423         regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 424         if (!regs) {
 425                 dev_err(dev, "ioremap failed\n");
 426                 return -ENOMEM;
 427         }
 428
 429         if (node) {
 430                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 431                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 432         } else {
 433                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 434                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 435         }
 436
 437         if (IS_ERR(dwc->usb2_phy)) {
 438                 ret = PTR_ERR(dwc->usb2_phy);
 439
 440                 /*
 441                  * if -ENXIO is returned, it means PHY layer wasn't
 442                  * enabled, so it makes no sense to return -EPROBE_DEFER
 443                  * in that case, since no PHY driver will ever probe.
 444                  */
 445                 if (ret == -ENXIO)
 446                         return ret;
 447
 448                 dev_err(dev, "no usb2 phy configured\n");
 449                 return -EPROBE_DEFER;
 450         }
 451
 452         if (IS_ERR(dwc->usb3_phy)) {
 453                 ret = PTR_ERR(dwc->usb3_phy);
 454
 455                 /*
 456                  * if -ENXIO is returned, it means PHY layer wasn't
 457                  * enabled, so it makes no sense to return -EPROBE_DEFER
 458                  * in that case, since no PHY driver will ever probe.
 459                  */
 460                 if (ret == -ENXIO)
 461                         return ret;
 462
 463                 dev_err(dev, "no usb3 phy configured\n");
 464                 return -EPROBE_DEFER;
 465         }
 466
 467         usb_phy_set_suspend(dwc->usb2_phy, 0);
 468         usb_phy_set_suspend(dwc->usb3_phy, 0);
 469
 470         spin_lock_init(&dwc->lock);
 471         platform_set_drvdata(pdev, dwc);
 472
 473         dwc->regs       = regs;
 474         dwc->regs_size  = resource_size(res);
 475         dwc->dev        = dev;
 476
 477         dev->dma_mask   = dev->parent->dma_mask;
 478         dev->dma_parms  = dev->parent->dma_parms;
 479         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 480
 481         if (!strncmp("super", maximum_speed, 5))
 482                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 483         else if (!strncmp("high", maximum_speed, 4))
 484                 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
 485         else if (!strncmp("full", maximum_speed, 4))
 486                 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
 487         else if (!strncmp("low", maximum_speed, 3))
 488                 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
 489         else
 490                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 491
 492         dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 493
 494         pm_runtime_enable(dev);
 495         pm_runtime_get_sync(dev);
 496         pm_runtime_forbid(dev);
 497
 498         dwc3_cache_hwparams(dwc);
 499
 500         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 501         if (ret) {
 502                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 503                 ret = -ENOMEM;
 504                 goto err0;
 505         }
 506
 507         ret = dwc3_core_init(dwc);
 508         if (ret) {
 509                 dev_err(dev, "failed to initialize core\n");
 510                 goto err0;
 511         }
 512
 513         ret = dwc3_event_buffers_setup(dwc);
 514         if (ret) {
 515                 dev_err(dwc->dev, "failed to setup event buffers\n");
 516                 goto err1;
 517         }
 518
 519         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 520                 mode = DWC3_MODE_HOST;
 521         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 522                 mode = DWC3_MODE_DEVICE;
 523         else
 524                 mode = DWC3_MODE_DRD;
 525
 526         switch (mode) {
 527         case DWC3_MODE_DEVICE:
 528                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 529                 ret = dwc3_gadget_init(dwc);
 530                 if (ret) {
 531                         dev_err(dev, "failed to initialize gadget\n");
 532                         goto err2;
 533                 }
 534                 break;
 535         case DWC3_MODE_HOST:
 536                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 537                 ret = dwc3_host_init(dwc);
 538                 if (ret) {
 539                         dev_err(dev, "failed to initialize host\n");
 540                         goto err2;
 541                 }
 542                 break;
 543         case DWC3_MODE_DRD:
 544                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 545                 ret = dwc3_host_init(dwc);
 546                 if (ret) {
 547                         dev_err(dev, "failed to initialize host\n");
 548                         goto err2;
 549                 }
 550
 551                 ret = dwc3_gadget_init(dwc);
 552                 if (ret) {
 553                         dev_err(dev, "failed to initialize gadget\n");
 554                         goto err2;
 555                 }
 556                 break;
 557         default:
 558                 dev_err(dev, "Unsupported mode of operation %d\n", mode);
 559                 goto err2;
 560         }
 561         dwc->mode = mode;
 562
 563         ret = dwc3_debugfs_init(dwc);
 564         if (ret) {
 565                 dev_err(dev, "failed to initialize debugfs\n");
 566                 goto err3;
 567         }
 568
 569         pm_runtime_allow(dev);
 570
 571         return 0;
 572
 573 err3:
 574         switch (mode) {
 575         case DWC3_MODE_DEVICE:
 576                 dwc3_gadget_exit(dwc);
 577                 break;
 578         case DWC3_MODE_HOST:
 579                 dwc3_host_exit(dwc);
 580                 break;
 581         case DWC3_MODE_DRD:
 582                 dwc3_host_exit(dwc);
 583                 dwc3_gadget_exit(dwc);
 584                 break;
 585         default:
 586                 /* do nothing */
 587                 break;
 588         }
 589
 590 err2:
 591         dwc3_event_buffers_cleanup(dwc);
 592
 593 err1:
 594         dwc3_core_exit(dwc);
 595
 596 err0:
 597         dwc3_free_event_buffers(dwc);
 598
 599         return ret;
 600 }
 601
 602 static int dwc3_remove(struct platform_device *pdev)
 603 {
 604         struct dwc3     *dwc = platform_get_drvdata(pdev);
 605
 606         usb_phy_set_suspend(dwc->usb2_phy, 1);
 607         usb_phy_set_suspend(dwc->usb3_phy, 1);
 608
 609         pm_runtime_put(&pdev->dev);
 610         pm_runtime_disable(&pdev->dev);
 611
 612         dwc3_debugfs_exit(dwc);
 613
 614         switch (dwc->mode) {
 615         case DWC3_MODE_DEVICE:
 616                 dwc3_gadget_exit(dwc);
 617                 break;
 618         case DWC3_MODE_HOST:
 619                 dwc3_host_exit(dwc);
 620                 break;
 621         case DWC3_MODE_DRD:
 622                 dwc3_host_exit(dwc);
 623                 dwc3_gadget_exit(dwc);
 624                 break;
 625         default:
 626                 /* do nothing */
 627                 break;
 628         }
 629
 630         dwc3_event_buffers_cleanup(dwc);
 631         dwc3_free_event_buffers(dwc);
 632         dwc3_core_exit(dwc);
 633
 634         return 0;
 635 }
 636
 637 #ifdef CONFIG_PM_SLEEP
 638 static int dwc3_prepare(struct device *dev)
 639 {
 640         struct dwc3     *dwc = dev_get_drvdata(dev);
 641         unsigned long   flags;
 642
 643         spin_lock_irqsave(&dwc->lock, flags);
 644
 645         switch (dwc->mode) {
 646         case DWC3_MODE_DEVICE:
 647         case DWC3_MODE_DRD:
 648                 dwc3_gadget_prepare(dwc);
 649                 /* FALLTHROUGH */
 650         case DWC3_MODE_HOST:
 651         default:
 652                 dwc3_event_buffers_cleanup(dwc);
 653                 break;
 654         }
 655
 656         spin_unlock_irqrestore(&dwc->lock, flags);
 657
 658         return 0;
 659 }
 660
 661 static void dwc3_complete(struct device *dev)
 662 {
 663         struct dwc3     *dwc = dev_get_drvdata(dev);
 664         unsigned long   flags;
 665
 666         spin_lock_irqsave(&dwc->lock, flags);
 667
 668         switch (dwc->mode) {
 669         case DWC3_MODE_DEVICE:
 670         case DWC3_MODE_DRD:
 671                 dwc3_gadget_complete(dwc);
 672                 /* FALLTHROUGH */
 673         case DWC3_MODE_HOST:
 674         default:
 675                 dwc3_event_buffers_setup(dwc);
 676                 break;
 677         }
 678
 679         spin_unlock_irqrestore(&dwc->lock, flags);
 680 }
 681
 682 static int dwc3_suspend(struct device *dev)
 683 {
 684         struct dwc3     *dwc = dev_get_drvdata(dev);
 685         unsigned long   flags;
 686
 687         spin_lock_irqsave(&dwc->lock, flags);
 688
 689         switch (dwc->mode) {
 690         case DWC3_MODE_DEVICE:
 691         case DWC3_MODE_DRD:
 692                 dwc3_gadget_suspend(dwc);
 693                 /* FALLTHROUGH */
 694         case DWC3_MODE_HOST:
 695         default:
 696                 /* do nothing */
 697                 break;
 698         }
 699
 700         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 701         spin_unlock_irqrestore(&dwc->lock, flags);
 702
 703         usb_phy_shutdown(dwc->usb3_phy);
 704         usb_phy_shutdown(dwc->usb2_phy);
 705
 706         return 0;
 707 }
 708
 709 static int dwc3_resume(struct device *dev)
 710 {
 711         struct dwc3     *dwc = dev_get_drvdata(dev);
 712         unsigned long   flags;
 713
 714         usb_phy_init(dwc->usb3_phy);
 715         usb_phy_init(dwc->usb2_phy);
 716         msleep(100);
 717
 718         spin_lock_irqsave(&dwc->lock, flags);
 719
 720         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 721
 722         switch (dwc->mode) {
 723         case DWC3_MODE_DEVICE:
 724         case DWC3_MODE_DRD:
 725                 dwc3_gadget_resume(dwc);
 726                 /* FALLTHROUGH */
 727         case DWC3_MODE_HOST:
 728         default:
 729                 /* do nothing */
 730                 break;
 731         }
 732
 733         spin_unlock_irqrestore(&dwc->lock, flags);
 734
 735         pm_runtime_disable(dev);
 736         pm_runtime_set_active(dev);
 737         pm_runtime_enable(dev);
 738
 739         return 0;
 740 }
 741
 742 static const struct dev_pm_ops dwc3_dev_pm_ops = {
 743         .prepare        = dwc3_prepare,
 744         .complete       = dwc3_complete,
 745
 746         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
 747 };
 748
 749 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
 750 #else
 751 #define DWC3_PM_OPS     NULL
 752 #endif
 753
 754 #ifdef CONFIG_OF
 755 static const struct of_device_id of_dwc3_match[] = {
 756         {
 757                 .compatible = "synopsys,dwc3"
 758         },
 759         { },
 760 };
 761 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 762 #endif
 763
 764 static struct platform_driver dwc3_driver = {
 765         .probe          = dwc3_probe,
 766         .remove         = dwc3_remove,
 767         .driver         = {
 768                 .name   = "dwc3",
 769                 .of_match_table = of_match_ptr(of_dwc3_match),
 770                 .pm     = DWC3_PM_OPS,
 771         },
 772 };
 773
 774 module_platform_driver(dwc3_driver);
 775
 776 MODULE_ALIAS("platform:dwc3");
 777 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 778 MODULE_LICENSE("Dual BSD/GPL");
 779 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");