drivers/usb/dwc3/core.h

   1 /**
   2  * core.h - DesignWare USB3 DRD Core Header
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef __DRIVERS_USB_DWC3_CORE_H
  40 #define __DRIVERS_USB_DWC3_CORE_H
  41
  42 #include <linux/device.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/ioport.h>
  45 #include <linux/list.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/mm.h>
  48 #include <linux/debugfs.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 /* Global constants */
  54 #define DWC3_EP0_BOUNCE_SIZE    512
  55 #define DWC3_ENDPOINTS_NUM      32
  56 #define DWC3_XHCI_RESOURCES_NUM 2
  57
  58 #define DWC3_EVENT_SIZE         4       /* bytes */
  59 #define DWC3_EVENT_MAX_NUM      64      /* 2 events/endpoint */
  60 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
  61 #define DWC3_EVENT_TYPE_MASK    0xfe
  62
  63 #define DWC3_EVENT_TYPE_DEV     0
  64 #define DWC3_EVENT_TYPE_CARKIT  3
  65 #define DWC3_EVENT_TYPE_I2C     4
  66
  67 #define DWC3_DEVICE_EVENT_DISCONNECT            0
  68 #define DWC3_DEVICE_EVENT_RESET                 1
  69 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
  70 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
  71 #define DWC3_DEVICE_EVENT_WAKEUP                4
  72 #define DWC3_DEVICE_EVENT_HIBER_REQ             5
  73 #define DWC3_DEVICE_EVENT_EOPF                  6
  74 #define DWC3_DEVICE_EVENT_SOF                   7
  75 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
  76 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
  77 #define DWC3_DEVICE_EVENT_OVERFLOW              11
  78
  79 #define DWC3_GEVNTCOUNT_MASK    0xfffc
  80 #define DWC3_GSNPSID_MASK       0xffff0000
  81 #define DWC3_GSNPSREV_MASK      0xffff
  82
  83 /* DWC3 registers memory space boundries */
  84 #define DWC3_XHCI_REGS_START            0x0
  85 #define DWC3_XHCI_REGS_END              0x7fff
  86 #define DWC3_GLOBALS_REGS_START         0xc100
  87 #define DWC3_GLOBALS_REGS_END           0xc6ff
  88 #define DWC3_DEVICE_REGS_START          0xc700
  89 #define DWC3_DEVICE_REGS_END            0xcbff
  90 #define DWC3_OTG_REGS_START             0xcc00
  91 #define DWC3_OTG_REGS_END               0xccff
  92
  93 /* Global Registers */
  94 #define DWC3_GSBUSCFG0          0xc100
  95 #define DWC3_GSBUSCFG1          0xc104
  96 #define DWC3_GTXTHRCFG          0xc108
  97 #define DWC3_GRXTHRCFG          0xc10c
  98 #define DWC3_GCTL               0xc110
  99 #define DWC3_GEVTEN             0xc114
 100 #define DWC3_GSTS               0xc118
 101 #define DWC3_GSNPSID            0xc120
 102 #define DWC3_GGPIO              0xc124
 103 #define DWC3_GUID               0xc128
 104 #define DWC3_GUCTL              0xc12c
 105 #define DWC3_GBUSERRADDR0       0xc130
 106 #define DWC3_GBUSERRADDR1       0xc134
 107 #define DWC3_GPRTBIMAP0         0xc138
 108 #define DWC3_GPRTBIMAP1         0xc13c
 109 #define DWC3_GHWPARAMS0         0xc140
 110 #define DWC3_GHWPARAMS1         0xc144
 111 #define DWC3_GHWPARAMS2         0xc148
 112 #define DWC3_GHWPARAMS3         0xc14c
 113 #define DWC3_GHWPARAMS4         0xc150
 114 #define DWC3_GHWPARAMS5         0xc154
 115 #define DWC3_GHWPARAMS6         0xc158
 116 #define DWC3_GHWPARAMS7         0xc15c
 117 #define DWC3_GDBGFIFOSPACE      0xc160
 118 #define DWC3_GDBGLTSSM          0xc164
 119 #define DWC3_GPRTBIMAP_HS0      0xc180
 120 #define DWC3_GPRTBIMAP_HS1      0xc184
 121 #define DWC3_GPRTBIMAP_FS0      0xc188
 122 #define DWC3_GPRTBIMAP_FS1      0xc18c
 123
 124 #define DWC3_GUSB2PHYCFG(n)     (0xc200 + (n * 0x04))
 125 #define DWC3_GUSB2I2CCTL(n)     (0xc240 + (n * 0x04))
 126
 127 #define DWC3_GUSB2PHYACC(n)     (0xc280 + (n * 0x04))
 128
 129 #define DWC3_GUSB3PIPECTL(n)    (0xc2c0 + (n * 0x04))
 130
 131 #define DWC3_GTXFIFOSIZ(n)      (0xc300 + (n * 0x04))
 132 #define DWC3_GRXFIFOSIZ(n)      (0xc380 + (n * 0x04))
 133
 134 #define DWC3_GEVNTADRLO(n)      (0xc400 + (n * 0x10))
 135 #define DWC3_GEVNTADRHI(n)      (0xc404 + (n * 0x10))
 136 #define DWC3_GEVNTSIZ(n)        (0xc408 + (n * 0x10))
 137 #define DWC3_GEVNTCOUNT(n)      (0xc40c + (n * 0x10))
 138
 139 #define DWC3_GHWPARAMS8         0xc600
 140
 141 /* Device Registers */
 142 #define DWC3_DCFG               0xc700
 143 #define DWC3_DCTL               0xc704
 144 #define DWC3_DEVTEN             0xc708
 145 #define DWC3_DSTS               0xc70c
 146 #define DWC3_DGCMDPAR           0xc710
 147 #define DWC3_DGCMD              0xc714
 148 #define DWC3_DALEPENA           0xc720
 149 #define DWC3_DEPCMDPAR2(n)      (0xc800 + (n * 0x10))
 150 #define DWC3_DEPCMDPAR1(n)      (0xc804 + (n * 0x10))
 151 #define DWC3_DEPCMDPAR0(n)      (0xc808 + (n * 0x10))
 152 #define DWC3_DEPCMD(n)          (0xc80c + (n * 0x10))
 153
 154 /* OTG Registers */
 155 #define DWC3_OCFG               0xcc00
 156 #define DWC3_OCTL               0xcc04
 157 #define DWC3_OEVTEN             0xcc08
 158 #define DWC3_OSTS               0xcc0C
 159
 160 /* Bit fields */
 161
 162 /* Global Configuration Register */
 163 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
 164 #define DWC3_GCTL_U2RSTECN      (1 << 16)
 165 #define DWC3_GCTL_RAMCLKSEL(x)  (((x) & DWC3_GCTL_CLK_MASK) << 6)
 166 #define DWC3_GCTL_CLK_BUS       (0)
 167 #define DWC3_GCTL_CLK_PIPE      (1)
 168 #define DWC3_GCTL_CLK_PIPEHALF  (2)
 169 #define DWC3_GCTL_CLK_MASK      (3)
 170
 171 #define DWC3_GCTL_PRTCAP(n)     (((n) & (3 << 12)) >> 12)
 172 #define DWC3_GCTL_PRTCAPDIR(n)  ((n) << 12)
 173 #define DWC3_GCTL_PRTCAP_HOST   1
 174 #define DWC3_GCTL_PRTCAP_DEVICE 2
 175 #define DWC3_GCTL_PRTCAP_OTG    3
 176
 177 #define DWC3_GCTL_CORESOFTRESET         (1 << 11)
 178 #define DWC3_GCTL_SCALEDOWN(n)          ((n) << 4)
 179 #define DWC3_GCTL_SCALEDOWN_MASK        DWC3_GCTL_SCALEDOWN(3)
 180 #define DWC3_GCTL_DISSCRAMBLE           (1 << 3)
 181 #define DWC3_GCTL_GBLHIBERNATIONEN      (1 << 1)
 182 #define DWC3_GCTL_DSBLCLKGTNG           (1 << 0)
 183
 184 /* Global USB2 PHY Configuration Register */
 185 #define DWC3_GUSB2PHYCFG_PHYSOFTRST     (1 << 31)
 186 #define DWC3_GUSB2PHYCFG_SUSPHY         (1 << 6)
 187
 188 /* Global USB3 PIPE Control Register */
 189 #define DWC3_GUSB3PIPECTL_PHYSOFTRST    (1 << 31)
 190 #define DWC3_GUSB3PIPECTL_SUSPHY        (1 << 17)
 191
 192 /* Global TX Fifo Size Register */
 193 #define DWC3_GTXFIFOSIZ_TXFDEF(n)       ((n) & 0xffff)
 194 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)    ((n) & 0xffff0000)
 195
 196 /* Global HWPARAMS1 Register */
 197 #define DWC3_GHWPARAMS1_EN_PWROPT(n)    (((n) & (3 << 24)) >> 24)
 198 #define DWC3_GHWPARAMS1_EN_PWROPT_NO    0
 199 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK   1
 200 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB   2
 201 #define DWC3_GHWPARAMS1_PWROPT(n)       ((n) << 24)
 202 #define DWC3_GHWPARAMS1_PWROPT_MASK     DWC3_GHWPARAMS1_PWROPT(3)
 203
 204 /* Global HWPARAMS4 Register */
 205 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)    (((n) & (0x0f << 13)) >> 13)
 206 #define DWC3_MAX_HIBER_SCRATCHBUFS              15
 207
 208 /* Device Configuration Register */
 209 #define DWC3_DCFG_LPM_CAP       (1 << 22)
 210 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
 211 #define DWC3_DCFG_DEVADDR_MASK  DWC3_DCFG_DEVADDR(0x7f)
 212
 213 #define DWC3_DCFG_SPEED_MASK    (7 << 0)
 214 #define DWC3_DCFG_SUPERSPEED    (4 << 0)
 215 #define DWC3_DCFG_HIGHSPEED     (0 << 0)
 216 #define DWC3_DCFG_FULLSPEED2    (1 << 0)
 217 #define DWC3_DCFG_LOWSPEED      (2 << 0)
 218 #define DWC3_DCFG_FULLSPEED1    (3 << 0)
 219
 220 #define DWC3_DCFG_LPM_CAP       (1 << 22)
 221
 222 /* Device Control Register */
 223 #define DWC3_DCTL_RUN_STOP      (1 << 31)
 224 #define DWC3_DCTL_CSFTRST       (1 << 30)
 225 #define DWC3_DCTL_LSFTRST       (1 << 29)
 226
 227 #define DWC3_DCTL_HIRD_THRES_MASK       (0x1f << 24)
 228 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
 229
 230 #define DWC3_DCTL_APPL1RES      (1 << 23)
 231
 232 /* These apply for core versions 1.87a and earlier */
 233 #define DWC3_DCTL_TRGTULST_MASK         (0x0f << 17)
 234 #define DWC3_DCTL_TRGTULST(n)           ((n) << 17)
 235 #define DWC3_DCTL_TRGTULST_U2           (DWC3_DCTL_TRGTULST(2))
 236 #define DWC3_DCTL_TRGTULST_U3           (DWC3_DCTL_TRGTULST(3))
 237 #define DWC3_DCTL_TRGTULST_SS_DIS       (DWC3_DCTL_TRGTULST(4))
 238 #define DWC3_DCTL_TRGTULST_RX_DET       (DWC3_DCTL_TRGTULST(5))
 239 #define DWC3_DCTL_TRGTULST_SS_INACT     (DWC3_DCTL_TRGTULST(6))
 240
 241 /* These apply for core versions 1.94a and later */
 242 #define DWC3_DCTL_KEEP_CONNECT  (1 << 19)
 243 #define DWC3_DCTL_L1_HIBER_EN   (1 << 18)
 244 #define DWC3_DCTL_CRS           (1 << 17)
 245 #define DWC3_DCTL_CSS           (1 << 16)
 246
 247 #define DWC3_DCTL_INITU2ENA     (1 << 12)
 248 #define DWC3_DCTL_ACCEPTU2ENA   (1 << 11)
 249 #define DWC3_DCTL_INITU1ENA     (1 << 10)
 250 #define DWC3_DCTL_ACCEPTU1ENA   (1 << 9)
 251 #define DWC3_DCTL_TSTCTRL_MASK  (0xf << 1)
 252
 253 #define DWC3_DCTL_ULSTCHNGREQ_MASK      (0x0f << 5)
 254 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 255
 256 #define DWC3_DCTL_ULSTCHNG_NO_ACTION    (DWC3_DCTL_ULSTCHNGREQ(0))
 257 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED  (DWC3_DCTL_ULSTCHNGREQ(4))
 258 #define DWC3_DCTL_ULSTCHNG_RX_DETECT    (DWC3_DCTL_ULSTCHNGREQ(5))
 259 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE  (DWC3_DCTL_ULSTCHNGREQ(6))
 260 #define DWC3_DCTL_ULSTCHNG_RECOVERY     (DWC3_DCTL_ULSTCHNGREQ(8))
 261 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE   (DWC3_DCTL_ULSTCHNGREQ(10))
 262 #define DWC3_DCTL_ULSTCHNG_LOOPBACK     (DWC3_DCTL_ULSTCHNGREQ(11))
 263
 264 /* Device Event Enable Register */
 265 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN   (1 << 12)
 266 #define DWC3_DEVTEN_EVNTOVERFLOWEN      (1 << 11)
 267 #define DWC3_DEVTEN_CMDCMPLTEN          (1 << 10)
 268 #define DWC3_DEVTEN_ERRTICERREN         (1 << 9)
 269 #define DWC3_DEVTEN_SOFEN               (1 << 7)
 270 #define DWC3_DEVTEN_EOPFEN              (1 << 6)
 271 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
 272 #define DWC3_DEVTEN_WKUPEVTEN           (1 << 4)
 273 #define DWC3_DEVTEN_ULSTCNGEN           (1 << 3)
 274 #define DWC3_DEVTEN_CONNECTDONEEN       (1 << 2)
 275 #define DWC3_DEVTEN_USBRSTEN            (1 << 1)
 276 #define DWC3_DEVTEN_DISCONNEVTEN        (1 << 0)
 277
 278 /* Device Status Register */
 279 #define DWC3_DSTS_DCNRD                 (1 << 29)
 280
 281 /* This applies for core versions 1.87a and earlier */
 282 #define DWC3_DSTS_PWRUPREQ              (1 << 24)
 283
 284 /* These apply for core versions 1.94a and later */
 285 #define DWC3_DSTS_RSS                   (1 << 25)
 286 #define DWC3_DSTS_SSS                   (1 << 24)
 287
 288 #define DWC3_DSTS_COREIDLE              (1 << 23)
 289 #define DWC3_DSTS_DEVCTRLHLT            (1 << 22)
 290
 291 #define DWC3_DSTS_USBLNKST_MASK         (0x0f << 18)
 292 #define DWC3_DSTS_USBLNKST(n)           (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 293
 294 #define DWC3_DSTS_RXFIFOEMPTY           (1 << 17)
 295
 296 #define DWC3_DSTS_SOFFN_MASK            (0x3fff << 3)
 297 #define DWC3_DSTS_SOFFN(n)              (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 298
 299 #define DWC3_DSTS_CONNECTSPD            (7 << 0)
 300
 301 #define DWC3_DSTS_SUPERSPEED            (4 << 0)
 302 #define DWC3_DSTS_HIGHSPEED             (0 << 0)
 303 #define DWC3_DSTS_FULLSPEED2            (1 << 0)
 304 #define DWC3_DSTS_LOWSPEED              (2 << 0)
 305 #define DWC3_DSTS_FULLSPEED1            (3 << 0)
 306
 307 /* Device Generic Command Register */
 308 #define DWC3_DGCMD_SET_LMP              0x01
 309 #define DWC3_DGCMD_SET_PERIODIC_PAR     0x02
 310 #define DWC3_DGCMD_XMIT_FUNCTION        0x03
 311
 312 /* These apply for core versions 1.94a and later */
 313 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO       0x04
 314 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI       0x05
 315
 316 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH  0x09
 317 #define DWC3_DGCMD_ALL_FIFO_FLUSH       0x0a
 318 #define DWC3_DGCMD_SET_ENDPOINT_NRDY    0x0c
 319 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
 320
 321 #define DWC3_DGCMD_STATUS(n)            (((n) >> 15) & 1)
 322 #define DWC3_DGCMD_CMDACT               (1 << 10)
 323 #define DWC3_DGCMD_CMDIOC               (1 << 8)
 324
 325 /* Device Generic Command Parameter Register */
 326 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT       (1 << 0)
 327 #define DWC3_DGCMDPAR_FIFO_NUM(n)               ((n) << 0)
 328 #define DWC3_DGCMDPAR_RX_FIFO                   (0 << 5)
 329 #define DWC3_DGCMDPAR_TX_FIFO                   (1 << 5)
 330 #define DWC3_DGCMDPAR_LOOPBACK_DIS              (0 << 0)
 331 #define DWC3_DGCMDPAR_LOOPBACK_ENA              (1 << 0)
 332
 333 /* Device Endpoint Command Register */
 334 #define DWC3_DEPCMD_PARAM_SHIFT         16
 335 #define DWC3_DEPCMD_PARAM(x)            ((x) << DWC3_DEPCMD_PARAM_SHIFT)
 336 #define DWC3_DEPCMD_GET_RSC_IDX(x)     (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 337 #define DWC3_DEPCMD_STATUS(x)           (((x) >> 15) & 1)
 338 #define DWC3_DEPCMD_HIPRI_FORCERM       (1 << 11)
 339 #define DWC3_DEPCMD_CMDACT              (1 << 10)
 340 #define DWC3_DEPCMD_CMDIOC              (1 << 8)
 341
 342 #define DWC3_DEPCMD_DEPSTARTCFG         (0x09 << 0)
 343 #define DWC3_DEPCMD_ENDTRANSFER         (0x08 << 0)
 344 #define DWC3_DEPCMD_UPDATETRANSFER      (0x07 << 0)
 345 #define DWC3_DEPCMD_STARTTRANSFER       (0x06 << 0)
 346 #define DWC3_DEPCMD_CLEARSTALL          (0x05 << 0)
 347 #define DWC3_DEPCMD_SETSTALL            (0x04 << 0)
 348 /* This applies for core versions 1.90a and earlier */
 349 #define DWC3_DEPCMD_GETSEQNUMBER        (0x03 << 0)
 350 /* This applies for core versions 1.94a and later */
 351 #define DWC3_DEPCMD_GETEPSTATE          (0x03 << 0)
 352 #define DWC3_DEPCMD_SETTRANSFRESOURCE   (0x02 << 0)
 353 #define DWC3_DEPCMD_SETEPCONFIG         (0x01 << 0)
 354
 355 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 356 #define DWC3_DALEPENA_EP(n)             (1 << n)
 357
 358 #define DWC3_DEPCMD_TYPE_CONTROL        0
 359 #define DWC3_DEPCMD_TYPE_ISOC           1
 360 #define DWC3_DEPCMD_TYPE_BULK           2
 361 #define DWC3_DEPCMD_TYPE_INTR           3
 362
 363 /* Structures */
 364
 365 struct dwc3_trb;
 366
 367 /**
 368  * struct dwc3_event_buffer - Software event buffer representation
 369  * @list: a list of event buffers
 370  * @buf: _THE_ buffer
 371  * @length: size of this buffer
 372  * @lpos: event offset
 373  * @count: cache of last read event count register
 374  * @flags: flags related to this event buffer
 375  * @dma: dma_addr_t
 376  * @dwc: pointer to DWC controller
 377  */
 378 struct dwc3_event_buffer {
 379         void                    *buf;
 380         unsigned                length;
 381         unsigned int            lpos;
 382         unsigned int            count;
 383         unsigned int            flags;
 384
 385 #define DWC3_EVENT_PENDING      BIT(0)
 386
 387         dma_addr_t              dma;
 388
 389         struct dwc3             *dwc;
 390 };
 391
 392 #define DWC3_EP_FLAG_STALLED    (1 << 0)
 393 #define DWC3_EP_FLAG_WEDGED     (1 << 1)
 394
 395 #define DWC3_EP_DIRECTION_TX    true
 396 #define DWC3_EP_DIRECTION_RX    false
 397
 398 #define DWC3_TRB_NUM            32
 399 #define DWC3_TRB_MASK           (DWC3_TRB_NUM - 1)
 400
 401 /**
 402  * struct dwc3_ep - device side endpoint representation
 403  * @endpoint: usb endpoint
 404  * @request_list: list of requests for this endpoint
 405  * @req_queued: list of requests on this ep which have TRBs setup
 406  * @trb_pool: array of transaction buffers
 407  * @trb_pool_dma: dma address of @trb_pool
 408  * @free_slot: next slot which is going to be used
 409  * @busy_slot: first slot which is owned by HW
 410  * @desc: usb_endpoint_descriptor pointer
 411  * @dwc: pointer to DWC controller
 412  * @flags: endpoint flags (wedged, stalled, ...)
 413  * @current_trb: index of current used trb
 414  * @number: endpoint number (1 - 15)
 415  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 416  * @resource_index: Resource transfer index
 417  * @interval: the intervall on which the ISOC transfer is started
 418  * @name: a human readable name e.g. ep1out-bulk
 419  * @direction: true for TX, false for RX
 420  * @stream_capable: true when streams are enabled
 421  */
 422 struct dwc3_ep {
 423         struct usb_ep           endpoint;
 424         struct list_head        request_list;
 425         struct list_head        req_queued;
 426
 427         struct dwc3_trb         *trb_pool;
 428         dma_addr_t              trb_pool_dma;
 429         u32                     free_slot;
 430         u32                     busy_slot;
 431         const struct usb_ss_ep_comp_descriptor *comp_desc;
 432         struct dwc3             *dwc;
 433
 434         unsigned                flags;
 435 #define DWC3_EP_ENABLED         (1 << 0)
 436 #define DWC3_EP_STALL           (1 << 1)
 437 #define DWC3_EP_WEDGE           (1 << 2)
 438 #define DWC3_EP_BUSY            (1 << 4)
 439 #define DWC3_EP_PENDING_REQUEST (1 << 5)
 440 #define DWC3_EP_MISSED_ISOC     (1 << 6)
 441
 442         /* This last one is specific to EP0 */
 443 #define DWC3_EP0_DIR_IN         (1 << 31)
 444
 445         unsigned                current_trb;
 446
 447         u8                      number;
 448         u8                      type;
 449         u8                      resource_index;
 450         u32                     interval;
 451
 452         char                    name[20];
 453
 454         unsigned                direction:1;
 455         unsigned                stream_capable:1;
 456 };
 457
 458 enum dwc3_phy {
 459         DWC3_PHY_UNKNOWN = 0,
 460         DWC3_PHY_USB3,
 461         DWC3_PHY_USB2,
 462 };
 463
 464 enum dwc3_ep0_next {
 465         DWC3_EP0_UNKNOWN = 0,
 466         DWC3_EP0_COMPLETE,
 467         DWC3_EP0_NRDY_DATA,
 468         DWC3_EP0_NRDY_STATUS,
 469 };
 470
 471 enum dwc3_ep0_state {
 472         EP0_UNCONNECTED         = 0,
 473         EP0_SETUP_PHASE,
 474         EP0_DATA_PHASE,
 475         EP0_STATUS_PHASE,
 476 };
 477
 478 enum dwc3_link_state {
 479         /* In SuperSpeed */
 480         DWC3_LINK_STATE_U0              = 0x00, /* in HS, means ON */
 481         DWC3_LINK_STATE_U1              = 0x01,
 482         DWC3_LINK_STATE_U2              = 0x02, /* in HS, means SLEEP */
 483         DWC3_LINK_STATE_U3              = 0x03, /* in HS, means SUSPEND */
 484         DWC3_LINK_STATE_SS_DIS          = 0x04,
 485         DWC3_LINK_STATE_RX_DET          = 0x05, /* in HS, means Early Suspend */
 486         DWC3_LINK_STATE_SS_INACT        = 0x06,
 487         DWC3_LINK_STATE_POLL            = 0x07,
 488         DWC3_LINK_STATE_RECOV           = 0x08,
 489         DWC3_LINK_STATE_HRESET          = 0x09,
 490         DWC3_LINK_STATE_CMPLY           = 0x0a,
 491         DWC3_LINK_STATE_LPBK            = 0x0b,
 492         DWC3_LINK_STATE_RESET           = 0x0e,
 493         DWC3_LINK_STATE_RESUME          = 0x0f,
 494         DWC3_LINK_STATE_MASK            = 0x0f,
 495 };
 496
 497 /* TRB Length, PCM and Status */
 498 #define DWC3_TRB_SIZE_MASK      (0x00ffffff)
 499 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
 500 #define DWC3_TRB_SIZE_PCM1(n)   (((n) & 0x03) << 24)
 501 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
 502
 503 #define DWC3_TRBSTS_OK                  0
 504 #define DWC3_TRBSTS_MISSED_ISOC         1
 505 #define DWC3_TRBSTS_SETUP_PENDING       2
 506 #define DWC3_TRB_STS_XFER_IN_PROG       4
 507
 508 /* TRB Control */
 509 #define DWC3_TRB_CTRL_HWO               (1 << 0)
 510 #define DWC3_TRB_CTRL_LST               (1 << 1)
 511 #define DWC3_TRB_CTRL_CHN               (1 << 2)
 512 #define DWC3_TRB_CTRL_CSP               (1 << 3)
 513 #define DWC3_TRB_CTRL_TRBCTL(n)         (((n) & 0x3f) << 4)
 514 #define DWC3_TRB_CTRL_ISP_IMI           (1 << 10)
 515 #define DWC3_TRB_CTRL_IOC               (1 << 11)
 516 #define DWC3_TRB_CTRL_SID_SOFN(n)       (((n) & 0xffff) << 14)
 517
 518 #define DWC3_TRBCTL_NORMAL              DWC3_TRB_CTRL_TRBCTL(1)
 519 #define DWC3_TRBCTL_CONTROL_SETUP       DWC3_TRB_CTRL_TRBCTL(2)
 520 #define DWC3_TRBCTL_CONTROL_STATUS2     DWC3_TRB_CTRL_TRBCTL(3)
 521 #define DWC3_TRBCTL_CONTROL_STATUS3     DWC3_TRB_CTRL_TRBCTL(4)
 522 #define DWC3_TRBCTL_CONTROL_DATA        DWC3_TRB_CTRL_TRBCTL(5)
 523 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST   DWC3_TRB_CTRL_TRBCTL(6)
 524 #define DWC3_TRBCTL_ISOCHRONOUS         DWC3_TRB_CTRL_TRBCTL(7)
 525 #define DWC3_TRBCTL_LINK_TRB            DWC3_TRB_CTRL_TRBCTL(8)
 526
 527 /**
 528  * struct dwc3_trb - transfer request block (hw format)
 529  * @bpl: DW0-3
 530  * @bph: DW4-7
 531  * @size: DW8-B
 532  * @trl: DWC-F
 533  */
 534 struct dwc3_trb {
 535         u32             bpl;
 536         u32             bph;
 537         u32             size;
 538         u32             ctrl;
 539 } __packed;
 540
 541 /**
 542  * dwc3_hwparams - copy of HWPARAMS registers
 543  * @hwparams0 - GHWPARAMS0
 544  * @hwparams1 - GHWPARAMS1
 545  * @hwparams2 - GHWPARAMS2
 546  * @hwparams3 - GHWPARAMS3
 547  * @hwparams4 - GHWPARAMS4
 548  * @hwparams5 - GHWPARAMS5
 549  * @hwparams6 - GHWPARAMS6
 550  * @hwparams7 - GHWPARAMS7
 551  * @hwparams8 - GHWPARAMS8
 552  */
 553 struct dwc3_hwparams {
 554         u32     hwparams0;
 555         u32     hwparams1;
 556         u32     hwparams2;
 557         u32     hwparams3;
 558         u32     hwparams4;
 559         u32     hwparams5;
 560         u32     hwparams6;
 561         u32     hwparams7;
 562         u32     hwparams8;
 563 };
 564
 565 /* HWPARAMS0 */
 566 #define DWC3_MODE(n)            ((n) & 0x7)
 567
 568 #define DWC3_MODE_DEVICE        0
 569 #define DWC3_MODE_HOST          1
 570 #define DWC3_MODE_DRD           2
 571 #define DWC3_MODE_HUB           3
 572
 573 #define DWC3_MDWIDTH(n)         (((n) & 0xff00) >> 8)
 574
 575 /* HWPARAMS1 */
 576 #define DWC3_NUM_INT(n)         (((n) & (0x3f << 15)) >> 15)
 577
 578 /* HWPARAMS7 */
 579 #define DWC3_RAM1_DEPTH(n)      ((n) & 0xffff)
 580
 581 struct dwc3_request {
 582         struct usb_request      request;
 583         struct list_head        list;
 584         struct dwc3_ep          *dep;
 585         u32                     start_slot;
 586
 587         u8                      epnum;
 588         struct dwc3_trb         *trb;
 589         dma_addr_t              trb_dma;
 590
 591         unsigned                direction:1;
 592         unsigned                mapped:1;
 593         unsigned                queued:1;
 594 };
 595
 596 /*
 597  * struct dwc3_scratchpad_array - hibernation scratchpad array
 598  * (format defined by hw)
 599  */
 600 struct dwc3_scratchpad_array {
 601         __le64  dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
 602 };
 603
 604 /**
 605  * struct dwc3 - representation of our controller
 606  * @ctrl_req: usb control request which is used for ep0
 607  * @ep0_trb: trb which is used for the ctrl_req
 608  * @ep0_bounce: bounce buffer for ep0
 609  * @setup_buf: used while precessing STD USB requests
 610  * @ctrl_req_addr: dma address of ctrl_req
 611  * @ep0_trb: dma address of ep0_trb
 612  * @ep0_usb_req: dummy req used while handling STD USB requests
 613  * @ep0_bounce_addr: dma address of ep0_bounce
 614  * @lock: for synchronizing
 615  * @dev: pointer to our struct device
 616  * @xhci: pointer to our xHCI child
 617  * @event_buffer_list: a list of event buffers
 618  * @gadget: device side representation of the peripheral controller
 619  * @gadget_driver: pointer to the gadget driver
 620  * @regs: base address for our registers
 621  * @regs_size: address space size
 622  * @num_event_buffers: calculated number of event buffers
 623  * @u1u2: only used on revisions <1.83a for workaround
 624  * @maximum_speed: maximum speed requested (mainly for testing purposes)
 625  * @revision: revision register contents
 626  * @mode: mode of operation
 627  * @usb2_phy: pointer to USB2 PHY
 628  * @usb3_phy: pointer to USB3 PHY
 629  * @dcfg: saved contents of DCFG register
 630  * @gctl: saved contents of GCTL register
 631  * @is_selfpowered: true when we are selfpowered
 632  * @three_stage_setup: set if we perform a three phase setup
 633  * @ep0_bounced: true when we used bounce buffer
 634  * @ep0_expect_in: true when we expect a DATA IN transfer
 635  * @start_config_issued: true when StartConfig command has been issued
 636  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
 637  * @needs_fifo_resize: not all users might want fifo resizing, flag it
 638  * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
 639  * @isoch_delay: wValue from Set Isochronous Delay request;
 640  * @u2sel: parameter from Set SEL request.
 641  * @u2pel: parameter from Set SEL request.
 642  * @u1sel: parameter from Set SEL request.
 643  * @u1pel: parameter from Set SEL request.
 644  * @ep0_next_event: hold the next expected event
 645  * @ep0state: state of endpoint zero
 646  * @link_state: link state
 647  * @speed: device speed (super, high, full, low)
 648  * @mem: points to start of memory which is used for this struct.
 649  * @hwparams: copy of hwparams registers
 650  * @root: debugfs root folder pointer
 651  */
 652 struct dwc3 {
 653         struct usb_ctrlrequest  *ctrl_req;
 654         struct dwc3_trb         *ep0_trb;
 655         void                    *ep0_bounce;
 656         u8                      *setup_buf;
 657         dma_addr_t              ctrl_req_addr;
 658         dma_addr_t              ep0_trb_addr;
 659         dma_addr_t              ep0_bounce_addr;
 660         struct dwc3_request     ep0_usb_req;
 661         /* device lock */
 662         spinlock_t              lock;
 663         struct device           *dev;
 664
 665         struct platform_device  *xhci;
 666         struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
 667
 668         struct dwc3_event_buffer **ev_buffs;
 669         struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
 670
 671         struct usb_gadget       gadget;
 672         struct usb_gadget_driver *gadget_driver;
 673
 674         struct usb_phy          *usb2_phy;
 675         struct usb_phy          *usb3_phy;
 676
 677         void __iomem            *regs;
 678         size_t                  regs_size;
 679
 680         /* used for suspend/resume */
 681         u32                     dcfg;
 682         u32                     gctl;
 683
 684         u32                     num_event_buffers;
 685         u32                     u1u2;
 686         u32                     maximum_speed;
 687         u32                     revision;
 688         u32                     mode;
 689
 690 #define DWC3_REVISION_173A      0x5533173a
 691 #define DWC3_REVISION_175A      0x5533175a
 692 #define DWC3_REVISION_180A      0x5533180a
 693 #define DWC3_REVISION_183A      0x5533183a
 694 #define DWC3_REVISION_185A      0x5533185a
 695 #define DWC3_REVISION_187A      0x5533187a
 696 #define DWC3_REVISION_188A      0x5533188a
 697 #define DWC3_REVISION_190A      0x5533190a
 698 #define DWC3_REVISION_194A      0x5533194a
 699 #define DWC3_REVISION_200A      0x5533200a
 700 #define DWC3_REVISION_202A      0x5533202a
 701 #define DWC3_REVISION_210A      0x5533210a
 702 #define DWC3_REVISION_220A      0x5533220a
 703 #define DWC3_REVISION_230A      0x5533230a
 704 #define DWC3_REVISION_240A      0x5533240a
 705 #define DWC3_REVISION_250A      0x5533250a
 706
 707         unsigned                is_selfpowered:1;
 708         unsigned                three_stage_setup:1;
 709         unsigned                ep0_bounced:1;
 710         unsigned                ep0_expect_in:1;
 711         unsigned                start_config_issued:1;
 712         unsigned                setup_packet_pending:1;
 713         unsigned                delayed_status:1;
 714         unsigned                needs_fifo_resize:1;
 715         unsigned                resize_fifos:1;
 716         unsigned                pullups_connected:1;
 717
 718         enum dwc3_ep0_next      ep0_next_event;
 719         enum dwc3_ep0_state     ep0state;
 720         enum dwc3_link_state    link_state;
 721
 722         u16                     isoch_delay;
 723         u16                     u2sel;
 724         u16                     u2pel;
 725         u8                      u1sel;
 726         u8                      u1pel;
 727
 728         u8                      speed;
 729
 730         void                    *mem;
 731
 732         struct dwc3_hwparams    hwparams;
 733         struct dentry           *root;
 734         struct debugfs_regset32 *regset;
 735
 736         u8                      test_mode;
 737         u8                      test_mode_nr;
 738 };
 739
 740 /* -------------------------------------------------------------------------- */
 741
 742 /* -------------------------------------------------------------------------- */
 743
 744 struct dwc3_event_type {
 745         u32     is_devspec:1;
 746         u32     type:6;
 747         u32     reserved8_31:25;
 748 } __packed;
 749
 750 #define DWC3_DEPEVT_XFERCOMPLETE        0x01
 751 #define DWC3_DEPEVT_XFERINPROGRESS      0x02
 752 #define DWC3_DEPEVT_XFERNOTREADY        0x03
 753 #define DWC3_DEPEVT_RXTXFIFOEVT         0x04
 754 #define DWC3_DEPEVT_STREAMEVT           0x06
 755 #define DWC3_DEPEVT_EPCMDCMPLT          0x07
 756
 757 /**
 758  * struct dwc3_event_depvt - Device Endpoint Events
 759  * @one_bit: indicates this is an endpoint event (not used)
 760  * @endpoint_number: number of the endpoint
 761  * @endpoint_event: The event we have:
 762  *      0x00    - Reserved
 763  *      0x01    - XferComplete
 764  *      0x02    - XferInProgress
 765  *      0x03    - XferNotReady
 766  *      0x04    - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
 767  *      0x05    - Reserved
 768  *      0x06    - StreamEvt
 769  *      0x07    - EPCmdCmplt
 770  * @reserved11_10: Reserved, don't use.
 771  * @status: Indicates the status of the event. Refer to databook for
 772  *      more information.
 773  * @parameters: Parameters of the current event. Refer to databook for
 774  *      more information.
 775  */
 776 struct dwc3_event_depevt {
 777         u32     one_bit:1;
 778         u32     endpoint_number:5;
 779         u32     endpoint_event:4;
 780         u32     reserved11_10:2;
 781         u32     status:4;
 782
 783 /* Within XferNotReady */
 784 #define DEPEVT_STATUS_TRANSFER_ACTIVE   (1 << 3)
 785
 786 /* Within XferComplete */
 787 #define DEPEVT_STATUS_BUSERR    (1 << 0)
 788 #define DEPEVT_STATUS_SHORT     (1 << 1)
 789 #define DEPEVT_STATUS_IOC       (1 << 2)
 790 #define DEPEVT_STATUS_LST       (1 << 3)
 791
 792 /* Stream event only */
 793 #define DEPEVT_STREAMEVT_FOUND          1
 794 #define DEPEVT_STREAMEVT_NOTFOUND       2
 795
 796 /* Control-only Status */
 797 #define DEPEVT_STATUS_CONTROL_DATA      1
 798 #define DEPEVT_STATUS_CONTROL_STATUS    2
 799
 800         u32     parameters:16;
 801 } __packed;
 802
 803 /**
 804  * struct dwc3_event_devt - Device Events
 805  * @one_bit: indicates this is a non-endpoint event (not used)
 806  * @device_event: indicates it's a device event. Should read as 0x00
 807  * @type: indicates the type of device event.
 808  *      0       - DisconnEvt
 809  *      1       - USBRst
 810  *      2       - ConnectDone
 811  *      3       - ULStChng
 812  *      4       - WkUpEvt
 813  *      5       - Reserved
 814  *      6       - EOPF
 815  *      7       - SOF
 816  *      8       - Reserved
 817  *      9       - ErrticErr
 818  *      10      - CmdCmplt
 819  *      11      - EvntOverflow
 820  *      12      - VndrDevTstRcved
 821  * @reserved15_12: Reserved, not used
 822  * @event_info: Information about this event
 823  * @reserved31_24: Reserved, not used
 824  */
 825 struct dwc3_event_devt {
 826         u32     one_bit:1;
 827         u32     device_event:7;
 828         u32     type:4;
 829         u32     reserved15_12:4;
 830         u32     event_info:8;
 831         u32     reserved31_24:8;
 832 } __packed;
 833
 834 /**
 835  * struct dwc3_event_gevt - Other Core Events
 836  * @one_bit: indicates this is a non-endpoint event (not used)
 837  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
 838  * @phy_port_number: self-explanatory
 839  * @reserved31_12: Reserved, not used.
 840  */
 841 struct dwc3_event_gevt {
 842         u32     one_bit:1;
 843         u32     device_event:7;
 844         u32     phy_port_number:4;
 845         u32     reserved31_12:20;
 846 } __packed;
 847
 848 /**
 849  * union dwc3_event - representation of Event Buffer contents
 850  * @raw: raw 32-bit event
 851  * @type: the type of the event
 852  * @depevt: Device Endpoint Event
 853  * @devt: Device Event
 854  * @gevt: Global Event
 855  */
 856 union dwc3_event {
 857         u32                             raw;
 858         struct dwc3_event_type          type;
 859         struct dwc3_event_depevt        depevt;
 860         struct dwc3_event_devt          devt;
 861         struct dwc3_event_gevt          gevt;
 862 };
 863
 864 /*
 865  * DWC3 Features to be used as Driver Data
 866  */
 867
 868 #define DWC3_HAS_PERIPHERAL             BIT(0)
 869 #define DWC3_HAS_XHCI                   BIT(1)
 870 #define DWC3_HAS_OTG                    BIT(3)
 871
 872 /* prototypes */
 873 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
 874 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
 875
 876 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
 877 int dwc3_host_init(struct dwc3 *dwc);
 878 void dwc3_host_exit(struct dwc3 *dwc);
 879 #else
 880 static inline int dwc3_host_init(struct dwc3 *dwc)
 881 { return 0; }
 882 static inline void dwc3_host_exit(struct dwc3 *dwc)
 883 { }
 884 #endif
 885
 886 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
 887 int dwc3_gadget_init(struct dwc3 *dwc);
 888 void dwc3_gadget_exit(struct dwc3 *dwc);
 889 #else
 890 static inline int dwc3_gadget_init(struct dwc3 *dwc)
 891 { return 0; }
 892 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
 893 { }
 894 #endif
 895
 896 /* power management interface */
 897 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
 898 int dwc3_gadget_prepare(struct dwc3 *dwc);
 899 void dwc3_gadget_complete(struct dwc3 *dwc);
 900 int dwc3_gadget_suspend(struct dwc3 *dwc);
 901 int dwc3_gadget_resume(struct dwc3 *dwc);
 902 #else
 903 static inline int dwc3_gadget_prepare(struct dwc3 *dwc)
 904 {
 905         return 0;
 906 }
 907
 908 static inline void dwc3_gadget_complete(struct dwc3 *dwc)
 909 {
 910 }
 911
 912 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
 913 {
 914         return 0;
 915 }
 916
 917 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
 918 {
 919         return 0;
 920 }
 921 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
 922
 923 #endif /* __DRIVERS_USB_DWC3_CORE_H */