drivers/usb/dwc3/core.h

   1 /**
   2  * core.h - DesignWare USB3 DRD Core Header
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef __DRIVERS_USB_DWC3_CORE_H
  20 #define __DRIVERS_USB_DWC3_CORE_H
  21
  22 #include <linux/device.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/ioport.h>
  25 #include <linux/list.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/mm.h>
  28 #include <linux/debugfs.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/otg.h>
  33
  34 /* Global constants */
  35 #define DWC3_EP0_BOUNCE_SIZE    512
  36 #define DWC3_ENDPOINTS_NUM      32
  37 #define DWC3_XHCI_RESOURCES_NUM 2
  38
  39 #define DWC3_EVENT_SIZE         4       /* bytes */
  40 #define DWC3_EVENT_MAX_NUM      64      /* 2 events/endpoint */
  41 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
  42 #define DWC3_EVENT_TYPE_MASK    0xfe
  43
  44 #define DWC3_EVENT_TYPE_DEV     0
  45 #define DWC3_EVENT_TYPE_CARKIT  3
  46 #define DWC3_EVENT_TYPE_I2C     4
  47
  48 #define DWC3_DEVICE_EVENT_DISCONNECT            0
  49 #define DWC3_DEVICE_EVENT_RESET                 1
  50 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
  51 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
  52 #define DWC3_DEVICE_EVENT_WAKEUP                4
  53 #define DWC3_DEVICE_EVENT_HIBER_REQ             5
  54 #define DWC3_DEVICE_EVENT_EOPF                  6
  55 #define DWC3_DEVICE_EVENT_SOF                   7
  56 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
  57 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
  58 #define DWC3_DEVICE_EVENT_OVERFLOW              11
  59
  60 #define DWC3_GEVNTCOUNT_MASK    0xfffc
  61 #define DWC3_GSNPSID_MASK       0xffff0000
  62 #define DWC3_GSNPSREV_MASK      0xffff
  63
  64 /* DWC3 registers memory space boundries */
  65 #define DWC3_XHCI_REGS_START            0x0
  66 #define DWC3_XHCI_REGS_END              0x7fff
  67 #define DWC3_GLOBALS_REGS_START         0xc100
  68 #define DWC3_GLOBALS_REGS_END           0xc6ff
  69 #define DWC3_DEVICE_REGS_START          0xc700
  70 #define DWC3_DEVICE_REGS_END            0xcbff
  71 #define DWC3_OTG_REGS_START             0xcc00
  72 #define DWC3_OTG_REGS_END               0xccff
  73
  74 /* Global Registers */
  75 #define DWC3_GSBUSCFG0          0xc100
  76 #define DWC3_GSBUSCFG1          0xc104
  77 #define DWC3_GTXTHRCFG          0xc108
  78 #define DWC3_GRXTHRCFG          0xc10c
  79 #define DWC3_GCTL               0xc110
  80 #define DWC3_GEVTEN             0xc114
  81 #define DWC3_GSTS               0xc118
  82 #define DWC3_GSNPSID            0xc120
  83 #define DWC3_GGPIO              0xc124
  84 #define DWC3_GUID               0xc128
  85 #define DWC3_GUCTL              0xc12c
  86 #define DWC3_GBUSERRADDR0       0xc130
  87 #define DWC3_GBUSERRADDR1       0xc134
  88 #define DWC3_GPRTBIMAP0         0xc138
  89 #define DWC3_GPRTBIMAP1         0xc13c
  90 #define DWC3_GHWPARAMS0         0xc140
  91 #define DWC3_GHWPARAMS1         0xc144
  92 #define DWC3_GHWPARAMS2         0xc148
  93 #define DWC3_GHWPARAMS3         0xc14c
  94 #define DWC3_GHWPARAMS4         0xc150
  95 #define DWC3_GHWPARAMS5         0xc154
  96 #define DWC3_GHWPARAMS6         0xc158
  97 #define DWC3_GHWPARAMS7         0xc15c
  98 #define DWC3_GDBGFIFOSPACE      0xc160
  99 #define DWC3_GDBGLTSSM          0xc164
 100 #define DWC3_GPRTBIMAP_HS0      0xc180
 101 #define DWC3_GPRTBIMAP_HS1      0xc184
 102 #define DWC3_GPRTBIMAP_FS0      0xc188
 103 #define DWC3_GPRTBIMAP_FS1      0xc18c
 104
 105 #define DWC3_GUSB2PHYCFG(n)     (0xc200 + (n * 0x04))
 106 #define DWC3_GUSB2I2CCTL(n)     (0xc240 + (n * 0x04))
 107
 108 #define DWC3_GUSB2PHYACC(n)     (0xc280 + (n * 0x04))
 109
 110 #define DWC3_GUSB3PIPECTL(n)    (0xc2c0 + (n * 0x04))
 111
 112 #define DWC3_GTXFIFOSIZ(n)      (0xc300 + (n * 0x04))
 113 #define DWC3_GRXFIFOSIZ(n)      (0xc380 + (n * 0x04))
 114
 115 #define DWC3_GEVNTADRLO(n)      (0xc400 + (n * 0x10))
 116 #define DWC3_GEVNTADRHI(n)      (0xc404 + (n * 0x10))
 117 #define DWC3_GEVNTSIZ(n)        (0xc408 + (n * 0x10))
 118 #define DWC3_GEVNTCOUNT(n)      (0xc40c + (n * 0x10))
 119
 120 #define DWC3_GHWPARAMS8         0xc600
 121
 122 /* Device Registers */
 123 #define DWC3_DCFG               0xc700
 124 #define DWC3_DCTL               0xc704
 125 #define DWC3_DEVTEN             0xc708
 126 #define DWC3_DSTS               0xc70c
 127 #define DWC3_DGCMDPAR           0xc710
 128 #define DWC3_DGCMD              0xc714
 129 #define DWC3_DALEPENA           0xc720
 130 #define DWC3_DEPCMDPAR2(n)      (0xc800 + (n * 0x10))
 131 #define DWC3_DEPCMDPAR1(n)      (0xc804 + (n * 0x10))
 132 #define DWC3_DEPCMDPAR0(n)      (0xc808 + (n * 0x10))
 133 #define DWC3_DEPCMD(n)          (0xc80c + (n * 0x10))
 134
 135 /* OTG Registers */
 136 #define DWC3_OCFG               0xcc00
 137 #define DWC3_OCTL               0xcc04
 138 #define DWC3_OEVT               0xcc08
 139 #define DWC3_OEVTEN             0xcc0C
 140 #define DWC3_OSTS               0xcc10
 141
 142 /* Bit fields */
 143
 144 /* Global Configuration Register */
 145 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
 146 #define DWC3_GCTL_U2RSTECN      (1 << 16)
 147 #define DWC3_GCTL_RAMCLKSEL(x)  (((x) & DWC3_GCTL_CLK_MASK) << 6)
 148 #define DWC3_GCTL_CLK_BUS       (0)
 149 #define DWC3_GCTL_CLK_PIPE      (1)
 150 #define DWC3_GCTL_CLK_PIPEHALF  (2)
 151 #define DWC3_GCTL_CLK_MASK      (3)
 152
 153 #define DWC3_GCTL_PRTCAP(n)     (((n) & (3 << 12)) >> 12)
 154 #define DWC3_GCTL_PRTCAPDIR(n)  ((n) << 12)
 155 #define DWC3_GCTL_PRTCAP_HOST   1
 156 #define DWC3_GCTL_PRTCAP_DEVICE 2
 157 #define DWC3_GCTL_PRTCAP_OTG    3
 158
 159 #define DWC3_GCTL_CORESOFTRESET         (1 << 11)
 160 #define DWC3_GCTL_SCALEDOWN(n)          ((n) << 4)
 161 #define DWC3_GCTL_SCALEDOWN_MASK        DWC3_GCTL_SCALEDOWN(3)
 162 #define DWC3_GCTL_DISSCRAMBLE           (1 << 3)
 163 #define DWC3_GCTL_GBLHIBERNATIONEN      (1 << 1)
 164 #define DWC3_GCTL_DSBLCLKGTNG           (1 << 0)
 165
 166 /* Global USB2 PHY Configuration Register */
 167 #define DWC3_GUSB2PHYCFG_PHYSOFTRST     (1 << 31)
 168 #define DWC3_GUSB2PHYCFG_SUSPHY         (1 << 6)
 169
 170 /* Global USB3 PIPE Control Register */
 171 #define DWC3_GUSB3PIPECTL_PHYSOFTRST    (1 << 31)
 172 #define DWC3_GUSB3PIPECTL_SUSPHY        (1 << 17)
 173
 174 /* Global TX Fifo Size Register */
 175 #define DWC3_GTXFIFOSIZ_TXFDEF(n)       ((n) & 0xffff)
 176 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)    ((n) & 0xffff0000)
 177
 178 /* Global HWPARAMS1 Register */
 179 #define DWC3_GHWPARAMS1_EN_PWROPT(n)    (((n) & (3 << 24)) >> 24)
 180 #define DWC3_GHWPARAMS1_EN_PWROPT_NO    0
 181 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK   1
 182 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB   2
 183 #define DWC3_GHWPARAMS1_PWROPT(n)       ((n) << 24)
 184 #define DWC3_GHWPARAMS1_PWROPT_MASK     DWC3_GHWPARAMS1_PWROPT(3)
 185
 186 /* Global HWPARAMS4 Register */
 187 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)    (((n) & (0x0f << 13)) >> 13)
 188 #define DWC3_MAX_HIBER_SCRATCHBUFS              15
 189
 190 /* Device Configuration Register */
 191 #define DWC3_DCFG_LPM_CAP       (1 << 22)
 192 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
 193 #define DWC3_DCFG_DEVADDR_MASK  DWC3_DCFG_DEVADDR(0x7f)
 194
 195 #define DWC3_DCFG_SPEED_MASK    (7 << 0)
 196 #define DWC3_DCFG_SUPERSPEED    (4 << 0)
 197 #define DWC3_DCFG_HIGHSPEED     (0 << 0)
 198 #define DWC3_DCFG_FULLSPEED2    (1 << 0)
 199 #define DWC3_DCFG_LOWSPEED      (2 << 0)
 200 #define DWC3_DCFG_FULLSPEED1    (3 << 0)
 201
 202 #define DWC3_DCFG_LPM_CAP       (1 << 22)
 203
 204 /* Device Control Register */
 205 #define DWC3_DCTL_RUN_STOP      (1 << 31)
 206 #define DWC3_DCTL_CSFTRST       (1 << 30)
 207 #define DWC3_DCTL_LSFTRST       (1 << 29)
 208
 209 #define DWC3_DCTL_HIRD_THRES_MASK       (0x1f << 24)
 210 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
 211
 212 #define DWC3_DCTL_APPL1RES      (1 << 23)
 213
 214 /* These apply for core versions 1.87a and earlier */
 215 #define DWC3_DCTL_TRGTULST_MASK         (0x0f << 17)
 216 #define DWC3_DCTL_TRGTULST(n)           ((n) << 17)
 217 #define DWC3_DCTL_TRGTULST_U2           (DWC3_DCTL_TRGTULST(2))
 218 #define DWC3_DCTL_TRGTULST_U3           (DWC3_DCTL_TRGTULST(3))
 219 #define DWC3_DCTL_TRGTULST_SS_DIS       (DWC3_DCTL_TRGTULST(4))
 220 #define DWC3_DCTL_TRGTULST_RX_DET       (DWC3_DCTL_TRGTULST(5))
 221 #define DWC3_DCTL_TRGTULST_SS_INACT     (DWC3_DCTL_TRGTULST(6))
 222
 223 /* These apply for core versions 1.94a and later */
 224 #define DWC3_DCTL_KEEP_CONNECT  (1 << 19)
 225 #define DWC3_DCTL_L1_HIBER_EN   (1 << 18)
 226 #define DWC3_DCTL_CRS           (1 << 17)
 227 #define DWC3_DCTL_CSS           (1 << 16)
 228
 229 #define DWC3_DCTL_INITU2ENA     (1 << 12)
 230 #define DWC3_DCTL_ACCEPTU2ENA   (1 << 11)
 231 #define DWC3_DCTL_INITU1ENA     (1 << 10)
 232 #define DWC3_DCTL_ACCEPTU1ENA   (1 << 9)
 233 #define DWC3_DCTL_TSTCTRL_MASK  (0xf << 1)
 234
 235 #define DWC3_DCTL_ULSTCHNGREQ_MASK      (0x0f << 5)
 236 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 237
 238 #define DWC3_DCTL_ULSTCHNG_NO_ACTION    (DWC3_DCTL_ULSTCHNGREQ(0))
 239 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED  (DWC3_DCTL_ULSTCHNGREQ(4))
 240 #define DWC3_DCTL_ULSTCHNG_RX_DETECT    (DWC3_DCTL_ULSTCHNGREQ(5))
 241 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE  (DWC3_DCTL_ULSTCHNGREQ(6))
 242 #define DWC3_DCTL_ULSTCHNG_RECOVERY     (DWC3_DCTL_ULSTCHNGREQ(8))
 243 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE   (DWC3_DCTL_ULSTCHNGREQ(10))
 244 #define DWC3_DCTL_ULSTCHNG_LOOPBACK     (DWC3_DCTL_ULSTCHNGREQ(11))
 245
 246 /* Device Event Enable Register */
 247 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN   (1 << 12)
 248 #define DWC3_DEVTEN_EVNTOVERFLOWEN      (1 << 11)
 249 #define DWC3_DEVTEN_CMDCMPLTEN          (1 << 10)
 250 #define DWC3_DEVTEN_ERRTICERREN         (1 << 9)
 251 #define DWC3_DEVTEN_SOFEN               (1 << 7)
 252 #define DWC3_DEVTEN_EOPFEN              (1 << 6)
 253 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
 254 #define DWC3_DEVTEN_WKUPEVTEN           (1 << 4)
 255 #define DWC3_DEVTEN_ULSTCNGEN           (1 << 3)
 256 #define DWC3_DEVTEN_CONNECTDONEEN       (1 << 2)
 257 #define DWC3_DEVTEN_USBRSTEN            (1 << 1)
 258 #define DWC3_DEVTEN_DISCONNEVTEN        (1 << 0)
 259
 260 /* Device Status Register */
 261 #define DWC3_DSTS_DCNRD                 (1 << 29)
 262
 263 /* This applies for core versions 1.87a and earlier */
 264 #define DWC3_DSTS_PWRUPREQ              (1 << 24)
 265
 266 /* These apply for core versions 1.94a and later */
 267 #define DWC3_DSTS_RSS                   (1 << 25)
 268 #define DWC3_DSTS_SSS                   (1 << 24)
 269
 270 #define DWC3_DSTS_COREIDLE              (1 << 23)
 271 #define DWC3_DSTS_DEVCTRLHLT            (1 << 22)
 272
 273 #define DWC3_DSTS_USBLNKST_MASK         (0x0f << 18)
 274 #define DWC3_DSTS_USBLNKST(n)           (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 275
 276 #define DWC3_DSTS_RXFIFOEMPTY           (1 << 17)
 277
 278 #define DWC3_DSTS_SOFFN_MASK            (0x3fff << 3)
 279 #define DWC3_DSTS_SOFFN(n)              (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 280
 281 #define DWC3_DSTS_CONNECTSPD            (7 << 0)
 282
 283 #define DWC3_DSTS_SUPERSPEED            (4 << 0)
 284 #define DWC3_DSTS_HIGHSPEED             (0 << 0)
 285 #define DWC3_DSTS_FULLSPEED2            (1 << 0)
 286 #define DWC3_DSTS_LOWSPEED              (2 << 0)
 287 #define DWC3_DSTS_FULLSPEED1            (3 << 0)
 288
 289 /* Device Generic Command Register */
 290 #define DWC3_DGCMD_SET_LMP              0x01
 291 #define DWC3_DGCMD_SET_PERIODIC_PAR     0x02
 292 #define DWC3_DGCMD_XMIT_FUNCTION        0x03
 293
 294 /* These apply for core versions 1.94a and later */
 295 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO       0x04
 296 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI       0x05
 297
 298 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH  0x09
 299 #define DWC3_DGCMD_ALL_FIFO_FLUSH       0x0a
 300 #define DWC3_DGCMD_SET_ENDPOINT_NRDY    0x0c
 301 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
 302
 303 #define DWC3_DGCMD_STATUS(n)            (((n) >> 15) & 1)
 304 #define DWC3_DGCMD_CMDACT               (1 << 10)
 305 #define DWC3_DGCMD_CMDIOC               (1 << 8)
 306
 307 /* Device Generic Command Parameter Register */
 308 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT       (1 << 0)
 309 #define DWC3_DGCMDPAR_FIFO_NUM(n)               ((n) << 0)
 310 #define DWC3_DGCMDPAR_RX_FIFO                   (0 << 5)
 311 #define DWC3_DGCMDPAR_TX_FIFO                   (1 << 5)
 312 #define DWC3_DGCMDPAR_LOOPBACK_DIS              (0 << 0)
 313 #define DWC3_DGCMDPAR_LOOPBACK_ENA              (1 << 0)
 314
 315 /* Device Endpoint Command Register */
 316 #define DWC3_DEPCMD_PARAM_SHIFT         16
 317 #define DWC3_DEPCMD_PARAM(x)            ((x) << DWC3_DEPCMD_PARAM_SHIFT)
 318 #define DWC3_DEPCMD_GET_RSC_IDX(x)     (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 319 #define DWC3_DEPCMD_STATUS(x)           (((x) >> 15) & 1)
 320 #define DWC3_DEPCMD_HIPRI_FORCERM       (1 << 11)
 321 #define DWC3_DEPCMD_CMDACT              (1 << 10)
 322 #define DWC3_DEPCMD_CMDIOC              (1 << 8)
 323
 324 #define DWC3_DEPCMD_DEPSTARTCFG         (0x09 << 0)
 325 #define DWC3_DEPCMD_ENDTRANSFER         (0x08 << 0)
 326 #define DWC3_DEPCMD_UPDATETRANSFER      (0x07 << 0)
 327 #define DWC3_DEPCMD_STARTTRANSFER       (0x06 << 0)
 328 #define DWC3_DEPCMD_CLEARSTALL          (0x05 << 0)
 329 #define DWC3_DEPCMD_SETSTALL            (0x04 << 0)
 330 /* This applies for core versions 1.90a and earlier */
 331 #define DWC3_DEPCMD_GETSEQNUMBER        (0x03 << 0)
 332 /* This applies for core versions 1.94a and later */
 333 #define DWC3_DEPCMD_GETEPSTATE          (0x03 << 0)
 334 #define DWC3_DEPCMD_SETTRANSFRESOURCE   (0x02 << 0)
 335 #define DWC3_DEPCMD_SETEPCONFIG         (0x01 << 0)
 336
 337 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 338 #define DWC3_DALEPENA_EP(n)             (1 << n)
 339
 340 #define DWC3_DEPCMD_TYPE_CONTROL        0
 341 #define DWC3_DEPCMD_TYPE_ISOC           1
 342 #define DWC3_DEPCMD_TYPE_BULK           2
 343 #define DWC3_DEPCMD_TYPE_INTR           3
 344
 345 /* Structures */
 346
 347 struct dwc3_trb;
 348
 349 /**
 350  * struct dwc3_event_buffer - Software event buffer representation
 351  * @buf: _THE_ buffer
 352  * @length: size of this buffer
 353  * @lpos: event offset
 354  * @count: cache of last read event count register
 355  * @flags: flags related to this event buffer
 356  * @dma: dma_addr_t
 357  * @dwc: pointer to DWC controller
 358  */
 359 struct dwc3_event_buffer {
 360         void                    *buf;
 361         unsigned                length;
 362         unsigned int            lpos;
 363         unsigned int            count;
 364         unsigned int            flags;
 365
 366 #define DWC3_EVENT_PENDING      BIT(0)
 367
 368         dma_addr_t              dma;
 369
 370         struct dwc3             *dwc;
 371 };
 372
 373 #define DWC3_EP_FLAG_STALLED    (1 << 0)
 374 #define DWC3_EP_FLAG_WEDGED     (1 << 1)
 375
 376 #define DWC3_EP_DIRECTION_TX    true
 377 #define DWC3_EP_DIRECTION_RX    false
 378
 379 #define DWC3_TRB_NUM            32
 380 #define DWC3_TRB_MASK           (DWC3_TRB_NUM - 1)
 381
 382 /**
 383  * struct dwc3_ep - device side endpoint representation
 384  * @endpoint: usb endpoint
 385  * @request_list: list of requests for this endpoint
 386  * @req_queued: list of requests on this ep which have TRBs setup
 387  * @trb_pool: array of transaction buffers
 388  * @trb_pool_dma: dma address of @trb_pool
 389  * @free_slot: next slot which is going to be used
 390  * @busy_slot: first slot which is owned by HW
 391  * @desc: usb_endpoint_descriptor pointer
 392  * @dwc: pointer to DWC controller
 393  * @flags: endpoint flags (wedged, stalled, ...)
 394  * @current_trb: index of current used trb
 395  * @number: endpoint number (1 - 15)
 396  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 397  * @resource_index: Resource transfer index
 398  * @interval: the intervall on which the ISOC transfer is started
 399  * @name: a human readable name e.g. ep1out-bulk
 400  * @direction: true for TX, false for RX
 401  * @stream_capable: true when streams are enabled
 402  */
 403 struct dwc3_ep {
 404         struct usb_ep           endpoint;
 405         struct list_head        request_list;
 406         struct list_head        req_queued;
 407
 408         struct dwc3_trb         *trb_pool;
 409         dma_addr_t              trb_pool_dma;
 410         u32                     free_slot;
 411         u32                     busy_slot;
 412         const struct usb_ss_ep_comp_descriptor *comp_desc;
 413         struct dwc3             *dwc;
 414
 415         unsigned                flags;
 416 #define DWC3_EP_ENABLED         (1 << 0)
 417 #define DWC3_EP_STALL           (1 << 1)
 418 #define DWC3_EP_WEDGE           (1 << 2)
 419 #define DWC3_EP_BUSY            (1 << 4)
 420 #define DWC3_EP_PENDING_REQUEST (1 << 5)
 421 #define DWC3_EP_MISSED_ISOC     (1 << 6)
 422
 423         /* This last one is specific to EP0 */
 424 #define DWC3_EP0_DIR_IN         (1 << 31)
 425
 426         unsigned                current_trb;
 427
 428         u8                      number;
 429         u8                      type;
 430         u8                      resource_index;
 431         u32                     interval;
 432
 433         char                    name[20];
 434
 435         unsigned                direction:1;
 436         unsigned                stream_capable:1;
 437 };
 438
 439 enum dwc3_phy {
 440         DWC3_PHY_UNKNOWN = 0,
 441         DWC3_PHY_USB3,
 442         DWC3_PHY_USB2,
 443 };
 444
 445 enum dwc3_ep0_next {
 446         DWC3_EP0_UNKNOWN = 0,
 447         DWC3_EP0_COMPLETE,
 448         DWC3_EP0_NRDY_DATA,
 449         DWC3_EP0_NRDY_STATUS,
 450 };
 451
 452 enum dwc3_ep0_state {
 453         EP0_UNCONNECTED         = 0,
 454         EP0_SETUP_PHASE,
 455         EP0_DATA_PHASE,
 456         EP0_STATUS_PHASE,
 457 };
 458
 459 enum dwc3_link_state {
 460         /* In SuperSpeed */
 461         DWC3_LINK_STATE_U0              = 0x00, /* in HS, means ON */
 462         DWC3_LINK_STATE_U1              = 0x01,
 463         DWC3_LINK_STATE_U2              = 0x02, /* in HS, means SLEEP */
 464         DWC3_LINK_STATE_U3              = 0x03, /* in HS, means SUSPEND */
 465         DWC3_LINK_STATE_SS_DIS          = 0x04,
 466         DWC3_LINK_STATE_RX_DET          = 0x05, /* in HS, means Early Suspend */
 467         DWC3_LINK_STATE_SS_INACT        = 0x06,
 468         DWC3_LINK_STATE_POLL            = 0x07,
 469         DWC3_LINK_STATE_RECOV           = 0x08,
 470         DWC3_LINK_STATE_HRESET          = 0x09,
 471         DWC3_LINK_STATE_CMPLY           = 0x0a,
 472         DWC3_LINK_STATE_LPBK            = 0x0b,
 473         DWC3_LINK_STATE_RESET           = 0x0e,
 474         DWC3_LINK_STATE_RESUME          = 0x0f,
 475         DWC3_LINK_STATE_MASK            = 0x0f,
 476 };
 477
 478 /* TRB Length, PCM and Status */
 479 #define DWC3_TRB_SIZE_MASK      (0x00ffffff)
 480 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
 481 #define DWC3_TRB_SIZE_PCM1(n)   (((n) & 0x03) << 24)
 482 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
 483
 484 #define DWC3_TRBSTS_OK                  0
 485 #define DWC3_TRBSTS_MISSED_ISOC         1
 486 #define DWC3_TRBSTS_SETUP_PENDING       2
 487 #define DWC3_TRB_STS_XFER_IN_PROG       4
 488
 489 /* TRB Control */
 490 #define DWC3_TRB_CTRL_HWO               (1 << 0)
 491 #define DWC3_TRB_CTRL_LST               (1 << 1)
 492 #define DWC3_TRB_CTRL_CHN               (1 << 2)
 493 #define DWC3_TRB_CTRL_CSP               (1 << 3)
 494 #define DWC3_TRB_CTRL_TRBCTL(n)         (((n) & 0x3f) << 4)
 495 #define DWC3_TRB_CTRL_ISP_IMI           (1 << 10)
 496 #define DWC3_TRB_CTRL_IOC               (1 << 11)
 497 #define DWC3_TRB_CTRL_SID_SOFN(n)       (((n) & 0xffff) << 14)
 498
 499 #define DWC3_TRBCTL_NORMAL              DWC3_TRB_CTRL_TRBCTL(1)
 500 #define DWC3_TRBCTL_CONTROL_SETUP       DWC3_TRB_CTRL_TRBCTL(2)
 501 #define DWC3_TRBCTL_CONTROL_STATUS2     DWC3_TRB_CTRL_TRBCTL(3)
 502 #define DWC3_TRBCTL_CONTROL_STATUS3     DWC3_TRB_CTRL_TRBCTL(4)
 503 #define DWC3_TRBCTL_CONTROL_DATA        DWC3_TRB_CTRL_TRBCTL(5)
 504 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST   DWC3_TRB_CTRL_TRBCTL(6)
 505 #define DWC3_TRBCTL_ISOCHRONOUS         DWC3_TRB_CTRL_TRBCTL(7)
 506 #define DWC3_TRBCTL_LINK_TRB            DWC3_TRB_CTRL_TRBCTL(8)
 507
 508 /**
 509  * struct dwc3_trb - transfer request block (hw format)
 510  * @bpl: DW0-3
 511  * @bph: DW4-7
 512  * @size: DW8-B
 513  * @trl: DWC-F
 514  */
 515 struct dwc3_trb {
 516         u32             bpl;
 517         u32             bph;
 518         u32             size;
 519         u32             ctrl;
 520 } __packed;
 521
 522 /**
 523  * dwc3_hwparams - copy of HWPARAMS registers
 524  * @hwparams0 - GHWPARAMS0
 525  * @hwparams1 - GHWPARAMS1
 526  * @hwparams2 - GHWPARAMS2
 527  * @hwparams3 - GHWPARAMS3
 528  * @hwparams4 - GHWPARAMS4
 529  * @hwparams5 - GHWPARAMS5
 530  * @hwparams6 - GHWPARAMS6
 531  * @hwparams7 - GHWPARAMS7
 532  * @hwparams8 - GHWPARAMS8
 533  */
 534 struct dwc3_hwparams {
 535         u32     hwparams0;
 536         u32     hwparams1;
 537         u32     hwparams2;
 538         u32     hwparams3;
 539         u32     hwparams4;
 540         u32     hwparams5;
 541         u32     hwparams6;
 542         u32     hwparams7;
 543         u32     hwparams8;
 544 };
 545
 546 /* HWPARAMS0 */
 547 #define DWC3_MODE(n)            ((n) & 0x7)
 548
 549 #define DWC3_MDWIDTH(n)         (((n) & 0xff00) >> 8)
 550
 551 /* HWPARAMS1 */
 552 #define DWC3_NUM_INT(n)         (((n) & (0x3f << 15)) >> 15)
 553
 554 /* HWPARAMS3 */
 555 #define DWC3_NUM_IN_EPS_MASK    (0x1f << 18)
 556 #define DWC3_NUM_EPS_MASK       (0x3f << 12)
 557 #define DWC3_NUM_EPS(p)         (((p)->hwparams3 &              \
 558                         (DWC3_NUM_EPS_MASK)) >> 12)
 559 #define DWC3_NUM_IN_EPS(p)      (((p)->hwparams3 &              \
 560                         (DWC3_NUM_IN_EPS_MASK)) >> 18)
 561
 562 /* HWPARAMS7 */
 563 #define DWC3_RAM1_DEPTH(n)      ((n) & 0xffff)
 564
 565 struct dwc3_request {
 566         struct usb_request      request;
 567         struct list_head        list;
 568         struct dwc3_ep          *dep;
 569         u32                     start_slot;
 570
 571         u8                      epnum;
 572         struct dwc3_trb         *trb;
 573         dma_addr_t              trb_dma;
 574
 575         unsigned                direction:1;
 576         unsigned                mapped:1;
 577         unsigned                queued:1;
 578 };
 579
 580 /*
 581  * struct dwc3_scratchpad_array - hibernation scratchpad array
 582  * (format defined by hw)
 583  */
 584 struct dwc3_scratchpad_array {
 585         __le64  dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
 586 };
 587
 588 /**
 589  * struct dwc3 - representation of our controller
 590  * @ctrl_req: usb control request which is used for ep0
 591  * @ep0_trb: trb which is used for the ctrl_req
 592  * @ep0_bounce: bounce buffer for ep0
 593  * @setup_buf: used while precessing STD USB requests
 594  * @ctrl_req_addr: dma address of ctrl_req
 595  * @ep0_trb: dma address of ep0_trb
 596  * @ep0_usb_req: dummy req used while handling STD USB requests
 597  * @ep0_bounce_addr: dma address of ep0_bounce
 598  * @lock: for synchronizing
 599  * @dev: pointer to our struct device
 600  * @xhci: pointer to our xHCI child
 601  * @event_buffer_list: a list of event buffers
 602  * @gadget: device side representation of the peripheral controller
 603  * @gadget_driver: pointer to the gadget driver
 604  * @regs: base address for our registers
 605  * @regs_size: address space size
 606  * @num_event_buffers: calculated number of event buffers
 607  * @u1u2: only used on revisions <1.83a for workaround
 608  * @maximum_speed: maximum speed requested (mainly for testing purposes)
 609  * @revision: revision register contents
 610  * @dr_mode: requested mode of operation
 611  * @usb2_phy: pointer to USB2 PHY
 612  * @usb3_phy: pointer to USB3 PHY
 613  * @dcfg: saved contents of DCFG register
 614  * @gctl: saved contents of GCTL register
 615  * @is_selfpowered: true when we are selfpowered
 616  * @three_stage_setup: set if we perform a three phase setup
 617  * @ep0_bounced: true when we used bounce buffer
 618  * @ep0_expect_in: true when we expect a DATA IN transfer
 619  * @start_config_issued: true when StartConfig command has been issued
 620  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
 621  * @needs_fifo_resize: not all users might want fifo resizing, flag it
 622  * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
 623  * @isoch_delay: wValue from Set Isochronous Delay request;
 624  * @u2sel: parameter from Set SEL request.
 625  * @u2pel: parameter from Set SEL request.
 626  * @u1sel: parameter from Set SEL request.
 627  * @u1pel: parameter from Set SEL request.
 628  * @num_out_eps: number of out endpoints
 629  * @num_in_eps: number of in endpoints
 630  * @ep0_next_event: hold the next expected event
 631  * @ep0state: state of endpoint zero
 632  * @link_state: link state
 633  * @speed: device speed (super, high, full, low)
 634  * @mem: points to start of memory which is used for this struct.
 635  * @hwparams: copy of hwparams registers
 636  * @root: debugfs root folder pointer
 637  */
 638 struct dwc3 {
 639         struct usb_ctrlrequest  *ctrl_req;
 640         struct dwc3_trb         *ep0_trb;
 641         void                    *ep0_bounce;
 642         u8                      *setup_buf;
 643         dma_addr_t              ctrl_req_addr;
 644         dma_addr_t              ep0_trb_addr;
 645         dma_addr_t              ep0_bounce_addr;
 646         struct dwc3_request     ep0_usb_req;
 647
 648         /* device lock */
 649         spinlock_t              lock;
 650
 651         struct device           *dev;
 652
 653         struct platform_device  *xhci;
 654         struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
 655
 656         struct dwc3_event_buffer **ev_buffs;
 657         struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
 658
 659         struct usb_gadget       gadget;
 660         struct usb_gadget_driver *gadget_driver;
 661
 662         struct usb_phy          *usb2_phy;
 663         struct usb_phy          *usb3_phy;
 664
 665         void __iomem            *regs;
 666         size_t                  regs_size;
 667
 668         enum usb_dr_mode        dr_mode;
 669
 670         /* used for suspend/resume */
 671         u32                     dcfg;
 672         u32                     gctl;
 673
 674         u32                     num_event_buffers;
 675         u32                     u1u2;
 676         u32                     maximum_speed;
 677         u32                     revision;
 678
 679 #define DWC3_REVISION_173A      0x5533173a
 680 #define DWC3_REVISION_175A      0x5533175a
 681 #define DWC3_REVISION_180A      0x5533180a
 682 #define DWC3_REVISION_183A      0x5533183a
 683 #define DWC3_REVISION_185A      0x5533185a
 684 #define DWC3_REVISION_187A      0x5533187a
 685 #define DWC3_REVISION_188A      0x5533188a
 686 #define DWC3_REVISION_190A      0x5533190a
 687 #define DWC3_REVISION_194A      0x5533194a
 688 #define DWC3_REVISION_200A      0x5533200a
 689 #define DWC3_REVISION_202A      0x5533202a
 690 #define DWC3_REVISION_210A      0x5533210a
 691 #define DWC3_REVISION_220A      0x5533220a
 692 #define DWC3_REVISION_230A      0x5533230a
 693 #define DWC3_REVISION_240A      0x5533240a
 694 #define DWC3_REVISION_250A      0x5533250a
 695
 696         unsigned                is_selfpowered:1;
 697         unsigned                three_stage_setup:1;
 698         unsigned                ep0_bounced:1;
 699         unsigned                ep0_expect_in:1;
 700         unsigned                start_config_issued:1;
 701         unsigned                setup_packet_pending:1;
 702         unsigned                delayed_status:1;
 703         unsigned                needs_fifo_resize:1;
 704         unsigned                resize_fifos:1;
 705         unsigned                pullups_connected:1;
 706
 707         enum dwc3_ep0_next      ep0_next_event;
 708         enum dwc3_ep0_state     ep0state;
 709         enum dwc3_link_state    link_state;
 710
 711         u16                     isoch_delay;
 712         u16                     u2sel;
 713         u16                     u2pel;
 714         u8                      u1sel;
 715         u8                      u1pel;
 716
 717         u8                      speed;
 718
 719         u8                      num_out_eps;
 720         u8                      num_in_eps;
 721
 722         void                    *mem;
 723
 724         struct dwc3_hwparams    hwparams;
 725         struct dentry           *root;
 726         struct debugfs_regset32 *regset;
 727
 728         u8                      test_mode;
 729         u8                      test_mode_nr;
 730 };
 731
 732 /* -------------------------------------------------------------------------- */
 733
 734 /* -------------------------------------------------------------------------- */
 735
 736 struct dwc3_event_type {
 737         u32     is_devspec:1;
 738         u32     type:7;
 739         u32     reserved8_31:24;
 740 } __packed;
 741
 742 #define DWC3_DEPEVT_XFERCOMPLETE        0x01
 743 #define DWC3_DEPEVT_XFERINPROGRESS      0x02
 744 #define DWC3_DEPEVT_XFERNOTREADY        0x03
 745 #define DWC3_DEPEVT_RXTXFIFOEVT         0x04
 746 #define DWC3_DEPEVT_STREAMEVT           0x06
 747 #define DWC3_DEPEVT_EPCMDCMPLT          0x07
 748
 749 /**
 750  * struct dwc3_event_depvt - Device Endpoint Events
 751  * @one_bit: indicates this is an endpoint event (not used)
 752  * @endpoint_number: number of the endpoint
 753  * @endpoint_event: The event we have:
 754  *      0x00    - Reserved
 755  *      0x01    - XferComplete
 756  *      0x02    - XferInProgress
 757  *      0x03    - XferNotReady
 758  *      0x04    - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
 759  *      0x05    - Reserved
 760  *      0x06    - StreamEvt
 761  *      0x07    - EPCmdCmplt
 762  * @reserved11_10: Reserved, don't use.
 763  * @status: Indicates the status of the event. Refer to databook for
 764  *      more information.
 765  * @parameters: Parameters of the current event. Refer to databook for
 766  *      more information.
 767  */
 768 struct dwc3_event_depevt {
 769         u32     one_bit:1;
 770         u32     endpoint_number:5;
 771         u32     endpoint_event:4;
 772         u32     reserved11_10:2;
 773         u32     status:4;
 774
 775 /* Within XferNotReady */
 776 #define DEPEVT_STATUS_TRANSFER_ACTIVE   (1 << 3)
 777
 778 /* Within XferComplete */
 779 #define DEPEVT_STATUS_BUSERR    (1 << 0)
 780 #define DEPEVT_STATUS_SHORT     (1 << 1)
 781 #define DEPEVT_STATUS_IOC       (1 << 2)
 782 #define DEPEVT_STATUS_LST       (1 << 3)
 783
 784 /* Stream event only */
 785 #define DEPEVT_STREAMEVT_FOUND          1
 786 #define DEPEVT_STREAMEVT_NOTFOUND       2
 787
 788 /* Control-only Status */
 789 #define DEPEVT_STATUS_CONTROL_DATA      1
 790 #define DEPEVT_STATUS_CONTROL_STATUS    2
 791
 792         u32     parameters:16;
 793 } __packed;
 794
 795 /**
 796  * struct dwc3_event_devt - Device Events
 797  * @one_bit: indicates this is a non-endpoint event (not used)
 798  * @device_event: indicates it's a device event. Should read as 0x00
 799  * @type: indicates the type of device event.
 800  *      0       - DisconnEvt
 801  *      1       - USBRst
 802  *      2       - ConnectDone
 803  *      3       - ULStChng
 804  *      4       - WkUpEvt
 805  *      5       - Reserved
 806  *      6       - EOPF
 807  *      7       - SOF
 808  *      8       - Reserved
 809  *      9       - ErrticErr
 810  *      10      - CmdCmplt
 811  *      11      - EvntOverflow
 812  *      12      - VndrDevTstRcved
 813  * @reserved15_12: Reserved, not used
 814  * @event_info: Information about this event
 815  * @reserved31_24: Reserved, not used
 816  */
 817 struct dwc3_event_devt {
 818         u32     one_bit:1;
 819         u32     device_event:7;
 820         u32     type:4;
 821         u32     reserved15_12:4;
 822         u32     event_info:8;
 823         u32     reserved31_24:8;
 824 } __packed;
 825
 826 /**
 827  * struct dwc3_event_gevt - Other Core Events
 828  * @one_bit: indicates this is a non-endpoint event (not used)
 829  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
 830  * @phy_port_number: self-explanatory
 831  * @reserved31_12: Reserved, not used.
 832  */
 833 struct dwc3_event_gevt {
 834         u32     one_bit:1;
 835         u32     device_event:7;
 836         u32     phy_port_number:4;
 837         u32     reserved31_12:20;
 838 } __packed;
 839
 840 /**
 841  * union dwc3_event - representation of Event Buffer contents
 842  * @raw: raw 32-bit event
 843  * @type: the type of the event
 844  * @depevt: Device Endpoint Event
 845  * @devt: Device Event
 846  * @gevt: Global Event
 847  */
 848 union dwc3_event {
 849         u32                             raw;
 850         struct dwc3_event_type          type;
 851         struct dwc3_event_depevt        depevt;
 852         struct dwc3_event_devt          devt;
 853         struct dwc3_event_gevt          gevt;
 854 };
 855
 856 /*
 857  * DWC3 Features to be used as Driver Data
 858  */
 859
 860 #define DWC3_HAS_PERIPHERAL             BIT(0)
 861 #define DWC3_HAS_XHCI                   BIT(1)
 862 #define DWC3_HAS_OTG                    BIT(3)
 863
 864 /* prototypes */
 865 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
 866 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
 867
 868 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
 869 int dwc3_host_init(struct dwc3 *dwc);
 870 void dwc3_host_exit(struct dwc3 *dwc);
 871 #else
 872 static inline int dwc3_host_init(struct dwc3 *dwc)
 873 { return 0; }
 874 static inline void dwc3_host_exit(struct dwc3 *dwc)
 875 { }
 876 #endif
 877
 878 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
 879 int dwc3_gadget_init(struct dwc3 *dwc);
 880 void dwc3_gadget_exit(struct dwc3 *dwc);
 881 #else
 882 static inline int dwc3_gadget_init(struct dwc3 *dwc)
 883 { return 0; }
 884 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
 885 { }
 886 #endif
 887
 888 /* power management interface */
 889 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
 890 int dwc3_gadget_prepare(struct dwc3 *dwc);
 891 void dwc3_gadget_complete(struct dwc3 *dwc);
 892 int dwc3_gadget_suspend(struct dwc3 *dwc);
 893 int dwc3_gadget_resume(struct dwc3 *dwc);
 894 #else
 895 static inline int dwc3_gadget_prepare(struct dwc3 *dwc)
 896 {
 897         return 0;
 898 }
 899
 900 static inline void dwc3_gadget_complete(struct dwc3 *dwc)
 901 {
 902 }
 903
 904 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
 905 {
 906         return 0;
 907 }
 908
 909 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
 910 {
 911         return 0;
 912 }
 913 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
 914
 915 #endif /* __DRIVERS_USB_DWC3_CORE_H */