drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/platform_data/dwc3-omap.h>
  46 #include <linux/usb/dwc3-omap.h>
  47 #include <linux/pm_runtime.h>
  48 #include <linux/dma-mapping.h>
  49 #include <linux/ioport.h>
  50 #include <linux/io.h>
  51 #include <linux/of.h>
  52 #include <linux/of_platform.h>
  53
  54 #include <linux/usb/otg.h>
  55
  56 /*
  57  * All these registers belong to OMAP's Wrapper around the
  58  * DesignWare USB3 Core.
  59  */
  60
  61 #define USBOTGSS_REVISION                       0x0000
  62 #define USBOTGSS_SYSCONFIG                      0x0010
  63 #define USBOTGSS_IRQ_EOI                        0x0020
  64 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  65 #define USBOTGSS_IRQSTATUS_0                    0x0028
  66 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  67 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  68 #define USBOTGSS_IRQSTATUS_RAW_1                0x0034
  69 #define USBOTGSS_IRQSTATUS_1                    0x0038
  70 #define USBOTGSS_IRQENABLE_SET_1                0x003c
  71 #define USBOTGSS_IRQENABLE_CLR_1                0x0040
  72 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  73 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  74 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  75 #define USBOTGSS_FLADJ                          0x0104
  76 #define USBOTGSS_DEBUG_CFG                      0x0108
  77 #define USBOTGSS_DEBUG_DATA                     0x010c
  78
  79 /* SYSCONFIG REGISTER */
  80 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  81
  82 /* IRQ_EOI REGISTER */
  83 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  84
  85 /* IRQS0 BITS */
  86 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  87
  88 /* IRQ1 BITS */
  89 #define USBOTGSS_IRQ1_DMADISABLECLR             (1 << 17)
  90 #define USBOTGSS_IRQ1_OEVT                      (1 << 16)
  91 #define USBOTGSS_IRQ1_DRVVBUS_RISE              (1 << 13)
  92 #define USBOTGSS_IRQ1_CHRGVBUS_RISE             (1 << 12)
  93 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE          (1 << 11)
  94 #define USBOTGSS_IRQ1_IDPULLUP_RISE             (1 << 8)
  95 #define USBOTGSS_IRQ1_DRVVBUS_FALL              (1 << 5)
  96 #define USBOTGSS_IRQ1_CHRGVBUS_FALL             (1 << 4)
  97 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL          (1 << 3)
  98 #define USBOTGSS_IRQ1_IDPULLUP_FALL             (1 << 0)
  99
 100 /* UTMI_OTG_CTRL REGISTER */
 101 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 102 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 103 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 104 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 105
 106 /* UTMI_OTG_STATUS REGISTER */
 107 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 108 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 109 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 110 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 111 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 112 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 113 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 114
 115 struct dwc3_omap {
 116         /* device lock */
 117         spinlock_t              lock;
 118
 119         struct device           *dev;
 120
 121         int                     irq;
 122         void __iomem            *base;
 123
 124         u32                     utmi_otg_status;
 125
 126         u32                     dma_status:1;
 127 };
 128
 129 struct dwc3_omap                *_omap;
 130
 131 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 132 {
 133         return readl(base + offset);
 134 }
 135
 136 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 137 {
 138         writel(value, base + offset);
 139 }
 140
 141 void dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
 142 {
 143         u32                     val;
 144         struct dwc3_omap        *omap = _omap;
 145
 146         switch (status) {
 147         case OMAP_DWC3_ID_GROUND:
 148                 dev_dbg(omap->dev, "ID GND\n");
 149
 150                 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
 151                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 152                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 153                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 154                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 155                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 156                 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
 157                 break;
 158
 159         case OMAP_DWC3_VBUS_VALID:
 160                 dev_dbg(omap->dev, "VBUS Connect\n");
 161
 162                 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
 163                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 164                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 165                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 166                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 167                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 168                 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
 169                 break;
 170
 171         case OMAP_DWC3_ID_FLOAT:
 172         case OMAP_DWC3_VBUS_OFF:
 173                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 174
 175                 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
 176                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 177                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 178                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 179                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 180                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 181                 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
 182                 break;
 183
 184         default:
 185                 dev_dbg(omap->dev, "ID float\n");
 186         }
 187
 188         return;
 189 }
 190 EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
 191
 192 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 193 {
 194         struct dwc3_omap        *omap = _omap;
 195         u32                     reg;
 196
 197         spin_lock(&omap->lock);
 198
 199         reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
 200
 201         if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
 202                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 203                 omap->dma_status = false;
 204         }
 205
 206         if (reg & USBOTGSS_IRQ1_OEVT)
 207                 dev_dbg(omap->dev, "OTG Event\n");
 208
 209         if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
 210                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 211
 212         if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
 213                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 214
 215         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
 216                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 217
 218         if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
 219                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 220
 221         if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
 222                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 223
 224         if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
 225                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 226
 227         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
 228                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 229
 230         if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
 231                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 232
 233         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
 234
 235         reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
 236         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
 237
 238         spin_unlock(&omap->lock);
 239
 240         return IRQ_HANDLED;
 241 }
 242
 243 static int dwc3_omap_remove_core(struct device *dev, void *c)
 244 {
 245         struct platform_device *pdev = to_platform_device(dev);
 246
 247         platform_device_unregister(pdev);
 248
 249         return 0;
 250 }
 251
 252 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 253 {
 254         u32                     reg;
 255
 256         /* enable all IRQs */
 257         reg = USBOTGSS_IRQO_COREIRQ_ST;
 258         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
 259
 260         reg = (USBOTGSS_IRQ1_OEVT |
 261                         USBOTGSS_IRQ1_DRVVBUS_RISE |
 262                         USBOTGSS_IRQ1_CHRGVBUS_RISE |
 263                         USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
 264                         USBOTGSS_IRQ1_IDPULLUP_RISE |
 265                         USBOTGSS_IRQ1_DRVVBUS_FALL |
 266                         USBOTGSS_IRQ1_CHRGVBUS_FALL |
 267                         USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
 268                         USBOTGSS_IRQ1_IDPULLUP_FALL);
 269
 270         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
 271 }
 272
 273 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 274 {
 275         /* disable all IRQs */
 276         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
 277         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
 278 }
 279
 280 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 281
 282 static int dwc3_omap_probe(struct platform_device *pdev)
 283 {
 284         struct device_node      *node = pdev->dev.of_node;
 285
 286         struct dwc3_omap        *omap;
 287         struct resource         *res;
 288         struct device           *dev = &pdev->dev;
 289
 290         int                     ret = -ENOMEM;
 291         int                     irq;
 292
 293         int                     utmi_mode = 0;
 294
 295         u32                     reg;
 296
 297         void __iomem            *base;
 298
 299         if (!node) {
 300                 dev_err(dev, "device node not found\n");
 301                 return -EINVAL;
 302         }
 303
 304         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 305         if (!omap) {
 306                 dev_err(dev, "not enough memory\n");
 307                 return -ENOMEM;
 308         }
 309
 310         platform_set_drvdata(pdev, omap);
 311
 312         irq = platform_get_irq(pdev, 0);
 313         if (irq < 0) {
 314                 dev_err(dev, "missing IRQ resource\n");
 315                 return -EINVAL;
 316         }
 317
 318         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 319         if (!res) {
 320                 dev_err(dev, "missing memory base resource\n");
 321                 return -EINVAL;
 322         }
 323
 324         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 325         if (!base) {
 326                 dev_err(dev, "ioremap failed\n");
 327                 return -ENOMEM;
 328         }
 329
 330         spin_lock_init(&omap->lock);
 331
 332         omap->dev       = dev;
 333         omap->irq       = irq;
 334         omap->base      = base;
 335         dev->dma_mask   = &dwc3_omap_dma_mask;
 336
 337         /*
 338          * REVISIT if we ever have two instances of the wrapper, we will be
 339          * in big trouble
 340          */
 341         _omap   = omap;
 342
 343         pm_runtime_enable(dev);
 344         ret = pm_runtime_get_sync(dev);
 345         if (ret < 0) {
 346                 dev_err(dev, "get_sync failed with err %d\n", ret);
 347                 return ret;
 348         }
 349
 350         reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
 351
 352         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 353
 354         switch (utmi_mode) {
 355         case DWC3_OMAP_UTMI_MODE_SW:
 356                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 357                 break;
 358         case DWC3_OMAP_UTMI_MODE_HW:
 359                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 360                 break;
 361         default:
 362                 dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 363         }
 364
 365         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
 366
 367         /* check the DMA Status */
 368         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 369         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 370
 371         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 372                         "dwc3-omap", omap);
 373         if (ret) {
 374                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 375                                 omap->irq, ret);
 376                 return ret;
 377         }
 378
 379         dwc3_omap_enable_irqs(omap);
 380
 381         ret = of_platform_populate(node, NULL, NULL, dev);
 382         if (ret) {
 383                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 384                 return ret;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int dwc3_omap_remove(struct platform_device *pdev)
 391 {
 392         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 393
 394         dwc3_omap_disable_irqs(omap);
 395         pm_runtime_put_sync(&pdev->dev);
 396         pm_runtime_disable(&pdev->dev);
 397         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
 398
 399         return 0;
 400 }
 401
 402 static const struct of_device_id of_dwc3_match[] = {
 403         {
 404                 .compatible =   "ti,dwc3"
 405         },
 406         { },
 407 };
 408 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 409
 410 #ifdef CONFIG_PM
 411 static int dwc3_omap_prepare(struct device *dev)
 412 {
 413         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 414
 415         dwc3_omap_disable_irqs(omap);
 416
 417         return 0;
 418 }
 419
 420 static void dwc3_omap_complete(struct device *dev)
 421 {
 422         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 423
 424         dwc3_omap_enable_irqs(omap);
 425 }
 426
 427 static int dwc3_omap_suspend(struct device *dev)
 428 {
 429         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 430
 431         omap->utmi_otg_status = dwc3_omap_readl(omap->base,
 432                         USBOTGSS_UTMI_OTG_STATUS);
 433
 434         return 0;
 435 }
 436
 437 static int dwc3_omap_resume(struct device *dev)
 438 {
 439         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 440
 441         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
 442                         omap->utmi_otg_status);
 443
 444         pm_runtime_disable(dev);
 445         pm_runtime_set_active(dev);
 446         pm_runtime_enable(dev);
 447
 448         return 0;
 449 }
 450
 451 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 452         .prepare        = dwc3_omap_prepare,
 453         .complete       = dwc3_omap_complete,
 454
 455         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 456 };
 457
 458 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 459 #else
 460 #define DEV_PM_OPS      NULL
 461 #endif /* CONFIG_PM */
 462
 463 static struct platform_driver dwc3_omap_driver = {
 464         .probe          = dwc3_omap_probe,
 465         .remove         = dwc3_omap_remove,
 466         .driver         = {
 467                 .name   = "omap-dwc3",
 468                 .of_match_table = of_dwc3_match,
 469                 .pm     = DEV_PM_OPS,
 470         },
 471 };
 472
 473 module_platform_driver(dwc3_omap_driver);
 474
 475 MODULE_ALIAS("platform:omap-dwc3");
 476 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 477 MODULE_LICENSE("Dual BSD/GPL");
 478 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");