drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = dwc->ep0_trb;
  74
  75         trb->bpl = lower_32_bits(buf_dma);
  76         trb->bph = upper_32_bits(buf_dma);
  77         trb->size = len;
  78         trb->ctrl = type;
  79
  80         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  81                         | DWC3_TRB_CTRL_LST
  82                         | DWC3_TRB_CTRL_IOC
  83                         | DWC3_TRB_CTRL_ISP_IMI);
  84
  85         memset(&params, 0, sizeof(params));
  86         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  87         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  88
  89         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  90                         DWC3_DEPCMD_STARTTRANSFER, &params);
  91         if (ret < 0) {
  92                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
  93                                 dep->name);
  94                 return ret;
  95         }
  96
  97         dep->flags |= DWC3_EP_BUSY;
  98         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  99                         dep->number);
 100
 101         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 102
 103         return 0;
 104 }
 105
 106 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 107                 struct dwc3_request *req)
 108 {
 109         struct dwc3             *dwc = dep->dwc;
 110
 111         req->request.actual     = 0;
 112         req->request.status     = -EINPROGRESS;
 113         req->epnum              = dep->number;
 114
 115         list_add_tail(&req->list, &dep->request_list);
 116
 117         /*
 118          * Gadget driver might not be quick enough to queue a request
 119          * before we get a Transfer Not Ready event on this endpoint.
 120          *
 121          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 122          * flag is set, it's telling us that as soon as Gadget queues the
 123          * required request, we should kick the transfer here because the
 124          * IRQ we were waiting for is long gone.
 125          */
 126         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 127                 unsigned        direction;
 128
 129                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 130
 131                 if (dwc->ep0state != EP0_DATA_PHASE) {
 132                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 133                         return 0;
 134                 }
 135
 136                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 137
 138                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 139                                 DWC3_EP0_DIR_IN);
 140
 141                 return 0;
 142         }
 143
 144         /*
 145          * In case gadget driver asked us to delay the STATUS phase,
 146          * handle it here.
 147          */
 148         if (dwc->delayed_status) {
 149                 unsigned        direction;
 150
 151                 direction = !dwc->ep0_expect_in;
 152                 dwc->delayed_status = false;
 153                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 154
 155                 if (dwc->ep0state == EP0_STATUS_PHASE)
 156                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 157                 else
 158                         dwc3_trace(trace_dwc3_ep0,
 159                                         "too early for delayed status");
 160
 161                 return 0;
 162         }
 163
 164         /*
 165          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 166          *
 167          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 168          * come before issueing Start Transfer command, but if we do, we will
 169          * miss situations where the host starts another SETUP phase instead of
 170          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 171          * Layer Compliance Suite.
 172          *
 173          * The problem surfaces due to the fact that in case of back-to-back
 174          * SETUP packets there will be no XferNotReady(DATA) generated and we
 175          * will be stuck waiting for XferNotReady(DATA) forever.
 176          *
 177          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 178          * it tells us to start Data Phase right away. It also mentions that if
 179          * we receive a SETUP phase instead of the DATA phase, core will issue
 180          * XferComplete for the DATA phase, before actually initiating it in
 181          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 182          * can only be used to print some debugging logs, as the core expects
 183          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 184          * just so it completes right away, without transferring anything and,
 185          * only then, we can go back to the SETUP phase.
 186          *
 187          * Because of this scenario, SNPS decided to change the programming
 188          * model of control transfers and support on-demand transfers only for
 189          * the STATUS phase. To fix the issue we have now, we will always wait
 190          * for gadget driver to queue the DATA phase's struct usb_request, then
 191          * start it right away.
 192          *
 193          * If we're actually in a 2-stage transfer, we will wait for
 194          * XferNotReady(STATUS).
 195          */
 196         if (dwc->three_stage_setup) {
 197                 unsigned        direction;
 198
 199                 direction = dwc->ep0_expect_in;
 200                 dwc->ep0state = EP0_DATA_PHASE;
 201
 202                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 203
 204                 dep->flags &= ~DWC3_EP0_DIR_IN;
 205         }
 206
 207         return 0;
 208 }
 209
 210 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 211                 gfp_t gfp_flags)
 212 {
 213         struct dwc3_request             *req = to_dwc3_request(request);
 214         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 215         struct dwc3                     *dwc = dep->dwc;
 216
 217         unsigned long                   flags;
 218
 219         int                             ret;
 220
 221         spin_lock_irqsave(&dwc->lock, flags);
 222         if (!dep->endpoint.desc) {
 223                 dwc3_trace(trace_dwc3_ep0,
 224                                 "trying to queue request %p to disabled %s",
 225                                 request, dep->name);
 226                 ret = -ESHUTDOWN;
 227                 goto out;
 228         }
 229
 230         /* we share one TRB for ep0/1 */
 231         if (!list_empty(&dep->request_list)) {
 232                 ret = -EBUSY;
 233                 goto out;
 234         }
 235
 236         dwc3_trace(trace_dwc3_ep0,
 237                         "queueing request %p to %s length %d state '%s'",
 238                         request, dep->name, request->length,
 239                         dwc3_ep0_state_string(dwc->ep0state));
 240
 241         ret = __dwc3_gadget_ep0_queue(dep, req);
 242
 243 out:
 244         spin_unlock_irqrestore(&dwc->lock, flags);
 245
 246         return ret;
 247 }
 248
 249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 250 {
 251         struct dwc3_ep          *dep;
 252
 253         /* reinitialize physical ep1 */
 254         dep = dwc->eps[1];
 255         dep->flags = DWC3_EP_ENABLED;
 256
 257         /* stall is always issued on EP0 */
 258         dep = dwc->eps[0];
 259         __dwc3_gadget_ep_set_halt(dep, 1, false);
 260         dep->flags = DWC3_EP_ENABLED;
 261         dwc->delayed_status = false;
 262
 263         if (!list_empty(&dep->request_list)) {
 264                 struct dwc3_request     *req;
 265
 266                 req = next_request(&dep->request_list);
 267                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 268         }
 269
 270         dwc->ep0state = EP0_SETUP_PHASE;
 271         dwc3_ep0_out_start(dwc);
 272 }
 273
 274 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 275 {
 276         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 277         struct dwc3                     *dwc = dep->dwc;
 278
 279         dwc3_ep0_stall_and_restart(dwc);
 280
 281         return 0;
 282 }
 283
 284 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 285 {
 286         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 287         struct dwc3                     *dwc = dep->dwc;
 288         unsigned long                   flags;
 289         int                             ret;
 290
 291         spin_lock_irqsave(&dwc->lock, flags);
 292         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 293         spin_unlock_irqrestore(&dwc->lock, flags);
 294
 295         return ret;
 296 }
 297
 298 void dwc3_ep0_out_start(struct dwc3 *dwc)
 299 {
 300         int                             ret;
 301
 302         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 303                         DWC3_TRBCTL_CONTROL_SETUP);
 304         WARN_ON(ret < 0);
 305 }
 306
 307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 308 {
 309         struct dwc3_ep          *dep;
 310         u32                     windex = le16_to_cpu(wIndex_le);
 311         u32                     epnum;
 312
 313         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 314         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 315                 epnum |= 1;
 316
 317         dep = dwc->eps[epnum];
 318         if (dep->flags & DWC3_EP_ENABLED)
 319                 return dep;
 320
 321         return NULL;
 322 }
 323
 324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 325 {
 326 }
 327 /*
 328  * ch 9.4.5
 329  */
 330 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 331                 struct usb_ctrlrequest *ctrl)
 332 {
 333         struct dwc3_ep          *dep;
 334         u32                     recip;
 335         u32                     reg;
 336         u16                     usb_status = 0;
 337         __le16                  *response_pkt;
 338
 339         recip = ctrl->bRequestType & USB_RECIP_MASK;
 340         switch (recip) {
 341         case USB_RECIP_DEVICE:
 342                 /*
 343                  * LTM will be set once we know how to set this in HW.
 344                  */
 345                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 346
 347                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 348                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 349                         if (reg & DWC3_DCTL_INITU1ENA)
 350                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 351                         if (reg & DWC3_DCTL_INITU2ENA)
 352                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 353                 }
 354
 355                 break;
 356
 357         case USB_RECIP_INTERFACE:
 358                 /*
 359                  * Function Remote Wake Capable D0
 360                  * Function Remote Wakeup       D1
 361                  */
 362                 break;
 363
 364         case USB_RECIP_ENDPOINT:
 365                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 366                 if (!dep)
 367                         return -EINVAL;
 368
 369                 if (dep->flags & DWC3_EP_STALL)
 370                         usb_status = 1 << USB_ENDPOINT_HALT;
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         }
 375
 376         response_pkt = (__le16 *) dwc->setup_buf;
 377         *response_pkt = cpu_to_le16(usb_status);
 378
 379         dep = dwc->eps[0];
 380         dwc->ep0_usb_req.dep = dep;
 381         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 382         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 383         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 384
 385         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 386 }
 387
 388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 389                 struct usb_ctrlrequest *ctrl, int set)
 390 {
 391         struct dwc3_ep          *dep;
 392         u32                     recip;
 393         u32                     wValue;
 394         u32                     wIndex;
 395         u32                     reg;
 396         int                     ret;
 397         enum usb_device_state   state;
 398
 399         wValue = le16_to_cpu(ctrl->wValue);
 400         wIndex = le16_to_cpu(ctrl->wIndex);
 401         recip = ctrl->bRequestType & USB_RECIP_MASK;
 402         state = dwc->gadget.state;
 403
 404         switch (recip) {
 405         case USB_RECIP_DEVICE:
 406
 407                 switch (wValue) {
 408                 case USB_DEVICE_REMOTE_WAKEUP:
 409                         break;
 410                 /*
 411                  * 9.4.1 says only only for SS, in AddressState only for
 412                  * default control pipe
 413                  */
 414                 case USB_DEVICE_U1_ENABLE:
 415                         if (state != USB_STATE_CONFIGURED)
 416                                 return -EINVAL;
 417                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 418                                 return -EINVAL;
 419
 420                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 421                         if (set)
 422                                 reg |= DWC3_DCTL_INITU1ENA;
 423                         else
 424                                 reg &= ~DWC3_DCTL_INITU1ENA;
 425                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 426                         break;
 427
 428                 case USB_DEVICE_U2_ENABLE:
 429                         if (state != USB_STATE_CONFIGURED)
 430                                 return -EINVAL;
 431                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU2ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU2ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_LTM_ENABLE:
 443                         return -EINVAL;
 444                         break;
 445
 446                 case USB_DEVICE_TEST_MODE:
 447                         if ((wIndex & 0xff) != 0)
 448                                 return -EINVAL;
 449                         if (!set)
 450                                 return -EINVAL;
 451
 452                         dwc->test_mode_nr = wIndex >> 8;
 453                         dwc->test_mode = true;
 454                         break;
 455                 default:
 456                         return -EINVAL;
 457                 }
 458                 break;
 459
 460         case USB_RECIP_INTERFACE:
 461                 switch (wValue) {
 462                 case USB_INTRF_FUNC_SUSPEND:
 463                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 464                                 /* XXX enable Low power suspend */
 465                                 ;
 466                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 467                                 /* XXX enable remote wakeup */
 468                                 ;
 469                         break;
 470                 default:
 471                         return -EINVAL;
 472                 }
 473                 break;
 474
 475         case USB_RECIP_ENDPOINT:
 476                 switch (wValue) {
 477                 case USB_ENDPOINT_HALT:
 478                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 479                         if (!dep)
 480                                 return -EINVAL;
 481                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 482                                 break;
 483                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 484                         if (ret)
 485                                 return -EINVAL;
 486                         break;
 487                 default:
 488                         return -EINVAL;
 489                 }
 490                 break;
 491
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 500 {
 501         enum usb_device_state state = dwc->gadget.state;
 502         u32 addr;
 503         u32 reg;
 504
 505         addr = le16_to_cpu(ctrl->wValue);
 506         if (addr > 127) {
 507                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 508                 return -EINVAL;
 509         }
 510
 511         if (state == USB_STATE_CONFIGURED) {
 512                 dwc3_trace(trace_dwc3_ep0,
 513                                 "trying to set address when configured");
 514                 return -EINVAL;
 515         }
 516
 517         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 518         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 519         reg |= DWC3_DCFG_DEVADDR(addr);
 520         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 521
 522         if (addr)
 523                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 524         else
 525                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 526
 527         return 0;
 528 }
 529
 530 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 531 {
 532         int ret;
 533
 534         spin_unlock(&dwc->lock);
 535         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 536         spin_lock(&dwc->lock);
 537         return ret;
 538 }
 539
 540 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 541 {
 542         enum usb_device_state state = dwc->gadget.state;
 543         u32 cfg;
 544         int ret;
 545         u32 reg;
 546
 547         dwc->start_config_issued = false;
 548         cfg = le16_to_cpu(ctrl->wValue);
 549
 550         switch (state) {
 551         case USB_STATE_DEFAULT:
 552                 return -EINVAL;
 553                 break;
 554
 555         case USB_STATE_ADDRESS:
 556                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 557                 /* if the cfg matches and the cfg is non zero */
 558                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 559
 560                         /*
 561                          * only change state if set_config has already
 562                          * been processed. If gadget driver returns
 563                          * USB_GADGET_DELAYED_STATUS, we will wait
 564                          * to change the state on the next usb_ep_queue()
 565                          */
 566                         if (ret == 0)
 567                                 usb_gadget_set_state(&dwc->gadget,
 568                                                 USB_STATE_CONFIGURED);
 569
 570                         /*
 571                          * Enable transition to U1/U2 state when
 572                          * nothing is pending from application.
 573                          */
 574                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 575                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 576                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 577
 578                         dwc->resize_fifos = true;
 579                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 580                 }
 581                 break;
 582
 583         case USB_STATE_CONFIGURED:
 584                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 585                 if (!cfg && !ret)
 586                         usb_gadget_set_state(&dwc->gadget,
 587                                         USB_STATE_ADDRESS);
 588                 break;
 589         default:
 590                 ret = -EINVAL;
 591         }
 592         return ret;
 593 }
 594
 595 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 596 {
 597         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 598         struct dwc3     *dwc = dep->dwc;
 599
 600         u32             param = 0;
 601         u32             reg;
 602
 603         struct timing {
 604                 u8      u1sel;
 605                 u8      u1pel;
 606                 u16     u2sel;
 607                 u16     u2pel;
 608         } __packed timing;
 609
 610         int             ret;
 611
 612         memcpy(&timing, req->buf, sizeof(timing));
 613
 614         dwc->u1sel = timing.u1sel;
 615         dwc->u1pel = timing.u1pel;
 616         dwc->u2sel = le16_to_cpu(timing.u2sel);
 617         dwc->u2pel = le16_to_cpu(timing.u2pel);
 618
 619         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 620         if (reg & DWC3_DCTL_INITU2ENA)
 621                 param = dwc->u2pel;
 622         if (reg & DWC3_DCTL_INITU1ENA)
 623                 param = dwc->u1pel;
 624
 625         /*
 626          * According to Synopsys Databook, if parameter is
 627          * greater than 125, a value of zero should be
 628          * programmed in the register.
 629          */
 630         if (param > 125)
 631                 param = 0;
 632
 633         /* now that we have the time, issue DGCMD Set Sel */
 634         ret = dwc3_send_gadget_generic_command(dwc,
 635                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 636         WARN_ON(ret < 0);
 637 }
 638
 639 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 640 {
 641         struct dwc3_ep  *dep;
 642         enum usb_device_state state = dwc->gadget.state;
 643         u16             wLength;
 644         u16             wValue;
 645
 646         if (state == USB_STATE_DEFAULT)
 647                 return -EINVAL;
 648
 649         wValue = le16_to_cpu(ctrl->wValue);
 650         wLength = le16_to_cpu(ctrl->wLength);
 651
 652         if (wLength != 6) {
 653                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 654                                 wLength);
 655                 return -EINVAL;
 656         }
 657
 658         /*
 659          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 660          * queue a usb_request for 6 bytes.
 661          *
 662          * Remember, though, this controller can't handle non-wMaxPacketSize
 663          * aligned transfers on the OUT direction, so we queue a request for
 664          * wMaxPacketSize instead.
 665          */
 666         dep = dwc->eps[0];
 667         dwc->ep0_usb_req.dep = dep;
 668         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 669         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 670         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 671
 672         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 673 }
 674
 675 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 676 {
 677         u16             wLength;
 678         u16             wValue;
 679         u16             wIndex;
 680
 681         wValue = le16_to_cpu(ctrl->wValue);
 682         wLength = le16_to_cpu(ctrl->wLength);
 683         wIndex = le16_to_cpu(ctrl->wIndex);
 684
 685         if (wIndex || wLength)
 686                 return -EINVAL;
 687
 688         /*
 689          * REVISIT It's unclear from Databook what to do with this
 690          * value. For now, just cache it.
 691          */
 692         dwc->isoch_delay = wValue;
 693
 694         return 0;
 695 }
 696
 697 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 698 {
 699         int ret;
 700
 701         switch (ctrl->bRequest) {
 702         case USB_REQ_GET_STATUS:
 703                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS\n");
 704                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 705                 break;
 706         case USB_REQ_CLEAR_FEATURE:
 707                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE\n");
 708                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 709                 break;
 710         case USB_REQ_SET_FEATURE:
 711                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE\n");
 712                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 713                 break;
 714         case USB_REQ_SET_ADDRESS:
 715                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS\n");
 716                 ret = dwc3_ep0_set_address(dwc, ctrl);
 717                 break;
 718         case USB_REQ_SET_CONFIGURATION:
 719                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION\n");
 720                 ret = dwc3_ep0_set_config(dwc, ctrl);
 721                 break;
 722         case USB_REQ_SET_SEL:
 723                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL\n");
 724                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 725                 break;
 726         case USB_REQ_SET_ISOCH_DELAY:
 727                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY\n");
 728                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 729                 break;
 730         default:
 731                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver\n");
 732                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 733                 break;
 734         }
 735
 736         return ret;
 737 }
 738
 739 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 740                 const struct dwc3_event_depevt *event)
 741 {
 742         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 743         int ret = -EINVAL;
 744         u32 len;
 745
 746         if (!dwc->gadget_driver)
 747                 goto out;
 748
 749         trace_dwc3_ctrl_req(ctrl);
 750
 751         len = le16_to_cpu(ctrl->wLength);
 752         if (!len) {
 753                 dwc->three_stage_setup = false;
 754                 dwc->ep0_expect_in = false;
 755                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 756         } else {
 757                 dwc->three_stage_setup = true;
 758                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 759                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 760         }
 761
 762         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 763                 ret = dwc3_ep0_std_request(dwc, ctrl);
 764         else
 765                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 766
 767         if (ret == USB_GADGET_DELAYED_STATUS)
 768                 dwc->delayed_status = true;
 769
 770 out:
 771         if (ret < 0)
 772                 dwc3_ep0_stall_and_restart(dwc);
 773 }
 774
 775 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 776                 const struct dwc3_event_depevt *event)
 777 {
 778         struct dwc3_request     *r = NULL;
 779         struct usb_request      *ur;
 780         struct dwc3_trb         *trb;
 781         struct dwc3_ep          *ep0;
 782         u32                     transferred;
 783         u32                     status;
 784         u32                     length;
 785         u8                      epnum;
 786
 787         epnum = event->endpoint_number;
 788         ep0 = dwc->eps[0];
 789
 790         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 791
 792         trb = dwc->ep0_trb;
 793
 794         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 795         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 796                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 797
 798                 if (r)
 799                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 800
 801                 return;
 802         }
 803
 804         r = next_request(&ep0->request_list);
 805         if (!r)
 806                 return;
 807
 808         ur = &r->request;
 809
 810         length = trb->size & DWC3_TRB_SIZE_MASK;
 811
 812         if (dwc->ep0_bounced) {
 813                 unsigned transfer_size = ur->length;
 814                 unsigned maxp = ep0->endpoint.maxpacket;
 815
 816                 transfer_size += (maxp - (transfer_size % maxp));
 817                 transferred = min_t(u32, ur->length,
 818                                 transfer_size - length);
 819                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 820         } else {
 821                 transferred = ur->length - length;
 822         }
 823
 824         ur->actual += transferred;
 825
 826         if ((epnum & 1) && ur->actual < ur->length) {
 827                 /* for some reason we did not get everything out */
 828
 829                 dwc3_ep0_stall_and_restart(dwc);
 830         } else {
 831                 dwc3_gadget_giveback(ep0, r, 0);
 832
 833                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 834                                 ur->length && ur->zero) {
 835                         int ret;
 836
 837                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 838
 839                         ret = dwc3_ep0_start_trans(dwc, epnum,
 840                                         dwc->ctrl_req_addr, 0,
 841                                         DWC3_TRBCTL_CONTROL_DATA);
 842                         WARN_ON(ret < 0);
 843                 }
 844         }
 845 }
 846
 847 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 848                 const struct dwc3_event_depevt *event)
 849 {
 850         struct dwc3_request     *r;
 851         struct dwc3_ep          *dep;
 852         struct dwc3_trb         *trb;
 853         u32                     status;
 854
 855         dep = dwc->eps[0];
 856         trb = dwc->ep0_trb;
 857
 858         if (!list_empty(&dep->request_list)) {
 859                 r = next_request(&dep->request_list);
 860
 861                 dwc3_gadget_giveback(dep, r, 0);
 862         }
 863
 864         if (dwc->test_mode) {
 865                 int ret;
 866
 867                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 868                 if (ret < 0) {
 869                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 870                                         dwc->test_mode_nr);
 871                         dwc3_ep0_stall_and_restart(dwc);
 872                         return;
 873                 }
 874         }
 875
 876         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 877         if (status == DWC3_TRBSTS_SETUP_PENDING)
 878                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received\n");
 879
 880         dwc->ep0state = EP0_SETUP_PHASE;
 881         dwc3_ep0_out_start(dwc);
 882 }
 883
 884 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 885                         const struct dwc3_event_depevt *event)
 886 {
 887         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 888
 889         dep->flags &= ~DWC3_EP_BUSY;
 890         dep->resource_index = 0;
 891         dwc->setup_packet_pending = false;
 892
 893         switch (dwc->ep0state) {
 894         case EP0_SETUP_PHASE:
 895                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 896                 dwc3_ep0_inspect_setup(dwc, event);
 897                 break;
 898
 899         case EP0_DATA_PHASE:
 900                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 901                 dwc3_ep0_complete_data(dwc, event);
 902                 break;
 903
 904         case EP0_STATUS_PHASE:
 905                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 906                 dwc3_ep0_complete_status(dwc, event);
 907                 break;
 908         default:
 909                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 910         }
 911 }
 912
 913 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 914                 struct dwc3_ep *dep, struct dwc3_request *req)
 915 {
 916         int                     ret;
 917
 918         req->direction = !!dep->number;
 919
 920         if (req->request.length == 0) {
 921                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 922                                 dwc->ctrl_req_addr, 0,
 923                                 DWC3_TRBCTL_CONTROL_DATA);
 924         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 925                         && (dep->number == 0)) {
 926                 u32     transfer_size;
 927                 u32     maxpacket;
 928
 929                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 930                                 dep->number);
 931                 if (ret) {
 932                         dev_dbg(dwc->dev, "failed to map request\n");
 933                         return;
 934                 }
 935
 936                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 937
 938                 maxpacket = dep->endpoint.maxpacket;
 939                 transfer_size = roundup(req->request.length, maxpacket);
 940
 941                 dwc->ep0_bounced = true;
 942
 943                 /*
 944                  * REVISIT in case request length is bigger than
 945                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 946                  * TRBs to handle the transfer.
 947                  */
 948                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 949                                 dwc->ep0_bounce_addr, transfer_size,
 950                                 DWC3_TRBCTL_CONTROL_DATA);
 951         } else {
 952                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 953                                 dep->number);
 954                 if (ret) {
 955                         dev_dbg(dwc->dev, "failed to map request\n");
 956                         return;
 957                 }
 958
 959                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 960                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 961         }
 962
 963         WARN_ON(ret < 0);
 964 }
 965
 966 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 967 {
 968         struct dwc3             *dwc = dep->dwc;
 969         u32                     type;
 970
 971         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 972                 : DWC3_TRBCTL_CONTROL_STATUS2;
 973
 974         return dwc3_ep0_start_trans(dwc, dep->number,
 975                         dwc->ctrl_req_addr, 0, type);
 976 }
 977
 978 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 979 {
 980         if (dwc->resize_fifos) {
 981                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
 982                 dwc3_gadget_resize_tx_fifos(dwc);
 983                 dwc->resize_fifos = 0;
 984         }
 985
 986         WARN_ON(dwc3_ep0_start_control_status(dep));
 987 }
 988
 989 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 990                 const struct dwc3_event_depevt *event)
 991 {
 992         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 993
 994         __dwc3_ep0_do_control_status(dwc, dep);
 995 }
 996
 997 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
 998 {
 999         struct dwc3_gadget_ep_cmd_params params;
1000         u32                     cmd;
1001         int                     ret;
1002
1003         if (!dep->resource_index)
1004                 return;
1005
1006         cmd = DWC3_DEPCMD_ENDTRANSFER;
1007         cmd |= DWC3_DEPCMD_CMDIOC;
1008         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1009         memset(&params, 0, sizeof(params));
1010         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1011         WARN_ON_ONCE(ret);
1012         dep->resource_index = 0;
1013 }
1014
1015 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1016                 const struct dwc3_event_depevt *event)
1017 {
1018         dwc->setup_packet_pending = true;
1019
1020         switch (event->status) {
1021         case DEPEVT_STATUS_CONTROL_DATA:
1022                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1023
1024                 /*
1025                  * We already have a DATA transfer in the controller's cache,
1026                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1027                  * it's for the wrong direction.
1028                  *
1029                  * In that case, we must issue END_TRANSFER command to the Data
1030                  * Phase we already have started and issue SetStall on the
1031                  * control endpoint.
1032                  */
1033                 if (dwc->ep0_expect_in != event->endpoint_number) {
1034                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1035
1036                         dwc3_trace(trace_dwc3_ep0,
1037                                         "Wrong direction for Data phase");
1038                         dwc3_ep0_end_control_data(dwc, dep);
1039                         dwc3_ep0_stall_and_restart(dwc);
1040                         return;
1041                 }
1042
1043                 break;
1044
1045         case DEPEVT_STATUS_CONTROL_STATUS:
1046                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1047                         return;
1048
1049                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1050
1051                 dwc->ep0state = EP0_STATUS_PHASE;
1052
1053                 if (dwc->delayed_status) {
1054                         WARN_ON_ONCE(event->endpoint_number != 1);
1055                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1056                         return;
1057                 }
1058
1059                 dwc3_ep0_do_control_status(dwc, event);
1060         }
1061 }
1062
1063 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1064                 const struct dwc3_event_depevt *event)
1065 {
1066         u8                      epnum = event->endpoint_number;
1067
1068         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1069                         dwc3_ep_event_string(event->endpoint_event),
1070                         epnum >> 1, (epnum & 1) ? "in" : "out",
1071                         dwc3_ep0_state_string(dwc->ep0state));
1072
1073         switch (event->endpoint_event) {
1074         case DWC3_DEPEVT_XFERCOMPLETE:
1075                 dwc3_ep0_xfer_complete(dwc, event);
1076                 break;
1077
1078         case DWC3_DEPEVT_XFERNOTREADY:
1079                 dwc3_ep0_xfernotready(dwc, event);
1080                 break;
1081
1082         case DWC3_DEPEVT_XFERINPROGRESS:
1083         case DWC3_DEPEVT_RXTXFIFOEVT:
1084         case DWC3_DEPEVT_STREAMEVT:
1085         case DWC3_DEPEVT_EPCMDCMPLT:
1086                 break;
1087         }
1088 }