drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51
  52 #include "core.h"
  53 #include "gadget.h"
  54 #include "io.h"
  55
  56 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  57                 const struct dwc3_event_depevt *event);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb_hw              *trb_hw;
  80         struct dwc3_trb                 trb;
  81         struct dwc3_ep                  *dep;
  82
  83         int                             ret;
  84
  85         dep = dwc->eps[epnum];
  86         if (dep->flags & DWC3_EP_BUSY) {
  87                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  88                 return 0;
  89         }
  90
  91         trb_hw = dwc->ep0_trb;
  92         memset(&trb, 0, sizeof(trb));
  93
  94         trb.trbctl = type;
  95         trb.bplh = buf_dma;
  96         trb.length = len;
  97
  98         trb.hwo = 1;
  99         trb.lst = 1;
 100         trb.ioc = 1;
 101         trb.isp_imi = 1;
 102
 103         dwc3_trb_to_hw(&trb, trb_hw);
 104
 105         memset(&params, 0, sizeof(params));
 106         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 107         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 108
 109         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 110                         DWC3_DEPCMD_STARTTRANSFER, &params);
 111         if (ret < 0) {
 112                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 113                 return ret;
 114         }
 115
 116         dep->flags |= DWC3_EP_BUSY;
 117         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 118                         dep->number);
 119
 120         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 121
 122         return 0;
 123 }
 124
 125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 126                 struct dwc3_request *req)
 127 {
 128         int                     ret = 0;
 129
 130         req->request.actual     = 0;
 131         req->request.status     = -EINPROGRESS;
 132         req->epnum              = dep->number;
 133
 134         list_add_tail(&req->list, &dep->request_list);
 135
 136         /*
 137          * Gadget driver might not be quick enough to queue a request
 138          * before we get a Transfer Not Ready event on this endpoint.
 139          *
 140          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 141          * flag is set, it's telling us that as soon as Gadget queues the
 142          * required request, we should kick the transfer here because the
 143          * IRQ we were waiting for is long gone.
 144          */
 145         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 146                 struct dwc3     *dwc = dep->dwc;
 147                 unsigned        direction;
 148                 u32             type;
 149
 150                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 151
 152                 if (dwc->ep0state == EP0_STATUS_PHASE) {
 153                         type = dwc->three_stage_setup
 154                                 ? DWC3_TRBCTL_CONTROL_STATUS3
 155                                 : DWC3_TRBCTL_CONTROL_STATUS2;
 156                 } else if (dwc->ep0state == EP0_DATA_PHASE) {
 157                         type = DWC3_TRBCTL_CONTROL_DATA;
 158                 } else {
 159                         /* should never happen */
 160                         WARN_ON(1);
 161                         return 0;
 162                 }
 163
 164                 ret = dwc3_ep0_start_trans(dwc, direction,
 165                                 req->request.dma, req->request.length, type);
 166                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 167                                 DWC3_EP0_DIR_IN);
 168         }
 169
 170         return ret;
 171 }
 172
 173 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 174                 gfp_t gfp_flags)
 175 {
 176         struct dwc3_request             *req = to_dwc3_request(request);
 177         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 178         struct dwc3                     *dwc = dep->dwc;
 179
 180         unsigned long                   flags;
 181
 182         int                             ret;
 183
 184         spin_lock_irqsave(&dwc->lock, flags);
 185         if (!dep->desc) {
 186                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 187                                 request, dep->name);
 188                 ret = -ESHUTDOWN;
 189                 goto out;
 190         }
 191
 192         /* we share one TRB for ep0/1 */
 193         if (!list_empty(&dep->request_list)) {
 194                 ret = -EBUSY;
 195                 goto out;
 196         }
 197
 198         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 199                         request, dep->name, request->length,
 200                         dwc3_ep0_state_string(dwc->ep0state));
 201
 202         ret = __dwc3_gadget_ep0_queue(dep, req);
 203
 204 out:
 205         spin_unlock_irqrestore(&dwc->lock, flags);
 206
 207         return ret;
 208 }
 209
 210 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 211 {
 212         struct dwc3_ep          *dep = dwc->eps[0];
 213
 214         /* stall is always issued on EP0 */
 215         __dwc3_gadget_ep_set_halt(dep, 1);
 216         dep->flags = DWC3_EP_ENABLED;
 217
 218         if (!list_empty(&dep->request_list)) {
 219                 struct dwc3_request     *req;
 220
 221                 req = next_request(&dep->request_list);
 222                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 223         }
 224
 225         dwc->ep0state = EP0_SETUP_PHASE;
 226         dwc3_ep0_out_start(dwc);
 227 }
 228
 229 void dwc3_ep0_out_start(struct dwc3 *dwc)
 230 {
 231         int                             ret;
 232
 233         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 234                         DWC3_TRBCTL_CONTROL_SETUP);
 235         WARN_ON(ret < 0);
 236 }
 237
 238 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 239 {
 240         struct dwc3_ep          *dep;
 241         u32                     windex = le16_to_cpu(wIndex_le);
 242         u32                     epnum;
 243
 244         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 245         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 246                 epnum |= 1;
 247
 248         dep = dwc->eps[epnum];
 249         if (dep->flags & DWC3_EP_ENABLED)
 250                 return dep;
 251
 252         return NULL;
 253 }
 254
 255 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 256 {
 257 }
 258 /*
 259  * ch 9.4.5
 260  */
 261 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 262                 struct usb_ctrlrequest *ctrl)
 263 {
 264         struct dwc3_ep          *dep;
 265         u32                     recip;
 266         u16                     usb_status = 0;
 267         __le16                  *response_pkt;
 268
 269         recip = ctrl->bRequestType & USB_RECIP_MASK;
 270         switch (recip) {
 271         case USB_RECIP_DEVICE:
 272                 /*
 273                  * We are self-powered. U1/U2/LTM will be set later
 274                  * once we handle this states. RemoteWakeup is 0 on SS
 275                  */
 276                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 277                 break;
 278
 279         case USB_RECIP_INTERFACE:
 280                 /*
 281                  * Function Remote Wake Capable D0
 282                  * Function Remote Wakeup       D1
 283                  */
 284                 break;
 285
 286         case USB_RECIP_ENDPOINT:
 287                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 288                 if (!dep)
 289                         return -EINVAL;
 290
 291                 if (dep->flags & DWC3_EP_STALL)
 292                         usb_status = 1 << USB_ENDPOINT_HALT;
 293                 break;
 294         default:
 295                 return -EINVAL;
 296         };
 297
 298         response_pkt = (__le16 *) dwc->setup_buf;
 299         *response_pkt = cpu_to_le16(usb_status);
 300         dwc->ep0_usb_req.length = sizeof(*response_pkt);
 301         dwc->ep0_usb_req.dma = dwc->setup_buf_addr;
 302         dwc->ep0_usb_req.complete = dwc3_ep0_status_cmpl;
 303         return usb_ep_queue(&dwc->eps[0]->endpoint, &dwc->ep0_usb_req,
 304                         GFP_ATOMIC);
 305 }
 306
 307 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 308                 struct usb_ctrlrequest *ctrl, int set)
 309 {
 310         struct dwc3_ep          *dep;
 311         u32                     recip;
 312         u32                     wValue;
 313         u32                     wIndex;
 314         u32                     reg;
 315         int                     ret;
 316         u32                     mode;
 317
 318         wValue = le16_to_cpu(ctrl->wValue);
 319         wIndex = le16_to_cpu(ctrl->wIndex);
 320         recip = ctrl->bRequestType & USB_RECIP_MASK;
 321         switch (recip) {
 322         case USB_RECIP_DEVICE:
 323
 324                 /*
 325                  * 9.4.1 says only only for SS, in AddressState only for
 326                  * default control pipe
 327                  */
 328                 switch (wValue) {
 329                 case USB_DEVICE_U1_ENABLE:
 330                 case USB_DEVICE_U2_ENABLE:
 331                 case USB_DEVICE_LTM_ENABLE:
 332                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 333                                 return -EINVAL;
 334                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 335                                 return -EINVAL;
 336                 }
 337
 338                 /* XXX add U[12] & LTM */
 339                 switch (wValue) {
 340                 case USB_DEVICE_REMOTE_WAKEUP:
 341                         break;
 342                 case USB_DEVICE_U1_ENABLE:
 343                         break;
 344                 case USB_DEVICE_U2_ENABLE:
 345                         break;
 346                 case USB_DEVICE_LTM_ENABLE:
 347                         break;
 348
 349                 case USB_DEVICE_TEST_MODE:
 350                         if ((wIndex & 0xff) != 0)
 351                                 return -EINVAL;
 352                         if (!set)
 353                                 return -EINVAL;
 354
 355                         mode = wIndex >> 8;
 356                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 357                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 358
 359                         switch (mode) {
 360                         case TEST_J:
 361                         case TEST_K:
 362                         case TEST_SE0_NAK:
 363                         case TEST_PACKET:
 364                         case TEST_FORCE_EN:
 365                                 reg |= mode << 1;
 366                                 break;
 367                         default:
 368                                 return -EINVAL;
 369                         }
 370                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 371                         break;
 372                 default:
 373                         return -EINVAL;
 374                 }
 375                 break;
 376
 377         case USB_RECIP_INTERFACE:
 378                 switch (wValue) {
 379                 case USB_INTRF_FUNC_SUSPEND:
 380                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 381                                 /* XXX enable Low power suspend */
 382                                 ;
 383                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 384                                 /* XXX enable remote wakeup */
 385                                 ;
 386                         break;
 387                 default:
 388                         return -EINVAL;
 389                 }
 390                 break;
 391
 392         case USB_RECIP_ENDPOINT:
 393                 switch (wValue) {
 394                 case USB_ENDPOINT_HALT:
 395                         dep =  dwc3_wIndex_to_dep(dwc, wIndex);
 396                         if (!dep)
 397                                 return -EINVAL;
 398                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 399                         if (ret)
 400                                 return -EINVAL;
 401                         break;
 402                 default:
 403                         return -EINVAL;
 404                 }
 405                 break;
 406
 407         default:
 408                 return -EINVAL;
 409         };
 410
 411         return 0;
 412 }
 413
 414 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 415 {
 416         u32 addr;
 417         u32 reg;
 418
 419         addr = le16_to_cpu(ctrl->wValue);
 420         if (addr > 127) {
 421                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 422                 return -EINVAL;
 423         }
 424
 425         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 426                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 427                 return -EINVAL;
 428         }
 429
 430         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 431         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 432         reg |= DWC3_DCFG_DEVADDR(addr);
 433         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 434
 435         if (addr)
 436                 dwc->dev_state = DWC3_ADDRESS_STATE;
 437         else
 438                 dwc->dev_state = DWC3_DEFAULT_STATE;
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 444 {
 445         int ret;
 446
 447         spin_unlock(&dwc->lock);
 448         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 449         spin_lock(&dwc->lock);
 450         return ret;
 451 }
 452
 453 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 454 {
 455         u32 cfg;
 456         int ret;
 457
 458         dwc->start_config_issued = false;
 459         cfg = le16_to_cpu(ctrl->wValue);
 460
 461         switch (dwc->dev_state) {
 462         case DWC3_DEFAULT_STATE:
 463                 return -EINVAL;
 464                 break;
 465
 466         case DWC3_ADDRESS_STATE:
 467                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 468                 /* if the cfg matches and the cfg is non zero */
 469                 if (!ret && cfg)
 470                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 471                 break;
 472
 473         case DWC3_CONFIGURED_STATE:
 474                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 475                 if (!cfg)
 476                         dwc->dev_state = DWC3_ADDRESS_STATE;
 477                 break;
 478         }
 479         return 0;
 480 }
 481
 482 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 483 {
 484         int ret;
 485
 486         switch (ctrl->bRequest) {
 487         case USB_REQ_GET_STATUS:
 488                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 489                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 490                 break;
 491         case USB_REQ_CLEAR_FEATURE:
 492                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 493                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 494                 break;
 495         case USB_REQ_SET_FEATURE:
 496                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 497                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 498                 break;
 499         case USB_REQ_SET_ADDRESS:
 500                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 501                 ret = dwc3_ep0_set_address(dwc, ctrl);
 502                 break;
 503         case USB_REQ_SET_CONFIGURATION:
 504                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 505                 ret = dwc3_ep0_set_config(dwc, ctrl);
 506                 break;
 507         default:
 508                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 509                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 510                 break;
 511         };
 512
 513         return ret;
 514 }
 515
 516 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 517                 const struct dwc3_event_depevt *event)
 518 {
 519         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 520         int ret;
 521         u32 len;
 522
 523         if (!dwc->gadget_driver)
 524                 goto err;
 525
 526         len = le16_to_cpu(ctrl->wLength);
 527         if (!len) {
 528                 dwc->three_stage_setup = false;
 529                 dwc->ep0_expect_in = false;
 530                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 531         } else {
 532                 dwc->three_stage_setup = true;
 533                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 534                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 535         }
 536
 537         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 538                 ret = dwc3_ep0_std_request(dwc, ctrl);
 539         else
 540                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 541
 542         if (ret >= 0)
 543                 return;
 544
 545 err:
 546         dwc3_ep0_stall_and_restart(dwc);
 547 }
 548
 549 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 550                 const struct dwc3_event_depevt *event)
 551 {
 552         struct dwc3_request     *r = NULL;
 553         struct usb_request      *ur;
 554         struct dwc3_trb         trb;
 555         struct dwc3_ep          *ep0;
 556         u32                     transferred;
 557         u8                      epnum;
 558
 559         epnum = event->endpoint_number;
 560         ep0 = dwc->eps[0];
 561
 562         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 563
 564         r = next_request(&ep0->request_list);
 565         ur = &r->request;
 566
 567         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 568
 569         if (dwc->ep0_bounced) {
 570
 571                 transferred = min_t(u32, ur->length,
 572                                 ep0->endpoint.maxpacket - trb.length);
 573                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 574                 dwc->ep0_bounced = false;
 575         } else {
 576                 transferred = ur->length - trb.length;
 577                 ur->actual += transferred;
 578         }
 579
 580         if ((epnum & 1) && ur->actual < ur->length) {
 581                 /* for some reason we did not get everything out */
 582
 583                 dwc3_ep0_stall_and_restart(dwc);
 584         } else {
 585                 /*
 586                  * handle the case where we have to send a zero packet. This
 587                  * seems to be case when req.length > maxpacket. Could it be?
 588                  */
 589                 if (r)
 590                         dwc3_gadget_giveback(ep0, r, 0);
 591         }
 592 }
 593
 594 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 595                 const struct dwc3_event_depevt *event)
 596 {
 597         struct dwc3_request     *r;
 598         struct dwc3_ep          *dep;
 599
 600         dep = dwc->eps[0];
 601
 602         if (!list_empty(&dep->request_list)) {
 603                 r = next_request(&dep->request_list);
 604
 605                 dwc3_gadget_giveback(dep, r, 0);
 606         }
 607
 608         dwc->ep0state = EP0_SETUP_PHASE;
 609         dwc3_ep0_out_start(dwc);
 610 }
 611
 612 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 613                         const struct dwc3_event_depevt *event)
 614 {
 615         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 616
 617         dep->flags &= ~DWC3_EP_BUSY;
 618
 619         switch (dwc->ep0state) {
 620         case EP0_SETUP_PHASE:
 621                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 622                 dwc3_ep0_inspect_setup(dwc, event);
 623                 break;
 624
 625         case EP0_DATA_PHASE:
 626                 dev_vdbg(dwc->dev, "Data Phase\n");
 627                 dwc3_ep0_complete_data(dwc, event);
 628                 break;
 629
 630         case EP0_STATUS_PHASE:
 631                 dev_vdbg(dwc->dev, "Status Phase\n");
 632                 dwc3_ep0_complete_req(dwc, event);
 633                 break;
 634         default:
 635                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 636         }
 637 }
 638
 639 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 640                 const struct dwc3_event_depevt *event)
 641 {
 642         dwc->ep0state = EP0_SETUP_PHASE;
 643         dwc3_ep0_out_start(dwc);
 644 }
 645
 646 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 647                 const struct dwc3_event_depevt *event)
 648 {
 649         struct dwc3_ep          *dep;
 650         struct dwc3_request     *req;
 651         int                     ret;
 652
 653         dep = dwc->eps[0];
 654         dwc->ep0state = EP0_DATA_PHASE;
 655
 656         if (list_empty(&dep->request_list)) {
 657                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 658                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 659
 660                 if (event->endpoint_number)
 661                         dep->flags |= DWC3_EP0_DIR_IN;
 662                 return;
 663         }
 664
 665         req = next_request(&dep->request_list);
 666         req->direction = !!event->endpoint_number;
 667
 668         dwc->ep0state = EP0_DATA_PHASE;
 669         if (req->request.length == 0) {
 670                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 671                                 dwc->ctrl_req_addr, 0,
 672                                 DWC3_TRBCTL_CONTROL_DATA);
 673         } else if ((req->request.length % dep->endpoint.maxpacket)
 674                         && (event->endpoint_number == 0)) {
 675                 dwc3_map_buffer_to_dma(req);
 676
 677                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 678
 679                 dwc->ep0_bounced = true;
 680
 681                 /*
 682                  * REVISIT in case request length is bigger than EP0
 683                  * wMaxPacketSize, we will need two chained TRBs to handle
 684                  * the transfer.
 685                  */
 686                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 687                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 688                                 DWC3_TRBCTL_CONTROL_DATA);
 689         } else {
 690                 dwc3_map_buffer_to_dma(req);
 691
 692                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 693                                 req->request.dma, req->request.length,
 694                                 DWC3_TRBCTL_CONTROL_DATA);
 695         }
 696
 697         WARN_ON(ret < 0);
 698 }
 699
 700 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 701                 const struct dwc3_event_depevt *event)
 702 {
 703         u32                     type;
 704         int                     ret;
 705
 706         dwc->ep0state = EP0_STATUS_PHASE;
 707
 708         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 709                 : DWC3_TRBCTL_CONTROL_STATUS2;
 710
 711         ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 712                         dwc->ctrl_req_addr, 0, type);
 713
 714         WARN_ON(ret < 0);
 715 }
 716
 717 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 718                 const struct dwc3_event_depevt *event)
 719 {
 720         /*
 721          * This part is very tricky: If we has just handled
 722          * XferNotReady(Setup) and we're now expecting a
 723          * XferComplete but, instead, we receive another
 724          * XferNotReady(Setup), we should STALL and restart
 725          * the state machine.
 726          *
 727          * In all other cases, we just continue waiting
 728          * for the XferComplete event.
 729          *
 730          * We are a little bit unsafe here because we're
 731          * not trying to ensure that last event was, indeed,
 732          * XferNotReady(Setup).
 733          *
 734          * Still, we don't expect any condition where that
 735          * should happen and, even if it does, it would be
 736          * another error condition.
 737          */
 738         if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
 739                 switch (event->status) {
 740                 case DEPEVT_STATUS_CONTROL_SETUP:
 741                         dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
 742                         dwc3_ep0_stall_and_restart(dwc);
 743                         break;
 744                 case DEPEVT_STATUS_CONTROL_DATA:
 745                         /* FALLTHROUGH */
 746                 case DEPEVT_STATUS_CONTROL_STATUS:
 747                         /* FALLTHROUGH */
 748                 default:
 749                         dev_vdbg(dwc->dev, "waiting for XferComplete\n");
 750                 }
 751
 752                 return;
 753         }
 754
 755         switch (event->status) {
 756         case DEPEVT_STATUS_CONTROL_SETUP:
 757                 dev_vdbg(dwc->dev, "Control Setup\n");
 758                 dwc3_ep0_do_control_setup(dwc, event);
 759                 break;
 760
 761         case DEPEVT_STATUS_CONTROL_DATA:
 762                 dev_vdbg(dwc->dev, "Control Data\n");
 763
 764                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 765                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 766                                         dwc->ep0_next_event,
 767                                         DWC3_EP0_NRDY_DATA);
 768
 769                         dwc3_ep0_stall_and_restart(dwc);
 770                         return;
 771                 }
 772
 773                 /*
 774                  * One of the possible error cases is when Host _does_
 775                  * request for Data Phase, but it does so on the wrong
 776                  * direction.
 777                  *
 778                  * Here, we already know ep0_next_event is DATA (see above),
 779                  * so we only need to check for direction.
 780                  */
 781                 if (dwc->ep0_expect_in != event->endpoint_number) {
 782                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 783                         dwc3_ep0_stall_and_restart(dwc);
 784                         return;
 785                 }
 786
 787                 dwc3_ep0_do_control_data(dwc, event);
 788                 break;
 789
 790         case DEPEVT_STATUS_CONTROL_STATUS:
 791                 dev_vdbg(dwc->dev, "Control Status\n");
 792
 793                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 794                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 795                                         dwc->ep0_next_event,
 796                                         DWC3_EP0_NRDY_STATUS);
 797
 798                         dwc3_ep0_stall_and_restart(dwc);
 799                         return;
 800                 }
 801                 dwc3_ep0_do_control_status(dwc, event);
 802         }
 803 }
 804
 805 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 806                 const const struct dwc3_event_depevt *event)
 807 {
 808         u8                      epnum = event->endpoint_number;
 809
 810         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 811                         dwc3_ep_event_string(event->endpoint_event),
 812                         epnum >> 1, (epnum & 1) ? "in" : "out",
 813                         dwc3_ep0_state_string(dwc->ep0state));
 814
 815         switch (event->endpoint_event) {
 816         case DWC3_DEPEVT_XFERCOMPLETE:
 817                 dwc3_ep0_xfer_complete(dwc, event);
 818                 break;
 819
 820         case DWC3_DEPEVT_XFERNOTREADY:
 821                 dwc3_ep0_xfernotready(dwc, event);
 822                 break;
 823
 824         case DWC3_DEPEVT_XFERINPROGRESS:
 825         case DWC3_DEPEVT_RXTXFIFOEVT:
 826         case DWC3_DEPEVT_STREAMEVT:
 827         case DWC3_DEPEVT_EPCMDCMPLT:
 828                 break;
 829         }
 830 }