2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
70 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
71 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
85 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
103 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
104 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
106 /* set requested state */
107 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
108 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
110 /* wait for a change in DSTS */
112 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
114 if (DWC3_DSTS_USBLNKST(reg
) == state
)
120 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
126 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
127 * @dwc: pointer to our context structure
129 * This function will a best effort FIFO allocation in order
130 * to improve FIFO usage and throughput, while still allowing
131 * us to enable as many endpoints as possible.
133 * Keep in mind that this operation will be highly dependent
134 * on the configured size for RAM1 - which contains TxFifo -,
135 * the amount of endpoints enabled on coreConsultant tool, and
136 * the width of the Master Bus.
138 * In the ideal world, we would always be able to satisfy the
139 * following equation:
141 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
142 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
144 * Unfortunately, due to many variables that's not always the case.
146 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
148 int last_fifo_depth
= 0;
154 if (!dwc
->needs_fifo_resize
)
157 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
158 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
160 /* MDWIDTH is represented in bits, we need it in bytes */
164 * FIXME For now we will only allocate 1 wMaxPacketSize space
165 * for each enabled endpoint, later patches will come to
166 * improve this algorithm so that we better use the internal
169 for (num
= 0; num
< DWC3_ENDPOINTS_NUM
; num
++) {
170 struct dwc3_ep
*dep
= dwc
->eps
[num
];
171 int fifo_number
= dep
->number
>> 1;
175 if (!(dep
->number
& 1))
178 if (!(dep
->flags
& DWC3_EP_ENABLED
))
181 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
182 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
186 * REVISIT: the following assumes we will always have enough
187 * space available on the FIFO RAM for all possible use cases.
188 * Make sure that's true somehow and change FIFO allocation
191 * If we have Bulk or Isochronous endpoints, we want
192 * them to be able to be very, very fast. So we're giving
193 * those endpoints a fifo_size which is enough for 3 full
196 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
199 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
201 fifo_size
|= (last_fifo_depth
<< 16);
203 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
204 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
206 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(fifo_number
),
209 last_fifo_depth
+= (fifo_size
& 0xffff);
215 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
218 struct dwc3
*dwc
= dep
->dwc
;
221 if (req
->request
.num_mapped_sgs
)
222 dep
->busy_slot
+= req
->request
.num_mapped_sgs
;
227 * Skip LINK TRB. We can't use req->trb and check for
228 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
229 * completed (not the LINK TRB).
231 if (((dep
->busy_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
232 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
235 list_del(&req
->list
);
238 if (req
->request
.status
== -EINPROGRESS
)
239 req
->request
.status
= status
;
241 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
244 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
245 req
, dep
->name
, req
->request
.actual
,
246 req
->request
.length
, status
);
248 spin_unlock(&dwc
->lock
);
249 req
->request
.complete(&dep
->endpoint
, &req
->request
);
250 spin_lock(&dwc
->lock
);
253 static const char *dwc3_gadget_ep_cmd_string(u8 cmd
)
256 case DWC3_DEPCMD_DEPSTARTCFG
:
257 return "Start New Configuration";
258 case DWC3_DEPCMD_ENDTRANSFER
:
259 return "End Transfer";
260 case DWC3_DEPCMD_UPDATETRANSFER
:
261 return "Update Transfer";
262 case DWC3_DEPCMD_STARTTRANSFER
:
263 return "Start Transfer";
264 case DWC3_DEPCMD_CLEARSTALL
:
265 return "Clear Stall";
266 case DWC3_DEPCMD_SETSTALL
:
268 case DWC3_DEPCMD_GETSEQNUMBER
:
269 return "Get Data Sequence Number";
270 case DWC3_DEPCMD_SETTRANSFRESOURCE
:
271 return "Set Endpoint Transfer Resource";
272 case DWC3_DEPCMD_SETEPCONFIG
:
273 return "Set Endpoint Configuration";
275 return "UNKNOWN command";
279 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, int cmd
, u32 param
)
284 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
285 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
288 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
289 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
290 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
291 DWC3_DGCMD_STATUS(reg
));
296 * We can't sleep here, because it's also called from
306 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
307 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
309 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
313 dev_vdbg(dwc
->dev
, "%s: cmd '%s' params %08x %08x %08x\n",
315 dwc3_gadget_ep_cmd_string(cmd
), params
->param0
,
316 params
->param1
, params
->param2
);
318 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
319 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
320 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
322 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
324 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
325 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
326 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
327 DWC3_DEPCMD_STATUS(reg
));
332 * We can't sleep here, because it is also called from
343 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
344 struct dwc3_trb
*trb
)
346 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
348 return dep
->trb_pool_dma
+ offset
;
351 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
353 struct dwc3
*dwc
= dep
->dwc
;
358 if (dep
->number
== 0 || dep
->number
== 1)
361 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
362 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
363 &dep
->trb_pool_dma
, GFP_KERNEL
);
364 if (!dep
->trb_pool
) {
365 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
373 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
375 struct dwc3
*dwc
= dep
->dwc
;
377 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
378 dep
->trb_pool
, dep
->trb_pool_dma
);
380 dep
->trb_pool
= NULL
;
381 dep
->trb_pool_dma
= 0;
384 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
386 struct dwc3_gadget_ep_cmd_params params
;
389 memset(¶ms
, 0x00, sizeof(params
));
391 if (dep
->number
!= 1) {
392 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
393 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
394 if (dep
->number
> 1) {
395 if (dwc
->start_config_issued
)
397 dwc
->start_config_issued
= true;
398 cmd
|= DWC3_DEPCMD_PARAM(2);
401 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
407 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
408 const struct usb_endpoint_descriptor
*desc
,
409 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
411 struct dwc3_gadget_ep_cmd_params params
;
413 memset(¶ms
, 0x00, sizeof(params
));
415 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
416 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
))
417 | DWC3_DEPCFG_BURST_SIZE(dep
->endpoint
.maxburst
);
419 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
420 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
422 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
423 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
424 | DWC3_DEPCFG_STREAM_EVENT_EN
;
425 dep
->stream_capable
= true;
428 if (usb_endpoint_xfer_isoc(desc
))
429 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
432 * We are doing 1:1 mapping for endpoints, meaning
433 * Physical Endpoints 2 maps to Logical Endpoint 2 and
434 * so on. We consider the direction bit as part of the physical
435 * endpoint number. So USB endpoint 0x81 is 0x03.
437 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
440 * We must use the lower 16 TX FIFOs even though
444 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
446 if (desc
->bInterval
) {
447 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
448 dep
->interval
= 1 << (desc
->bInterval
- 1);
451 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
452 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
455 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
457 struct dwc3_gadget_ep_cmd_params params
;
459 memset(¶ms
, 0x00, sizeof(params
));
461 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
463 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
464 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
468 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
469 * @dep: endpoint to be initialized
470 * @desc: USB Endpoint Descriptor
472 * Caller should take care of locking
474 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
475 const struct usb_endpoint_descriptor
*desc
,
476 const struct usb_ss_ep_comp_descriptor
*comp_desc
)
478 struct dwc3
*dwc
= dep
->dwc
;
482 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
483 ret
= dwc3_gadget_start_config(dwc
, dep
);
488 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
);
492 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
493 struct dwc3_trb
*trb_st_hw
;
494 struct dwc3_trb
*trb_link
;
496 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
500 dep
->endpoint
.desc
= desc
;
501 dep
->comp_desc
= comp_desc
;
502 dep
->type
= usb_endpoint_type(desc
);
503 dep
->flags
|= DWC3_EP_ENABLED
;
505 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
506 reg
|= DWC3_DALEPENA_EP(dep
->number
);
507 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
509 if (!usb_endpoint_xfer_isoc(desc
))
512 memset(&trb_link
, 0, sizeof(trb_link
));
514 /* Link TRB for ISOC. The HWO bit is never reset */
515 trb_st_hw
= &dep
->trb_pool
[0];
517 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
519 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
520 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
521 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
522 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
528 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
);
529 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
531 struct dwc3_request
*req
;
533 if (!list_empty(&dep
->req_queued
))
534 dwc3_stop_active_transfer(dwc
, dep
->number
);
536 while (!list_empty(&dep
->request_list
)) {
537 req
= next_request(&dep
->request_list
);
539 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
544 * __dwc3_gadget_ep_disable - Disables a HW endpoint
545 * @dep: the endpoint to disable
547 * This function also removes requests which are currently processed ny the
548 * hardware and those which are not yet scheduled.
549 * Caller should take care of locking.
551 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
553 struct dwc3
*dwc
= dep
->dwc
;
556 dwc3_remove_requests(dwc
, dep
);
558 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
559 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
560 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
562 dep
->stream_capable
= false;
563 dep
->endpoint
.desc
= NULL
;
564 dep
->comp_desc
= NULL
;
571 /* -------------------------------------------------------------------------- */
573 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
574 const struct usb_endpoint_descriptor
*desc
)
579 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
584 /* -------------------------------------------------------------------------- */
586 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
587 const struct usb_endpoint_descriptor
*desc
)
594 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
595 pr_debug("dwc3: invalid parameters\n");
599 if (!desc
->wMaxPacketSize
) {
600 pr_debug("dwc3: missing wMaxPacketSize\n");
604 dep
= to_dwc3_ep(ep
);
607 switch (usb_endpoint_type(desc
)) {
608 case USB_ENDPOINT_XFER_CONTROL
:
609 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
611 case USB_ENDPOINT_XFER_ISOC
:
612 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
614 case USB_ENDPOINT_XFER_BULK
:
615 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
617 case USB_ENDPOINT_XFER_INT
:
618 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
621 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
624 if (dep
->flags
& DWC3_EP_ENABLED
) {
625 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
630 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
632 spin_lock_irqsave(&dwc
->lock
, flags
);
633 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
);
634 spin_unlock_irqrestore(&dwc
->lock
, flags
);
639 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
647 pr_debug("dwc3: invalid parameters\n");
651 dep
= to_dwc3_ep(ep
);
654 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
655 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
660 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
662 (dep
->number
& 1) ? "in" : "out");
664 spin_lock_irqsave(&dwc
->lock
, flags
);
665 ret
= __dwc3_gadget_ep_disable(dep
);
666 spin_unlock_irqrestore(&dwc
->lock
, flags
);
671 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
674 struct dwc3_request
*req
;
675 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
676 struct dwc3
*dwc
= dep
->dwc
;
678 req
= kzalloc(sizeof(*req
), gfp_flags
);
680 dev_err(dwc
->dev
, "not enough memory\n");
684 req
->epnum
= dep
->number
;
687 return &req
->request
;
690 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
691 struct usb_request
*request
)
693 struct dwc3_request
*req
= to_dwc3_request(request
);
699 * dwc3_prepare_one_trb - setup one TRB from one request
700 * @dep: endpoint for which this request is prepared
701 * @req: dwc3_request pointer
703 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
704 struct dwc3_request
*req
, dma_addr_t dma
,
705 unsigned length
, unsigned last
, unsigned chain
)
707 struct dwc3
*dwc
= dep
->dwc
;
708 struct dwc3_trb
*trb
;
710 unsigned int cur_slot
;
712 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
713 dep
->name
, req
, (unsigned long long) dma
,
714 length
, last
? " last" : "",
715 chain
? " chain" : "");
717 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
718 cur_slot
= dep
->free_slot
;
721 /* Skip the LINK-TRB on ISOC */
722 if (((cur_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
723 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
727 dwc3_gadget_move_request_queued(req
);
729 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
732 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
733 trb
->bpl
= lower_32_bits(dma
);
734 trb
->bph
= upper_32_bits(dma
);
736 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
737 case USB_ENDPOINT_XFER_CONTROL
:
738 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
741 case USB_ENDPOINT_XFER_ISOC
:
742 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
744 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
745 if (!(cur_slot
% (DWC3_TRB_NUM
/ 4)))
746 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
749 case USB_ENDPOINT_XFER_BULK
:
750 case USB_ENDPOINT_XFER_INT
:
751 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
755 * This is only possible with faulty memory because we
756 * checked it already :)
761 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
762 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
763 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
766 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
769 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
772 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
773 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
775 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
779 * dwc3_prepare_trbs - setup TRBs from requests
780 * @dep: endpoint for which requests are being prepared
781 * @starting: true if the endpoint is idle and no requests are queued.
783 * The function goes through the requests list and sets up TRBs for the
784 * transfers. The function returns once there are no more TRBs available or
785 * it runs out of requests.
787 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
789 struct dwc3_request
*req
, *n
;
792 unsigned int last_one
= 0;
794 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
796 /* the first request must not be queued */
797 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
799 /* Can't wrap around on a non-isoc EP since there's no link TRB */
800 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
801 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
807 * If busy & slot are equal than it is either full or empty. If we are
808 * starting to process requests then we are empty. Otherwise we are
809 * full and don't do anything
814 trbs_left
= DWC3_TRB_NUM
;
816 * In case we start from scratch, we queue the ISOC requests
817 * starting from slot 1. This is done because we use ring
818 * buffer and have no LST bit to stop us. Instead, we place
819 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
820 * after the first request so we start at slot 1 and have
821 * 7 requests proceed before we hit the first IOC.
822 * Other transfer types don't use the ring buffer and are
823 * processed from the first TRB until the last one. Since we
824 * don't wrap around we have to start at the beginning.
826 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
835 /* The last TRB is a link TRB, not used for xfer */
836 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
839 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
843 if (req
->request
.num_mapped_sgs
> 0) {
844 struct usb_request
*request
= &req
->request
;
845 struct scatterlist
*sg
= request
->sg
;
846 struct scatterlist
*s
;
849 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
850 unsigned chain
= true;
852 length
= sg_dma_len(s
);
853 dma
= sg_dma_address(s
);
855 if (i
== (request
->num_mapped_sgs
- 1) ||
868 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
875 dma
= req
->request
.dma
;
876 length
= req
->request
.length
;
882 /* Is this the last request? */
883 if (list_is_last(&req
->list
, &dep
->request_list
))
886 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
895 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
898 struct dwc3_gadget_ep_cmd_params params
;
899 struct dwc3_request
*req
;
900 struct dwc3
*dwc
= dep
->dwc
;
904 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
905 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
908 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
911 * If we are getting here after a short-out-packet we don't enqueue any
912 * new requests as we try to set the IOC bit only on the last request.
915 if (list_empty(&dep
->req_queued
))
916 dwc3_prepare_trbs(dep
, start_new
);
918 /* req points to the first request which will be sent */
919 req
= next_request(&dep
->req_queued
);
921 dwc3_prepare_trbs(dep
, start_new
);
924 * req points to the first request where HWO changed from 0 to 1
926 req
= next_request(&dep
->req_queued
);
929 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
933 memset(¶ms
, 0, sizeof(params
));
934 params
.param0
= upper_32_bits(req
->trb_dma
);
935 params
.param1
= lower_32_bits(req
->trb_dma
);
938 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
940 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
942 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
943 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
945 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
948 * FIXME we need to iterate over the list of requests
949 * here and stop, unmap, free and del each of the linked
950 * requests instead of what we do now.
952 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
954 list_del(&req
->list
);
958 dep
->flags
|= DWC3_EP_BUSY
;
961 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
963 WARN_ON_ONCE(!dep
->res_trans_idx
);
969 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
971 struct dwc3
*dwc
= dep
->dwc
;
974 req
->request
.actual
= 0;
975 req
->request
.status
= -EINPROGRESS
;
976 req
->direction
= dep
->direction
;
977 req
->epnum
= dep
->number
;
980 * We only add to our list of requests now and
981 * start consuming the list once we get XferNotReady
984 * That way, we avoid doing anything that we don't need
985 * to do now and defer it until the point we receive a
986 * particular token from the Host side.
988 * This will also avoid Host cancelling URBs due to too
991 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
996 list_add_tail(&req
->list
, &dep
->request_list
);
998 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && (dep
->flags
& DWC3_EP_BUSY
))
999 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1002 * There are two special cases:
1004 * 1. XferNotReady with empty list of requests. We need to kick the
1005 * transfer here in that situation, otherwise we will be NAKing
1006 * forever. If we get XferNotReady before gadget driver has a
1007 * chance to queue a request, we will ACK the IRQ but won't be
1008 * able to receive the data until the next request is queued.
1009 * The following code is handling exactly that.
1011 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1012 * kick the transfer here after queuing a request, otherwise the
1013 * core may not see the modified TRB(s).
1015 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1017 int start_trans
= 1;
1018 u8 trans_idx
= dep
->res_trans_idx
;
1020 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1021 (dep
->flags
& DWC3_EP_BUSY
)) {
1023 WARN_ON_ONCE(!trans_idx
);
1028 ret
= __dwc3_gadget_kick_transfer(dep
, trans_idx
, start_trans
);
1029 if (ret
&& ret
!= -EBUSY
) {
1030 struct dwc3
*dwc
= dep
->dwc
;
1032 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1040 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1043 struct dwc3_request
*req
= to_dwc3_request(request
);
1044 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1045 struct dwc3
*dwc
= dep
->dwc
;
1047 unsigned long flags
;
1051 if (!dep
->endpoint
.desc
) {
1052 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1057 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1058 request
, ep
->name
, request
->length
);
1060 spin_lock_irqsave(&dwc
->lock
, flags
);
1061 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1062 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1067 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1068 struct usb_request
*request
)
1070 struct dwc3_request
*req
= to_dwc3_request(request
);
1071 struct dwc3_request
*r
= NULL
;
1073 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1074 struct dwc3
*dwc
= dep
->dwc
;
1076 unsigned long flags
;
1079 spin_lock_irqsave(&dwc
->lock
, flags
);
1081 list_for_each_entry(r
, &dep
->request_list
, list
) {
1087 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1092 /* wait until it is processed */
1093 dwc3_stop_active_transfer(dwc
, dep
->number
);
1096 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1102 /* giveback the request */
1103 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1106 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1111 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
)
1113 struct dwc3_gadget_ep_cmd_params params
;
1114 struct dwc3
*dwc
= dep
->dwc
;
1117 memset(¶ms
, 0x00, sizeof(params
));
1120 if (dep
->number
== 0 || dep
->number
== 1) {
1122 * Whenever EP0 is stalled, we will restart
1123 * the state machine, thus moving back to
1126 dwc
->ep0state
= EP0_SETUP_PHASE
;
1129 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1130 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1132 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1133 value
? "set" : "clear",
1136 dep
->flags
|= DWC3_EP_STALL
;
1138 if (dep
->flags
& DWC3_EP_WEDGE
)
1141 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1142 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1144 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1145 value
? "set" : "clear",
1148 dep
->flags
&= ~DWC3_EP_STALL
;
1154 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1156 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1157 struct dwc3
*dwc
= dep
->dwc
;
1159 unsigned long flags
;
1163 spin_lock_irqsave(&dwc
->lock
, flags
);
1165 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1166 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1171 ret
= __dwc3_gadget_ep_set_halt(dep
, value
);
1173 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1178 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1180 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1181 struct dwc3
*dwc
= dep
->dwc
;
1182 unsigned long flags
;
1184 spin_lock_irqsave(&dwc
->lock
, flags
);
1185 dep
->flags
|= DWC3_EP_WEDGE
;
1186 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1188 return dwc3_gadget_ep_set_halt(ep
, 1);
1191 /* -------------------------------------------------------------------------- */
1193 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1194 .bLength
= USB_DT_ENDPOINT_SIZE
,
1195 .bDescriptorType
= USB_DT_ENDPOINT
,
1196 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1199 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1200 .enable
= dwc3_gadget_ep0_enable
,
1201 .disable
= dwc3_gadget_ep0_disable
,
1202 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1203 .free_request
= dwc3_gadget_ep_free_request
,
1204 .queue
= dwc3_gadget_ep0_queue
,
1205 .dequeue
= dwc3_gadget_ep_dequeue
,
1206 .set_halt
= dwc3_gadget_ep_set_halt
,
1207 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1210 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1211 .enable
= dwc3_gadget_ep_enable
,
1212 .disable
= dwc3_gadget_ep_disable
,
1213 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1214 .free_request
= dwc3_gadget_ep_free_request
,
1215 .queue
= dwc3_gadget_ep_queue
,
1216 .dequeue
= dwc3_gadget_ep_dequeue
,
1217 .set_halt
= dwc3_gadget_ep_set_halt
,
1218 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1221 /* -------------------------------------------------------------------------- */
1223 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1225 struct dwc3
*dwc
= gadget_to_dwc(g
);
1228 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1229 return DWC3_DSTS_SOFFN(reg
);
1232 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1234 struct dwc3
*dwc
= gadget_to_dwc(g
);
1236 unsigned long timeout
;
1237 unsigned long flags
;
1246 spin_lock_irqsave(&dwc
->lock
, flags
);
1249 * According to the Databook Remote wakeup request should
1250 * be issued only when the device is in early suspend state.
1252 * We can check that via USB Link State bits in DSTS register.
1254 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1256 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1257 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1258 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1263 link_state
= DWC3_DSTS_USBLNKST(reg
);
1265 switch (link_state
) {
1266 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1267 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1270 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1276 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1278 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1282 /* write zeroes to Link Change Request */
1283 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1284 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1286 /* poll until Link State changes to ON */
1287 timeout
= jiffies
+ msecs_to_jiffies(100);
1289 while (!time_after(jiffies
, timeout
)) {
1290 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1292 /* in HS, means ON */
1293 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1297 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1298 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1303 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1308 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1311 struct dwc3
*dwc
= gadget_to_dwc(g
);
1312 unsigned long flags
;
1314 spin_lock_irqsave(&dwc
->lock
, flags
);
1315 dwc
->is_selfpowered
= !!is_selfpowered
;
1316 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1321 static void dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
)
1326 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1328 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1329 reg
|= (DWC3_DCTL_RUN_STOP
1330 | DWC3_DCTL_TRGTULST_RX_DET
);
1332 reg
&= ~DWC3_DCTL_RUN_STOP
;
1335 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1338 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1340 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1343 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1352 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1354 ? dwc
->gadget_driver
->function
: "no-function",
1355 is_on
? "connect" : "disconnect");
1358 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1360 struct dwc3
*dwc
= gadget_to_dwc(g
);
1361 unsigned long flags
;
1365 spin_lock_irqsave(&dwc
->lock
, flags
);
1366 dwc3_gadget_run_stop(dwc
, is_on
);
1367 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1372 static int dwc3_gadget_start(struct usb_gadget
*g
,
1373 struct usb_gadget_driver
*driver
)
1375 struct dwc3
*dwc
= gadget_to_dwc(g
);
1376 struct dwc3_ep
*dep
;
1377 unsigned long flags
;
1381 spin_lock_irqsave(&dwc
->lock
, flags
);
1383 if (dwc
->gadget_driver
) {
1384 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1386 dwc
->gadget_driver
->driver
.name
);
1391 dwc
->gadget_driver
= driver
;
1392 dwc
->gadget
.dev
.driver
= &driver
->driver
;
1394 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1395 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1398 * WORKAROUND: DWC3 revision < 2.20a have an issue
1399 * which would cause metastability state on Run/Stop
1400 * bit if we try to force the IP to USB2-only mode.
1402 * Because of that, we cannot configure the IP to any
1403 * speed other than the SuperSpeed
1407 * STAR#9000525659: Clock Domain Crossing on DCTL in
1410 if (dwc
->revision
< DWC3_REVISION_220A
)
1411 reg
|= DWC3_DCFG_SUPERSPEED
;
1413 reg
|= dwc
->maximum_speed
;
1414 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1416 dwc
->start_config_issued
= false;
1418 /* Start with SuperSpeed Default */
1419 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1422 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1424 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1429 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
1431 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1435 /* begin to receive SETUP packets */
1436 dwc
->ep0state
= EP0_SETUP_PHASE
;
1437 dwc3_ep0_out_start(dwc
);
1439 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1444 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1447 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1452 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1453 struct usb_gadget_driver
*driver
)
1455 struct dwc3
*dwc
= gadget_to_dwc(g
);
1456 unsigned long flags
;
1458 spin_lock_irqsave(&dwc
->lock
, flags
);
1460 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1461 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1463 dwc
->gadget_driver
= NULL
;
1464 dwc
->gadget
.dev
.driver
= NULL
;
1466 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1470 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1471 .get_frame
= dwc3_gadget_get_frame
,
1472 .wakeup
= dwc3_gadget_wakeup
,
1473 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1474 .pullup
= dwc3_gadget_pullup
,
1475 .udc_start
= dwc3_gadget_start
,
1476 .udc_stop
= dwc3_gadget_stop
,
1479 /* -------------------------------------------------------------------------- */
1481 static int __devinit
dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1483 struct dwc3_ep
*dep
;
1486 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1488 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1489 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1491 dev_err(dwc
->dev
, "can't allocate endpoint %d\n",
1497 dep
->number
= epnum
;
1498 dwc
->eps
[epnum
] = dep
;
1500 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1501 (epnum
& 1) ? "in" : "out");
1502 dep
->endpoint
.name
= dep
->name
;
1503 dep
->direction
= (epnum
& 1);
1505 if (epnum
== 0 || epnum
== 1) {
1506 dep
->endpoint
.maxpacket
= 512;
1507 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1509 dwc
->gadget
.ep0
= &dep
->endpoint
;
1513 dep
->endpoint
.maxpacket
= 1024;
1514 dep
->endpoint
.max_streams
= 15;
1515 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1516 list_add_tail(&dep
->endpoint
.ep_list
,
1517 &dwc
->gadget
.ep_list
);
1519 ret
= dwc3_alloc_trb_pool(dep
);
1524 INIT_LIST_HEAD(&dep
->request_list
);
1525 INIT_LIST_HEAD(&dep
->req_queued
);
1531 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1533 struct dwc3_ep
*dep
;
1536 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1537 dep
= dwc
->eps
[epnum
];
1538 dwc3_free_trb_pool(dep
);
1540 if (epnum
!= 0 && epnum
!= 1)
1541 list_del(&dep
->endpoint
.ep_list
);
1547 static void dwc3_gadget_release(struct device
*dev
)
1549 dev_dbg(dev
, "%s\n", __func__
);
1552 /* -------------------------------------------------------------------------- */
1553 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1554 const struct dwc3_event_depevt
*event
, int status
)
1556 struct dwc3_request
*req
;
1557 struct dwc3_trb
*trb
;
1559 unsigned int s_pkt
= 0;
1562 req
= next_request(&dep
->req_queued
);
1570 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1572 * We continue despite the error. There is not much we
1573 * can do. If we don't clean it up we loop forever. If
1574 * we skip the TRB then it gets overwritten after a
1575 * while since we use them in a ring buffer. A BUG()
1576 * would help. Lets hope that if this occurs, someone
1577 * fixes the root cause instead of looking away :)
1579 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1580 dep
->name
, req
->trb
);
1581 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1583 if (dep
->direction
) {
1585 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1587 status
= -ECONNRESET
;
1590 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1595 * We assume here we will always receive the entire data block
1596 * which we should receive. Meaning, if we program RX to
1597 * receive 4K but we receive only 2K, we assume that's all we
1598 * should receive and we simply bounce the request back to the
1599 * gadget driver for further processing.
1601 req
->request
.actual
+= req
->request
.length
- count
;
1602 dwc3_gadget_giveback(dep
, req
, status
);
1605 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1606 (trb
->ctrl
& DWC3_TRB_CTRL_LST
))
1608 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1609 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1613 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1614 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1619 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1620 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
,
1623 unsigned status
= 0;
1626 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1627 status
= -ECONNRESET
;
1629 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1631 dep
->flags
&= ~DWC3_EP_BUSY
;
1634 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1635 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1637 if (dwc
->revision
< DWC3_REVISION_183A
) {
1641 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1642 struct dwc3_ep
*dep
= dwc
->eps
[i
];
1644 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1647 if (!list_empty(&dep
->req_queued
))
1651 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1653 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1659 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1660 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1664 if (list_empty(&dep
->request_list
)) {
1665 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1670 mask
= ~(dep
->interval
- 1);
1671 uf
= event
->parameters
& mask
;
1672 /* 4 micro frames in the future */
1673 uf
+= dep
->interval
* 4;
1675 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1678 static void dwc3_process_ep_cmd_complete(struct dwc3_ep
*dep
,
1679 const struct dwc3_event_depevt
*event
)
1681 struct dwc3
*dwc
= dep
->dwc
;
1682 struct dwc3_event_depevt mod_ev
= *event
;
1685 * We were asked to remove one request. It is possible that this
1686 * request and a few others were started together and have the same
1687 * transfer index. Since we stopped the complete endpoint we don't
1688 * know how many requests were already completed (and not yet)
1689 * reported and how could be done (later). We purge them all until
1690 * the end of the list.
1692 mod_ev
.status
= DEPEVT_STATUS_LST
;
1693 dwc3_cleanup_done_reqs(dwc
, dep
, &mod_ev
, -ESHUTDOWN
);
1694 dep
->flags
&= ~DWC3_EP_BUSY
;
1695 /* pending requests are ignored and are queued on XferNotReady */
1698 static void dwc3_ep_cmd_compl(struct dwc3_ep
*dep
,
1699 const struct dwc3_event_depevt
*event
)
1701 u32 param
= event
->parameters
;
1702 u32 cmd_type
= (param
>> 8) & ((1 << 5) - 1);
1705 case DWC3_DEPCMD_ENDTRANSFER
:
1706 dwc3_process_ep_cmd_complete(dep
, event
);
1708 case DWC3_DEPCMD_STARTTRANSFER
:
1709 dep
->res_trans_idx
= param
& 0x7f;
1712 printk(KERN_ERR
"%s() unknown /unexpected type: %d\n",
1713 __func__
, cmd_type
);
1718 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1719 const struct dwc3_event_depevt
*event
)
1721 struct dwc3_ep
*dep
;
1722 u8 epnum
= event
->endpoint_number
;
1724 dep
= dwc
->eps
[epnum
];
1726 dev_vdbg(dwc
->dev
, "%s: %s\n", dep
->name
,
1727 dwc3_ep_event_string(event
->endpoint_event
));
1729 if (epnum
== 0 || epnum
== 1) {
1730 dwc3_ep0_interrupt(dwc
, event
);
1734 switch (event
->endpoint_event
) {
1735 case DWC3_DEPEVT_XFERCOMPLETE
:
1736 dep
->res_trans_idx
= 0;
1738 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1739 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1744 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 1);
1746 case DWC3_DEPEVT_XFERINPROGRESS
:
1747 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1748 dev_dbg(dwc
->dev
, "%s is not an Isochronous endpoint\n",
1753 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 0);
1755 case DWC3_DEPEVT_XFERNOTREADY
:
1756 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1757 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1761 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1762 dep
->name
, event
->status
&
1763 DEPEVT_STATUS_TRANSFER_ACTIVE
1765 : "Transfer Not Active");
1767 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1768 if (!ret
|| ret
== -EBUSY
)
1771 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1776 case DWC3_DEPEVT_STREAMEVT
:
1777 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1778 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1783 switch (event
->status
) {
1784 case DEPEVT_STREAMEVT_FOUND
:
1785 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1789 case DEPEVT_STREAMEVT_NOTFOUND
:
1792 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
1795 case DWC3_DEPEVT_RXTXFIFOEVT
:
1796 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
1798 case DWC3_DEPEVT_EPCMDCMPLT
:
1799 dwc3_ep_cmd_compl(dep
, event
);
1804 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
1806 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
1807 spin_unlock(&dwc
->lock
);
1808 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
1809 spin_lock(&dwc
->lock
);
1813 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
)
1815 struct dwc3_ep
*dep
;
1816 struct dwc3_gadget_ep_cmd_params params
;
1820 dep
= dwc
->eps
[epnum
];
1822 WARN_ON(!dep
->res_trans_idx
);
1823 if (dep
->res_trans_idx
) {
1824 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1825 cmd
|= DWC3_DEPCMD_HIPRI_FORCERM
| DWC3_DEPCMD_CMDIOC
;
1826 cmd
|= DWC3_DEPCMD_PARAM(dep
->res_trans_idx
);
1827 memset(¶ms
, 0, sizeof(params
));
1828 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1830 dep
->res_trans_idx
= 0;
1834 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
1838 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1839 struct dwc3_ep
*dep
;
1841 dep
= dwc
->eps
[epnum
];
1842 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1845 dwc3_remove_requests(dwc
, dep
);
1849 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
1853 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1854 struct dwc3_ep
*dep
;
1855 struct dwc3_gadget_ep_cmd_params params
;
1858 dep
= dwc
->eps
[epnum
];
1860 if (!(dep
->flags
& DWC3_EP_STALL
))
1863 dep
->flags
&= ~DWC3_EP_STALL
;
1865 memset(¶ms
, 0, sizeof(params
));
1866 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1867 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1872 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
1874 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1877 U1
/U2 is powersave optimization
. Skip it
for now
. Anyway we need to
1878 enable it before we can disable it
.
1880 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1881 reg
&= ~DWC3_DCTL_INITU1ENA
;
1882 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1884 reg
&= ~DWC3_DCTL_INITU2ENA
;
1885 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1888 dwc3_stop_active_transfers(dwc
);
1889 dwc3_disconnect_gadget(dwc
);
1890 dwc
->start_config_issued
= false;
1892 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1893 dwc
->setup_packet_pending
= false;
1896 static void dwc3_gadget_usb3_phy_power(struct dwc3
*dwc
, int on
)
1900 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
1903 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
1905 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
1907 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
1910 static void dwc3_gadget_usb2_phy_power(struct dwc3
*dwc
, int on
)
1914 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
1917 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
1919 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
1921 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
1924 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
1928 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1931 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1932 * would cause a missing Disconnect Event if there's a
1933 * pending Setup Packet in the FIFO.
1935 * There's no suggested workaround on the official Bug
1936 * report, which states that "unless the driver/application
1937 * is doing any special handling of a disconnect event,
1938 * there is no functional issue".
1940 * Unfortunately, it turns out that we _do_ some special
1941 * handling of a disconnect event, namely complete all
1942 * pending transfers, notify gadget driver of the
1943 * disconnection, and so on.
1945 * Our suggested workaround is to follow the Disconnect
1946 * Event steps here, instead, based on a setup_packet_pending
1947 * flag. Such flag gets set whenever we have a XferNotReady
1948 * event on EP0 and gets cleared on XferComplete for the
1953 * STAR#9000466709: RTL: Device : Disconnect event not
1954 * generated if setup packet pending in FIFO
1956 if (dwc
->revision
< DWC3_REVISION_188A
) {
1957 if (dwc
->setup_packet_pending
)
1958 dwc3_gadget_disconnect_interrupt(dwc
);
1961 /* after reset -> Default State */
1962 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
1965 dwc3_gadget_usb2_phy_power(dwc
, true);
1966 dwc3_gadget_usb3_phy_power(dwc
, true);
1968 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
1969 dwc3_disconnect_gadget(dwc
);
1971 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1972 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
1973 reg
&= ~(DWC3_DCTL_INITU1ENA
| DWC3_DCTL_INITU2ENA
);
1974 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1975 dwc
->test_mode
= false;
1977 dwc3_stop_active_transfers(dwc
);
1978 dwc3_clear_stall_all_ep(dwc
);
1979 dwc
->start_config_issued
= false;
1981 /* Reset device address to zero */
1982 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1983 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
1984 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1987 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
1990 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
1993 * We change the clock only at SS but I dunno why I would want to do
1994 * this. Maybe it becomes part of the power saving plan.
1997 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2001 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2002 * each time on Connect Done.
2007 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2008 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2009 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2012 static void dwc3_gadget_disable_phy(struct dwc3
*dwc
, u8 speed
)
2015 case USB_SPEED_SUPER
:
2016 dwc3_gadget_usb2_phy_power(dwc
, false);
2018 case USB_SPEED_HIGH
:
2019 case USB_SPEED_FULL
:
2021 dwc3_gadget_usb3_phy_power(dwc
, false);
2026 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2028 struct dwc3_gadget_ep_cmd_params params
;
2029 struct dwc3_ep
*dep
;
2034 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2036 memset(¶ms
, 0x00, sizeof(params
));
2038 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2039 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2042 dwc3_update_ram_clk_sel(dwc
, speed
);
2045 case DWC3_DCFG_SUPERSPEED
:
2047 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2048 * would cause a missing USB3 Reset event.
2050 * In such situations, we should force a USB3 Reset
2051 * event by calling our dwc3_gadget_reset_interrupt()
2056 * STAR#9000483510: RTL: SS : USB3 reset event may
2057 * not be generated always when the link enters poll
2059 if (dwc
->revision
< DWC3_REVISION_190A
)
2060 dwc3_gadget_reset_interrupt(dwc
);
2062 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2063 dwc
->gadget
.ep0
->maxpacket
= 512;
2064 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2066 case DWC3_DCFG_HIGHSPEED
:
2067 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2068 dwc
->gadget
.ep0
->maxpacket
= 64;
2069 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2071 case DWC3_DCFG_FULLSPEED2
:
2072 case DWC3_DCFG_FULLSPEED1
:
2073 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2074 dwc
->gadget
.ep0
->maxpacket
= 64;
2075 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2077 case DWC3_DCFG_LOWSPEED
:
2078 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2079 dwc
->gadget
.ep0
->maxpacket
= 8;
2080 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2084 /* Disable unneded PHY */
2085 dwc3_gadget_disable_phy(dwc
, dwc
->gadget
.speed
);
2088 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
2090 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2095 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
);
2097 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2102 * Configure PHY via GUSB3PIPECTLn if required.
2104 * Update GTXFIFOSIZn
2106 * In both cases reset values should be sufficient.
2110 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2112 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2115 * TODO take core out of low power mode when that's
2119 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2122 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2123 unsigned int evtinfo
)
2125 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2128 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2129 * on the link partner, the USB session might do multiple entry/exit
2130 * of low power states before a transfer takes place.
2132 * Due to this problem, we might experience lower throughput. The
2133 * suggested workaround is to disable DCTL[12:9] bits if we're
2134 * transitioning from U1/U2 to U0 and enable those bits again
2135 * after a transfer completes and there are no pending transfers
2136 * on any of the enabled endpoints.
2138 * This is the first half of that workaround.
2142 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2143 * core send LGO_Ux entering U0
2145 if (dwc
->revision
< DWC3_REVISION_183A
) {
2146 if (next
== DWC3_LINK_STATE_U0
) {
2150 switch (dwc
->link_state
) {
2151 case DWC3_LINK_STATE_U1
:
2152 case DWC3_LINK_STATE_U2
:
2153 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2154 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2155 | DWC3_DCTL_ACCEPTU2ENA
2156 | DWC3_DCTL_INITU1ENA
2157 | DWC3_DCTL_ACCEPTU1ENA
);
2160 dwc
->u1u2
= reg
& u1u2
;
2164 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2173 dwc
->link_state
= next
;
2175 dev_vdbg(dwc
->dev
, "%s link %d\n", __func__
, dwc
->link_state
);
2178 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2179 const struct dwc3_event_devt
*event
)
2181 switch (event
->type
) {
2182 case DWC3_DEVICE_EVENT_DISCONNECT
:
2183 dwc3_gadget_disconnect_interrupt(dwc
);
2185 case DWC3_DEVICE_EVENT_RESET
:
2186 dwc3_gadget_reset_interrupt(dwc
);
2188 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2189 dwc3_gadget_conndone_interrupt(dwc
);
2191 case DWC3_DEVICE_EVENT_WAKEUP
:
2192 dwc3_gadget_wakeup_interrupt(dwc
);
2194 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2195 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2197 case DWC3_DEVICE_EVENT_EOPF
:
2198 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2200 case DWC3_DEVICE_EVENT_SOF
:
2201 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2203 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2204 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2206 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2207 dev_vdbg(dwc
->dev
, "Command Complete\n");
2209 case DWC3_DEVICE_EVENT_OVERFLOW
:
2210 dev_vdbg(dwc
->dev
, "Overflow\n");
2213 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2217 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2218 const union dwc3_event
*event
)
2220 /* Endpoint IRQ, handle it and return early */
2221 if (event
->type
.is_devspec
== 0) {
2223 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2226 switch (event
->type
.type
) {
2227 case DWC3_EVENT_TYPE_DEV
:
2228 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2230 /* REVISIT what to do with Carkit and I2C events ? */
2232 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2236 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2238 struct dwc3_event_buffer
*evt
;
2242 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2243 count
&= DWC3_GEVNTCOUNT_MASK
;
2247 evt
= dwc
->ev_buffs
[buf
];
2251 union dwc3_event event
;
2253 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2255 dwc3_process_event_entry(dwc
, &event
);
2257 * XXX we wrap around correctly to the next entry as almost all
2258 * entries are 4 bytes in size. There is one entry which has 12
2259 * bytes which is a regular entry followed by 8 bytes data. ATM
2260 * I don't know how things are organized if were get next to the
2261 * a boundary so I worry about that once we try to handle that.
2263 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2266 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2272 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2274 struct dwc3
*dwc
= _dwc
;
2276 irqreturn_t ret
= IRQ_NONE
;
2278 spin_lock(&dwc
->lock
);
2280 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2283 status
= dwc3_process_event_buf(dwc
, i
);
2284 if (status
== IRQ_HANDLED
)
2288 spin_unlock(&dwc
->lock
);
2294 * dwc3_gadget_init - Initializes gadget related registers
2295 * @dwc: pointer to our controller context structure
2297 * Returns 0 on success otherwise negative errno.
2299 int __devinit
dwc3_gadget_init(struct dwc3
*dwc
)
2305 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2306 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2307 if (!dwc
->ctrl_req
) {
2308 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2313 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2314 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2315 if (!dwc
->ep0_trb
) {
2316 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2321 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2322 if (!dwc
->setup_buf
) {
2323 dev_err(dwc
->dev
, "failed to allocate setup buffer\n");
2328 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2329 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2331 if (!dwc
->ep0_bounce
) {
2332 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2337 dev_set_name(&dwc
->gadget
.dev
, "gadget");
2339 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2340 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2341 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2342 dwc
->gadget
.dev
.parent
= dwc
->dev
;
2343 dwc
->gadget
.sg_supported
= true;
2345 dma_set_coherent_mask(&dwc
->gadget
.dev
, dwc
->dev
->coherent_dma_mask
);
2347 dwc
->gadget
.dev
.dma_parms
= dwc
->dev
->dma_parms
;
2348 dwc
->gadget
.dev
.dma_mask
= dwc
->dev
->dma_mask
;
2349 dwc
->gadget
.dev
.release
= dwc3_gadget_release
;
2350 dwc
->gadget
.name
= "dwc3-gadget";
2353 * REVISIT: Here we should clear all pending IRQs to be
2354 * sure we're starting from a well known location.
2357 ret
= dwc3_gadget_init_endpoints(dwc
);
2361 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2363 ret
= request_irq(irq
, dwc3_interrupt
, IRQF_SHARED
,
2366 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2371 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2372 reg
|= DWC3_DCFG_LPM_CAP
;
2373 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2375 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2376 reg
|= DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
;
2377 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2379 /* Enable all but Start and End of Frame IRQs */
2380 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
2381 DWC3_DEVTEN_EVNTOVERFLOWEN
|
2382 DWC3_DEVTEN_CMDCMPLTEN
|
2383 DWC3_DEVTEN_ERRTICERREN
|
2384 DWC3_DEVTEN_WKUPEVTEN
|
2385 DWC3_DEVTEN_ULSTCNGEN
|
2386 DWC3_DEVTEN_CONNECTDONEEN
|
2387 DWC3_DEVTEN_USBRSTEN
|
2388 DWC3_DEVTEN_DISCONNEVTEN
);
2389 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
2391 ret
= device_register(&dwc
->gadget
.dev
);
2393 dev_err(dwc
->dev
, "failed to register gadget device\n");
2394 put_device(&dwc
->gadget
.dev
);
2398 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2400 dev_err(dwc
->dev
, "failed to register udc\n");
2407 device_unregister(&dwc
->gadget
.dev
);
2410 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2414 dwc3_gadget_free_endpoints(dwc
);
2417 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2418 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2421 kfree(dwc
->setup_buf
);
2424 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2425 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2428 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2429 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2435 void dwc3_gadget_exit(struct dwc3
*dwc
)
2439 usb_del_gadget_udc(&dwc
->gadget
);
2440 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2442 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2445 dwc3_gadget_free_endpoints(dwc
);
2447 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2448 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2450 kfree(dwc
->setup_buf
);
2452 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2453 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2455 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2456 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2458 device_unregister(&dwc
->gadget
.dev
);